A gate sidewall structure, manufacturing method thereof and DRAM

Abstract

The present invention relates to a gate sidewall structure, a manufacturing method thereof and a DRAM, belonging to the field of semiconductor manufacturing technology, and is used to solve the problems of small spacing between gates and poor device reliability caused by existing processes. The gate sidewall structure includes: a semiconductor substrate; a gate located on the semiconductor substrate; a gate sidewall located on the sidewall of the gate; the outer side surface of the gate sidewall is a curved surface concave toward the gate sidewall. The manufacturing method of the gate sidewall includes: providing a semiconductor substrate; forming a gate material layer on the substrate, etching the gate material layer to form a gate of a transistor; forming a gate sidewall material layer on the semiconductor substrate and the gate; forming an oxide insulating film on the gate sidewall material layer; performing a first chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall; and performing a second chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall. The present invention increases the voltage between gates and improves device reliability.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a gate sidewall structure, a manufacturing method thereof, and a DRAM. Background Art

[0002] As the integration density of semiconductor devices continues to increase, the gate size is gradually reduced, and the aspect ratio of the gate trench is gradually increased. In DRAM devices, the preparation of the gate is a necessary process step in forming transistors.

[0003] The traditional gate sidewall process includes: step 1, using chemical vapor deposition to prepare a layer of polysilicon on the surface of the silicon substrate, then using a gate layer mask to form a photoresist pattern, and then etching the polysilicon to form the gate of the transistor; step 2, annealing the polysilicon gate, and then placing the silicon wafer in an oxidation furnace to oxidize it to form a gate silicon dioxide protective layer; step 3, using plasma implantation to form a lightly doped source and drain region; step 4, using chemical vapor deposition to deposit silicon nitride and silicon dioxide on the gate surface oxidized to silicon dioxide, and then etching the silicon wafer to form gate sidewalls, and then using wet etching to remove the silicon dioxide on the gate sidewalls and the top of the gate; step 5, implanting the source and drain of the transistor.

[0004] In the traditional gate sidewall preparation process, there is an over-etching phenomenon during the gate sidewall etching process, resulting in uneven volume of the sidewalls on both sides of the gate. The sidewalls are mostly curved surfaces convex to the outside of the gate, such as Figure 1 As shown in Figure 2, this gate structure results in a small spacing between the two gates, which can easily lead to gate breakdown. Furthermore, during the subsequent contact hole formation process, the spacing between the contact hole and the gate is also too small, reducing the breakdown voltage between the two. As device sizes decrease, this sidewall structure is more likely to lead to poor device reliability. Summary of the Invention

[0005] In view of the above analysis, embodiments of the present invention aim to provide a gate spacer structure, a manufacturing method thereof, and a DRAM to solve the problems of small spacing between gates and poor device reliability caused by existing processes.

[0006] On the one hand, the present invention provides a gate sidewall structure, comprising: a semiconductor substrate; a gate located on the semiconductor substrate; a gate sidewall located on the sidewall of the gate; and the outer side surface of the gate sidewall is a curved surface concave toward the gate sidewall.

[0007] Furthermore, the width of the gate spacer increases gradually from top to bottom, and the bottom width of the gate spacer is 50 to 200 angstroms.

[0008] On the other hand, the present invention provides a DRAM including the gate spacer structure described above.

[0009] On the other hand, the present invention provides a method for manufacturing a gate sidewall structure, which is used to manufacture the above-mentioned gate sidewall structure, including: providing a semiconductor substrate; forming a gate material layer on the substrate, and etching the gate material layer to form a gate of a transistor; forming a gate sidewall material layer on the semiconductor substrate and the gate; forming an oxide insulating film on the gate sidewall material layer; performing a first chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall; and performing a second chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall.

[0010] Furthermore, the first chemical mechanical planarization treatment is performed on the oxide insulating film on the top of the gate spacer and the gate spacer on the top of the gate.

[0011] Furthermore, the second chemical mechanical planarization is a process for processing the gate sidewall spacer and the oxide insulating film outside the gate sidewall spacer.

[0012] Furthermore, the first chemical mechanical planarization process needs to be polished to the top surface of the gate.

[0013] Furthermore, the selectivity ratio of the gate sidewall to the oxide insulating film in the first chemical mechanical planarization process is 1:1.

[0014] Furthermore, the selectivity ratio of the gate sidewall to the oxide insulating film in the second chemical mechanical planarization process is 1:1.

[0015] Furthermore, during the second chemical mechanical planarization process, the hardness of the polishing pad is less than Shore D 30.

[0016] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0017] 1. By changing the structure of the gate sidewall, the masking effect of the gate sidewall can be guaranteed, the spacing between the gates can be reduced, and the breakdown voltage between the gates can be increased.

[0018] 2. By adopting the first and second chemical mechanical planarization processes to prepare the gate sidewalls, the over-etching problem that often occurs in the existing process is avoided, and the stability of the gate sidewall manufacturing process is improved.

[0019] 3. Through the first chemical mechanical planarization, the oxide insulating film on the top of the gate sidewall and the gate sidewall on the top of the gate are processed. The selectivity ratio of the gate sidewall to the oxide insulating film is 1:1. The thickness of the gate sidewall and the oxide insulating film is accurately positioned to prepare for the second chemical mechanical planarization.

[0020] 4. The hardness of the polishing pad for the second chemical mechanical planarization is less than Shore D 30, which can reduce the concave phenomenon during the second chemical mechanical planarization process and ensure the symmetry and uniformity of the gate sidewall structure.

[0021] 5. From the perspective of improving the process of highly integrated devices, the present invention proposes a method for forming a gate sidewall to meet the needs of preparing a small linewidth gate. By reducing the size of the upper and middle parts of the gate sidewall, the overall size of the gate is reduced, thereby reducing the overall size of the chip and meeting the requirements of high integration.

[0022] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.

[0024] Figure 1 Schematic diagram of the cross section of the gate sidewall in the existing process;

[0025] Figure 2 is a schematic cross-sectional view of the gate sidewall structure of the present invention;

[0026] Figure 3 A schematic cross-sectional view of the gate sidewall structure of the present invention at an intermediate stage during its formation process. Figure 1 ;

[0027] Figure 4 A schematic cross-sectional view of the gate sidewall structure of the present invention at an intermediate stage during its formation process. Figure 2 .

[0028] Reference numerals:

[0029] 1-gate; 2-gate sidewall; 3-oxide insulating film. DETAILED DESCRIPTION

[0030] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.

[0031] The present invention provides a gate sidewall structure, comprising: a semiconductor substrate; a gate 1 located on the semiconductor substrate; a gate sidewall 2 located on the sidewall of the gate 1; and the outer side surface of the gate sidewall 2 is a curved surface concave toward the sidewall of the gate 1.

[0032] Furthermore, the width of the gate spacer 2 increases gradually from top to bottom, and the bottom width of the gate spacer 2 is 50 to 200 angstroms.

[0033] Compared with the prior art, the outer side surface of the gate sidewall 2 proposed in the present invention is a curved surface concave toward the side wall of the gate 1, which improves the problem of poor device reliability caused by the small spacing between the gates 1 and increases the breakdown voltage between the gates 1.

[0034] On the other hand, the present invention provides a DRAM including the gate spacer 2 structure described above.

[0035] It should be noted that the outer side surface of the gate sidewall 2 of the DRAM device is the curved surface concave toward the sidewall of the gate 1 as described above. This structure reduces the overall size of the gate 1 by reducing the size of the upper and middle parts of the gate sidewall 2, thereby reducing the overall size of the chip and meeting the requirements of high integration.

[0036] On the other hand, the present invention provides a method for manufacturing a gate sidewall structure, comprising: providing a semiconductor substrate; forming a gate material layer on the substrate, and etching the gate material layer to form a gate 1 of a transistor; forming a gate sidewall 2 material layer on the semiconductor substrate and the gate 1; forming an oxide insulating film 3 on the gate sidewall 2 material layer; performing a first chemical mechanical planarization treatment on the oxide insulating film 3 and the gate sidewall 2; and performing a second chemical mechanical planarization treatment on the oxide insulating film 3 and the gate sidewall 2.

[0037] Specifically, the semiconductor substrate is cleaned with deionized water at 70-80°C for 20-30 minutes, then dried, and placed in an oxidation furnace. The temperature in the oxidation furnace is raised to 900-1200°C, and O2 is introduced at 2.5-5slm for 20-40 minutes to prepare silicon dioxide with a thickness of 20-60 angstroms.

[0038] Secondly, a semiconductor substrate prepared with a silicon dioxide oxide layer is placed in a chemical vapor deposition device, and a mixture of 20% to 30% silane and nitrogen is introduced into the reaction chamber. The temperature is raised to 575 to 650°C, and a gate material layer is deposited at a pressure of 0.2 to 1.0 torr. The deposition rate is approximately 100 to 200 angstroms per minute, and the thickness of the gate material layer is 1500 to 2000 angstroms.

[0039] Next, in the photolithography area, deep ultraviolet lithography is used to etch the fine structure of the gate material layer. There is usually an anti-reflective coating (ARC) between the gate material layer and the photoresist to reduce unwanted reflections. Next, the gate material layer is dry-etched. First, the gate material layer is pre-etched to remove the natural oxide, hard mask layer and surface contaminants on the surface of the gate material layer to reduce surface defects caused by contaminants that serve as a micro-mask layer during etching. Then, the gate material layer is mainly etched, the etching gas is CF4, and the selectivity of the gate material layer to silicon dioxide is 150:1 to 200:1. Next, an over-etching process is performed to remove the etching residues and the remaining gate material layer to obtain the gate 1. As shown Figure 3 After the gate 1 is formed, it is poly-oxidized and a layer of silicon dioxide is thermally grown on the gate 1. Finally, the silicon wafer is implanted with shallow channel doping.

[0040] Next, the gate sidewall 2 is deposited by chemical vapor deposition, as shown in FIG. Figure 3 As shown, the material of the gate sidewall 2 is silicon nitride. Specifically, a mixed gas of dichlorosilane (SiCl2H2) and ammonia (NH3) is introduced into the oxidation furnace, and the gate sidewall 2 is deposited at a pressure of 0.1 to 5 torr and a temperature of 300 to 900°C. Subsequently, dry etching is used to etch the gate sidewall 2, and the silicon nitride on the sidewall and upper part of the gate sidewall 2 is retained, and the silicon nitride in other places is removed. Next, chemical vapor deposition is used, O2 is introduced, and an oxide insulating film 3 with a thickness of 2000 to 3000 angstroms is deposited at a pressure of 0.1 to 3 torr and a temperature of 650 to 750°C, as shown. Figure 3 shown.

[0041] Then, the first chemical mechanical planarization is used to process the oxide insulating film 3 on the top of the gate sidewall 2 and the gate sidewall 2 on the top of the gate 1. Specifically, the grinding head pressure is 20-25 kPa, the turntable speed is 40-60 rpm, the abrasive is Al2O3 or ZrO2, the pH value of the grinding liquid is 10-13, and the polishing time is 2-5 minutes. The selectivity of the gate sidewall 2 to the oxide insulating film 3 is 1:1. The first chemical mechanical planarization treatment needs to be polished to the top surface of the gate 1, such as Figure 4 Then, the silicon wafer is cleaned and dried.

[0042] Finally, the oxide insulating film 3 and the gate sidewall 2 are subjected to a second chemical mechanical planarization treatment. The grinding head pressure is 30-35 kPa, the turntable speed is 45-65 rpm, the abrasive is Al2O3 or Mn2O3, the pH value of the grinding liquid is 2-6, and the polishing time is 3-6 minutes. In the second chemical mechanical planarization treatment, the selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 is the same, 1:1. To avoid concavity, the hardness of the grinding pad is below Shore D 30. Finally, the gate sidewall 2 is a curved surface concave toward the gate 1, as shown in FIG. Figure 2 shown.

[0043] It should be noted that the present invention utilizes a first and second chemical mechanical planarization process to prepare the gate sidewall 2, thereby avoiding the overetching problem commonly encountered in existing processes and improving the stability of the gate sidewall 2 manufacturing process. During the first chemical mechanical planarization process, the selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 is 1:1, accurately positioning the thickness of the gate sidewall 2 and the oxide insulating film 3 in preparation for the second chemical mechanical planarization process. The hardness of the polishing pad used in the second chemical mechanical planarization process is less than Shore D 30, which can reduce the sagging phenomenon during the second chemical mechanical planarization process and ensure the symmetry and uniformity of the gate sidewall 2.

[0044] Example 1

[0045] A specific embodiment of the present invention discloses a gate spacer 2 structure, wherein the outer side surface of the gate spacer 2 is a curved surface concave toward the side wall of the gate 1 .

[0046] Compared with the prior art, this embodiment improves the structural features of the gate spacer 2, thereby ensuring the masking effect of the gate spacer 2 and increasing the distance between the gates 1, thereby increasing the breakdown voltage between the gates 1 and improving the reliability of the device.

[0047] Example 2

[0048] Another specific embodiment of the present invention discloses a DRAM including the gate sidewall 2 structure described above. The active area in the DRAM product should be a strip-shaped active area with staggered and tilted distribution. In a DRAM device, the transistor is typically a buried channel transistor, with the gate 1 buried in the substrate, thereby generating a channel in the active area within the substrate. Above the transistor, a bit line, storage node contacts, and a capacitor above can be included to form a complete DRAM product.

[0049] Example 3

[0050] Another specific embodiment of the present invention discloses a method for manufacturing a gate spacer 2. The structure of the gate spacer 2 is the same as that in Example 1. The manufacturing process is as follows:

[0051] First, the silicon wafer was cleaned with deionized water at 70°C for 20 minutes, then dried and placed in an oxidation furnace. The temperature in the oxidation furnace was raised to 900°C, and O2 was introduced at 2.5 slm for 30 minutes to prepare a silicon dioxide layer with a thickness of 30 angstroms.

[0052] Secondly, the silicon wafer prepared with the silicon dioxide oxide layer was placed in the chemical vapor deposition equipment, and a mixture of 20% silane and nitrogen was introduced into the reaction chamber. The temperature was raised to 575°C, and polysilicon was deposited at a pressure of 0.2 Torr. The deposition rate was 100 angstroms / minute, and the thickness of the polysilicon was 1500 angstroms.

[0053] Next, in the photolithography area, deep ultraviolet lithography is used to etch the fine structure of the polysilicon gate. An anti-reflective coating (ARC) is formed between the polysilicon and the photoresist, and the polysilicon is dry-etched. First, the polysilicon is pre-etched to remove the natural oxide, hard mask layer, and surface contaminants on the polysilicon surface. Then, the polysilicon is subjected to a main etch using CF4 as the etching gas with a polysilicon to silicon dioxide selectivity of 150:1. Next, an overetch is performed to remove the etching residue and remaining polysilicon, resulting in gate 1. After gate 1 is formed, gate 1 is polycrystalline oxidized and a layer of silicon dioxide is thermally grown on gate 1. Finally, the silicon wafer is shallow channel doping implanted.

[0054] Next, chemical vapor deposition (CVD) is used to deposit the gate sidewalls 2. A mixture of dichlorosilane (SiCl2H2) and ammonia (NH3) is introduced into an oxidation furnace at a pressure of 0.1 Torr and a temperature of 500°C. The gate sidewalls 2 are made of silicon nitride. Subsequently, dry etching is performed to etch the gate sidewalls 2, retaining the silicon nitride on the sidewalls and upper portion while removing the silicon nitride elsewhere. Next, chemical vapor deposition (CVD) is used to deposit a 2000 angstrom thick oxide insulating film 3 by introducing O2 at a pressure of 0.1 Torr and a temperature of 650°C.

[0055] Next, a first chemical mechanical planarization (CMP) process is performed on the oxide insulating film 3 on top of the gate sidewall 2 and the gate sidewall 2 on top of the gate 1. Specifically, the grinding head pressure is 25 kPa, the turntable speed is 60 rpm, the abrasive is Al2O3, the pH value of the polishing liquid is 10, and the polishing time is 3 minutes. The selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 is 1:1. The first CMP process is performed until the top surface of the gate 1 is reached. The silicon wafer is then cleaned and dried.

[0056] Finally, a second chemical mechanical planarization treatment was performed on the oxide insulating film 3 and gate sidewall 2. The grinding head pressure was 35 kPa, the turntable speed was 65 rpm, the abrasive was Mn2O3, the pH value of the polishing liquid was 3, and the polishing time was 5 minutes. The selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 was 1:1, and the polishing pad hardness was Shore D 15. The resulting gate sidewall 2 had a curved surface concave toward the gate 1, and the bottom width of the gate sidewall was 50 angstroms.

[0057] Example 4

[0058] Another specific embodiment of the present invention discloses a method for manufacturing a gate spacer 2. The structure of the gate spacer 2 is the same as that in Example 1. The manufacturing process is as follows:

[0059] First, the silicon wafer was cleaned with deionized water at 70°C for 20 minutes, then dried and placed in an oxidation furnace. The temperature in the oxidation furnace was raised to 1200°C, and O2 was introduced at 3 slm for 40 minutes to prepare a silicon dioxide layer with a thickness of 60 angstroms.

[0060] Secondly, the silicon wafer prepared with the silicon dioxide oxide layer was placed in the chemical vapor deposition equipment, and a mixture of 30% silane and nitrogen was introduced into the reaction chamber. The temperature was raised to 650°C, and polysilicon was deposited at a pressure of 0.5 torr. The deposition rate was 150 angstroms / minute, and the thickness of the polysilicon was 2000 angstroms.

[0061] Next, deep ultraviolet lithography is used in the photolithography area to create the fine structure of the polysilicon gate. An antireflective coating (ARC) is formed between the polysilicon and the photoresist. The polysilicon is dry-etched with a polysilicon to silicon dioxide selectivity of 150:1, forming gate 1. After gate 1 is formed, polycrystalline oxidation is performed, and a layer of silicon dioxide is thermally grown on top of gate 1. Finally, shallow channel doping is performed on the silicon wafer.

[0062] Next, chemical vapor deposition (CVD) is used to deposit the gate sidewalls 2. A mixture of dichlorosilane (SiCl2H2) and ammonia (NH3) is introduced into an oxidation furnace at a pressure of 0.2 Torr and a temperature of 550°C. The gate sidewalls 2 are made of silicon nitride. Subsequently, dry etching is used to etch the gate sidewalls 2, retaining the silicon nitride on the sidewalls and upper portion of the gate sidewalls 2 while removing the silicon nitride elsewhere. Next, chemical vapor deposition (CVD) is used to deposit a 3000 angstrom thick oxide insulating film 3 by introducing O2 at a pressure of 0.5 Torr and a temperature of 680°C.

[0063] Next, a first chemical mechanical planarization (CMP) process is performed on the oxide insulating film 3 on top of the gate sidewall 2 and the gate sidewall 2 on top of the gate 1. Specifically, the grinding head pressure is 25 kPa, the turntable speed is 60 rpm, the abrasive is ZrO2, the pH value of the polishing liquid is 10, and the polishing time is 2 minutes. The selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 is 1:1. The first CMP process is performed until the top surface of the gate 1 is reached. The silicon wafer is then cleaned and dried.

[0064] Finally, a second chemical mechanical planarization process was performed on the oxide insulating film 3 and gate sidewall 2. The grinding head pressure was 25 kPa, the turntable speed was 55 rpm, the abrasive was Mn2O3, the pH value of the polishing liquid was 3, and the polishing time was 5 minutes. The selectivity ratio of the gate sidewall 2 to the oxide insulating film 3 was 1:1, and the polishing pad hardness was Shore D 20. The resulting gate sidewall 2 had a curved surface concave toward the gate 1, and the bottom width of the gate sidewall was 200 angstroms.

[0065] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

Claims

1. A method for manufacturing a gate spacer structure, characterized in that: The gate spacer structure includes: a semiconductor substrate; a gate, located on the semiconductor substrate; A gate sidewall, located on a sidewall of the gate; Wherein, the outer side surface of the gate sidewall is a curved surface concave toward the gate sidewall; The manufacturing method comprises: providing a semiconductor substrate; forming a gate material layer on the substrate, and etching the gate material layer to form a gate of the transistor; forming a gate spacer material layer on the semiconductor substrate and the gate; forming an oxide insulating film on the gate spacer material layer; Performing a first chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall; the first chemical mechanical planarization treatment is a treatment of the oxide insulating film on the top of the gate sidewall and the gate sidewall on the top of the gate; A second chemical mechanical planarization process is performed on the oxide insulating film and the gate sidewall; the second chemical mechanical planarization process is performed on the gate sidewall and the oxide insulating film outside the gate sidewall.

2. The method for manufacturing a gate spacer structure according to claim 1, wherein: The first chemical mechanical planarization process needs to be polished to the top surface of the gate.

3. The method for manufacturing a gate spacer structure according to claim 1, wherein: The selectivity ratio of the gate sidewall to the oxide insulating film in the first chemical mechanical planarization process is 1:

1.

4. The method for manufacturing a gate spacer structure according to claim 1, wherein: The selectivity ratio of the gate sidewall to the oxide insulating film in the second chemical mechanical planarization process is 1:

1.

5. The method for manufacturing a gate spacer structure according to claim 1, wherein: During the second chemical mechanical planarization process, the hardness of the polishing pad is less than Shore D 30.

6. The method for manufacturing a gate spacer structure according to claim 1, wherein: The width of the gate sidewall increases gradually from top to bottom, and the width of the bottom of the gate sidewall is 50 to 200 angstroms.

Images