An etching method for a gate groove at the nanometer scale

Abstract

The present invention discloses an etching method for a gate groove at the nanometer scale, comprising the following steps: First, a first conductive metal layer, a photoresist layer, and a second conductive metal layer are sequentially formed on a semiconductor epitaxial wafer, then electron beam exposure is performed, then the second conductive metal layer is etched, then the photoresist layer is developed and fixed to expose the gate groove region, then the gate groove region is etched to form a gate groove, and after stripping the photoresist layer, the first conductive metal layer is etched, thereby forming a gate groove at the nanometer scale. By sputtering thin conductive metal layers at the bottom and top of the photoresist, the present invention suppresses the electron proximity effect and backscattering effect during the electron beam lithography process, and greatly improves the etching accuracy of the gate groove at the nanometer scale.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to an etching method for a gate groove at the hundred-nanometer level. Background Art

[0002] High electron mobility transistors with AlGaN / GaN and GaAs / AlGaAs heterojunction structures have characteristics such as high frequency, high speed, high voltage resistance, and high power, and are widely used in the radio frequency and microwave fields. However, with the further improvement of the requirements for device frequency characteristics, the gate length of the device gradually decreases. In the fabrication of high-frequency devices, in order to obtain higher frequency characteristics, the gate length generally needs to be controlled below 200 nm, which has exceeded the exposure size limit of traditional optical lithography process equipment.

[0003] Currently, the mainstream processes for etching gate grooves at the hundred-nanometer level at home and abroad include the following steps: first, spin-coat an electron beam photoresist on the epitaxial structure, then use electron beam exposure, develop to form a gate trench area, and then etch this area to form a gate groove. However, during the process of electron beam lithography, the electron beam will undergo forward scattering and backscattering in different substrates, causing the electron exposure trajectory to expand into adjacent areas. The backscattering expansion range of substrates with a smaller atomic number is larger, up to 5 μm - 10 μm at most, but the relative intensity is weaker. As the atomic number of the substrate increases, the backscattering range will shrink while the backscattering intensity will increase significantly. The backscattering effect is the main factor causing the exposure of adjacent areas to expand mutually, the adhesion of dense patterns, and the serious distortion of large-area patterns. Due to the different backscattering effects of different substrates, it is currently difficult to achieve the high-precision preparation of hundred-nanometer semiconductor gates.

[0004] Therefore, it is urgent to improve the lithography and etching processes of the gate groove, improve the preparation accuracy of the gate, and finally obtain a gate groove with high lithography and etching accuracy. Summary of the Invention

[0005] The purpose of the present invention is to provide an etching method for a gate groove at the hundred-nanometer level.

[0006] The technical solution adopted by the present invention is as follows:

[0007] An etching method for a gate groove at the hundred-nanometer level includes the following steps: first, sequentially form a first conductive metal layer, a photoresist layer, and a second conductive metal layer on a semiconductor epitaxial wafer, then perform electron beam exposure, then etch the second conductive metal layer, then develop and fix the photoresist layer to expose the gate groove area, then etch the gate groove area to form a gate groove, and then strip the photoresist layer and etch the first conductive metal layer to form a gate groove at the hundred-nanometer level.

[0008] Preferably, a method for etching a gate groove in the order of hundreds of nanometers includes the following steps:

[0009] 1) Clean and dry the semiconductor epitaxial wafer, and then form a first conductive metal layer on the semiconductor epitaxial wafer;

[0010] 2) Form a photoresist layer on the first conductive metal layer and perform a hardening treatment;

[0011] 3) Form a second conductive metal layer on the photoresist layer to obtain a semiconductor epitaxial wafer with a metal-photoresist-metal structure;

[0012] 4) Perform electron beam exposure on the semiconductor epitaxial wafer with the metal-photoresist-metal structure and perform post-exposure baking;

[0013] 5) Etch the second conductive metal layer;

[0014] 6) Develop and fix the photoresist layer to expose the gate groove area;

[0015] 7) Etch the gate groove area to form a gate groove;

[0016] 8) After stripping the photoresist layer, etch the first conductive metal layer to form a gate groove in the order of hundreds of nanometers.

[0017] Preferably, the composition of the first conductive metal layer includes at least one of Au, Ti, Cu, Al, Cr, Au, and Pd.

[0018] Preferably, the thickness of the first conductive metal layer ≤ 10 nm.

[0019] Preferably, the formation method of the first conductive metal layer is selected from one of sputtering, electroplating, and thermal evaporation.

[0020] Preferably, the photoresist in the photoresist layer is selected from one of PMMA photoresist, PMMA-MAA photoresist, ZEP520 photoresist, EBR-9 photoresist, HSQ photoresist, and AR-N 7520 photoresist.

[0021] Preferably, the formation method of the photoresist layer is spin coating.

[0022] Preferably, the composition of the second conductive metal layer includes at least one of Au, Ti, Cu, Al, Cr, Au, and Pd.

[0023] Preferably, the thickness of the second conductive metal layer ≤ 10 nm.

[0024] Preferably, the formation method of the second conductive metal layer is selected from one of sputtering, electroplating, and thermal evaporation.

[0025] Preferably, the developer used for development is selected from one of MIBK:IPA developer, xylene:p-dioxane developer, TMAH developer, and AR 300-47 developer.

[0026] Preferably, the etching method in step 5) is wet etching.

[0027] Preferably, the etching method in step 7) is plasma etching.

[0028] Preferably, the plasma etching is carried out in an F-based gas or a Cl-based gas.

[0029] Preferably, the etching method in step 8) is wet etching.

[0030] The beneficial effects of the present invention are as follows: By sputtering thin layers of conductive metal on the bottom and top of the photoresist respectively, the present invention suppresses the electron proximity effect and backscattering effect during the electron beam lithography process, and greatly improves the etching accuracy of the gate grooves at the nanometer level.

[0031] Specifically:

[0032] 1) By introducing upper / lower thin layers of conductive metal, the present invention effectively suppresses the electron proximity effect and backscattering effect, avoiding the mutual expansion of adjacent area exposures, the adhesion of dense patterns, and the serious distortion of large-area patterns.

[0033] 2) By using a wet etching liquid with a high selectivity to etch the thin layer of conductive metal, the present invention does not affect the etching resistance of the photoresist while etching the thin layer of conductive metal.

[0034] 3) The present invention is not affected by the substrate material of the semiconductor epitaxial wafer and is applicable to common substrates such as ordinary Si, high-resistance Si, SiC, and sapphire, and can achieve the effect of improving the lithography and etching accuracy. Description of the Drawings

[0035] Figure 1 It is a schematic structural diagram of a semiconductor epitaxial wafer with a metal-photoresist-metal structure in Example 1 (1 is the semiconductor epitaxial wafer, 2 is the first conductive metal Ti layer, 3 is the photoresist layer, and 4 is the second conductive metal Ti layer).

[0036] Figure 2 It is an SEM image of the 140-nm gate groove prepared on a sapphire substrate in Example 1.

[0037] Figure 3 It is an SEM image of the 180-nm gate groove prepared on a SiC substrate in Example 2.

[0038] Figure 4Schematic diagram of the structure of a T-gate AlGaN / GaN device on a high-resistance Si substrate prepared in Example 3 (1 is the high-resistance Si substrate, 2 is the GaN epitaxial structure on the high-resistance Si substrate, 3 is the source electrode, 4 is the drain electrode, 5 is the T-gate structure, and 6 is the passivation layer).

[0039] Figure 5 Small-signal characteristic diagram of the T-gate AlGaN / GaN HEMT device on the high-resistance Si substrate of Example 3.

[0040] Figure 6 SEM image of the 140-nm gate recess prepared on an Si substrate in the comparative example. Detailed implementation manners

[0041] The present invention will be further explained and described below in conjunction with specific embodiments.

[0042] Example 1:

[0043] An etching method for a gate recess in the nanometer scale, comprising the following steps:

[0044] 1) A SiN passivation layer with a thickness of 100 nm is grown on a sapphire substrate by plasma-enhanced chemical vapor deposition (PECVD) to obtain a semiconductor epitaxial wafer, which is then cleaned and dried. Then, a first conductive metal Ti layer with a thickness of 7 nm is formed on the SiN passivation layer by magnetron sputtering;

[0045] 2) A ZEP520 photoresist is spin-coated on the first conductive metal Ti layer to form a photoresist layer, and a hard-baking treatment is performed;

[0046] 3) A second conductive metal Ti layer with a thickness of 7 nm is formed on the photoresist layer by magnetron sputtering to obtain a semiconductor epitaxial wafer with a metal-photoresist-metal structure (the schematic diagram of the structure is as Figure 1 shown);

[0047] 4) Electron beam exposure is performed on the semiconductor epitaxial wafer with the metal-photoresist-metal structure, and post-exposure baking is carried out;

[0048] 5) The second conductive metal Ti layer is wet-etched with a BOE solution, and the etching time is 8 s;

[0049] 6) The photoresist layer is developed, fixed, and dried to expose the gate recess region, and the designed width of the gate trench region is 140 nm;

[0050] 7) Inductively coupled plasma etching (ICP) is performed on the gate recess region to form a gate recess. The etching reaction gas is SF6, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively;

[0051] 8) After stripping the photoresist layer, the first conductive metal Ti layer is wet-etched with BOE solution for 8 s to form a gate groove in the order of hundreds of nanometers.

[0052] Performance test:

[0053] The scanning electron microscope (SEM) image of the 140-nm gate groove prepared on the sapphire substrate in this embodiment is as Figure 2 shown.

[0054] It can be Figure 2 seen that the precision error of the 140-nm gate groove prepared on the sapphire substrate in this embodiment is only 0.7%, and the morphology is good.

[0055] Example 2:

[0056] An etching method for a gate groove in the order of hundreds of nanometers, comprising the following steps:

[0057] 1) A semiconductor epitaxial wafer is obtained by growing a 100-nm-thick SiN passivation layer on a SiC substrate by plasma-enhanced chemical vapor deposition (PECVD), followed by cleaning and drying. Then, a 7-nm-thick first conductive metal Ti layer is formed on the SiN passivation layer by magnetron sputtering;

[0058] 2) PMMA-A4 photoresist is spin-coated on the first conductive metal Ti layer to form a photoresist layer, and a hard-baking treatment is performed;

[0059] 3) A 7-nm-thick second conductive metal Ti layer is formed on the photoresist layer by magnetron sputtering to obtain a semiconductor epitaxial wafer with a metal-photoresist-metal structure;

[0060] 4) Electron beam exposure is performed on the semiconductor epitaxial wafer with a metal-photoresist-metal structure, and post-exposure baking is carried out;

[0061] 5) The second conductive metal Ti layer is wet-etched with BOE solution for 8 s;

[0062] 6) The photoresist layer is developed, fixed, and dried to expose the gate groove region, and the designed width of the gate groove region is 180 nm;

[0063] 7) Inductively coupled plasma etching (ICP) is performed on the gate groove region to form a gate groove. The etching reactive gas is SF6, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively;

[0064] 8) After stripping the photoresist layer, the first conductive metal Ti layer is wet-etched with BOE solution for 8 s to form a gate groove in the order of hundreds of nanometers.

[0065] Performance test:

[0066] The SEM image of the 180-nm gate groove prepared on the SiC substrate in this embodiment is as Figure 3 shown.

[0067] It can be Figure 3 seen that the precision error of the 180-nm gate groove prepared on the SiC substrate in this embodiment is only 2.0%, and the morphology is good.

[0068] Example 3:

[0069] A preparation method of a T-gate AlGaN / GaN HEMT device on a high-resistance Si substrate, which includes the following steps:

[0070] 1) Lithography and etching are carried out on the AlGaN / GaN HEMT epitaxial wafer grown on the high-resistance Si substrate. The etching method is inductively coupled plasma etching (ICP). The etching reaction gas is a mixed gas of Cl2 and BCl3, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively. Marking points are made.

[0071] 2) Align the marking points in step 1) for lithography, and then use etching for mesa isolation of the epitaxial wafer. The etching method is inductively coupled plasma etching (ICP). The etching reaction gas is a mixed gas of Cl2 and BCl3, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively.

[0072] 3) The source metal electrode 1 and the drain metal electrode 2 are formed by lithography, evaporation, stripping and annealing. The annealing atmosphere is N2, the annealing temperature is 850 °C, the holding time is 30 s, the heating rate is 15 °C / s, and both the source metal electrode 1 and the drain metal electrode 2 are alloys formed by Ti, Al, Ni, and Au.

[0073] 4) A SiN passivation layer with a thickness of 100 nm is grown by plasma-enhanced chemical vapor deposition (PECVD).

[0074] 5) A first conductive metal Ti layer with a thickness of 6 nm is deposited on the SiN passivation layer by magnetron sputtering.

[0075] 6) Spin-coat ZEP520 photoresist on the first conductive metal Ti layer to form a photoresist layer, and perform hardening treatment.

[0076] 7) A second conductive metal Ti layer with a thickness of 6 nm is formed on the photoresist layer by magnetron sputtering to obtain a semiconductor epitaxial wafer with a metal-photoresist-metal structure;

[0077] 8) Electron beam exposure is performed on the semiconductor epitaxial wafer with a metal-photoresist-metal structure, and post-exposure baking is carried out;

[0078] 9) The second conductive metal Ti layer is wet-etched using a BOE solution, and the etching time is 10 s;

[0079] 10) The photoresist layer is developed, fixed, and dried to expose the gate recess area, and the designed width of the gate trench area is 100 nm;

[0080] 11) Inductively coupled plasma etching (ICP) is performed on the gate recess area to form a gate recess. The etching reactive gas is SF6, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively;

[0081] 12) After stripping the photoresist layer, the first conductive metal Ti layer is wet-etched using a BOE solution, and the etching time is 8 s to form a gate recess in the order of hundreds of nanometers;

[0082] 13) The gate root area is formed by photolithography and etching of the passivation layer;

[0083] 14) The gate cap area and the gate metal electrode are formed by ordinary electron beam lithography, evaporation, and stripping. The gate metal electrode is composed of two metals, Ni and Au;

[0084] 15) The epitaxial wafer is taken out, and the photoresist on the epitaxial wafer is removed with acetone;

[0085] 16) Photolithography and evaporation are performed to form the gate-source-drain metal electrode PAD. The gate-source-drain metal electrode is composed of two metals, Ni and Au, and thus the T-gate AlGaN / GaN HEMT device on a high-resistance Si substrate is obtained (the structural schematic diagram is as Figure 4 shown).

[0086] Performance test:

[0087] The small-signal characteristic diagram of the T-gate AlGaN / GaN HEMT device on a high-resistance Si substrate in this embodiment is as Figure 5 shown.

[0088] It can be seen from Figure 5 that the cut-off frequency f T and the maximum oscillation frequency f max of the device are 93 GHz and 107 GHz respectively, showing excellent radio frequency characteristics.

[0089] Comparative example:

[0090] An etching method for a gate groove at the nanometer scale includes the following steps:

[0091] 1) Using plasma enhanced chemical vapor deposition (PECVD), grow a 100-nm-thick SiN passivation layer on a SiC substrate to obtain a semiconductor epitaxial wafer, and then perform cleaning and drying;

[0092] 2) Spin-coat ZEP520 photoresist on the SiN passivation layer to form a photoresist layer, and perform a hard-baking process to obtain a semiconductor epitaxial wafer with photoresist;

[0093] 3) Perform electron beam exposure on the semiconductor epitaxial wafer with photoresist, and perform post-exposure baking;

[0094] 4) Develop, fix, and dry the photoresist layer to expose the gate groove area, and the designed width of the gate groove area is 140 nm;

[0095] 5) Perform inductively coupled plasma etching (ICP) on the gate groove area to form a gate groove. The etching reaction gas is SF6, the pressure is 5 mTorr, the upper radio frequency power is 300 W, the lower radio frequency power is 50 W, and the etching times are 150 s and 80 s respectively, so as to form a gate groove at the nanometer scale.

[0096] Performance test:

[0097] The SEM image of the 140-nm gate groove prepared on the SiC substrate in this comparative example is as Figure 6 shown.

[0098] It can be Figure 6 seen that: the precision error of the 140-nm gate groove prepared on the SiC substrate in this comparative example is as high as 14.9%, there are protrusions in the groove, and the etching is incomplete.

[0099] The above embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A method for etching a gate groove at the nanometer scale, characterized in that, It includes the following steps: 1) Clean and dry the semiconductor epitaxial wafer, and then form a first conductive metal layer on the semiconductor epitaxial wafer; 2) Form a photoresist layer on the first conductive metal layer and perform a hardening treatment; 3) Form a second conductive metal layer on the photoresist layer to obtain a semiconductor epitaxial wafer with a metal-photoresist-metal structure; 4) Perform electron beam exposure on the semiconductor epitaxial wafer with the metal-photoresist-metal structure and perform post-exposure baking; 5) Etch the second conductive metal layer; 6) Develop and fix the photoresist layer to expose the gate groove area; 7) Etch the gate groove area to form a gate groove; 8) After stripping the photoresist layer, etch the first conductive metal layer to form a gate groove with a size of hundreds of nanometers; The etching method in step 5) is wet etching; The etching method in step 7) is plasma etching; The etching method in step 8) is wet etching.

2. The etching method of the nanometer-level gate groove according to claim 1, wherein: The composition of the first conductive metal layer includes at least one of Au, Ti, Cu, Al, Cr, Au, Pd; the composition of the second conductive metal layer includes at least one of Au, Ti, Cu, Al, Cr, Au, Pd.

3. The etching method of the gate groove at the nanometer scale according to claim 1, wherein: The thickness of the first conductive metal layer ≤ 10 nm; the thickness of the second conductive metal layer ≤ 10 nm.

4. The etching method of the nanometer-level gate groove according to claim 1, wherein: The formation method of the first conductive metal layer is selected from one of sputtering, electroplating, and thermal evaporation; the formation method of the second conductive metal layer is selected from one of sputtering, electroplating, and thermal evaporation.

5. The etching method of the gate groove at the nanometer level according to claim 1, characterized in that: The photoresist in the photoresist layer is selected from one of PMMA photoresist, PMMA-MAA photoresist, ZEP520 photoresist, EBR-9 photoresist, HSQ photoresist, AR-N7520 photoresist; the developer used for development is selected from one of MIBK:IPA developer, xylene:p-dioxane developer, TMAH developer, AR 300-47 developer.

6. The etching method of the nanometer-level gate groove according to claim 1, wherein: The formation method of the photoresist layer is spin coating.

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