switching element

Abstract

A switching element includes a semiconductor substrate provided with a trench, a gate insulating film, and a gate electrode. The semiconductor substrate has a source region, a body region, a drift region, a first electric field relaxation region, and a connection region. The drift region is in contact with the gate insulating film on a side surface of the trench on a lower side of the body region and a bottom surface of the trench. The first electric field relaxation region is disposed inside the drift region, is disposed in a lower portion of the trench at a distance from the bottom surface of the trench, and extends along the bottom surface of the trench. The connection region protrudes downward from the body region in a manner reaching the first electric field relaxation region, and extends longer in a direction intersecting the trench when viewed from above. When a dielectric constant of the connection region is ε (F / cm), a critical electric field strength of the connection region is Ec (V / cm), elementary charge is e (C), and a surface density of p-type impurities when the connection region in the lower portion of the trench is viewed from above is Q (cm ‑2 ), Q > ε·Ec / e is satisfied.

Description

TECHNICAL FIELD

[0001] The technology disclosed in this specification relates to a switching element.

[0002] The switching element disclosed in Japanese Patent Publication No. 2009-158681 has a semiconductor substrate and a gate electrode. A trench is provided on an upper surface of the semiconductor substrate. The gate electrode is disposed in the trench. The gate electrode is insulated from the semiconductor substrate by a gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, and an electric field relaxation region (bottom region). The source region is an n-type region that interfaces with the gate insulating film on a side surface of the trench. The body region is a p-type region that interfaces with the gate insulating film on a side surface of the trench on a lower side of the source region. The drift region is an n-type region that is disposed on a lower side of the body region and that interfaces with the gate insulating film on a side surface of the trench on the lower side of the body region and on a bottom surface of the trench. The electric field relaxation region is a p-type region that is disposed inside the drift region and that is disposed in a lower portion of the trench at a separation from the bottom surface of the trench. SUMMARY

[0003] Problem to be Solved by the Invention

[0004] In the switching element of Patent Literature 1, in the case where avalanche breakdown occurs, a part of the holes generated in the vicinity of the electric field relaxation region is injected into the gate insulating film in the process of flowing from the drift region to the body region. Thereby, problems such as a change in characteristics of the gate insulating film and a variation in gate threshold value occur. In this specification, a technology capable of suppressing a change in characteristics of the gate insulating film in the case where avalanche breakdown occurs is proposed.

[0005] Solution to Problem

[0006] The switching element disclosed in the present specification includes a semiconductor substrate provided with a trench on an upper surface, a gate insulating film covering an inner surface of the trench, and a gate electrode disposed in the trench and insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has a source region, a body region, a drift region, a first electric field relaxation region, and a connection region. The source region is an n-type region where a side surface of the trench and the gate insulating film meet. The body region is a p-type region where a lower side of the source region and the gate insulating film meet. The drift region is an n-type region disposed on a lower side of the body region, where a side surface of the lower side of the body region and the gate insulating film meet, and where a bottom surface of the trench and the gate insulating film meet. The first electric field relaxation region is a p-type region disposed inside the drift region, disposed in a lower portion of the trench at a distance from the bottom surface of the trench, and extending along the bottom surface of the trench. The connection region is a p-type region protruding downward from the body region in a manner reaching the first electric field relaxation region, and extending longer in a direction intersecting the trench when viewed from above. When a dielectric constant of the connection region is ε (F / cm), a critical electric field strength of the connection region is Ec (V / cm), elementary charge is e (C), and a surface density of p-type impurities when the connection region in the lower portion of the trench is viewed from above is Q (cm -2 ), Q > ε·Ec / e is satisfied.

[0007] In the switching element, an avalanche breakdown occurs in a portion where the connection region and the first electric field relaxation region are connected. Holes generated due to the avalanche breakdown flow to the body region via the connection region. In the switching element, the surface density Q satisfies the above equation, and thus a depletion layer spreading in the connection region does not reach the lower end of the trench. That is, a non-depleted region (a region where a depletion layer does not spread) remains in the connection region around the lower end of the trench. The non-depleted region suppresses injection of holes (holes generated due to the avalanche breakdown) flowing in the connection region into the gate insulating film. Thus, in the above-described switching element, even in a case where an avalanche breakdown occurs, a change in characteristics of the gate insulating film can be suppressed. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a cross-sectional view of the MOSFET of Example 1.

[0009] Figure 2 is a cross-sectional view of Figure 1 on a plane II.

[0010] Figure 3 is a cross-sectional view of Figure 1 on a plane III.

[0011] Figure 4 is a sectional view on plane IV of Figure 1

[0012] Figure 5 is a sectional view on plane V of Figure 1

[0013] is a sectional view of the MOSFET of Example 2 corresponding to Figure 6 Figure 3

[0014] Figure 7 is a sectional view of the MOSFET of Example 2 corresponding to Figure 4

[0015] Figure 8 is a plan view of the MOSFET of Example 2. DETAILED DESCRIPTION

[0016] The following lists technical elements disclosed in the present specification. Furthermore, each of the following technical elements is useful independently.

[0017] In one example structure disclosed in the present specification, the semiconductor substrate can be composed of silicon carbide, and satisfy Q > 1.49 x 10 13 .

[0018] In one example structure disclosed in the present specification, a plurality of the trenches can be provided on the upper surface of the semiconductor substrate, a plurality of the connection regions can be provided, a plurality of the first electric field relaxation regions can be provided, and a plurality of second electric field relaxation regions of p-type can be further provided, each of the first electric field relaxation regions can be arranged at a lower portion of the corresponding trench, each of the connection regions can extend in a manner of crossing the plurality of trenches, and each of the second electric field relaxation regions can be arranged at a lower portion of the corresponding connection region, connected to the corresponding connection region, and extend in a manner of crossing the plurality of first electric field relaxation regions.

[0019] In such a structure, concentration of an electric field in the vicinity of a lower end of a connection region in a state where a switching element is off is suppressed. Also, a first electric field relaxation region and a second electric field relaxation region are arranged in a lattice shape when viewed from above. Therefore, when the switching element is off, a depletion layer rapidly spreads from the first electric field relaxation region and the second electric field relaxation region to a drift region surrounded by the first electric field relaxation region and the second electric field relaxation region. In this way, the depletion layer rapidly spreads within the drift region, and thus a drain-source capacitance of the switching element can be reduced.

[0020] In one example structure disclosed in the present specification, a p-type impurity concentration of the connection region can be higher than a p-type impurity concentration of the first electric field relaxation region.

[0021] ​​​​In this structure, the electric field is more likely to concentrate near the portion where the connecting region connects to the first electric field mitigation region. Therefore, avalanche breakdown can occur near the portion where the connecting region connects to the first electric field mitigation region.

[0022] (Example 1)

[0023] Figures 1-5 The MOSFET (metal-oxide-semiconductor field-effect transistor) 10 is shown as an embodiment. The MOSFET 10 has a semiconductor substrate 12. Hereinafter, a direction parallel to the upper surface 12a of the semiconductor substrate 12 will be referred to as the x-direction, a direction parallel to the upper surface 12a and perpendicular to the x-direction will be referred to as the y-direction, and the thickness direction of the semiconductor substrate 12 will be referred to as the z-direction. Figures 2-5 As shown, electrodes, insulating films, etc., are disposed on the upper surface 12a of the semiconductor substrate 12. Furthermore, in Figure 1 For illustrative purposes, the diagram of the structure on the upper surface 12a of the semiconductor substrate 12 is omitted.

[0024] The semiconductor substrate 12 is made of silicon carbide (SiC). Multiple trenches 22 are formed on the upper surface 12a of the semiconductor substrate 12. For example... Figure 1 As shown, a plurality of trenches 22 extend parallel to each other on the upper surface 12a. The plurality of trenches 22 extend relatively long in a straight line along the y-direction. The plurality of trenches 22 are arranged at intervals in the x-direction. A gate insulating film 24 and a gate electrode 26 are disposed inside each trench 22.

[0025] The gate insulating film 24 covers the inner surface of the trench 22. The gate insulating film 24 has a side insulating film 24a covering the sides of the trench 22 and a bottom insulating film 24b covering the bottom surface of the trench 22. The gate insulating film 24 is made of silicon oxide, for example.

[0026] Gate electrode 26 is disposed within trench 22. Gate electrode 26 is insulated from semiconductor substrate 12 by gate insulating film 24. Figure 2 , Figure 3 as well as Figure 5 As shown, the upper surface of the gate electrode 26 is covered by an interlayer insulating film 28.

[0027] A source electrode 70 is disposed on the upper surface 12a of the semiconductor substrate 12. The source electrode 70 covers the upper surface 12a and the interlayer insulating film 28. The portion of the source electrode 70 without the interlayer insulating film 28 is in contact with the upper surface 12a of the semiconductor substrate 12. The source electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28. A drain electrode 72 is disposed on the lower surface 12b of the semiconductor substrate 12. The drain electrode 72 is in contact with the lower surface 12b of the semiconductor substrate 12.

[0028] like Figure 1 As shown, multiple source regions 30, body regions 32, drift regions 34, drain regions 35, multiple first electric field relaxation regions 36, and multiple connection regions 38 are disposed inside the semiconductor substrate 12.

[0029] Each source pole region 30 is an n-type region. For example... Figure 1 and Figure 2 As shown, multiple source regions 30 are arranged in each semiconductor region (hereinafter referred to as the inter-trench region) sandwiched by adjacent trenches 22. Figure 1 and Figure 4 As shown, in each trench region, multiple source regions 30 are arranged at intervals along the y-direction. Figure 2 and Figure 4 As shown, each source region 30 is disposed on the upper surface 12a facing the semiconductor substrate 12 and makes ohmic contact with the source electrode 70. Each source region 30 is connected to two trenches 22 located on both sides of the trench region. Each source region 30 is connected to the side insulating film 24a at the upper end of the trench 22.

[0030] Body region 32 is a p-type region. Body region 32 has multiple contact regions 32a and main body regions 32b.

[0031] Each contact region 32a is a p-type region with a high concentration of p-type impurities. For example... Figure 1 and Figure 3 As shown, each contact region 32a is disposed in the inter-trench region. Each contact region 32a is disposed in the area facing the upper surface 12a of the semiconductor substrate 12. Multiple contact regions 32a are disposed in each inter-trench region. Figure 1 and Figure 4 As shown, in each trench region, the source region 30 and the contact region 32a are alternately arranged in the y-direction. Therefore, the contact region 32a is positioned between the two source regions 30. Each contact region 32a makes ohmic contact with the source electrode 70.

[0032] The main region 32b is a p-type region where the concentration of p-type impurities is lower than that of each contact region 32a. For example... Figures 1-4As shown, the body region 32b is disposed on the lower side of each source region 30 and each contact region 32a. The body region 32b is in contact with each source region 30 and each contact region 32a from the lower side. The body region 32b is distributed over the entire region on the lower side of each source region 30 and each contact region 32a. As Figure 2 and Figure 3 As shown, the body region 32b is in contact with the side surface insulating film 24a on the lower side of the source region 30. The lower end of the body region 32b is disposed at a position higher than the lower end of the gate electrode 26.

[0033] As shown, Figure 3 and Figure 4 As shown, a plurality of connection regions 38 extending downward from the body region 32b are provided in the lower portion of the contact region 32a. Each connection region 38 extends to a position lower than the lower end of the trench 22. As Figure 2 and Figure 4 As shown, no connection region 38 is provided in the lower portion of the source region 30. As Figure 3 As shown, the connection region 38 extends in the direction (x direction) intersecting the trench 22. As Figure 1 and Figure 4 As shown, similarly to the contact region 32a, a plurality of connection regions 38 are disposed at intervals in the y direction. The p-type impurity concentration of each connection region 38 is higher than the p-type impurity concentration of the body region 32b.

[0034] The drift region 34 is an n-type region having a low n-type impurity concentration. As Figures 1-4 As shown, the drift region 34 is disposed on the lower side of the body region 32 (more specifically, the body region 32b) and the connection region 38. The drift region 34 is in contact with the body region 32b and the connection region 38 from the lower side. In addition, as Figure 4 As shown, the drift region 34 is also distributed in a region sandwiched by 2 connection regions 38 adjacent in the y direction. That is, in Figure 4 As shown in the cross section, the drift region 34 is in contact with the connection region 38 from the side. The drift region 34 is separated from each source region 30 by the body region 32b. As Figure 1 and Figure 2 As shown, the drift region 34 is distributed from each inter-trench region to a region lower than each trench 22. As Figure 2 As shown, the drift region 34 is in contact with the side surface insulating film 24a on the lower side of the body region 32b. In addition, the drift region 34 is in contact with the bottom surface insulating film 24b in a range where no connection region 38 is present. In a position lower than the lower end of the connection region 38, the drift region 34 is distributed over substantially the entire region of the semiconductor substrate 12 in the x direction and the y direction.

[0035] The drain region 35 is an n-type region having a higher n-type impurity concentration than the drift region 34. As Figures 1-5As shown, the drain region 35 is disposed on the lower side of the drift region 34. The drain region 35 is in contact with the drift region 34 from the lower side. The drain region 35 is provided in a range facing the lower surface 12b of the semiconductor substrate 12, and is in ohmic contact with the drain electrode 72.

[0036] Each first electric field relaxation region 36 is a p-type region. The p-type impurity concentration of each first electric field relaxation region 36 is lower than the p-type impurity concentration of the connection region 38. Each first electric field relaxation region 36 is disposed inside the drift region 34. As shown, Figures 1-3 As shown, each first electric field relaxation region 36 is disposed in the lower portion of the trench 22 at a distance from the bottom surface of the corresponding trench 22. As shown, Figure 1 and Figure 5 As shown, each first electric field relaxation region 36 extends longer in the y direction along the bottom surface of the corresponding trench 22. As shown, Figure 2 and Figure 5 As shown, in a range where the connection region 38 is not present, the periphery of the first electric field relaxation region 36 is surrounded by the drift region 34. Thus, the drift region 34 is disposed at a distance between the bottom surface of the trench 22 and the first electric field relaxation region 36. As shown, Figure 2 As shown in the cross section, the first electric field relaxation region 36 is in contact with the drift region 34 on its upper surface, side surface, and lower surface. As shown, Figure 3 As shown, in the lower portion of the connection region 38, the first electric field relaxation region 36 is connected to the lower end of the connection region 38. That is, each connection region 38 protrudes downward from the body region 32b in a manner reaching each first electric field relaxation region 36. The lower end of each first electric field relaxation region 36 is disposed at a position lower than the lower end of each connection region 38. As described above, the upper end of the connection region 38 is connected to the body region 32b. Thus, the first electric field relaxation region 36 is connected to the body region 32b via the connection region 38. Therefore, the first electric field relaxation region 36 is connected to the source electrode 70 via the connection region 38, the body region 32b, and the contact region 32a. Thus, the potential of the first electric field relaxation region 36 is substantially equal to the potential of the source electrode 70.

[0037] The MOSFET 10 of the present embodiment is configured to satisfy the relationship Q > ε · Ec / e. Here, the symbol ε denotes the dielectric constant (F / cm) of the connection region 38. The symbol Ec denotes the critical electric field strength (V / cm) of the connection region 38. The symbol e denotes the elementary charge (C). The symbol Q denotes the surface density Q (cm -2 ) of the p-type impurities when viewed from above the connection region 38 located in the lower portion of the trench 22 (i.e., the connection region 38 located between the first electric field relaxation region 36 and the bottom surface of the trench 22). The surface density Q is equal to the value obtained by integrating the p-type impurity concentration (cm -3 ) of the connection region 38 located in the lower portion of the trench 22 in the z direction. In the present embodiment, the semiconductor substrate 12 is composed of silicon carbide, and thus ε = 8.55 x 10-13 (F / cm), Ec = 2.8 x 10 6 (V / cm). In addition, e = 1.6 x 10 -19 (C). Thus, the area density Q of the connection region 38 is adjusted in a manner so as to satisfy Q > 1.49 x 10 13

[0038] In use of the MOSFET 10, the drain electrode 72 is applied with a higher potential than the source electrode 70. When a voltage above a gate threshold is applied to the gate electrode 26, a channel is formed in the body region 32b in the range where the gate insulating film 24 is in contact, and the switching element 10 is turned on. When the voltage applied to the gate electrode 26 is lowered to be less than the gate threshold, the channel disappears, and the MOSFET 10 is turned off.

[0039] In a state where the MOSFET 10 is turned off, the potential of the drain electrode 72 is much higher than the potential of the source electrode 70. In this state, the drift region 34 has a potential close to the potential of the drain electrode 72. In addition, as described above, the first electric field relaxation region 36 has a potential substantially equal to that of the source electrode 70. Therefore, a pn junction at the interface of the drift region 34 and the first electric field relaxation region 36 is applied with a high reverse voltage. Thus, a depletion layer extends widely from the first electric field relaxation region 36 to the drift region 34. Thereby, the withstand voltage of the MOSFET 10 is secured.

[0040] When the MOSFET 10 is turned off, the drift region 34 is depleted, and a depletion layer 80 (hatched area) also extends within the p-type region (i.e., the first electric field relaxation region 36, the connection region 38, and the body region 32). In a range where the connection region 38 is not provided, as shown in FIG. 6, the depletion layer 80 extends over substantially the entire region of the first electric field relaxation region 36, and the depletion layer 80 extends from the drift region 34 to a portion of the body region 32b. As shown in FIG. 7, the depletion layer 80 extends along the interface of the p-type region (the connection region 38 and the body region 32b) and the drift region 34 to the inside of the p-type region. Figure 2 Figure 4

[0041] In the MOSFET 10 of the present embodiment, the p-type impurity concentration of the connection region 38 is higher than the p-type impurity concentration of the first electric field relaxation region 36. Therefore, the connection region 38 is less likely to be depleted than the first electric field relaxation region 36. In addition, the p-type impurity concentration of the connection region 38 is high, and thus the first electric field relaxation region 36 in the range adjacent to the connection region 38 is less likely to be depleted than the first electric field relaxation region 36 in other ranges. Thus, in the range where both the first electric field relaxation region 36 and the connection region 38 are provided, as shown in FIG. 8, the depletion layer 80 extends from the drift region 34 to the inside of the p-type region (the connection region 38 and the body region 32b). Figure 3 Figure 5 ​​​​As shown, the depletion layer 80 is curved. That is, a non-depleted region remains in the first electric field mitigation region 36 located in the lower part of the connection region 38. As a result, in the lower part of the connection region 38, the equipotential lines are curved, and the spacing between the equipotential lines becomes narrower. Thus, in the MOSFET 10 of this embodiment, the electric field is concentrated near the portion where the connection region 38 is connected to the first electric field mitigation region 36. Therefore, avalanche breakdown is prone to occur near the portion where the connection region 38 is connected to the first electric field mitigation region 36. Holes generated due to avalanche breakdown flow to the source electrode 70 via the connection region 38 and the body region 32. Here, if the areal density Q of the connection region 38 satisfies the above-described relationship, the depletion layer 80 extending in the connection region 38 will not reach the lower end of the trench 22. That is, even if an electric field of critical electric field strength is applied to the connection region 38, the depletion layer 80 will not reach the lower end of the trench 22. Therefore, a non-depletion region remains in the connection region 38 around the lower end of trench 22. In the non-depletion region, the hole movement speed is slower compared to the depletion region. Therefore, holes flowing in the connection region 38 (holes generated near the connection region 38 due to avalanche breakdown) suppressed by the non-depletion region are injected into the gate insulating film 24, and most of the holes flow to the source electrode 70. Thus, in this MOSFET 10, even in the event of avalanche breakdown, changes in the characteristics of the gate insulating film 24 can be suppressed.

[0042] (Example 2)

[0043] Figures 6-8 This refers to MOSFET 100 in Example 2. Figure 6 This indicates the corresponding to Example 1. Figure 3 The cross section, Figure 7 This indicates the corresponding to Example 1. Figure 4 The cross-section. Additionally... Figure 8 This diagram shows a top view of the semiconductor substrate 12. Hereinafter, the same reference numerals are used for the same structural elements as in Embodiment 1, and their descriptions are omitted. In the MOSFET 10 of Embodiment 2, based on the structure of Embodiment 1, a plurality of second electric field mitigation regions 37 are provided inside the semiconductor substrate 12. Furthermore, in… Figure 8 In the diagram, the first electric field easing region 36 and the second electric field easing region 37 are represented by shaded areas.

[0044] like Figure 7 As shown, each second electric field mitigation region 37 is disposed at the lower part of the corresponding connection region 38. Each second electric field mitigation region 37 is connected to the corresponding connection region 38. The upper end of each second electric field mitigation region 37 is connected to the lower end of the corresponding connection region 38. Figure 6 As shown, each second electric field mitigation region 37 is positioned at approximately the same depth as each first electric field mitigation region 36. Figure 6 and Figure 8As shown, each second electric field relaxation region 37 extends in the x direction along the lower end of the corresponding connection region 38 in a manner that intersects the plurality of first electric field relaxation regions 36. That is, each second electric field relaxation region 37 connects the plurality of first electric field relaxation regions 36 to each other. That is, as shown in FIG. 2, the plurality of first electric field relaxation regions 36 and the plurality of second electric field relaxation regions 37 are arranged in a lattice shape in plan view. Figure 8 As shown, each first electric field relaxation region 36 and each second electric field relaxation region 37 are configured to be in a lattice shape in plan view. Each second electric field relaxation region 37 has substantially the same p-type impurity concentration as each first electric field relaxation region 36.

[0045] In the present embodiment, the second electric field relaxation region 37 having a lower p-type impurity concentration than the connection region 38 is arranged in the lower portion of the connection region 38. Therefore, in a state in which the MOSFET 100 is off, the second electric field relaxation region 37 is depleted, and the electric field applied to the connection region 38 is relaxed. Also, the first electric field relaxation region 36 and the second electric field relaxation region 37 are configured to be in a lattice shape in plan view. Therefore, the depletion layer rapidly spreads from the first electric field relaxation region 36 and the second electric field relaxation region 37 to the drift region 34 surrounded by the first electric field relaxation region 36 and the second electric field relaxation region 37, and the drift region 34 of the inter-trench region located in the upper portion thereof. In this way, the depletion layer rapidly spreads within the drift region 34, and thus the capacitance between the drain and the source of the MOSFET 100 is reduced. As a result, the output capacitance of the MOSFET 100 is reduced, and the loss generated in the MOSFET 100 can be reduced. For example, in a case in which the MOSFET 100 is caused to perform diode action, the recovery loss can be reduced.

[0046] In each of the above embodiments, the connection region 38 is arranged in the lower portion of the contact region 32a. However, the connection region 38 can also be arranged in the lower portion of the source region 30, for example, instead of being arranged in the lower portion of the contact region 32a.

[0047] In each of the above embodiments, the semiconductor substrate 12 is composed of silicon carbide. However, the semiconductor substrate 12 can also be composed of other semiconductor materials such as silicon (Si), gallium nitride (GaN), or the like. In this case, the planar density Q is appropriately set based on the dielectric constant and the critical electric field strength of the material employed.

[0048] The embodiments have been described in detail above, but these are merely examples and do not limit the claims. Various modifications, changes, and alterations to the specific examples described above are included in the technology recited in the claims. The technical elements described in the specification or drawings singly or through various combinations exert technical usefulness, and are not limited to the combinations recited in the claims at the time of filing. In addition, the technology exemplified in the specification or drawings simultaneously achieves multiple objects, and achieving one of the objects itself has technical usefulness.

Claims

1. A switching element, characterized in that, have: A semiconductor substrate with trenches formed on its upper surface; A gate insulating film covering the inner surface of the trench; and The gate electrode is disposed within the trench and is insulated from the semiconductor substrate by the gate insulating film. The semiconductor substrate has: The n-type source region is in contact with the gate insulating film on the side of the trench; The p-type body region is in contact with the gate insulating film on the side below the source region; An n-type drift region is disposed on the lower side of the body region, the side surface of the lower side of the body region is in contact with the gate insulating film, and the bottom surface of the trench is in contact with the gate insulating film. A p-type first electric field mitigation region is disposed inside the drift region, spaced apart from the bottom surface of the trench, and extends along the bottom surface of the trench. as well as The p-shaped connection region protrudes downward from the body region in a manner that reaches the first electric field mitigation region, and extends in the direction intersecting the groove when viewed from above. Let the dielectric constant of the connection region be ε (F / cm), the critical electric field strength of the connection region be Ec (V / cm), the elementary charge be e (C), and the areal density of the p-type impurities in the connection region located at the bottom of the trench when viewed from above be Q (cm). -2 When ), Q > ε·Ec / e, The p-type impurity concentration in the connection region is higher than that in the first electric field mitigation region. The switching element further includes a source electrode disposed on the upper surface of the semiconductor substrate. The body region has: The contact area, which makes ohmic contact with the source electrode; and The main body region has a lower p-type impurity concentration than the contact region. This main body region is connected to the source region and the contact region from below, and is also connected to the gate insulating film from below the source region. The connecting area protrudes downward from the main body area. The concentration of p-type impurities in the connection region is higher than that in the main body region.

2. The switching element according to claim 1, characterized in that, The semiconductor substrate is made of silicon carbide. Satisfying Q>1.49×10 13 .

3. The switching element according to claim 1 or 2, characterized in that, A plurality of trenches are provided on the upper surface of the semiconductor substrate. Multiple connection areas are provided. Multiple first electric field mitigation zones are provided. It also has multiple p-type second electric field mitigation regions. Each of the first electric field mitigation zones is disposed at the lower part of the corresponding trench. Each of the aforementioned connection areas extends in a manner that intersects with the plurality of trenches. Each of the second electric field mitigation regions is disposed at the lower part of the corresponding connection region, connected to the corresponding connection region, and extends in a manner that intersects with the plurality of first electric field mitigation regions.

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