Silicon photonic device layout method, apparatus, and silicon photonic chip

Abstract

A silicon photonic device layout method, apparatus and silicon photonic chip are provided. The method includes obtaining a netlist for information describing a silicon photonic device to be laid out. The information includes a kind of the silicon photonic device and a connection relationship between the silicon photonic devices. The method further includes parameterizing the netlist into at least one graph structure, each graph structure including a plurality of nodes. The method further includes determining an adjacency pattern of each node of the plurality of nodes in each graph structure, the adjacency pattern including a connection type to which the node belongs and associated nodes related to the connection type. The method further includes determining a layout of the silicon photonic device based on the adjacency pattern.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of photonics, in particular to the field of silicon photonic devices, and more particularly to a silicon photonic device layout method, apparatus, computer device, computer readable storage medium, computer program product, and a silicon photonic chip. BACKGROUND

[0002] In recent years, with the rapid development of silicon photonic technology, higher requirements are put forward for the design of silicon photonic devices and even silicon photonic chips, so as to meet the growing technical and industrial needs. Similar to the layout of traditional integrated circuits (IC), silicon photonic devices also involve corresponding layout methods. However, the layout method specially for silicon photonic devices is still in the exploratory stage, and is still one of the hot and difficult problems in research. SUMMARY

[0003] The present disclosure provides a silicon photonic device layout method, apparatus, computer device, computer readable storage medium, computer program product, and a silicon photonic chip.

[0004] According to an aspect of the present disclosure, a silicon photonic device layout method is provided. The method includes obtaining a netlist for describing information of a silicon photonic device to be laid out, the information including a type of the silicon photonic device and a connection relationship between the silicon photonic devices. The method further includes parameterizing the netlist into at least one graph structure, each graph structure including a plurality of nodes. The method further includes determining an adjacency pattern of each node of the plurality of nodes in each graph structure, the adjacency pattern including a connection type to which the node belongs and associated nodes related to the connection type. The method further includes determining a layout of the silicon photonic device based on the adjacency pattern.

[0005] According to another aspect of the present disclosure, a silicon photonic device layout apparatus is provided. The apparatus includes a netlist obtaining module configured to obtain a netlist for describing information of a silicon photonic device to be laid out, the information including a type of the silicon photonic device and a connection relationship between the silicon photonic devices. The apparatus further includes a graph generating module configured to parameterize the netlist into at least one graph structure, each graph structure including a plurality of nodes. The apparatus further includes an adjacency pattern determining module configured to determine an adjacency pattern of each node of the plurality of nodes in each graph structure, the adjacency pattern including a connection type to which the node belongs and associated nodes related to the connection type. The apparatus further includes a layout determining module configured to determine a layout of the silicon photonic device based on the adjacency pattern.

[0006] According to an aspect of the present disclosure, a computer device is provided, including at least one processor, and at least one memory having a computer program stored thereon, wherein the computer program, when executed by the processor, causes the processor to perform the method as described above.

[0007] According to an aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon a computer program, which, when executed by a processor, causes the processor to perform the method as described above.

[0008] According to an aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, causes the processor to perform the method as described above.

[0009] According to another aspect of the present disclosure, there is provided a silicon photonic chip comprising a silicon photonic device, wherein the silicon photonic device is laid out according to the method as described above.

[0010] According to one or more embodiments of the present disclosure, an automated layout for silicon photonic devices can be provided.

[0011] These and other aspects of the present disclosure will be apparent from the following description, taken in conjunction with the accompanying drawings, and from the detailed description which follows, particularly when considered in light of the examples described below. BRIEF DESCRIPTION OF DRAWINGS

[0012] In the following description of example embodiments, in conjunction with the accompanying drawings, more detailed descriptions of the present disclosure, its features, and its advantages will be disclosed. The present disclosure is not limited to the example embodiments described below, but can be implemented in various forms. The examples are provided to provide a thorough understanding of the present disclosure.

[0013] Figure 1 A flowchart of a method of layout of a silicon photonic device according to embodiments of the present disclosure is shown;

[0014] Figure 2 An example of a connection type according to embodiments of the present disclosure is shown;

[0015] Figures 3A to 3C An example of a process of determining an adjacency pattern of nodes in a graph structure and determining a layout according to embodiments of the present disclosure is shown;

[0016] Figure 4 An example of a partial layout of a photonic computing chip according to embodiments of the present disclosure is shown, in which an example of a process with respect to node grouping is also shown;

[0017] Figure 5 An example of a layout of a wavelength division multiplexing functional element according to embodiments of the present disclosure is shown;

[0018] Figure 6 A schematic block diagram of a layout apparatus of a silicon photonic device according to embodiments of the present disclosure is shown; and

[0019] Figure 7 An example configuration of a computer device that can be used to implement the methods described in the present disclosure is shown. DETAILED DESCRIPTION

[0020] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items and the phrase "at least one of A and B" means A alone, B alone, or both A and B.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the

[0023] In the related art, due to the low reusability of the layout method of the traditional IC, the layout of the silicon optical device is still mostly manually performed in an artificial manner.

[0024] On the one hand, the layout method of the traditional IC itself is prone to fall into local optimization, and the optimization efficiency decreases rapidly with the increase of the number of devices, which makes the reliability of the automatic layout of the traditional IC not high. In addition, the design objective function of the device layout has not yet formed a complete system in the layout of the silicon optical device, which makes it difficult to match the layout method of the traditional IC. The limitations in these aspects make it possible that the traditional optimization algorithm cannot be applied to the layout of the silicon optical device.

[0025] On the other hand, in the layout of the silicon optical device, many other factors also need to be considered. For example, since the silicon optical device is connected by waveguides and signal processing is realized by using the interference of light, the waveguide needs to meet certain optical path difference requirements. At the same time, the turning radius of the waveguide also has certain requirements. These considerations of the waveguide on the wiring also correspondingly affect the overall layout method, so that the layout needs to be able to meet the symmetry of the silicon optical device. At this point, the layout method of the traditional IC cannot meet the layout requirements of the silicon optical device.

[0026] Therefore, according to an aspect of an embodiment of the present disclosure, a silicon optical device layout method is provided. Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0027] Figure 1 A flowchart of a silicon optical device layout method 100 according to an embodiment of the present disclosure is shown. As shown in the figure, the method 100 includes steps S102 to S108. Figure 1

[0028] In step S102, a netlist of information describing the silicon optical device to be laid out is obtained. The information includes the types of silicon optical devices and the connection relationship between the silicon optical devices.

[0029] In an example, the layout can be for the entire silicon optical chip, so the silicon optical device to be laid out can refer to all silicon optical devices constituting the silicon optical chip. Alternatively, the layout can also be for a part of the silicon optical chip or a specific silicon optical link, so the silicon optical device to be laid out can also be the silicon optical device constituting the part or the specific silicon optical link of the silicon optical chip.

[0030] In an example, the netlist can indicate the types of silicon optical devices (for example, MZI modulator, resonant ring, etc.) and their connection relationship (for example, how to connect between ports, etc.) through the index of the serial number of the silicon optical device.

[0031] In step S104, the netlist is parameterized into at least one graph structure, and each graph structure includes a plurality of nodes.

[0032] Therefore, each node corresponds to a single silicon optical device, so that the entire netlist can be represented in the form of a graph.

[0033] In step S106, the adjacency pattern of each node of the plurality of nodes in each graph structure is determined. The adjacency pattern includes the connection type to which the node belongs and the associated node related to the connection type.

[0034] ​In some embodiments, the determination of the adjacency pattern can be implemented in a manner that each node only corresponds to one specific adjacency pattern. That is, for a certain node, when the connection type to which the node belongs is determined, the associated nodes related to the connection type are also determined, which include all the nodes constituting the connection type.

[0035] In an example, there can be a connection type including only a single node, in which case the associated nodes related to the connection type only include the single node.

[0036] In step S108, the layout of the silicon photonic device is determined based on the adjacency pattern.

[0037] Therefore, according to the embodiments of the present disclosure, an automated layout method for silicon photonic devices is provided.

[0038] The method of the embodiments of the present disclosure parameterizes the netlist of the silicon photonic device into a graph based on graph theory, so that each node in the graph corresponds to each silicon photonic device, thereby facilitating the determination of the layout by means of the method of graph theory. Further, by determining the adjacency pattern of each node in the graph, the connection characteristics or properties of each silicon photonic device required for the layout can be characterized, and then the layout can be derived based on the adjacency pattern.

[0039] The method of the embodiments of the present disclosure can not only break away from the shackles of traditional optimization algorithms, but also solve the current situation of relying on manual layout, and can realize the automated layout for silicon photonic devices. At the same time, since the layout result is derived according to the adjacency pattern of the node, the method can provide interpretability to support the checking of the layout result.

[0040] The method of the embodiments of the present disclosure can effectively assist the design of silicon photonic chips, reduce the design difficulty, and simplify the design workflow, thereby facilitating the shortening of the design and development cycle of silicon photonic chips.

[0041] The following detailed description describes various aspects of a silicon photonic device layout method 100 according to embodiments of the present disclosure.

[0042] According to some embodiments, in step S104, parameterizing the netlist into at least one graph structure can include: representing the connection relationship between the silicon photonic devices obtained through the netlist in the form of an adjacency matrix; and constructing at least one graph structure based on the adjacency matrix.

[0043] In an example, both the rows and columns of the adjacency matrix can indicate the index of the silicon photonic device. Therefore, the element of one in the adjacency matrix can represent that the corresponding silicon photonic devices have a connection relationship, and vice versa, the element of zero can represent that there is no connection relationship.

[0044] Here, since constructing a graph structure based on an adjacency matrix can be a technique known to those skilled in the art, details thereof will not be described herein.

[0045] In this way, the connection relationship between silicon optical devices can be expressed by means of an adjacency matrix, and a graph structure required by the present method based on graph theory can be constructed therefrom.

[0046] According to some embodiments, the at least one graph structure constructed based on the adjacency matrix can comprise one connected graph or a plurality of connected subgraphs.

[0047] In other words, the netlist can be parameterized as one connected graph or as a plurality of connected subgraphs, depending on the actual situation of the netlist.

[0048] In an example, a judgment can be made as to whether the graph structure is a connected graph. If the graph structure constructed based on the adjacency matrix of the netlist is a connected graph, the subsequent steps S106 and S108 can be executed accordingly with respect to the connected graph; and if the graph structure constructed based on the adjacency matrix of the netlist is not a connected graph, it means that a plurality of connected subgraphs are included at this time, and therefore the subsequent steps S106 and S108 can be executed accordingly with respect to the plurality of connected subgraphs respectively until all the connected subgraphs are processed.

[0049] In this way, an appropriate processing manner can be further selected according to the actual situation of the netlist to comprehensively cover the information contained in the netlist.

[0050] According to some embodiments, in step S106, determining the adjacency pattern of each node of the plurality of nodes in each graph structure can comprise:

[0051] dividing the plurality of nodes in each graph structure into at least one group according to the eigenvector centrality of each of the plurality of nodes, wherein a group containing an anchor node is a starting group in the at least one group, and the anchor node is a node preselected as a starting node of the graph structure; and identifying the adjacency pattern of each node in each group from the starting group.

[0052] Here, the eigenvector centrality can be a measure reflecting the centrality of a node, which indicates that the centrality of a node is a function of the centrality of adjacent nodes. According to the present embodiment, the plurality of nodes can be grouped based on the eigenvector centrality so that each group corresponds to a different eigenvector centrality. To this end, the eigenvector centrality of each of the plurality of nodes can be extracted first. Since extracting the eigenvector centrality of a node can be a technique known to those skilled in the art, details thereof will not be described herein.

[0053] Since step S106 involves traversing each node, after obtaining at least one group, the traversal of the nodes can be performed in units of groups. According to the present embodiment, a starting group in the traversal process can be set, which can be a group containing an anchor node. Since the anchor node can be a node pre-selected as the start of the graph structure, taking the group containing the anchor node as the starting group can take into account the relative positional relationship of the nodes when traversing.

[0054] In this way, the node grouping can be used to facilitate feature extraction of the node hierarchy to obtain the connection features or characteristics of each silicon optical device required for the layout.

[0055] According to some embodiments, at least one node divided in the same group can be assigned the same horizontal position in the layout.

[0056] According to some embodiments, the remaining nodes in the starting group other than the anchor node are assigned corresponding longitudinal positions according to their path lengths to the anchor node.

[0057] In this way, the node grouping can also be used to facilitate the layout of the silicon optical device in the horizontal and longitudinal directions.

[0058] According to some embodiments, after the node grouping in step S106, the longest non-repeating path formed across at least one group can be determined as a reference for the horizontal range of each graph structure. The maximum group length of the group with the most nodes in at least one group can also be determined as a reference for the longitudinal range of each graph structure. The longest non-repeating path and the maximum group length can be used to estimate the range of the layout of the silicon optical device.

[0059] In this way, the node grouping can also be used to facilitate feature extraction of the graph hierarchy to obtain an estimate of the length and width information for the layout. Further details will be described later in connection with Figure 4 An example of the process of node grouping will be described.

[0060] According to some embodiments, in step S108, determining the layout of the silicon optical device based on the adjacency pattern can include mapping each graph structure into a corresponding layout of the silicon optical device based on the connection type and associated nodes of each node in each graph structure.

[0061] In this way, the results obtained via the graph theory method can be output as the required device layout.

[0062] According to some embodiments, the connection type can be pre-set according to the number of nodes contained in the connection type and the connection manner between the nodes.

[0063] In an example, the number of nodes included in the connection type can be, for example, two, three, four, and so on. As mentioned previously, there can also be a connection type including only a single node, i.e., the number of nodes is one. In addition, considering that a silicon optical device has two ports at two ends respectively, different connection manners can occur, such as a series connection (1T1 type as shown in FIG. 1A), a bifurcation connection (1Y2 type as shown in FIG. 1B), a cross connection (2X2 type as shown in FIG. 1C), and so on. Therefore, the connection type can also be preset based on these different connection manners. Figure 2 Figure 2 Figure 2

[0064] In an example, the connection type can also be verified through expert layout experience. The following will illustrate examples of six preset and expert-verified connection types. Figure 2

[0065] In this way, it can be beneficial to map the result obtained via the graph theory method to the required device layout, thereby facilitating the implementation of automated layout.

[0066] In addition, the connection type can also be dynamically scalable, thereby providing scalability of the automated layout.

[0067] According to some embodiments, after step S108, the geometric information about the silicon optical devices can be obtained from a preset process library based on the category of the silicon optical devices, and the geometric information is applied in the layout of the silicon optical devices to determine the size of the silicon optical devices and the spacing between the silicon optical devices.

[0068] In an example, the preset process library can be, for example, an accessible PDK (Process Design Kit) library, which can include, for example, the geometric information of various basic silicon optical devices.

[0069] In this way, the layout assignment obtained based on the graph theory method can be completed, thereby completing the entire automated layout.

[0070] As mentioned previously, the method of the embodiments of the present disclosure can not only break away from the shackles of traditional optimization algorithms, but also solve the current situation of relying on manual layout, and can realize the automated layout of silicon optical devices. Therefore, it can effectively assist the design of silicon optical chips, reduce the design difficulty, and simplify the design workflow, thereby facilitating the shortening of the design and development cycle of silicon optical chips.

[0071] The following further describes examples of the method of the embodiments of the present disclosure in combination with Figure 2 , Figures 3A to 3C , Figure 4 and Figure 5 .

[0072] ​​​​Figure 2 An example of connection types is shown according to an embodiment of the present disclosure.

[0073] As shown in FIG. 2, six pre-set and expert-verified connection types are shown, which are labeled as T0 type, 1T1 type, 1Y2 type, 2X2 type, 2W3 type and 4X2 type respectively in the figure. The nodes in each connection type are exemplified with two ports included in the side surface, considering the correspondence with the ports of a silicon optical device. Figure 2 The T0 type can be a connection type including only a single node 201. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 201 belongs is the T0 type, the associated nodes related to the connection type include the single node 201.

[0074] Figure 1 The 1T1 type can include two nodes 202 and 203 connected in series. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 202 belongs is the 1T1 type, the associated nodes related to the connection type include the nodes 202 and 203.

[0075] The 1Y2 type can include three nodes 204, 205 and 206 connected in series. Alternatively, the 1Y2 type can include a node 204’ and two nodes 205’ and 206’ connected in bifurcation with the node 204’. That is, the two ports of the node 204’ facing the nodes 205’ and 206’ are connected with the nodes 205’ and 206’ respectively. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 204 or 204’ belongs is the 1Y2 type, the associated nodes related to the connection type include the nodes 204, 205 and 206, or 204’, 205’ and 206’. Figure 1 The 2X2 type can include four nodes 207 to 210, in which the node 207 is connected with the nodes 209 and 210 respectively, and the node 208 is also connected with the nodes 209 and 210 respectively, so that a cross connection is formed between the four nodes. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 207 or 208 belongs is the 2X2 type, the associated nodes related to the connection type include the four nodes 207 to 210.

[0076] Figure 1 The 2W3 type can include three nodes 211 to 213, in which the node 211 is connected with the nodes 212 and 213 respectively, and the node 212 is also connected with the nodes 212 and 213 respectively, so that a cross connection is formed between the three nodes. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 211 or 212 belongs is the 2W3 type, the associated nodes related to the connection type include the three nodes 211 to 213.

[0077] The 4X2 type can include four nodes 214 to 217, in which the node 214 is connected with the nodes 216 and 217 respectively, and the node 215 is also connected with the nodes 216 and 217 respectively, so that a cross connection is formed between the four nodes. When it is determined in step S106 as described in conjunction with FIG. 1 that the connection type to which the node 214 or 215 belongs is the 4X2 type, the associated nodes related to the connection type include the four nodes 214 to 217. Figure 1

[0078] ​​​The 2W3 type can be similar to the second type in the 1Y2 type, but can include five nodes 211 to 215, namely, two nodes 211 and 212, and three nodes 213, 214, and 215 connected to nodes 211 and 212 in a branching manner. Specifically, the two ports of node 211 facing nodes 213 and 214 are connected to nodes 213 and 214 respectively, and the two ports of node 212 facing nodes 214 and 215 are connected to nodes 214 and 215 respectively. In combination... Figure 1 When step S106 determines that the connection type of node 211 or 212 is type 2W3, the associated nodes related to this connection type include the five nodes 211 to 215.

[0079] The 4x2 configuration may include six nodes 216 to 221, wherein four ports of each of nodes 220 and 221 are connected to nodes 216 to 219 respectively. Specifically, the two ports of node 216 facing nodes 220 and 221 are connected to nodes 220 and 221 respectively, and the two ports of node 217 facing nodes 220 and 221 are also connected to nodes 220 and 221 respectively. Similarly, the two ports of node 218 facing nodes 220 and 221 are connected to nodes 220 and 221 respectively, and the two ports of node 219 facing nodes 220 and 221 are also connected to nodes 220 and 221 respectively. In combination... Figure 1 When step S106 determines that the connection type of one of nodes 216 to 219 is 4X2, the associated nodes related to that connection type include nodes 216 to 221.

[0080] Understandable, Figure 2 Only a few examples of connection types are illustrated. However, as mentioned earlier, connection types can be dynamically extensible.

[0081] By setting the connection type, the results obtained through graph theory can be mapped to the desired device layout.

[0082] Figures 3A to 3C An example is shown of a process for determining the adjacency pattern of nodes in a graph structure and determining the layout according to an embodiment of the present disclosure. Figure 3A This shows the execution of, such as Figure 1 The example graph structure obtained after step S104 shown (e.g., one of multiple connected subgraphs) Figure 3B As shown Figure 1 The example process shown in step S106, and Figure 3C As shown Figure 1 The example process for step S108 is shown.

[0083] like Figure 3AAs shown, the connected subgraph 310 may include nodes 3100 to 3107, from the first to the eighth. As previously mentioned, each node corresponds to a single silicon photonic device. For ease of illustration, in Figure 3A The index of each node is also shown, labeled from “0” to “7”.

[0084] like Figure 3B As shown, execute as follows Figure 1 Step S106, as shown, involves determining the adjacency pattern of each node from the first to the eighth nodes 3100 to 3107 in the connected subgraph 310. For clarity, column 320 shows the indices of the first to the eighth nodes 3100 to 3107, i.e., “0” to “7”; column 322 shows the connection type (such as combination) to which the first to the eighth nodes 3100 to 3107 belong. Figure 2 (The connection type mentioned above); Column 324 shows the associated nodes related to the corresponding connection type.

[0085] For the first node 3100 with index "0", it can be determined that the connection type of this node is 1T1, and the associated nodes related to this 1T1 type are the first node 3100 and the second node 3101, i.e., indices "0" and "1", respectively. Similarly, it can be determined that the connection type of the third node 3102 with index "2" and the fourth node 3103 with index "3" is also 1T1. Accordingly, the associated nodes related to this 1T1 type are marked as "2" and "3", and "3" and "4", respectively.

[0086] Furthermore, it can be determined that the connection type of the second node 3101 with index "1" and the sixth node 3105 with index "5" is 1Y2. Accordingly, the associated nodes related to this 1Y2 type are labeled "1", "2,5" and "5", "6,7", respectively. In other words, when the second node 3101 with index "1" is traversed, the third node 3102 with index "2" and the sixth node 3105 with index "5" can be considered as child nodes of the second node 3101 with index "1". Similarly, when the sixth node 3105 with index "5" is traversed, the seventh node 3106 with index "6" and the eighth node 3107 with index "7" can be considered as child nodes of the sixth node 3105 with index "5".

[0087] Furthermore, it can be determined that the fifth node 3104 with index "4", the seventh node 3106 with index "6", and the eighth node 3107 with index "7" belong to the T0 type of connection. The T0 type is a connection type that includes only a single node. Therefore, the associated nodes related to this T0 type are marked as "4", "[]" (representing "empty"); "6", "[]"; and "7", "[]".

[0088] As mentioned before, in this document, the determination of the adjacency pattern is implemented in a way that each node corresponds to only one specific adjacency pattern. That is, for a certain node, when the connection type to which the node belongs is determined, the associated nodes related to the connection type are also determined, which include all the nodes that constitute the connection type. As shown in column 322, the first to eighth nodes 3100 to 3107 have respectively one connection type. Accordingly, as shown in column 324, the associated nodes related to the corresponding connection type include all the nodes that constitute the connection type.

[0089] As Figure 3C shown, the step S108 shown in Figure 1 is performed, that is, the layout of the silicon photonic device is determined based on the adjacency pattern. After the adjacency pattern of each of the first to eighth nodes 3100 to 3107 is determined as shown in Figure 3B , the connected subgraph 310 can be mapped into the device layout 330 based on the adjacency pattern. To illustrate the mapping relationship, Figure 3C , the corresponding silicon photonic devices are also labeled with indexes “0” to “7”.

[0090] At this time, the geometric information of the silicon photonic device can also be obtained from the PDK library, so as to further determine the device size (as shown by “X e ”, “Y e1 ”) and the spacing between devices (as shown by “Y e2 ”, “Y e3 ”) in the device layout 330.

[0091] For the purpose of example, Figure 3C only part of the unknown distances are shown, and other unknown distances may, for example, also include the spacing between the device with index “0” and the device with index “1”, the spacing between the device with index “1” and the device with index “2”, and so on.

[0092] Therefore, the layout obtained based on the graph theory method can be assigned values, thereby completing the entire automated layout.

[0093] Figure 4 An example of a partial layout of a photonic computing chip according to an embodiment of the present disclosure is shown, wherein an example of the process regarding node grouping is also shown.

[0094] For ease of comparison, Figure 4 the result of the manual layout is shown in the upper part, and the result of the automated layout according to an embodiment of the present disclosure is shown in the lower part. As shown in Figure 4 the silicon photonic device shown can be, for example, an MZI modulator named “M2X2_TE_1550_extra_port” in the PDK library.

[0095] When performing the automated layout method according to the embodiments of the present disclosure, the layout completion time is less than 0.5 seconds. Therefore, the present method can provide extremely high layout speed, and is able to output layout results in almost real time.

[0096] In addition, compared with the manual layout shown in the upper part, Figure 4 Compared with the manual layout shown in the upper part, the present method is correct in terms of device sequence, connection proximity relationship, and / or placement logic, and the output results are stable each time. Therefore, the present method can also provide high result robustness and repeatability.

[0097] Here, the method according to the embodiments of the present disclosure is also combined with Figure 4 An example of node grouping in the method according to the embodiments of the present disclosure is described.

[0098] Referring to FIG. 1, the layout of a wave division multiplexing functional element according to the embodiments of the present disclosure is shown. Figure 4 The result of the automated layout according to the embodiments of the present disclosure is shown in the lower part, in which the nodes with indices “0”, “3”, “6”, and “9” can be divided into one group. Similarly, the nodes with indices “24”, “26”, “36”, and “38” can be divided into one group; the nodes with indices “25”, “27”, “37”, and “39” can be divided into one group; the nodes with indices “72”, “74”, “76”, and “78” can be divided into one group; and the nodes with indices “73”, “77”, “75”, and “79” can be divided into one group.

[0099] Among these groups, the node with index “0” can be a pre-selected anchor node, therefore, the group including the anchor node with index “0” can be a starting group, and the adjacency pattern of each node in each group is identified from the starting group.

[0100] In addition, the nodes divided in the same group (such as the nodes with indices “0”, “3”, “6”, and “9”, or the nodes with indices “24”, “26”, “36”, and “38”, etc.) can be assigned the same horizontal position in the layout. The remaining nodes in the starting group except for the anchor node with index “0” (i.e., the nodes with indices “3”, “6”, and “9”) are assigned corresponding vertical positions according to their path lengths to the anchor node with index “0”. In other words, the node with index “3” has the shortest path to the anchor node with index “0”, and the node with index “9” has the longest path to the anchor node with index “0”.

[0101] Figure 5 An example of the layout of a wave division multiplexing functional element according to the embodiments of the present disclosure is shown.

[0102] For ease of comparison, Figure 5The result of manual layout is shown on the left side, and the result of automated layout according to embodiments of the present disclosure is shown on the right side. As Figure 5 The silicon optical device as shown can be, for example, a directional coupler.

[0103] When performing the automated layout method according to embodiments of the present disclosure, the layout completion time is also less than 0.5 seconds. Therefore, the present method can provide extremely high layout speed, and is able to output the layout result in almost real time.

[0104] In addition, as previously described, since the present method can determine the horizontal range of the graph structure based on the longest non-repeating path, planning of horizontal space can be achieved. In addition, since the present method can determine the vertical range of the graph structure based on the maximum group length, vertical space can be reserved for accommodating branch structures.

[0105] According to an aspect of the present disclosure, there is also provided a silicon optical chip comprising a silicon optical device, which is laid out according to embodiments of any of the methods described above.

[0106] According to an aspect of the present disclosure, there is also provided a silicon optical device layout apparatus.

[0107] Figure 6 A schematic block diagram of a silicon optical device layout apparatus 600 according to embodiments of the present disclosure is shown.

[0108] As Figure 6 shown, the apparatus 600 comprises a netlist obtaining module 602, a graph generating module 604, an adjacency pattern determining module 606, and a layout determining module 608.

[0109] The netlist obtaining module 602 can be configured to obtain a netlist of information describing a silicon optical device to be laid out. The information includes the types of the silicon optical devices and the connection relationships between the silicon optical devices.

[0110] The graph generating module 604 can be configured to parameterize the netlist into at least one graph structure, each graph structure comprising a plurality of nodes.

[0111] The adjacency pattern determining module 606 can be configured to determine the adjacency pattern of each node of the plurality of nodes in each graph structure. The adjacency pattern includes the connection type to which the node belongs and the associated nodes related to the connection type.

[0112] The layout determining module 608 can be configured to determine the layout of the silicon optical device based on the adjacency pattern.

[0113] It should be understood that Figure 6 the various modules of the apparatus 600 as shown in FIG. 6 can be the same as those described with reference to Figure 1The various steps in the described method 100 correspond. Thus, the operations, features, and advantages described above for the method 100 apply equally to the apparatus 600 and its included modules. For the sake of brevity, certain operations, features, and advantages are not repeated here.

[0114] While specific functions are discussed above with reference to specific modules, it should be noted that the functions of the various modules discussed herein can be split among multiple modules and / or at least some of the functions of multiple modules can be combined into a single module. A specific module discussed herein performing an action includes that specific module itself performing the action, or alternatively, that specific module invoking or otherwise accessing another component or module that performs the action (or performs the portion of the action that is different from that

[0115] It should also be understood that various techniques described herein can be described in the general context of software hardware elements, or program modules. The terms "software" and "program" are used herein to refer to any computer program product, software, firmware, or microcode that contains any combination of machine executable instructions, including code for implementing the techniques described herein. The program modules described herein are generally executed by computer hardware, such as one or more processors, to perform the techniques described herein. Figure 6 The various modules described can be implemented in hardware or in hardware in combination with software and / or firmware. For example, the modules can be implemented as computer program code / instructions configured to be executed in one or more processors and stored in a computer-readable storage medium. Alternatively, the modules can be implemented as hardware logic / circuitry. For example, in some embodiments, one or more of the netlist acquisition module 602, the graph generation module 604, the adjacency pattern determination module 606, and the layout determination module 608 can be implemented together in a System on Chip (SoC). The SoC can include an integrated circuit chip (which includes one or more of a processor (e.g., a Central Processing Unit (CPU), a microcontroller, a microprocessor, a Digital Signal Processor (DSP), etc.), memory, one or more communication interfaces, and / or other circuitry), and can optionally execute received program code and / or include embedded firmware to perform functions.

[0116] According to an aspect of the present disclosure, there is also provided a computer device comprising a memory, a processor, and a computer program stored on the memory. The processor is configured to execute the computer program to implement the steps of any of the method embodiments described above.

[0117] According to an aspect of the present disclosure, there is also provided a non-transitory computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0118] According to an aspect of the present disclosure, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

[0119] In the following, illustrative examples of such computer devices, non-transitory computer-readable storage media, and computer program products are described. Figure 7 Illustrative examples of such computer devices, non-transitory computer-readable storage media, and computer program products are described.

[0120] Figure 7 An example configuration of a computer device 700 that can be used to implement the methods described in the present disclosure is shown. The silicon photonic device layout apparatus 600 described above can be implemented in whole or in part by the computer device 700 or a similar device or system.

[0121] The computer device 700 can be various different types of devices. Examples of the computer device 700 include, but are not limited to: a desktop computer, a server computer, a notebook or netbook computer, a mobile device (e.g., a tablet computer, a cellular or other wireless phone (e.g., a smart phone), a notepad computer, a mobile station), a wearable device (e.g., glasses, a watch), an entertainment device (e.g., an entertainment appliance, a set-top box, a game console), a television or other display device, an automobile computer, and so forth.

[0122] The computer device 700 can include at least one processor 702, memory 704, communication interface(s) 706, a display device 708, other input / output (I / O) devices 710, and one or more mass storage devices 712, which can communicate with one another by way of a system bus 714 or other appropriate connection, communication interface(s) 706 can include a modem, a network interface card, a

[0123] The processor 702 can be a single processing unit or a plurality of processing units, all of which can include single or multiple computing units or multiple cores. The processor 702 can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuitries, and / or any devices that manipulate signals based on operational instructions. Among other capabilities, the processor 702 can be configured to fetch and execute computer-readable instructions stored in the memory 704, the mass storage device 712, or any other computer-readable medium, such as program code for an operating system 716, program code for applications 718, program code for other programs 720, and the like.

[0124] Memory 704 and mass storage devices 712 are examples of computer readable storage media for storing instructions which are executed by processor 702 to practice the various functionalities described above. By way of example, memory 704 can generally include both volatile memory and nonvolatile memory (e.g., RAM, ROM, etc.). In addition, mass storage devices 712 can generally include hard disk drives, solid state drives, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CD, DVD), storage arrays, network attached storage, storage area networks, etc. Memory 704 and mass storage devices 712 can be collectively referred to herein as memory or computer readable storage media, and can be non-transitory media capable of storing computer readable, processor executable program instructions as computer program code which can be executed by processor 702 as a particular machine configured to implement the operations and functions described in the examples herein.

[0125] A number of programs can be stored on the mass storage devices 712. These programs include an operating system 716, one or more application programs 718, other programs 720, and program data 722, and they can be loaded into memory 704 for execution. Examples of such application or program modules can include, for example, computer program logic (e.g., computer program code or instructions) for implementing the netlist acquisition module 602, the graph generation module 604, the adjacency pattern determination module 606, and the layout determination module 608 and / or additional embodiments described herein.

[0126] Although illustrated in Figure 7 as being stored in the memory 704 of the computer device 700, the modules 716, 718, 720, and 722, or portions thereof, can be implemented using any form of computer readable media that is accessible by the computer device 700. As used herein, "computer readable media" includes both computer readable storage media and communication media.

[0127] Computer-readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer-readable storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by a computer, etc. In contrast, communication media can embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal, such as a carrier wave, or other transport mechanism. As defined herein, computer-readable storage media does not include communication media.

[0128] One or more communication interfaces 706 are used to exchange data with other devices, such as over a network, direct connection, etc. Such communication interfaces can be one or more of: any type of network interface (e.g., network interface card (NIC)), wired or wireless (such as IEEE 802.11 wireless LAN (WLAN)) wireless interface, Worldwide Interoperability Microwave Access (Wi-MAX) interface, Ethernet interface, Universal Serial Bus (USB) interface, cellular network interface, Bluetooth interface, near field communication (NFC) interface, etc. The communication interfaces 706 can facilitate communications within a variety of networks and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, etc. The communication interfaces 706 can also provide communication with external storage devices (not shown), such as storage arrays, network attached storage, storage area networks, etc. TM

[0129] In some examples, a display device 708, such as a monitor, can be included for displaying information and images to a user. Other I / O devices 710 can be devices that receive various inputs from a user and provide various outputs to the user, and can include touch input devices, gesture input devices, cameras, keyboards, remote controls, mice, printers, audio input / output devices, etc.

[0130] ​The techniques described herein can be supported by these various configurations of the computer device 700 and are not limited to the specific examples of the techniques described herein. For example, the functionality can also be implemented all or in part through use of a distributed system, e.g., cloud computing, over a network. Cloud computing can include and / or be represented as a platform of resources that includes and / or is represented by an abstraction of the underlying functionality of the hardware (e.g., servers) and software resources. Resources can include applications and / or data that can be utilized while performing computing processes on a server that is remote from the computer device 700. Resources can also include services provided over the Internet and / or through a subscriber network, such as a cellular or Wi-Fi network. The platform can abstract the underlying functionality of the resources and capabilities of the cloud to connect the computer device 700 with other computer devices. Thus, the functionality of the techniques described herein can be distributed throughout the cloud. For example, the functionality can be implemented in part on the computer device 700 and in part by the platform that abstracts the functionality of the cloud.

[0131] While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description is to be considered illustrative or exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps not listed in the claims, the word "a" or "an" does not exclude a plurality, the term "multiple" means two or more, and the term "based on" means "based at least in part on." The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method for laying out silicon photonic devices, comprising: Obtain a netlist for describing information about the silicon photonics devices to be laid out, including the types of silicon photonics devices and the connections between them; The netlist is parameterized into at least one graph structure, each graph structure including multiple nodes, wherein the at least one graph structure includes a connected graph or multiple connected subgraphs; Determine the adjacency pattern of each of the plurality of nodes in each graph structure, wherein each node corresponds to only one specific adjacency pattern, wherein the adjacency pattern includes the connection type to which the node belongs and the associated nodes related to the connection type, wherein the connection type is preset according to the number of nodes included in the connection type and the connection method between the nodes, wherein determining the adjacency pattern for each connected graph or connected subgraph includes: The first column lists the indexes of each of the nodes; The second column lists the connection types to which each of the plurality of nodes belongs, corresponding to the index, wherein the connection types include any one of the first to sixth connection types: The first connection type includes only a single node; The second connection type includes two nodes connected in series; The third connection type includes three nodes, wherein the first node to the third node are connected in series, or the two ports of the first node facing the second node and the third node are respectively connected to the second node and the third node; The fourth connection type includes four nodes. The first node of the four nodes is connected to the third node and the fourth node respectively, and the second node is also connected to the third node and the fourth node respectively, so that cross connections are formed among the four nodes. The fifth connection type includes five nodes, wherein the first node has two ports facing the third and fourth nodes respectively connected to the third and fourth nodes, and the second node has two ports facing the fourth and fifth nodes respectively connected to the fourth and fifth nodes; and The sixth connection type includes six nodes, wherein the first to fourth nodes of the six nodes each have two ports facing the fourth and fifth nodes respectively connected to the fourth and fifth nodes; and The third column lists the associated nodes corresponding to the index and related to the connection type to which each of the plurality of nodes belongs, wherein, for the first connection type, the associated nodes include the single node and nodes marked as empty; and The layout of the silicon photonics device is determined based on the adjacency pattern.

2. The method according to claim 1, wherein, The step of parameterizing the netlist into at least one graph structure includes: The connectivity between the silicon photonic devices obtained through the netlist is represented as an adjacency matrix; and The at least one graph structure is constructed based on the adjacency matrix.

3. The method according to claim 1 or 2, wherein, Determining the adjacency pattern of each of the plurality of nodes in each graph structure includes: The plurality of nodes in each graph structure are divided into at least one group based on the eigenvector centrality of each node, wherein the group containing the anchor node is the starting group among the at least one group, and the anchor node is a node pre-selected as the starting point of the graph structure; and The adjacency pattern of each node in each group is identified starting from the initial group.

4. The method according to claim 3, wherein, At least one node that is grouped into the same group is assigned the same lateral position in the layout.

5. The method according to claim 3, wherein, In the initial group, all nodes except the anchor node are assigned corresponding longitudinal positions according to the path length to the anchor node.

6. The method of claim 3, further comprising: Determine the longest non-repeating path formed across the at least one group as a reference for the lateral extent of each graph structure; as well as The maximum group length of the group with the most nodes among the at least one group is determined as a reference for the vertical range of each graph structure. The longest non-repeating path and the maximum group length are used to estimate the range of the silicon photonic device layout.

7. The method according to claim 1 or 2, wherein, The process of determining the layout of the silicon photonics based on the adjacency pattern includes: Based on the connection type and associated nodes of each node in each graph structure, each graph structure is mapped to a corresponding layout of the silicon photonics device.

8. The method according to claim 1 or 2, further comprising: Geometric information about the silicon photonics device is obtained from a pre-set process library based on the type of silicon photonics device. as well as The geometric information is applied in the layout of the silicon photonics to determine the size of the silicon photonics and the spacing between the silicon photonics.

9. A silicon photonics device layout apparatus, comprising: The netlist acquisition module is configured to acquire a netlist for describing information about the silicon photonic devices to be laid out, the information including the types of silicon photonic devices and the connection relationships between the silicon photonic devices; The graph generation module is configured to parameterize a netlist into at least one graph structure, each graph structure including multiple nodes, wherein the at least one graph structure includes a connected graph or multiple connected subgraphs; An adjacency pattern determination module is configured to determine the adjacency pattern of each of the plurality of nodes in each graph structure, wherein each node corresponds to only one specific adjacency pattern, wherein the adjacency pattern includes the connection type to which the node belongs and the associated nodes related to the connection type, wherein the connection type is preset according to the number of nodes included in the connection type and the connection method between the nodes, wherein, for each connected graph or connected subgraph, the adjacency pattern determination module includes: The first determining module is configured to list the indexes of the plurality of nodes in a first column; The second determining module is configured to list the connection types of each of the plurality of nodes in a second column corresponding to the index, wherein the connection types include any one of the first to sixth connection types: The first connection type includes only a single node; The second connection type includes two nodes connected in series; The third connection type includes three nodes, wherein the first node to the third node are connected in series, or the two ports of the first node facing the second node and the third node are respectively connected to the second node and the third node; The fourth connection type includes four nodes. The first node of the four nodes is connected to the third node and the fourth node respectively, and the second node is also connected to the third node and the fourth node respectively, so that cross connections are formed among the four nodes. The fifth connection type includes five nodes, wherein the first node has two ports facing the third and fourth nodes respectively connected to the third and fourth nodes, and the second node has two ports facing the fourth and fifth nodes respectively connected to the fourth and fifth nodes; and The sixth connection type includes six nodes, wherein the first to fourth nodes of the six nodes each have two ports facing the fourth and fifth nodes respectively connected to the fourth and fifth nodes; and The third determining module is configured to list, in a third column, the associated nodes corresponding to the index and related to the connection type to which each of the plurality of nodes belongs, wherein, for the first connection type, the associated nodes include the single node and nodes marked as empty; and The layout determination module is configured to determine the layout of the silicon photonics device based on the adjacency pattern.

10. A computer device, comprising: At least one processor; as well as At least one memory on which a computer program is stored, When the computer program is executed by the at least one processor, it causes the at least one processor to perform the method according to any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the processor to perform the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program that, when executed by a processor, causes the processor to perform the method according to any one of claims 1 to 8.

13. A silicon photonics chip, comprising silicon photonic devices, wherein, The silicon photonics device is arranged according to any one of claims 1 to 8.

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