Cmos imaging sensor, femosfet device, and related methods

Abstract

A CMOS imaging sensor, FeMOSFET device, and related methods are disclosed. The CMOS imaging sensor includes an imaging pixel that includes a semiconductor substrate, a photosensor block, and a FeMOSFET device. The Fe-MOSFET device such as for incorporation into pixel-internal circuitry of an imaging pixel array to provide reset and double conversion gain features. The Fe-MOSFET includes a source region and a drain region implanted into the semiconductor substrate and separated by a channel region. The source region can be a floating diffusion region of the photosensor. A gate structure is deposited on the substrate directly over at least the channel region, and an isolation layer is formed on a surface of the substrate to electrically isolate the gate structure from at least the channel region. The isolation layer is divided into a Fe segment of ferroelectric material that can be written into different polarization states for conversion gain control and a dielectric segment that can be used for current channel formation in the channel region.

Description

[0001] Cross-references

[0002] This application claims priority to U.S. non-provisional patent application No. 17 / 524,701, filed on November 11, 2021, entitled “FERROELECTRIC-OXIDE HYBRID GATE TRANSISTOR BLOCK FOR SEMICONDUCTOR IMAGING SENSORS,” which is a non-provisional application of U.S. provisional patent application No. 63 / 141,262, filed on January 25, 2021, entitled “FERROELECTRIC-OXIDE HYBRID GATE TRANSISTOR AND ITS APPLICATIONS IN SEMICONDUCTOR IMAGING SENSSTOR,” both of which are hereby incorporated by reference in their entirety. Technical Field

[0003] The present invention relates to complementary metal oxide semiconductor (CMOS) image sensors. More particularly, embodiments relate to a ferroelectric-oxide hybrid gate reset transistor for integration with in-pixel circuitry of a CMOS image sensor (CIS) pixel. Background Art

[0004] Many modern electronic applications include integrated digital cameras and / or other imaging systems based on complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology. A CIS can typically include an array of pixels, each including a single photosensor (e.g., a photodiode), or a group of multiple photosensors. Each imaging pixel can include a photosensitive element that responds to light to generate a photocharge, and intra-pixel circuitry for processing the generated photocharge to produce an electrical pixel output signal and for controlling the operation of each imaging pixel. The intra-pixel circuitry includes transistors for performing sensing and control functions.

[0005] The performance of an imaging sensor pixel is related to how well the pixel can convert photons into electrical charge. This performance can depend on a number of physical and electrical properties of the pixel, such as well capacity, dynamic range, and conversion gain. Well capacity is related to the amount of charge that the imaging pixel can hold during the integration period (i.e., during exposure and before readout). It may be desirable to have a large dynamic range, meaning that the pixel performs well over a wide range of lighting conditions, such as from very low lighting conditions up to high lighting conditions (i.e., what the full well capacity, or FWC, can achieve). It may also be desirable to have a higher conversion gain, meaning that the output signal voltage increases more with any increase in accumulated charge. Typically, the output signal level corresponds to the ratio between the charge accumulated in the well and the well capacitance. For example, a smaller well tends to have a smaller capacity for accumulating charge and a correspondingly smaller well capacitance, which may tend to result in larger changes in the output signal level for any changes in charge accumulation in the well. Summary of the Invention

[0006] Embodiments disclosed herein include, among other things, transistor designs having a unique hybrid structure to replace the gate oxide between the gate electrode and the transistor channel, the unique hybrid structure comprising a gate dielectric segment formed of a dielectric material (e.g., an oxide or a high-k dielectric) and a ferroelectric segment comprising a ferroelectric material placed between the gate electrode and the transistor channel such that the two segments below the gate electrode are controlled by a common gate voltage applied to the gate electrode. The ferroelectric material used in the transistor has two electrical polarization states that can be switched by applying a sufficiently large positive or negative gate voltage, thereby providing the transistor with unique functionality in various applications. Such a hybrid transistor can be used to perform gain control and reset operations in sensing pixels in semiconductor imaging sensor arrays to reduce the amount of circuitry hardware in each pixel and increase integration density while allowing sufficient space within the pixel to be allocated to the photosensitive element for collecting light.

[0007] For example, such a transistor having the unique hybrid structure described above can be included in the intra-pixel circuitry of an image sensor pixel to perform (1) a dual conversion gain (DCG) function for improving the low-light detection sensitivity and dynamic range of each sensing pixel, and (2) resetting the image sensor pixel before and after readout, without requiring two separate transistors, designated for the DCG function and the reset function, as used in some other image sensor designs. This embodiment advantageously reduces the number of transistors in the intra-pixel circuitry of an imaging sensor array and can advantageously reduce the size of each pixel, desirable features for various imaging sensor applications.

[0008] According to a first set of embodiments, a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS) is provided. The CIS includes one or more imaging pixels. Each imaging pixel includes: a semiconductor substrate doped according to a first doping type; a photosensor block including at least one photodiode configured to accumulate photocarriers in response to exposure to illumination and transfer the accumulated photocarriers to a floating diffusion region for readout, the floating diffusion region being formed by implanting a first well of a second doping type into the semiconductor substrate, the second doping type being different from the first doping type; and a hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET) device. The hybrid Fe-MOSFET includes: a drain region formed by implanting a second well of a second doping type material into a semiconductor substrate, the drain region being separated from the floating diffusion region by a channel region; a gate structure deposited on the semiconductor substrate, at least directly above the channel region and having a gate electrode patterned thereon; and a gate isolation layer formed on the surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer including: an Fe segment made of a ferroelectric material and sandwiched between the gate structure and a first channel sub-region of the channel region adjacent to the floating diffusion region, the Fe segment being configured to switch between a high conversion gain mode and a low conversion gain mode; and a dielectric segment sandwiched between the gate structure and a second channel sub-region of the channel region adjacent to the drain region and not overlapping with the first sub-region.

[0009] According to another set of embodiments, a hybrid ferroelectric-metal-oxide-semiconductor field-effect transistor (Fe-MOSFET) device is provided. The hybrid Fe-MOSFET includes: a semiconductor substrate doped according to a first doping type; a source region and a drain region, each formed by implanting a respective well of a second doping type material into the semiconductor substrate, the source region and the drain region being separated by a channel region; a gate structure deposited on the semiconductor substrate, at least directly above the channel region, and having a gate electrode patterned thereon; and a gate isolation layer formed on a surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer including: an Fe segment made of a ferroelectric material and sandwiched between the gate structure channel region and a first channel sub-region adjacent to the source region; and a dielectric segment sandwiched between the gate structure and a second channel sub-region of the channel region adjacent to the drain region and not overlapping with the first sub-region.

[0010] According to another set of embodiments, a method for generating pixel output signals with dual conversion gain in a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS) is provided. The method includes: transmitting a write pulse at a write amplitude and one of two write polarizations to a gate electrode of a hybrid ferroelectric-metal-oxide-semiconductor field effect transistor (Fe-MOSFET), the hybrid Fe-MOSFET including: a source region and a drain region, each formed by implanting a well of a second doping type into a semiconductor substrate of a first doping type, the source region and the drain region being separated by a channel region; a gate structure deposited on the semiconductor substrate, at least directly above the channel region and having a gate electrode patterned thereon; and a gate isolation layer formed on a surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer including: a Fe segment and a dielectric segment, the Fe segment being made of a ferroelectric material and sandwiched therebetween. between a gate structure and a first channel sub-region of the channel region adjacent to the floating diffusion region, and the dielectric segment is sandwiched between the gate structure and a second channel sub-region of the channel region adjacent to the drain region and not overlapping with the first sub-region, wherein a write pulse writes the Fe segment into a selected one of two conversion gain modes by arranging the dipoles of the ferroelectric material into a corresponding one of two ferroelectric polarization states according to the write polarization transmitted by the write pulse; and after transmitting the write pulse, a reset pulse is transmitted to the gate electrode of the hybrid Fe-MOSFET with a reset amplitude, the reset amplitude being less than the write amplitude, so that the dielectric segment responds to the reset pulse to form a current channel across the channel region between the source region and the drain region without affecting the arrangement of the dipoles in the Fe segment.

[0011] The following figures, description, and claims provide a more detailed description of the above and other aspects of transistors having a hybrid structure, their implementations, and features of the disclosed technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated herein and constitute a part thereof, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the invention.

[0013] Figure 1 Shown is a simplified block diagram of a portion of an illustrative digital imaging system as context for the various embodiments described herein.

[0014] Figure 2 An example of a conventional CIS imaging pixel with conventional in-pixel circuitry is shown.

[0015] Figure 3A and 3B A simplified layout diagram and a simplified circuit diagram are respectively shown of another illustrative conventional implementation of a CIS imaging pixel.

[0016] Figure 4 The behavior of a ferroelectric (Fe) material used as a gate insulating layer of a field effect transistor (FET), as used in conventional Fe-FETs, is demonstrated.

[0017] Figure 5 A CIS imaging pixel incorporating intra-pixel circuitry with an illustrative hybrid reset DCG (HRD) block implemented with a novel Fe-MOSFET structure is shown in accordance with various embodiments described herein.

[0018] Figure 6A and 6B Shown are a simplified layout diagram and a simplified circuit diagram, respectively, of an illustrative implementation of a novel CIS imaging pixel having an HRD block 510 in accordance with various embodiments described herein.

[0019] Figure 7A Shown is an example of a simplified timing diagram for guiding the operation of an HRD block according to various embodiments described herein.

[0020] Figure 7B The diagram shows the case where the Fe segment of the HRD block is set to high conversion gain mode. Figure 7A A series of simplified band diagrams at the time positions indicated in .

[0021] Figure 7C The diagram shows the case where the Fe segment of the HRD block is set to low conversion gain mode. Figure 7C A series of simplified band diagrams at the time positions indicated in .

[0022] Figure 8A An illustrative graph of electric field magnitude versus polarization is shown for a Fe-MOSFET structure used in embodiments of the HRD block described herein.

[0023] Figure 8B Shown Figure 8A The corresponding energy band diagram for each of the four states on the graph.

[0024] Figure 9 An example flow chart of a process by which a Fe-MOSFET structure is fabricated according to various embodiments described herein is shown.

[0025] Figure 10 A flow chart is shown of an illustrative method for generating pixel output signals with dual conversion gains in a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), according to various embodiments described herein.

[0026] In the accompanying drawings, similar components and / or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a second reference number that distinguishes the similar components. If only the first reference number is used in the specification, the description applies to any similar component having the same first reference number, regardless of the second reference number. DETAILED DESCRIPTION

[0027] In the following description, many specific details are provided to thoroughly understand the present invention. However, it will be understood by those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, features and techniques known in the art will not be described for the purpose of brevity.

[0028] Many modern electronic applications include integrated digital cameras and / or other imaging systems based on complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology. A CIS may typically include an array of pixels, each pixel including a single photosensor (e.g., a photodiode), or a group of multiple photosensors. Each imaging pixel may include a photosensitive element that responds to light to generate a photocharge, and an intra-pixel circuitry for processing the generated photocharge to generate an electrical pixel output signal and for controlling the operation of each imaging pixel. The intra-pixel circuitry of a CIS imaging pixel typically includes a plurality of metal oxide semiconductor field effect transistors (MOSFETs) for performing sensing and control functions.

[0029] Figure 1 A simplified block diagram of a portion of an illustrative digital imaging system 100 is shown as a context for various embodiments described herein. The digital imaging system 100 can be built around complementary metal oxide semiconductor (CMOS) image sensor (CIS) technology. Such a CIS system can generally include one or more arrays of pixels 105, such as a large number of pixels 105 arranged in rows and columns. Each pixel 105 can include a photosensor block 110, which can include a single photodiode 115 (e.g., or any suitable photosensor, such as a photogate, phototransistor, etc.), or a group of multiple photodiodes 115 (e.g., a group of four photodiodes).

[0030] Pixel 105 also includes additional components (in-pixel circuitry) to facilitate optical sensing using photosensor block 110. As shown, embodiments may include a dual conversion gain (DCG) block 120, a reset block 130, a source follower block 140, and a selection block 150. Each can be implemented using at least one corresponding transistor. Reset block 130 can selectively reset pixel 105 components. Source follower block 140 can support converting the output from photosensor block 110 into an electrical signal indicative of optical information detected by photosensor block 110. Selection block 150 can support selecting a pixel 105 signal from the array of pixels 105, for example, in response to a control signal received via bus 160. For example, bus 160 can be a column select bus, etc.

[0031] Many applications are driving a continued reduction in the size of imaging sensors, which is driving a corresponding reduction in the size of the imaging pixels 105. In order to maintain high conversion gain over a large dynamic range, some modern CIS applications use dual conversion gain (DCG), such as implemented by the DCG block 120. Using DCG, each imaging pixel 105 can effectively operate in a high gain mode to provide a higher amount of conversion gain in low light conditions, or in a low gain mode to provide a lower amount of gain in high light conditions (e.g., to avoid saturation or other undesirable effects). Typically, as shown, DCG is implemented by adding a separate DCG block 120 (i.e., at least one separate DCG transistor) to the in-pixel circuitry. Turning on the DCG transistor can effectively increase the well capacity to reduce the conversion gain, and turning off the DCG transistor can effectively reduce the well capacity to increase the conversion gain.

[0032] For added context, Figure 2 An example of a conventional CIS imaging pixel 200 with conventional in-pixel circuitry is shown. The pixel 200 may be Figure 1 1. An embodiment of a conventional pixel 105 of FIG. 1 includes an embodiment of a photosensor block 110, a DCG block 120, a reset block 130, a source follower block 140, and a select block 150. The photosensor block 110 is shown as a simplified pinned photodiode (PPD) 210 configured for backside illumination, but similar concepts can be applied to other types of photodiode embodiments. The photosensor block 110 and the reset block 130 (as well as the other blocks of the pixel 200) are implemented on a semiconductor substrate 207, such as a doped silicon wafer.

[0033] The photosensor block 110 includes a transfer gate 215, which can be activated by a Tx signal and can be isolated from the substrate 207 by an oxide layer 220. The substrate 207 can have a first doping type (e.g., P-type). The PPD 210 can be formed by implanting at least a collector region 230 of a second doping type (e.g., N-type) in the substrate 207 on one side of the transfer gate 215, and implanting a floating diffusion region 235 of the second doping type in the substrate 207 on the other side of the transfer gate 215. An isolation region 240 (e.g., shallow trench isolation, STI) can be formed to electrically isolate the structure of the photosensor block 205 from the structure of adjacent photosensor blocks and / or pixels.

[0034] When the photons reach the back side of the substrate 207 (e.g., as shown by arrow 243), they can be converted into photocarriers (i.e., electrons and holes), one of which is attracted and collected in the collection region 230 (e.g., as shown by dashed arrow 245). The accumulation of photocarriers in the collection region 230 can generally be considered as an accumulation of charge. For example, longer and / or brighter exposures can result in more charge accumulation in the collection region 230. Activating the Tx signal can form a depletion region below the transfer gate 215, which effectively becomes a current channel between the two second doped type (e.g., N-type) regions (the collection region 230 and the floating diffusion region 235). Thus, activation of the transfer gate 215 causes the charge accumulated in the collection region 230 to be transferred through the current channel to the floating diffusion region 235.

[0035] As shown, the intra-pixel circuitry is typically interfaced with the photosensor block 110 via the floating diffusion region 235. For example, components of the intra-pixel circuitry are used to read out the accumulated charge after it is transferred to the floating diffusion region 235. Before transferring the accumulated charge from the collection region 230 to the floating diffusion region 235, the reset block 130 can be used to effectively clear the accumulated charge from the floating diffusion region 235 to reset the pixel 200. Transferring the accumulated charge from the collection region 230 to the floating diffusion region 235 can effectively generate a gate voltage at the gate electrode of the source follower block 140 (corresponding to the amount of accumulated charge transferred to the floating diffusion region 235). As shown, the selection block 150 is coupled between the source terminal and the output voltage terminal (Vout) of the source follower block 140, and the constant current source is coupled between Vout and ground. Thus, when the select block 150 is activated (eg, as part of a row select operation), an output voltage is generated at Vout based on the gate voltage at the source follower block 140 (ie, therefore based on the accumulated charge transferred to the floating diffusion region 235).

[0036] As can be seen, the reset block 130 is implemented as a conventional MOSFET having an n-type source region (i.e., floating diffusion region 235) and an n-type drain region 255 implanted in a semiconductor substrate 207 (e.g., p-doped silicon). A multi-gate structure 250 having a reset gate electrode (labeled as RST) is patterned on top of a gate oxide layer 220 (i.e., a metal oxide layer) on the substrate 207, such that the gate oxide layer 220 electrically isolates the multi-gate structure 250 from the floating diffusion (source) region 235 and the drain region 255, and defines a channel region between the floating diffusion (source) region 235 and the drain region 255. Applying a positive gate voltage to the reset gate terminal can attract negative charge into the channel region between the n-doped floating diffusion (source) region 235 and the drain region 255, which forms an n-type current channel (turning on the transistor). Alternatively, the drain and source regions can be p-doped regions implanted into an n-doped substrate, and applying a negative gate voltage to the gate terminal can attract positive charge (e.g., repel negative charge) to the channel region between the p-doped source and drain regions to form a p-type current channel (turning on the transistor).

[0037] The gate oxide layer 220 forms a dielectric insulator layer between the multi-gate structure 250 and the transistor current channel, electrically insulating the gate electrode from the semiconductor n-channel or p-channel. Traditionally, the gate oxide layer 220 is formed using a metal oxide, such as silicon dioxide. With this insulated multi-gate structure 250 design, no current flows through the gate electrode; instead, a voltage applied to the gate electrode generates an electric field in the channel region to control the conductivity of the current channel.

[0038] The performance of an imaging sensor pixel is related to how well the pixel can convert photons into electrical charge. This performance can depend on many physical and electrical properties of the pixel, such as well capacity, dynamic range, and conversion gain. Well capacity is related to the amount of charge that an imaging pixel can hold during integration (i.e., during exposure, before readout). It is desirable to have a large dynamic range, which means that the pixel performs well under a wide range of lighting conditions, such as from very low light conditions up to high light conditions (i.e., conditions under which full well capacity or FWC can be reached). It is also desirable to have a higher conversion gain, which means that with any increase in accumulated charge, the output signal voltage increases significantly.

[0039] Typically, the output signal level corresponds to the ratio between the charge accumulated in the well and the well capacitance. For example, a smaller well may tend to have less capacity to accumulate charge and correspondingly have a smaller well capacitance, which may tend to result in larger changes in the output signal level for any change in charge accumulation in the well. As pixels decrease in size, their well capacitance also decreases. As mentioned above, to help maintain high conversion gain over a large dynamic range, many modern imaging sensors include DCG. Figure 2As shown, such DCG is typically implemented in a conventional imaging pixel by adding a DCG block 120 that includes at least a DCG transistor (e.g., some embodiments also include additional DCG transistors, capacitors, amplifiers, and / or other components). When the DCG transistor is turned on, it can be seen that the DCG transistor effectively adds well capacitance to the floating diffusion region 235 (e.g., and also increases the accumulated charge stored in the capacitor). The increased well capacitance can place the DCG block 120 in a low conversion gain mode, such that changes in the amount of charge transferred to the floating diffusion region 235 have a relatively small effect on the output signal level at Vout. As a corollary, turning off the DCG transistor tends to effectively reduce the well capacitance (i.e., or not increase the well capacitance), which can place the DCG block 120 in a high conversion gain mode, such that changes in the amount of charge transferred to the floating diffusion region 235 have a relatively large effect on the output signal level at Vout.

[0040] Figure 3A and 3B A simplified layout diagram 300 and a simplified circuit diagram 350 are shown, respectively, of another illustrative conventional embodiment of a CIS imaging pixel. Figure 1 and Figure 2 In the simplified layout diagram 300 and the simplified circuit diagram 350, the imaging pixel is shown as having a photosensor block 110 (here, having four photodiodes 115), a DCG block 120, a reset block 130, a source follower block 140, and a selection block 150. In the simplified layout diagram 300 and the simplified circuit diagram 350, it can be seen that a designated transistor is used to reset the photocharge stored in the imaging pixel (i.e., the reset block 130), and a separately designated transistor is used to provide the imaging pixel with DCG (i.e., the DCG block 120). The floating diffusion area 235 is also labeled in both views. As described above, the total capacitance and conversion gain of the floating diffusion area 235 are modulated by the DCG block 120 coupled to the floating diffusion area 235 and the reset block 130 (i.e., through the separately designated DCG transistor). Under higher light conditions, the low conversion gain mode is used to achieve higher full well capacity and wider dynamic range; under lower light conditions, the high conversion gain mode is used to reduce readout noise and achieve improved low light sensing performance.

[0041] While conventional implementations of DCG are often effective, adding at least one DCG transistor (e.g., a capacitor and / or additional components) may be undesirable. For example, the space of a pixel (e.g., imaging pixel 200) is shared by the photosensor block 110 and the in-pixel circuitry, and any addition of in-pixel circuitry components may tend to reduce the space available for the photosensor block 110's photodiode(s) 115 and / or other components, and / or may increase complexity, process variations, etc. Embodiments disclosed herein include a novel structure that effectively combines the reset block and the DCG block into a single hybrid transistor. The hybrid transistor, referred to herein as the Fe-MOSFET, combines the characteristics of a MOSFET with those of a ferroelectric field-effect transistor (Fe FET) by including a hybrid gate insulating layer comprising a dielectric segment and an Fe segment formed between the gate electrode and the channel region of the field-effect transistor. A first set of voltage levels can be applied at the gate terminal to switch the Fe segment between a high DCG mode and a low DCG mode, and a second set of voltage levels can be applied at the same gate terminal to switch the dielectric segment between a reset-ON mode and a reset-OFF mode in either of the DCG modes.

[0042] To add context, Figure 4 The behavior of a ferroelectric (Fe) material used as a gate insulating layer for a field effect transistor (FET) is demonstrated, as used in a conventional Fe-FET 400. As in a MOSFET, the Fe-FET 400 can be formed by implanting a drain region and a source region of a second doping type (e.g., n-type) into a silicon substrate of a first doping type (e.g., p-type), and patterning a gate structure having a gate electrode on the substrate, isolated from the substrate and the drain and source regions by an insulating layer. In the typical metal oxide insulating layer of a MOSFET, the charge distribution is often random and / or otherwise unpredictable. In contrast, the insulating layer of the Fe-FET 400 uses a ferroelectric material having a dipole that can be aligned by applying a voltage of a specific polarity and magnitude across the material.

[0043] Figure 4 A conventional Fe-FET 400 is shown in two polarization states. In the first polarization state (corresponding to Figure 4 In the Fe-FET 400a on the left, the dipoles in the Fe material are arranged with their positive sides pointing toward the substrate, thereby attracting negative charges (e.g., electrons) into the channel region between the drain and source regions. In the second polarization state (corresponding to Figure 4In the right-hand Fe-FET 400b, the dipoles in the Fe material align with their negative sides pointing toward the substrate, thereby attracting positive charge (e.g., attracting holes and repelling electrons) into the channel region between the drain and source regions. In the NPN doping configuration shown (i.e., with a p-doped substrate and n-doped source and drain regions), turning on the transistor involves applying a sufficiently high voltage to the gate terminal to form an n-channel. In the left-hand polarization state represented by Fe-FET 400a (where negative charge is already attracted to the channel region by the Fe material), only a relatively small positive gate voltage needs to be applied to form the n-channel. Therefore, in this state, the switching voltage (e.g., threshold voltage or Vth) is relatively low. However, in the right-hand polarization state represented by Fe-FET 400a (where negative charge is pushed away from the channel region by the Fe material), forming the n-channel can involve applying a relatively large positive gate voltage. Therefore, in this state, the switching voltage is relatively high.

[0044] Drain current-gate voltage graph 450 shows the relationship between drain current on the vertical axis and gate voltage on the horizontal axis for two different ferroelectric states. Curve 452 shows the drain current-gate voltage relationship for the polarization state represented by Fe-FET 400a (ferroelectric state), while curve 454 shows the drain current-gate voltage relationship for the polarization state represented by Fe-FET 400b (ferroelectric state). As shown in drain current-gate voltage graph 450, Fe-FET 400 is a relatively bi-stable device, with a relatively large separation between the Vth levels in each polarization state. Due to this property, Fe-FET 400 devices are often used to construct low-power non-volatile memories with fast random access, known as ferroelectric random access memories (FRAMs), with improved multi-read and write performance.

[0045] As noted above, embodiments described herein include a novel hybrid structure referred to herein as a Fe-MOSFET. Figure 5 A CIS imaging pixel 500 is shown incorporating in-pixel circuitry having an illustrative hybrid reset-DCG (HRD) block 510 implemented with a novel Fe-MOSFET structure, in accordance with various embodiments described herein. Figure 2 , imaging pixel 500 includes photosensor block 110 (shown as including conventional PPD 210), source follower block 140, and selection block 150. Unlike in Figure 2 In FIG. 5 , the intra-pixel circuitry does not include a designated reset block and a separately designated DCG block. Instead, the intra-pixel circuitry includes HRD block 510 to effectively implement both the reset block and DCG block features.

[0046] As shown, the Fe-MOSFET structure of the HRD block 510 is formed by implanting source and drain regions into the semiconductor substrate 207. For example, the substrate 207 is p-doped and the source and drain regions are n-doped; or the substrate 207 is n-doped and the source and drain regions are p-doped. The source region corresponds to the floating diffusion region 235 of the photosensor block 110. A multi-gate structure 530 (labeled as RST-DCG 535) with a reset DCG electrode 535 is patterned on top of the isolation layer on the substrate 207, such that the isolation layer electrically isolates the multi-gate structure 530 from the floating diffusion (source) region 235 and the drain region 255 and defines a channel region between the floating diffusion (source) region 235 and the drain region 255. In some embodiments, the drain region 255 is coupled to a reference voltage (e.g., Vdd).

[0047] As shown, the isolation layer beneath the multi-gate structure 530 includes an Fe segment 520 and a dielectric segment 525. The Fe segment 520 is formed by depositing a ferroelectric material layer, as described above. A variety of suitable materials can be used to form the hybrid structure. For example, the Fe material can include HfZrO, PbTiO, BiTiO, etc. The dielectric segment 525 is formed by depositing a metal oxide layer. For example, the dielectric segment 525 is part of the gate oxide layer 220 and / or is fabricated simultaneously with other portions of the gate oxide layer 220. In practice, a first portion of the channel region is directly beneath the Fe segment 520, and a second (non-overlapping) portion of the channel region is directly beneath the dielectric segment 525. In one embodiment, approximately half of the channel region is directly beneath the Fe segment 520, and the remaining approximately half of the channel region is directly beneath the dielectric segment 525. The dielectric segment 525 can comprise any suitable metal oxide or higher-k dielectric material. For example, the dielectric segment can be made of silicon dioxide with a dielectric constant k of approximately 3.9 and / or other suitable dielectric materials, such as higher-k dielectric materials with k values ​​greater than 10 (e.g., HfSiO4 with k of approximately 11, hafnium oxide or zirconium dioxide with k of approximately 25, titanium dioxide with k of approximately 22, etc.). The reset DCG electrode 535 can include a suitable conductive material, such as a doped dielectric material (e.g., polysilicon) and a suitable metal or metals. To implement a high-speed FET, the dielectric segment 525 can be a higher-k dielectric and the multi-gate structure 530 can be a metal gate having one or more metal layers.

[0048] A control voltage signal can be applied to the reset DCG electrode 535 to control both the reset and DCG characteristics of the HRD block 510. For example, applying a relatively large magnitude voltage to the reset DCG electrode 535 with a first polarity can cause the dipoles in the Fe segment 520 to align with their positive ends pointing toward the channel region. This causes negative charge to be attracted to the portion of the channel region directly below the Fe segment 520 and adjacent to the floating diffusion region 235, effectively adding well capacity to that of the floating diffusion region 235 and placing the HRD block 510 in a low conversion gain mode. Applying a relatively large magnitude voltage to the reset DCG electrode 535 with a second (opposite) polarity can cause the dipoles in the Fe segment 520 to align with their negative ends pointing toward the channel region. This causes negative charge to be pushed away from the portion of the channel region directly below the Fe segment 520, thereby not adding well capacity to the floating diffusion region 235 and placing the HRD block 510 in a high conversion gain mode. In either conversion gain mode, a lower amplitude voltage may be applied to the reset DCG electrode 535 to control the formation of a current channel in the portion of the channel region directly beneath the dielectric segment 525 , thereby controlling the reset characteristics of the HRD block 510 .

[0049] Figure 6A and 6B A simplified layout diagram 600 and a simplified circuit diagram 650 are shown, respectively, of an illustrative implementation of a novel CIS imaging pixel having an HRD block 510 according to various embodiments described herein. Figure 5 As described, the novel CIS imaging pixel includes a photosensor block 110 (here, with four photodiodes 115), a source follower block 140, a selection block 150, and an HRD block 510. In the simplified layout diagram 600 and in the simplified circuit diagram 650, it can be seen that a single transistor structure (i.e., a Fe-MOSFET) is used to reset the stored photocharge in the imaging pixel and to provide DCG for the imaging pixel. The floating diffusion region 235 is also labeled in both views. As described above, the total capacitance and conversion gain of the floating diffusion region 235 are modulated by triggering the ferroelectric polarization state of the Fe-MOSFET in the HRD block 510. Under higher light conditions, a low conversion gain mode is used to achieve higher full well capacity and wider dynamic range; under low light conditions, a high conversion gain mode is used to reduce readout noise and improve low light sensing performance.

[0050] Figure 7AAn example of a simplified timing diagram 700 for directing the operation of the HRD block 510 according to various embodiments described herein is shown. In particular, the timing diagram includes illustrative timing of a select control signal applied to the select block 150 (e.g., a gate voltage applied to a select transistor of the select block 150), a control signal applied at the reset DCG electrode 535 of the HRD block 150, and a control signal applied to the gate terminal of the transfer gate 215. The timing diagram 700 includes two identical cycles of a periodic signaling protocol, each cycle having six specific time positions identified (labeled "T0"-"T5").

[0051] To make it clearer, Figure 7B The case where the Fe segment 520 of the HRD block 510 is set to the high conversion gain mode is shown in FIG. Figure 7A A series of simplified band diagrams at the time positions indicated in , and Figure 7C The case where the Fe segment 520 of the HRD block 510 is set to the low conversion gain mode is shown in FIG. Figure 7A A series of simplified band diagrams at the time positions indicated in . Figure 7B and 7C Discussion and Figure 7A For example, Figure 7B and 7C The topmost band diagram in each of corresponds to the band diagram at time T0 as marked; the sequence proceeds down the drawing until Figure 7B and 7C The bottommost band diagram in each of the energy band diagrams corresponds to the band diagram at time T5 as marked. The vertical dashed lines in each energy band diagram indicate approximate structural boundaries. For example, each energy band diagram indicates an energy band diagram corresponding to the semiconductor substrate 207, the photodiode 115 (e.g., PPD 210) of the photosensor block 110, the transfer gate 215 of the photosensor block 110, the floating diffusion region 235 shared by the photosensor block 110 and the HRD block 510, and the HRD block 510. Within the HRD block 510, the dashed lines indicate the energy bands directly below the Fe segment 520 and the dielectric segment 525, respectively. The bold horizontal lines in the energy band diagrams indicate illustrative amounts of accumulated charge in specific structural regions.

[0052] At the beginning of each cycle, the control signal of the selection block 150 is asserted to turn on the selection block 150. For example, the row corresponding to the particular pixel being signaled is currently selected. At T0, Figure 7A A relatively large “write” pulse 702a is shown applied at the reset DCG electrode 535 to select the ferroelectric polarization state of the Fe segment 520 (ie, of the Fe-MOSFET) of the HRD block 510 . Figure 7BThe first energy band illustrates a situation in which a high-amplitude, negative-polarity write pulse 702 sets the Fe segment 520 into a ferroelectric polarization state that exhibits a relatively small FWC (indicated by arrow 710). For example, the write pulse orients the dipole of the Fe segment 520 material with its negative end pointing toward the channel region, thereby repelling negative charge from the channel region. In such an orientation, the effective FWC can be substantially equal to or less than the effective FWC of the floating diffusion region 235 itself. In contrast, Figure 7C The first band diagram shows the case where a high amplitude, positive polarity write pulse 702b sets the Fe segment 520 into a ferroelectric polarization state exhibiting a relatively large FWC (indicated by arrow 720). For example, the write pulse orients the dipoles of the Fe segment 520 material with their positive poles pointing toward the channel region, thereby attracting negative charge from the channel region. In such an orientation, the effective FWC is greater than the effective FWC of the floating diffusion region 235 itself. This can be seen in FIG. Figure 7C As can be seen from the band diagram of , there may be accumulated charge in the photodiode 115 (eg, in the collection region), and there may also be some accumulated charge in the floating diffusion region 235 (eg, from a previous charge transfer in a previous cycle).

[0053] At T1, Figure 7A A first reset pulse 704a is shown applied at the reset DCG electrode 535. As can be seen, the amplitude of the reset pulse 704 is significantly lower than the amplitude of the write pulse 702, such that the reset pulse 704 does not switch the ferroelectric polarization state of the Fe segment 520. Figure 7B and 7C The second energy band diagram shows that the first reset pulse 704a causes a significant drop in the energy band associated with the HRD block 510. Substantially all of the accumulated charge remaining in the floating diffusion area 235 from the previous cycle is flushed out of the floating diffusion area 235. In some cases, as shown, in the low conversion gain mode, a small amount of accumulated charge may remain in the floating diffusion area 235 and / or in the additional well capacity below the Fe segment 520.

[0054] Figure 7A T2 shows the time after the first reset pulse 704a but before the charge transfer across the transfer gate 215. At T2, the first reset pulse 704a is no longer active. Figure 7B and 7C As can be seen in the third energy band diagram of , the energy bands at the various structural regions return to levels similar to those of the energy band diagram at T0, except that substantially all previously accumulated charges have flushed out of the floating diffusion region 235.

[0055] At T3, Figure 7A A transfer pulse 706 is shown applied at the gate electrode of the transfer gate 215 to turn on the transfer gate 215 . Figure 7B and7C The fourth energy band diagram in FIG shows that the transfer pulse 706 causes a significant drop in the energy band associated with the transfer gate 215 (regardless of the ferroelectric polarization state). As a result, the accumulated charge efficiently flows out of the transfer gate 215 and into at least the floating diffusion region 235. In the high conversion gain mode, as in Figure 7B As can be seen in the fourth energy band diagram of FIG, based on the capacity of the floating diffusion region 235, the charge previously accumulated in the transfer gate 215 (e.g., from the exposure of the photosensor block 110 to light) flows out of the transfer gate 215 and into the floating diffusion region 235. In the low conversion gain mode, as Figure 7C As shown in the fourth energy band diagram in FIG, the charge previously accumulated in the transfer gate 215 flows out of the transfer gate 215 and into the extended capacity well provided by the floating diffusion region 235 and the area under the Fe segment 520.

[0056] At T4, Figure 7A The transfer pulse 706 is shown deactivated to turn the transfer gate 215 back off. At this point, the accumulated charge can be read out by the readout structure (e.g., via the source follower block 140). Figure 7B and 7C It can be seen from the fifth energy band diagram in that the energy bands at various structural regions return to a level similar to the energy bands of the energy band diagram at T2, where the transferred charges are effectively captured in the floating diffusion region 235 in the high conversion gain mode or in the extended capacity well provided by the floating diffusion region 235 and the area below the Fe segment 520 in the low conversion gain mode.

[0057] At T5, Figure 7A Application of a second reset pulse 704b at the reset DCG electrode 535 is shown. Figure 7B and 7C The sixth energy band diagram in FIG shows that the second reset pulse 704b causes substantially the same change in the energy band as described with reference to T1. This allows for the flushing out of substantially all of the accumulated charge that is transferred to the floating diffusion region 235 in the high conversion gain mode or to the extended capacity well provided by both the floating diffusion region 235 and the region below the Fe segment in the low conversion gain mode. Figure 7A As shown, some embodiments of the timing diagram 700 may also include a shutter pulse 708 .

[0058] By comparison Figure 7B The energy band diagram and Figure 7CFrom the energy band diagram, it can be seen that the reset feature of the HRD block 510 operates in essentially the same manner regardless of the ferroelectric polarization state of the Fe segment 520. However, when the Fe segment 520 is set to the high conversion gain mode, there is a smaller FWC that is actually associated with the floating diffusion region 235, and there is a higher energy barrier associated with applying a zero voltage level to the reset DCG electrode 535. As a corollary, when the Fe segment 520 is set to the low conversion gain mode, there is a larger FWC that is actually associated with the floating diffusion region 235 (with additional well capacity formed below the Fe segment 520), and there is a lower energy barrier associated with applying a zero voltage level to the reset DCG electrode 535. This can be seen in FIG. Figure 8A This is more clearly seen in Figure B.

[0059] Figure 8A An illustrative graph 800 of electric field magnitude versus polarization for a Fe-MOSFET structure used in embodiments of the HRD block 510 described herein is shown. Figure 8B Shown Figure 8A The corresponding energy band diagram 850 for each of the four states on the graph 800 of FIG. As described above, a relatively high voltage in either polarization can be applied at the reset DCG electrode 535 to write the Fe segment 520 into either of the two ferroelectric polarization states. Once set to a particular ferroelectric polarization state, a lower amplitude voltage signal can be applied at the reset DCG electrode 535 to turn the channel on or off (e.g., similar to a conventional MOSFET). Figure 8A , four illustrative states 810 of the Fe-MOSFET structure are shown. In the first state 810a, a high magnitude positive polarity voltage is applied at the reset DCG electrode 535 to write the Fe segment 520 into a high conversion gain mode. Figure 8B , the corresponding energy band diagram 850a shows a relatively high energy band in the channel region of the Fe-MOSFET. Figure 8A In the second state 810b shown, a high magnitude negative polarity voltage is applied at the reset DCG electrode 535 to write the Fe segment 520 into a low conversion gain mode. Figure 8B , the corresponding energy band diagram 850b shows a relatively low energy band in the channel region of the Fe-MOSFET.

[0060] Figure 8AThe third state 810c and the fourth state 810d shown correspond to the write pulse being turned off after writing the Fe segment 520 to the high conversion gain mode or the low conversion gain mode, respectively. Referring to the third state 810c, the write pulse is turned off after reaching state 810a (i.e., setting the device to the high conversion gain mode), which causes the dipoles in the Fe segment 520 to be slightly misaligned, thereby causing the energy band to drop by a relatively small amount. In this state 810c, it can be seen that the energy barrier in the Fe segment 520 remains high even when a zero voltage level is applied to the reset DCG electrode 535. This is in Figure 8B This is also evident in the corresponding energy band diagram 850c shown in FIG. Similarly, in the fourth state 810d, after reaching state 810b (i.e., setting the device to low conversion gain mode), the write pulse is turned off, which causes the dipoles in the Fe segment 520 to be slightly misaligned to pump the energy band by a relatively small amount. In this state 810d, it can be seen that the energy barrier in the Fe segment 520 remains low even when a zero voltage level is applied to the reset DCG electrode 535. This is shown in FIG. Figure 8B This is also evident in the corresponding band diagram 850d shown.

[0061] In fact, it can be seen that applying a relatively high amplitude pulse effectively writes the Fe segment 520 into one or the other of the two ferroelectric polarization states, corresponding to the high or low conversion gain mode. After deactivating the pulse, the device remains in the corresponding high or low conversion gain mode. In this state (e.g., state 810c or 801d), there is a range of voltage levels (indicated by arrow 820) that can be applied to the reset DCG electrode 535 to open or close the channel without switching the ferroelectric polarization of the device. Thus, for example, as described with reference to the timing diagram 700 of FIG7, the DCG and reset features of the HRD block 510 can be controlled by applying voltage signals with different amplitudes and polarities at the same reset DCG electrode 535.

[0062] As described above, embodiments of the HRD block 510 incorporate a novel hybrid Fe-MOSFET structure. Embodiments may also include a novel fabrication process for fabricating the Fe-MOSFET structure. Figure 9 An example flow chart of a process 900 for fabricating an Fe-MOSFET structure according to various embodiments described herein is shown. Some portions of the fabrication process may be similar to those used to fabricate a conventional MOSFET. However, unlike conventional MOSFET fabrication processes, fabrication of an Fe-MOSFET structure may involve depositing and patterning (e.g., etching) a ferroelectric material layer in addition to forming (e.g., growing) a metal oxide layer.

[0063] In the illustrated manufacturing process 900, a ferroelectric material layer is deposited before forming a metal oxide layer. Specifically, as shown, a ferroelectric material layer is deposited at stage 904. At stage 908, an etch mask may be applied on top of the region corresponding to the Fe segment 520 where the ferroelectric material is deposited. At stage 912, portions of the ferroelectric material layer not masked by the etch mask are removed to leave only the Fe segment 520. At stage 916, a gate oxide layer may be formed to include at least a portion adjacent to the Fe segment 520 and corresponding to the dielectric segment 525. At stage 920, a gate material (e.g., polysilicon) may be deposited and etched to form a multi-gate structure 530 on top of the Fe segment 520 and the dielectric segment 525.

[0064] Figure 10 A flow chart is shown of an illustrative method 1000 for generating pixel output signals with dual conversion gain in a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), according to various embodiments described herein. Embodiments of method 1000 can be performed using embodiments of the hybrid reset DCG block described above, including features using hybrid Fe-MOSFETs. Some embodiments of method 1000 correspond to timing diagram 700 of FIG. 7 .

[0065] An embodiment may begin at stage 1004 by delivering a write pulse having a write amplitude and one of two write polarizations to the gate electrode of the hybrid Fe-MOSFET. The write pulse writes the Fe segment of the Fe-MOSFET into a selected one of two conversion gain modes by aligning the dipoles of the ferroelectric material into a corresponding one of two ferroelectric polarization states depending on the write polarization delivered by the write pulse. For example, a write pulse of a first write polarization aligns the dipoles in a first orientation corresponding to a low conversion gain mode, while a write pulse of a second write polarization aligns the dipoles in a second orientation corresponding to a high conversion gain mode.

[0066] At stage 1008, embodiments may deliver a reset pulse at a reset amplitude to the gate electrode of the hybrid Fe-MOSFET after delivering the write pulse. The reset amplitude is significantly less than the write amplitude (e.g., less than half) such that the dielectric segment responds to the reset pulse to form a current channel across the channel region between the source and drain regions without affecting the alignment of the dipoles in the Fe segment. For example, as described above, after the write pulse ends, the Fe segment effectively relaxes to one of two stable states, wherein a range of voltages can be applied to the gate electrode without switching the state of the Fe segment.

[0067] In some embodiments, the source region of the Fe-MOSFET is a floating diffusion region of the photosensor block (e.g., supported by the same semiconductor substrate). In such embodiments, at stage 1012, method 1000 may expose the photosensors of the photosensor block to incident illumination to accumulate photocarriers in the photosensor block. At stage 1016, such embodiments may transmit a transfer signal to a transfer gate of the photosensor block after transmitting the write pulse and the reset pulse to transfer the accumulated photocarriers to the floating diffusion region. At stage 1020, some such embodiments may further read out the accumulated photocarriers from the floating diffusion region to generate a pixel output signal. The pixel output signal is generated to correspond to the amount of accumulated photocarriers having a conversion gain based on a selected one of two conversion gain modes.

[0068] It will be understood that when an element or component is referred to as being "connected to" or "coupled to" another element or component in this article, it can be connected or coupled to another element or component, or an intermediate element or component may also exist. On the contrary, when an element or component is referred to as being "directly connected to" or "directly coupled to" another element or component, there is no intermediate element or component between them. It will be understood that although the terms "first", "second", "third", etc. can be used herein to describe various elements and components, these elements, components, and regions should not be limited by these terms. These terms are only used to distinguish one element or component from another element or component. Therefore, without departing from the teachings of the present invention, the first element or component discussed below can be referred to as the second element or component. As used herein, the terms "logic low", "low state", "low level", "logic low level", "low" or "0" are used interchangeably. The terms "logic high", "high state", "high level", "logic high level", "high" or "1" are used interchangeably.

[0069] As used herein, the terms "a", "an", and "the" may include both singular and plural references. It will be further understood that the terms "comprises", "includes", "having", and variations thereof, when used in this specification, specify the presence of stated features, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or groups thereof. In contrast, the term "consisting of", when used in this specification, specifies the stated features, steps, operations, elements, and / or parts, and excludes additional features, steps, operations, elements, and / or parts. Furthermore, as used herein, the word "and / or" may refer to and encompass any possible combination of the relevant listed one or more items.

[0070] Although the present invention has been described herein with reference to illustrative embodiments, this description is not intended to be construed as limiting. Rather, the purpose of the illustrative embodiments is to enable those skilled in the art to better understand the spirit of the present invention. In order not to obscure the scope of the present invention, many details of well-known processes and manufacturing techniques have been omitted. Various modifications of the illustrative embodiments and other embodiments will be apparent to those skilled in the art when referring to the description. Therefore, the appended claims are intended to cover any such modifications.

Claims

1. A complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), comprising: Imaging pixels include: a semiconductor substrate doped according to a first doping type; a photosensor block including at least one photodiode configured to accumulate photocarriers in response to exposure to illumination and to transfer the accumulated photocarriers to a floating diffusion region for readout, the floating diffusion region being formed by implanting a first well of a second doping type into the semiconductor substrate, the second doping type being different from the first doping type; and Hybrid ferroelectric-metal-oxide-semiconductor field-effect transistor (Fe-MOSFET) devices, including: a drain region formed by implanting a second well of a second doping type material into the semiconductor substrate, the drain region being separated from the floating diffusion region by a channel region; a gate structure deposited on the semiconductor substrate at least directly above the channel region and having a gate electrode patterned thereon; and a gate isolation layer formed on a surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer comprising: An Fe segment made of a ferroelectric material and sandwiched between the gate structure and a first channel sub-region of the channel region adjacent to the floating diffusion region, the Fe segment being configured to switch between a high conversion gain mode and a low conversion gain mode; and A dielectric segment is sandwiched between the gate structure and a second channel sub-region of the channel region that is adjacent to the drain region and does not overlap with the first channel sub-region.

2. The CIS according to claim 1, wherein: The Fe segment includes a plurality of dipoles; The plurality of dipoles are configured to align in a first orientation in response to receiving a write pulse of a first polarity at the gate electrode and remain aligned in the first orientation after the write pulse, the first orientation corresponding to positive ends of the plurality of dipoles pointing toward the first channel sub-region; and The plurality of dipoles are configured to align in a second orientation in response to receiving a write pulse of a second polarity opposite to the first polarity at the gate electrode, and to remain aligned in the second orientation after the write pulse, the second orientation corresponding to negative ends of the plurality of dipoles pointing toward the first channel sub-region.

3. The CIS according to claim 2, wherein: The dielectric segment is configured to form a current channel across the channel region between the floating diffusion region and the drain region in response to receiving a reset pulse having a lower magnitude than the write pulse at the gate electrode.

4. The CIS according to claim 3, wherein: The reset pulse has an amplitude less than half an amplitude of the write pulse.

5. The CIS according to claim 1, wherein: Each of the first channel sub-region and the second channel sub-region extends over approximately half of the channel region.

6. The CIS according to claim 1, wherein: The photosensor block includes a plurality of photodiodes configured to share the floating diffusion region.

7. The CIS according to claim 1, wherein: The at least one photodiode is an imaging pixel array supported by the semiconductor substrate and configured to generate pixel output signals in response to exposure to incident light such that the pixel output signals collectively represent image information of an image carried by the incident light.

8. The CIS according to claim 1, wherein: The at least one photodiode comprises: a collection region that accumulates photocarriers before the accumulated photocarriers are transferred to the floating diffusion region for readout, the collection region being separated from the floating diffusion region by a transfer channel region; and A transfer gate is deposited on the semiconductor substrate above the transfer channel region and has a transfer electrode patterned thereon, the transfer electrode forming a transfer current channel when actuated to transfer accumulated photocarriers from the collection region across the transfer channel region to the floating diffusion region.

9. The CIS according to claim 1, wherein: The imaging pixel further includes: A source follower block is supported by the substrate and coupled to the floating diffusion region to generate a pixel output signal representing the amount of accumulated photocarriers transferred to the floating diffusion region based on whether the Fe segment is currently switched to the high conversion gain mode or the low conversion gain mode.

10. The CIS according to claim 9, wherein: The imaging pixel further includes: A select block is supported by the substrate and coupled to the source follower block to respond to an applied select control signal when selecting or deselecting the imaging pixel.

11. A hybrid ferroelectric-metal-oxide-semiconductor field-effect transistor (Fe-MOSFET) device, comprising: a semiconductor substrate doped according to a first doping type; a source region and a drain region, each of the source region and the drain region being formed by implanting a corresponding well of a second dopant type material into the semiconductor substrate, the source region and the drain region being separated by a channel region; a gate structure deposited on the semiconductor substrate directly above at least the channel region and having a gate electrode patterned thereon; and a gate isolation layer formed on a surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer comprising: An Fe segment is made of a ferroelectric material and is sandwiched between the gate structure and a first channel sub-region of the channel region adjacent to the source region; and A dielectric segment is sandwiched between the gate structure and a second channel sub-region of the channel region that is adjacent to the drain region and does not overlap with the first channel sub-region.

12. The hybrid Fe-MOSFET device of claim 11 , wherein: The Fe segment includes a plurality of dipoles; the plurality of dipoles being configured to align in a first orientation in response to receiving a write pulse of a first polarity at the gate electrode and to remain aligned in the first orientation after the write pulse, the first orientation corresponding to positive ends of the plurality of dipoles pointing toward the first channel sub-region; and The plurality of dipoles are configured to align in a second orientation in response to receiving a write pulse of a second polarity opposite to the first polarity at the gate electrode, and to remain aligned in the second orientation after the write pulse, the second orientation corresponding to negative ends of the plurality of dipoles pointing toward the first channel sub-region.

13. The hybrid Fe-MOSFET device of claim 12, wherein: The dielectric segment is configured to form a current channel across the channel region between the source region and the drain region in response to receiving a reset pulse having a lower magnitude than the write pulse at the gate electrode.

14. The hybrid Fe-MOSFET device of claim 13, wherein: The reset pulse has an amplitude less than half an amplitude of the write pulse.

15. The hybrid Fe-MOSFET device of claim 11, wherein: Each of the first channel sub-region and the second channel sub-region extends over approximately half of the channel region.

16. The hybrid Fe-MOSFET device of claim 11, wherein: The ferroelectric material includes one or more of HfZrO, PbTiO or BiTiO.

17. The hybrid Fe-MOSFET device of claim 11, wherein: The gate structure is formed of a non-metallic material doped to be conductive.

18. A method for generating pixel output signals using dual conversion gains in a complementary metal oxide semiconductor (CMOS) imaging sensor (CIS), the method comprising: A write pulse at a write amplitude and one of two write polarizations is delivered to a gate electrode of a hybrid ferroelectric-metal-oxide-semiconductor field effect transistor, Fe-MOSFET, comprising: a source region and a drain region, each of the source region and the drain region being formed by implanting a well of a second doping type into a semiconductor substrate of a first doping type, the source region and the drain region being separated by a channel region; a gate structure deposited on the semiconductor substrate at least directly above the channel region and having a gate electrode patterned thereon; and a gate isolation layer formed on the surface of the semiconductor substrate to electrically isolate the gate structure from at least the channel region, the gate isolation layer comprising: an Fe segment and a dielectric segment, the Fe segment being made of a ferroelectric material and sandwiched between the gate structure and a first channel sub-region of the channel region adjacent to the source region, the dielectric segment being sandwiched between the gate structure and a second channel sub-region of the channel region adjacent to the drain region and not overlapping with the first channel sub-region; wherein a write pulse writes the Fe segment into a selected one of two conversion gain modes by arranging the dipoles of the ferroelectric material into a respective one of two ferroelectric polarization states according to which of the write polarizations is conveyed by the write pulse; and A reset pulse at a reset amplitude is transmitted to the gate electrode of the hybrid Fe-MOSFET after transmitting the write pulse, so that the dielectric segment responds to the reset pulse to form a current channel across the channel region between the source region and the drain region without affecting the arrangement of dipoles in the Fe segment, the reset amplitude being smaller than the write amplitude.

19. The method according to claim 18, wherein The source region is a floating diffusion region of a photosensor block supported by the semiconductor substrate, and further includes: A transfer signal is transmitted to the transfer gate of the photosensor block after transmitting the write pulse and the reset pulse to transfer accumulated photocarriers to the floating diffusion region, wherein the accumulated photocarriers are accumulated in the photosensor block in response to exposing one or more photosensors of the photosensor block to incident radiation.

20. The method according to claim 19, further comprising: Accumulated photocarriers are read out from the floating diffusion region to generate a pixel output signal corresponding to an accumulated photocarrier amount having a conversion gain based on a selected one of two conversion gain modes.

Images