Stress sensor and method for determining a gradient-compensated mechanical stress component

Abstract

The innovative solution described herein relates to a transistor-based stress sensor having a semiconductor substrate with first and second MOS transistor devices. The first MOS transistor device may have first and second MOS transistors with first and second source-drain channel regions, respectively, wherein the first and second MOS transistors are oriented to each other such that a current flows in the first source-drain channel region in the opposite direction to a current flows in the second source-drain channel region. The second MOS transistor device may have third and fourth MOS transistors with third and fourth source-drain channel regions, respectively, wherein the third and fourth MOS transistors are oriented to each other such that a current flows in the third source-drain channel region in the opposite direction to a current flows in the fourth source-drain channel region. The transistor-based stress sensor provides a gradient-compensated output signal, which is used to determine a mechanical stress component acting on the semiconductor substrate.

Description

Technical Field

[0001] The innovative approach described herein relates to a transistor-based stress sensor disposed on a semiconductor substrate. This transistor-based stress sensor is used to determine mechanical stress components acting on the semiconductor substrate. Because the transistors within the transistor-based stress sensor have the innovative arrangement described herein, parameter gradients that may affect the determination of stress components can be fully or at least partially compensated. Therefore, the transistor-based stress sensor described herein enables gradient-compensated determination of mechanical stress components. The innovative approach described herein also relates to a method for gradient-compensated determination of mechanical stress components using this transistor-based stress sensor. Background Art

[0002] A stress sensor is designed to determine mechanical stress components, such as mechanical shear stress, mechanical total stress, or mechanical differential stress. The stress sensor described herein is a transistor-based stress sensor having multiple transistors. The mechanical stress components can be determined based on the output signals of the transistor-based stress sensor.

[0003] This output signal can be superimposed by undesirable effects, which can lead to inaccuracies in the determination of the stress components. Static effects that do not change over time can be compensated for with relatively simple means. In contrast, temporally variable effects (whose magnitude changes over time) are significantly more difficult to compensate for. Therefore, so-called aging effects often occur in electronic circuit components as they age, and these aging effects can lead to undesirable properties. However, such aging effects can only be calibrated or compensated for with difficulty.

[0004] The temporal variation of a particular parameter can be described using a gradient. For example, a gradient can describe the direction and magnitude of the temporal variation of the parameter. For example, a heat source generates increasing amounts of heat as the current supplied increases. This increase in heat can be represented by a thermal gradient.

[0005] This temporally variable gradient-based effect influences the output signal of the strain sensor in an undesirable manner, i.e., distorts the output signal of the strain sensor. More generally, the output signal of the strain sensor is undesirably influenced or distorted in the presence of one or more gradients by the direction and / or magnitude of the respective gradients. Thus, for example, in the presence of a thermal gradient, the output signal of the strain sensor becomes increasingly distorted as the heat increases.

[0006] It is therefore desirable to provide a stress sensor that provides a gradient-compensated output signal such that the output signal is substantially gradient-free. The gradient to be compensated is preferably a first-order gradient.

[0007] These gradient-based effects can have various causes. Thermal gradients can vary, for example, due to variable heating power. However, there are also layout gradients, which can vary depending on the layout of the circuits on the semiconductor substrate. Varying, non-uniform stress effects, which can arise due to varying global stresses in the plastic housing, also undesirably influence the determination of the mechanical stress components. This includes, for example, variable global stresses, which can be caused by the packaging process itself, by moisture, or by soldering.

[0008] Transistor-based strain sensors can preferably be integrated into a semiconductor substrate as part of a circuit arrangement. Integrated circuit arrangements, or integrated circuits (ICs), are often mounted in housings to protect the sensitive ICs from environmental influences. However, an undesirable side effect is that even the placement and installation of the ICs in the housing can exert significant mechanical stresses on the semiconductor material and, therefore, on the semiconductor substrate of the IC. This is particularly true for cost-effective housing designs designed for mass production, such as those in which the ICs are overmolded with a potting compound.

[0009] Due to various piezoelectric effects in semiconductor materials, such as the piezoresistive effect, the piezoelectric MOS effect, the piezoelectric junction effect, the piezoelectric Hall effect, and the piezoelectric tunneling effect, the mechanical stresses acting on the integrated circuit device also influence important electrical or electronic parameters of the integrated circuit device. In this context, the term "piezoelectric effect" generally refers to the change in electrical or electronic parameters of a circuit device integrated in the semiconductor material under the influence of mechanical stress in the semiconductor material.

[0010] Mechanical stress in semiconductor materials causes changes in charge carrier properties with respect to charge carrier transport, such as mobility, collision time, scattering factor, and Hall constant. Generally speaking, the piezoresistive effect describes the resistivity of a corresponding semiconductor material under the influence of mechanical stress. Furthermore, the piezoelectric junction effect causes changes in the characteristic curves of diodes and bipolar transistors. The piezoelectric Hall effect describes the dependence of the Hall constant of a semiconductor material on the mechanical stress state within the semiconductor material. Piezoelectric tunneling occurs at reverse-driven, highly doped, flat lateral pn junctions. This current flow is dominated by band-to-band tunneling and is also stress-dependent. The piezoresistive effect and the expression "piezoelectric MOS effect," which sometimes appears in the literature, can be categorized as equivalent, as the piezoelectric MOS effect is essentially identical to the piezoresistive effect: the mobility of charge carriers in the MOS channel of a MOS field-effect transistor changes under the influence of mechanical stress in the semiconductor material of an integrated circuit chip.

[0011] It is therefore clear that due to the presence of mechanical stress in the semiconductor material of an integrated circuit device, the electrical or electronic characteristics of the integrated circuit device may not be changed or affected in a predictable manner. In many cases, a degradation in the performance (behavior or parameters) of the integrated circuit device can be observed, for example, in the form of a reduction in control range, resolution, bandwidth, current consumption, or accuracy.

[0012] In particular, the piezoresistive effect described above describes how the specific ohmic resistance of a corresponding semiconductor material behaves under the influence of the mechanical stress tensor and the piezoresistive coefficient. In an integrated circuit device (IC), a corresponding current I, such as a control current, a reference current, etc., is generated by the circuit elements of the IC device on a semiconductor chip. In this case, a defined voltage U is generally generated across an integrated resistor having a resistance value R, and the current I is coupled out. Therefore, current I can generally be generated at each resistor element, for example, also at a MOS field-effect transistor in the linear operating range. For example, the voltage U can be generated relatively constant with respect to mechanical stress in the semiconductor material using the known bandgap principle (apart from relatively small piezoelectric junction effects on the generated bandgap voltage). However, the resistance value R is subject to the piezoresistive effect. Because mechanical stress in the semiconductor material acts on the semiconductor circuit chip through the housing of the IC device in a difficult-to-control manner, the resistance value R used to generate the current I, and thus the generated current I, can vary in undesirable and unpredictable ways.

[0013] Regarding the aforementioned piezoelectric effect, it should be noted that the coefficients defining the mechanical stresses occurring in semiconductor materials are so-called "tensors." This means that the resistance value R of a resistor element varies not only with the intensity of the mechanical stresses in the semiconductor material, but also with the direction of the stresses. This directional dependence of mechanical stresses in semiconductor materials applies to the commonly used {100} silicon materials for p-doped and n-doped resistors Rp and Rn. Furthermore, it should be noted that {100} and {001} crystals correspond to each other in a cubic crystal for reasons of symmetry.

[0014] Below, we will briefly explain how attempts have been made to reduce these disruptive piezoelectric influences. For example, in {100} silicon, the mechanical stress dependence of integrated resistors can be reduced by using p-doped resistors instead of n-doped resistors, if possible, since p-doped integrated resistors generally have a lower piezoelectric coefficient.

[0015] Furthermore, two resistors of nominally equal size can be arranged perpendicularly to one another and at a small distance from one another in a layout, and electrically connected in series or parallel (a so-called L-layout). This makes the total resistance largely independent of the direction of the mechanical stress in the semiconductor material and therefore as reproducible as possible. At the same time, this arrangement minimizes the piezoelectric sensitivity to any direction of the mechanical stress.

[0016] Furthermore, efforts are underway to design IC housings in such a way that the mechanical stresses on the semiconductor chip become more reproducible. To this end, either more expensive ceramic housings can be used, or the mechanical parameters of the housing components, i.e., the semiconductor chip, the leadframe, the potting compound, the adhesive material, or the solder material, can be coordinated with one another so that the influence of the various housing components is largely compensated for or the load on the integrated circuit arrangement during operation is at least as constant as possible. However, it should be understood that the coordination of the mechanical parameters of the housing components is extremely complex, and furthermore, even the slightest change in the process flow results in a change in the influence of the various housing components.

[0017] As is clear from the above-described embodiments, mechanical stresses in the semiconductor material can lead to undesirable and difficult-to-control influences on the physical functional parameters of semiconductor components of an integrated circuit arrangement on a semiconductor circuit chip due to various piezoelectric effects. Compensating for the influence of piezoelectric effects on the physical and electronic functional parameters of the semiconductor components is problematic because the stress components occurring in the semiconductor material are generally neither known in advance nor remain constant over the service life. Therefore, when the integrated circuit arrangement is housed in a housing, i.e., in a material such as a semiconductor chip, a wireframe, a potting compound, an adhesive, or a solder, mechanical parameters can only be matched with difficulty or not at all in order to appropriately control the aforementioned piezoelectric influences on the semiconductor material and, therefore, on the electronic and physical functional parameters of the semiconductor components. Summary of the Invention

[0018] Based on this, there is a need for improved solutions for compensating for piezoelectric influences on integrated circuit devices. This need is met by the device and method according to the present invention. In some cases, advantageous improvements are the following.

[0019] According to the approach described herein, a transistor-based stress sensor is provided. The stress sensor comprises a semiconductor substrate having a first MOS transistor arrangement and a second MOS transistor arrangement. The two MOS transistor arrangements are arranged in a substrate plane of the semiconductor substrate and are preferably structured or integrated within the semiconductor substrate. The first MOS transistor arrangement comprises a first MOS transistor having a first source-drain channel region and a second MOS transistor having a second source-drain channel region. The first MOS transistor and the second MOS transistor are oriented relative to each other in the substrate plane such that the current flow direction in the first source-drain channel region is opposite to the current flow direction in the second source-drain channel region. In other words, the two current flow directions are offset by 180° from each other. The second MOS transistor arrangement comprises a third MOS transistor having a third source-drain channel region and a fourth MOS transistor having a fourth source-drain channel region. The third MOS transistor and the fourth MOS transistor are oriented relative to each other in the substrate plane such that the current flow direction in the third source-drain channel region is opposite to the current flow direction in the fourth source-drain channel region. Due to this arrangement of the individual transistors relative to one another, the transistor-based stress sensor can provide a gradient-compensated output signal for determining a mechanical stress component acting on the semiconductor substrate.

[0020] According to the innovative solution described herein, a method for gradient-compensated determination of at least one mechanical stress component acting on a semiconductor substrate is also proposed, wherein, according to the innovative solution described herein, the mechanical stress component can be determined with the aid of a transistor-based stress sensor. The method also includes applying an input signal to the transistor-based stress sensor and tapping the gradient-compensated output signal of the transistor-based stress sensor. The method also includes comparing the gradient-compensated output signal with a reference signal, wherein the deviation relative to the reference signal defines a measure for the mechanical stress component to be determined. In addition, the method includes determining the value of the deviation based on the difference between the gradient-compensated output signal and the reference signal. Alternatively or additionally, the deviation can be determined based on a factorial ratio (faktoriellen) between the output signal and the reference signal. ) to determine the deviation value.

[0021] Furthermore, according to the innovative approach described herein, a stress measurement device is provided that includes at least two transistor-based stress sensors. A first transistor-based stress sensor of the at least two transistor-based stress sensors provides a gradient-compensated first output signal, which is used to determine a first mechanical stress component acting on a semiconductor substrate. A second transistor-based stress sensor of the at least two transistor-based stress sensors provides a second gradient-compensated output signal, which is used to determine a second mechanical stress component acting on the semiconductor substrate. The first transistor-based stress sensor is disposed in a first substrate region of the semiconductor substrate. The second transistor-based stress sensor is disposed in a second substrate region of the semiconductor substrate that is distinct from and spatially separated from the first substrate region. The stress measurement device is designed to determine the total mechanical stress acting on the semiconductor substrate based on the first and second gradient-compensated output signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Some exemplary embodiments are shown by way of example in the drawings and are explained below.

[0023] Figures 1A-1C shows the general definition of the crystallographic directions in the plane of semiconductor material (the wafer plane),

[0024] Figure 2 Schematic overview showing possible sources of stress components due to gradient effects,

[0025] Figure 3 is a schematic diagram of a transistor-based stress sensor in a + / -45° configuration according to an embodiment,

[0026] Figure 4 is a schematic diagram of a transistor-based stress sensor in a 0° / 90° configuration according to an embodiment,

[0027] Figure 5 is a schematic diagram of a transistor-based stress sensor in a + / -45° configuration according to an embodiment,

[0028] Figure 6 is a circuit diagram of a transistor-based stress sensor in a + / -45° configuration according to an embodiment,

[0029] Figure 7 is an equivalent circuit diagram of a transistor-based stress sensor in a + / -45° configuration according to an embodiment,

[0030] Figure 8 is an equivalent circuit diagram of a transistor-based stress sensor in a 0° / 90° configuration according to an embodiment,

[0031] Figure 9A is a schematic diagram of a transistor-based stress sensor in a 0° / 90° configuration according to an embodiment,

[0032] Figure 9B is a schematic diagram of a transistor-based stress sensor in a + / -45° configuration according to an embodiment,

[0033] Figure 10 is a schematic diagram of a transistor-based stress sensor having separate (p-MOS) transistors with a common drain terminal in a 0° / 90° configuration according to further embodiments,

[0034] Figure 11 yes Figure 10 The equivalent circuit diagram of the transistor-based stress sensor,

[0035] Figure 12 yes Figure 10 A simplified equivalent circuit diagram of a transistor-based stress sensor,

[0036] Figure 13 is a schematic diagram of a transistor-based stress sensor having a cascade circuit in a 0° / 90° configuration with separate (p-MOS) transistors and a cascode with a common drain terminal according to an embodiment,

[0037] Figure 14 yes Figure 13 The equivalent circuit diagram of the transistor-based stress sensor,

[0038] Figure 15 yes Figure 13 A simplified equivalent circuit diagram of a transistor-based stress sensor,

[0039] Figure 16 is a schematic diagram of a transistor-based stress sensor with a cascade circuit in a 0° / 90° configuration according to further embodiments,

[0040] Figure 17 is a circuit diagram of a transistor-based stress sensor in a + / -45° configuration with a voltage-based evaluation circuit according to an embodiment,

[0041] Figure 18 is a circuit diagram of a transistor-based stress sensor in a + / -45° configuration with a current-based evaluation circuit according to an embodiment,

[0042] Figure 19 is a circuit diagram of a transistor-based stress sensor in a + / -45° configuration for determining mechanical stress components according to an embodiment,

[0043] Figure 20 is a circuit diagram of a transistor-based stress sensor in a 0° / 90° configuration with a voltage-based evaluation circuit according to an embodiment,

[0044] Figure 21 is a circuit diagram of a transistor-based stress sensor in a 0° / 90° configuration with a current-based evaluation circuit according to an embodiment,

[0045] Figure 22 is a circuit diagram of a transistor-based stress sensor in a 0° / 90° configuration for determining mechanical stress components according to an embodiment,

[0046] Figure 23 is a circuit diagram of a transistor-based stress sensor in a 0° / 90° configuration with a common-mode controlled regulator according to an embodiment,

[0047] Figure 24A is a schematic diagram of a transistor-based stress sensor in a + / -45° configuration with star-connected transistors according to an embodiment,

[0048] Figure 24B is a schematic diagram of a transistor-based stress sensor in a + / -45° configuration with an alternative interconnection that saves space for transistors according to an embodiment, and

[0049] Figure 25 is a schematic diagram of a stress measurement device having at least two transistor-based stress sensors according to an embodiment. DETAILED DESCRIPTION

[0050] The embodiments are described in more detail below with reference to the accompanying drawings, wherein elements having the same or similar functions are provided with the same reference numerals.

[0051] The method steps shown in the block diagrams and explained with reference to the block diagrams can also be implemented in a sequence different from that shown or described. In addition, method steps relating to a specific feature of the device can be interchanged with the same feature of the device, and vice versa.

[0052] Whenever compensation of a specific variable, such as gradient compensation, is mentioned herein, this may be understood to mean partial compensation of this variable (e.g., gradient), which is essentially equivalent to a reduction of this variable. However, it may also be understood to mean complete compensation of this variable, such that this variable becomes negligibly small, or even zero.

[0053] In the following embodiments, a semiconductor substrate is described, wherein, for example, silicon or germanium, gallium arsenide (GaAs), InSb, InP, etc. can be used as the semiconductor material.

[0054] Furthermore, MOS transistor arrangements will be described below, wherein each of these MOS transistor arrangements may each have two or more individual transistors. For the sake of clarity, two individual transistors are shown for each MOS transistor arrangement in the following figures. However, this is to be regarded as an example only and does not exclude that a MOS transistor arrangement may also have more than the two individual transistors shown here.

[0055] In order to simplify the understanding of the following detailed description of a transistor-based stress sensor for gradient-compensated stress measurement, we will first Figures 1A to 1C The definitions used below are explained with regard to the semiconductor material used and the directions set thereon with respect to the crystal orientation of the semiconductor material.

[0056] To produce integrated circuits, semiconductor wafers, such as silicon wafers or disks, are sawn from a single crystal rod so that the wafer surface is provided with these crystallographic planes. To determine the individual planes in a cubic crystal, the so-called "Miller indices" are used. For example, Figure 1A A top view of a semiconductor wafer cut in the (100) plane is shown.

[0057] In addition, Figures 1A to 1C In the wafer plane, the main directions of crystallization are marked. Silicon wafer manufacturers typically provide so-called "primary planes" on the wafer. Similarly, notches or similar markings can also be used. Therefore, within the scope of this disclosure, such notches should also be understood as primary planes. Typically, the edges of the rectangular geometric shapes of the circuit structures on the semiconductor chip extend parallel or perpendicular to the primary planes.

[0058] exist Figure 1A In particular, the crystallographic directions or axes in the plane of the semiconductor wafer are shown, wherein these are indicated below in square brackets. A coordinate system is usually used such that the

[110] direction extends perpendicularly or orthogonally to the primary plane, while The directions

[010] and

[100] extend at an angle of ±45° to the

[110] direction defining the normal to the primary plane. and Relative to The direction extends at an angle of ±45°, which also defines the normal to the primary plane (in the direction opposite to

[110] ).

[0059] Furthermore, an angle Φ about the

[110] direction is defined, wherein the angle Φ is counted counterclockwise from the

[110] direction in a top view of the upper side of the wafer. Typically, the individual chips are positioned on the wafer such that the directions Φ=0° and Φ=90° correspond to the vertical or horizontal directions of the IC, respectively, wherein these directions can be interchanged depending on whether the IC is upright or horizontal. Furthermore, the direction Φ=90° is denoted below as the x-axis. direction), and the direction Φ=0° is represented as the negative y-axis (

[110] direction).

[0060] Assume that the x-axis is aligned with the crystal direction Same as, and the y-axis is The crystal directions are identical, which in particular means that the semiconductor circuit chip is made of a {100} semiconductor material (e.g. {100} silicon). Typically, this primary plane is parallel to the x-axis, so that the edges of the semiconductor circuit chip are parallel to the x-axis and the y-axis. The crystal directions

[100] and

[010] are then identical to the diagonals of the semiconductor circuit chip (see Figure 1B ).

[0061] Since {100} silicon is used in most semiconductor integrated circuit device applications, the following embodiments primarily refer to numerical values ​​for {100} silicon for ease of explanation and due to particular practical significance. These numerical values ​​are significant for this material. However, it will be apparent to those skilled in the art that other semiconductor materials or other silicon materials may also be used accordingly.

[0062] Mechanical tension, also known as mechanical stress, is a tensor quantity that represents the force per unit area acting within a rigid body under mechanical load. This force can be generated by cutting through a rigid body. Ideally, this force must be applied across the cross-section to maintain the body under the same load.

[0063] Figure 1C A small piece cut out of a rigid body is shown. As can be seen, such a cut of the body can have different orientations, which in turn affects the forces at the cross section. That is, the force (which is a vector) also depends on the orientation of the cut. Therefore, this force (i.e. the mechanical stress) also has more than three degrees of freedom. The piece shown has cross sections that are parallel to the x-axis, y-axis and z-axis respectively. The force on each cross section can be decomposed into individual components, which point in the x-, y- and z-directions respectively. On each cross section, there is a component perpendicular to the surface: this is the normal stress component (also: normal stress component) σ XX At each cross section, two adjacent components appear, extending parallel to the surface: these are the shear stress components (or: shear stress or shear stress components) σ XY ,σ XZThe first subscript indicates the direction of the surface, and the second subscript indicates the direction of the force.

[0064] Normal stress can be compressive or tensile, depending on its sign. Normal stress acts perpendicular to the coordinate plane, i.e., the normal direction coincides with the direction of action. Shear stress acts tangentially to the plane and represents shearing load.

[0065] There are nine components in total, specifically three cross sections, each with one normal stress component and two shear stress components. The forces at the opposite region (i.e., the negative plane with the normal vector in the negative x, y, z direction) are the same, but with a negative sign. If force or moment balance is applied to the Figure 1C On the block depicted in , it can be seen that the shear stress is the same if the subscripts of the shear stress are swapped: σ YZ =σ ZY ,σ XZ =σ ZX ,σ XY =σ YX Thus, one ends up with six independent components of the stress tensor, namely the three normal stress components σ XX , σ YY , σ ZZ and three shear stress components σ YZ , σ XZ , σ XY . The three normal stress components σ XX , σ YY , σ ZZ The two normal stress components in each case can form a difference, which results in a so-called stress component difference, such as σ XX –σ YY .

[0066] It is usually not necessary to observe all six stress components simultaneously, since in microelectronic packaging so-called stacks are often used whose lateral extension in the x, y directions is significantly greater than their thickness in the z direction (see also Figure 1B ).

[0067] As mentioned at the outset, gradient-based effects lead to temporally variable disturbance variables for the transistor-based strain sensors described here, which result in inaccurate or distorted output signals. Figure 2 A schematic overview is shown for displaying such gradient-based disturbance variables and their possible causes.

[0068] Figure 2The following example shows two transistors 1 and 2 arranged in an L-shape relative to each other in a transistor-based stress sensor 10 according to the innovative approach described herein. Transistor-based stress sensor 10 is arranged on or integrated into a semiconductor substrate and changes its output signal in response to mechanical stress acting on the semiconductor substrate. It is desirable to measure the actual instantaneous mechanical stress acting externally on the semiconductor substrate. However, undesirable stress components may also occur and should not be measured.

[0069] Here, undesirable static stress components can be compensated relatively easily, for example, by a one-time calibration. In contrast, undesirable stress components that vary over time can only be compensated with difficulty. These temporally variable stress components can be described by gradients. Gradients can, in particular, describe non-uniform stresses. For example, a heat source (e.g., a circuit) 100 can be present on a semiconductor substrate, which outputs increasing amounts of heat as the operating duration increases. This can be represented by a thermal gradient 200. This thermal gradient influences the output signal of a transistor-based stress sensor in an undesirable manner, since the stresses caused by the thermal gradient should not be measured at all.

[0070] Likewise, undesirable mechanical gradients 400 can affect the output signal of transistor-based stress sensors in undesirable ways. Consequently, some substrates have so-called "deep trenches" 300. In the immediate vicinity of these "deep trenches" 300, undesirable mechanical stresses exist, which, however, should not be measured by transistor-based stress sensors. As the distance from these "deep trenches" 300 increases, the magnitude of the mechanical stress generated thereby decreases. Consequently, mechanical gradients 400 exist that change in magnitude depending on the distance from the deep trenches 300.

[0071] Other conceivable mechanical gradients 500 can be caused, for example, by specific layout effects. For example, in the case of trench isolation (shallow trench isolation—STI), the creation of deep trenches results in a decrease in mechanical stress with increasing distance from the trench. Thus, mechanical gradients arise here as well, which should not be measured by the transistor-based stress sensor described herein.

[0072] Therefore, the transistor-based stress sensor described herein should be designed to measure only the stress actually acting externally on the semiconductor substrate (on which the stress sensor is arranged). Gradient-based effects should not be measured at all. Due to the arrangement of the individual transistors of the innovative transistor-based stress sensor described herein, it is possible to obtain a gradient-compensated output signal, and in the best case, an output signal with virtually no gradient. In particular, first-order gradients can be compensated. This also includes thermal gradients, mechanical stress gradients, layout gradients, and aging effects.

[0073] In other words, the innovative approach described herein creates a MOS transistor-based stress sensor designed to compensate, inter alia, for first-order thermal stress (non-uniform stress) and layout-related gradients. Hereinafter, the transistor-based stress sensor will be described in more detail structurally with reference to the accompanying drawings.

[0074] Figure 3 A schematic diagram of a transistor-based stress sensor 10 according to the innovations described herein is shown. The transistor-based stress sensor 10 has a semiconductor substrate 20 with a first MOS transistor arrangement 11 and a second MOS transistor arrangement 12.

[0075] The first MOS transistor arrangement 11 includes a first MOS transistor 1. The first MOS transistor 1 includes a source region 21 and a drain region 22. A gate region 23 is located between the source region 21 and the drain region 22. If a current is applied to the first MOS transistor 1, the current flows from the source region 21 to the drain region 22, resulting in a first current flow direction 24. The region between the source region 21 and the drain region 22, in which the current flows along this current flow direction 24, may also be referred to herein as a source-drain channel region. Therefore, in the present case of the first MOS transistor 1, this region may be a first source-drain channel region 23.

[0076] The first MOS transistor device 11 further includes a second MOS transistor 2. Like the first MOS transistor 1 described above, the second MOS transistor 2 includes a source region 31 and a drain region 32. A second source-drain channel region 33 is located between the source region 31 and the drain region 32. When current is applied to the second MOS transistor 2, the current flows from the source region 31 to the drain region 32, thereby establishing a second current flow direction 34 in the second source-drain channel region 33.

[0077] According to the innovative solution described herein, the first MOS transistor 1 and the second MOS transistor 2 are oriented relative to each other or arranged or positioned on the semiconductor substrate 20 such that a first current flow direction 24 in a first source-drain channel region 23 of the first MOS transistor 1 is opposite to a second current flow direction 34 in a second source-drain channel region 33 of the second MOS transistor 2. In other words, the first MOS transistor 1 is rotated 180° relative to the second MOS transistor 2 in the substrate plane.

[0078] The second MOS transistor arrangement 12 has a third MOS transistor 3 with a third source-drain channel region 43 and a fourth MOS transistor 4 with a fourth source-drain channel region 53 .

[0079] That is, the third MOS transistor 3 has a source region 41 and a drain region 42. The third source-drain channel region 43 is located between the source region 41 and the drain region 42. When current is applied to the third MOS transistor 3, the current flows from the source region 41 to the drain region 42, so that a third current flow direction 44 shown in the figure is set in the third source-drain channel region 43.

[0080] Like the aforementioned MOS transistors 1, 2, and 3, the fourth MOS transistor 4 has a source region 51 and a drain region 52. The fourth source-drain channel region 53 is located between the source region 51 and the drain region 52. When current is applied to the fourth MOS transistor 4, the current flows from the source region 51 to the drain region 52, so that a fourth current flow direction 54 shown in the figure is set in the fourth source-drain channel region 53.

[0081] According to the innovative solution described herein, the third MOS transistor 3 and the fourth MOS transistor 4 are oriented relative to each other or arranged or positioned on the semiconductor substrate 20 such that a third current flow direction 44 in the third source-drain channel region 43 of the third MOS transistor 3 is opposite to a fourth current flow direction 54 in the fourth source-drain channel region 53 of the fourth MOS transistor 4. In other words, the third MOS transistor 3 is rotated 180° relative to the fourth MOS transistor 4 in the substrate plane.

[0082] This arrangement of the individual transistors 1, 2, 3, 4 relative to one another enables the transistor-based stress sensor 10 to provide a gradient-compensated output signal. This gradient-compensated output signal can be used to determine the mechanical stress component acting on the semiconductor substrate 20. This can be done in an evaluation circuit provided for this purpose, as will be explained in more detail below.

[0083] As explained at the outset, gradients, possibly originating from various sources, can act on the semiconductor substrate. These gradients result in mechanical stresses that can be measured by the individual transistors 1, 2, 3, 4. However, because these gradient-based mechanical stresses are not taken into account in the actual stress measurement, such gradient-based stresses can lead to erroneous or inaccurate measurements.

[0084] However, the arrangement of the individual transistors 1, 2, 3, and 4 relative to one another, as described herein, allows for compensation of such gradient-based stresses. As previously described, the individual MOS transistors 1, 2, 3, and 4 are arranged relative to one another within the MOS transistor arrangements 11 and 12, that is, each rotated 180° relative to one another within the substrate plane. As a result, gradient-based mechanical stresses enter a transistor with a positive sign, while precisely the same gradient-based mechanical stresses enter another transistor with the same magnitude but a negative sign (rotated 180°). Thus, for example, if we consider the first MOS transistor 1 and the second MOS transistor 2 of the first MOS transistor arrangement 11, the first MOS transistor 1 measures a gradient-based mechanical stress with a first sign (e.g., a positive sign), and the second MOS transistor 2 measures the same gradient-based mechanical stress with the same magnitude but a second sign complementary to the first (e.g., a negative sign). This inherently compensates for undesirable gradient-based mechanical stresses.

[0085] Of course, the same applies correspondingly to the third transistor 3 and the fourth transistor 4 in the second MOS transistor arrangement 12 .

[0086] The transistor-based stress sensor 10 has further features regarding the relative arrangement of the individual transistors 1, 2, 3, 4. More specifically, the individual transistors 1, 2, 3, 4 are arranged on the semiconductor substrate 20 at a specific angle relative to each other in the substrate plane. Figure 3 The previously described Miller indices are depicted again in the lower right corner of .

[0087] The transistors 1, 2 of the first MOS transistor arrangement 11 are each arranged at a first angle of Φ1 = -45° in the substrate plane. The transistors 3, 4 of the second MOS transistor arrangement 12 are each arranged at a second angle of Φ2 = +45° in the substrate plane.

[0088] These angle specifications in turn relate to the primary plane, more precisely to the normal to the primary plane. In this example, the angle specifications relate to the negative y-axis in the

[110] direction.

[0089] The orientation of transistors 1, 2, 3, 4 can be best described by means of their respective current flow directions 24, 34, 44, 54. Thus, for example, the first transistor 1 is arranged in the substrate plane so that its current flow direction 24 in the first source-drain channel region 23 extends at a first angle (Φ1 = -45°) relative to the normal to the primary plane of the semiconductor substrate 20. The same applies correspondingly to the second transistor 2 rotated by 180°, wherein the positive y-axis can be used as a reference, i.e., in It can therefore also be said that the first transistor arrangement 11 is arranged in the substrate plane such that the respective current flow directions 24 , 34 of the associated transistors 1 , 2 extend at a first angle ( Φ1 =−45°) relative to the normal to the primary plane of the semiconductor substrate 20 .

[0090] The third transistor 3 is arranged in the substrate plane so that its current flow direction 44 in the third source-drain channel region 43 extends at a second angle (Φ2=+45°) relative to the normal to the primary plane of the semiconductor substrate 20. The same applies correspondingly to the fourth transistor 4 rotated by 180°, wherein the positive y-axis can again be used as a reference, i.e. It can therefore also be said that the second transistor arrangement 12 is arranged in the substrate plane such that the respective current flow directions 44 , 54 of the associated transistors 3 , 4 extend at a second angle ( Φ2 =+45°) relative to the normal to the primary plane of the semiconductor substrate 20 .

[0091] Therefore, in combination with the previously described orientation of the individual transistors 1 , 2 , 3 , 4 with respect to one another, the first angle Φ1 and the second angle Φ2 are perpendicular to one another.

[0092] exist Figure 3 The transistor-based stress sensor 10 depicted in FIG can be specifically designed to determine the mechanical shear stress component σ acting on the semiconductor substrate 20 based on the previously described arrangement of the individual transistors 1, 2, 3, 4 relative to each other. XY , σ YZ , σ XZ .

[0093] Preferably, the first MOS transistor 1 and the second MOS transistor 2 of the first MOS transistor arrangement 11 as well as the third MOS transistor 3 and the fourth MOS transistor 4 of the second MOS transistor arrangement 12 can each be of n-channel type. If the MOS transistor arrangements 11, 12 are to have more than the two individual transistors 1, 2, 3, 4 shown here purely by way of example, all of these individual transistors can be of n-channel type.

[0094] Figure 4 An alternative embodiment of a transistor-based stress sensor 10 according to the innovations described herein is shown. The structure is substantially the same as previously described with reference to FIG. Figure 3 The transistor-based stress sensor 10 described is identical, so all the above also applies accordingly. Figure 4 The stress sensor 10 is shown in FIG.

[0095] However, one difference lies in the arrangement of the transistors 1, 2, 3, 4 in the substrate plane with respect to the primary plane. Figure 4In the strain sensor 10 shown in FIG, transistors 1 and 2 of a first MOS transistor arrangement 11 are each arranged at a first angle Φ1 = 90° in the substrate plane. Transistors 3 and 4 of a second MOS transistor arrangement 12 are each arranged at a second angle Φ2 = 0° in the substrate plane.

[0096] Here again, these angle specifications relate to the primary plane, more precisely to the normal to the primary plane. In this example, the angle specifications are again relative to the negative y-axis in the

[110] direction.

[0097] exist Figure 4 The transistor-based stress sensor 10 depicted in FIG can be designed, due to the previously described arrangement of the individual transistors 1, 2, 3, 4 relative to one another, in particular to determine the difference σ of the mechanical stress components acting on the semiconductor substrate 20. XX -σ YY .

[0098] Preferably, the first MOS transistor 1 and the second MOS transistor 2 of the first MOS transistor arrangement 11 as well as the third MOS transistor 3 and the fourth MOS transistor 4 of the second MOS transistor arrangement 12 can each be of p-channel type. If the MOS transistor arrangements 11, 12 are to have more than the two individual transistors 1, 2, 3, 4 shown here purely by way of example, all of these individual transistors can be of p-channel type.

[0099] In general, it can be determined that Figure 3 The transistor-based stress sensor 10 depicted in FIG. 1 may be designed in particular to determine the mechanical shear stress component σ acting on the semiconductor substrate 20. XY , σ YZ , σ XZ This is caused by the arrangement of the individual transistors 1, 2, 3, 4 at an angle of + / - 45°. Figure 4 The transistor-based stress sensor 10 depicted in FIG. 1 may be designed in particular to determine the difference σ of the mechanical stress components acting on the semiconductor substrate 20. XX -σ YY This results from the arrangement of the individual transistors 1 , 2 , 3 , 4 at an angle of 0° or 90°.

[0100] In both cases, the transistor-based stress sensor 10 can provide a gradient-compensated output signal, which in turn is due to the fact that the current flow directions of the respective individual transistors 1, 2, 3, 4 of the respective MOS transistor devices 11, 12 are oriented opposite to each other, which leads to an intrinsic compensation of the respective gradient-based stress input.

[0101] Structurally, therefore, not only Figure 3 In and Figure 4In the embodiment shown in FIG, the first MOS transistor arrangement 11 can be arranged offset by 90° relative to the second MOS transistor arrangement 12. The individual transistors 1, 2, 3, 4 can be oriented relative to each other so that each transistor is offset by 90° with respect to its respective directly adjacent transistor (both in the clockwise direction and in the counterclockwise direction). This also refers again to the current flow directions 24, 34, 44, 54 in the respective source-drain channel regions 23, 33, 43, 53 of the respective transistors 1, 2, 3, 4.

[0102] Figure 5 Another example of a transistor-based stress sensor 10 is shown. As shown here, the same as previously described with reference to Figure 3 and Figure 4 Compared with the embodiment described above, the corresponding drain regions 22, 32, 42, 52 and the corresponding source regions 21, 31, 41, 51 of the transistors 1, 2, 3, 4 can also be arranged in reverse, that is, rotated 180°. Figure 3 and Figure 4 However, the above-described functional principle of the transistor-based strain sensor 10 remains unchanged.

[0103] As in Figure 5 As can be seen in FIG, the drain regions 22, 32 of the transistors 1, 2 of the first MOS transistor arrangement 11 can be interconnected. Similarly, the drain regions 42, 52 of the transistors 3, 4 of the second MOS transistor arrangement 12 can be interconnected. The source regions 21, 31, 41, 51 of all transistors 1, 2, 3, 4 can be at a common potential.

[0104] Figure 6 As shown in previous reference Figure 3 The circuit diagram of the transistor-based stress sensor 10 is described, but with a conceivable alternative notation relative to the Miller indices in the substrate plane. The illustrated circuit shows the individual transistors 1, 2, 3, and 4, along with their respective drain regions (drain1, drain2, drain3, and drain4). This results in corresponding current flow directions from the respective source regions to the respective drain regions of the respective transistors 1, 2, 3, and 4. The circuit also shows that the respective current flow directions of the first and second transistors 1 and 2 are oriented in opposite directions, and the current flow directions of the third and fourth transistors 3 and 4 are likewise oriented in opposite directions.

[0105] In this example, the second transistor 2 can be rotated by an angle of -45° and the third transistor 3 can be rotated by an angle of +45° relative to the normal to the primary plane (e.g., the negative y-axis). Thus, the first transistor 1 rotated 180° relative to the second transistor 2 will then be rotated by an angle of -45°+180°=+135° relative to the normal to the primary plane (e.g., the negative y-axis), and the fourth transistor 4 rotated 180° relative to the third transistor 3 will be rotated by an angle of +45°+180°=+225° relative to the normal to the primary plane (e.g., the negative y-axis).

[0106] Therefore, this mark is also considered. However, if the Figure 3 , it can be said that the first transistor 1 is rotated by -45° relative to the normal to the primary plane (e.g., the negative y-axis), and the second transistor 2 is rotated by -45° (+180°) relative to the normal to the primary plane (e.g., the negative y-axis), and the third transistor 3 is rotated by +45° relative to the normal to the primary plane (e.g., the negative y-axis), and the fourth transistor 4 is rotated by +45° (+180°) relative to the normal to the primary plane (e.g., the negative y-axis). Thus, it can be said that the first MOS transistor device 11 is rotated by a first angle Φ1 = +45° relative to the normal to the primary plane (e.g., the negative y-axis), and the second MOS transistor device 12 is rotated by a second angle Φ2 = -45° relative to the normal to the primary plane (e.g., the negative y-axis).

[0107] Therefore, we finally get Figure 3 FIG. 1 is an equivalent circuit diagram of a transistor-based stress sensor 10 , which is designed, based on the arrangement of the individual transistors 1 , 2 , 3 , 4 relative to one another, to determine a mechanical shear stress component σ acting on a semiconductor substrate 20 . XY , σ YZ , σ XZ .

[0108] Figure 7 Show the basis Figure 6 1 is a simplified equivalent circuit diagram of such a transistor-based strain sensor 10. In this case, instead of individual transistors 1, 2, 3, 4, only two MOS transistor arrangements 11, 12 are depicted.

[0109] The first MOS transistor arrangement 11 shown has a first transistor 1 and a second transistor 2, each rotated by -45° (or -45°+180°). Therefore, the first MOS transistor arrangement 11 is shown here only at -45°. The second MOS transistor arrangement 12 shown has a third transistor 3 and a fourth transistor 4, each rotated by +45° (or +45°+180°). Therefore, the second MOS transistor arrangement 12 is shown here only at +45°.

[0110] Figure 8 As shown in the previous reference Figure 4 Simplified equivalent circuit diagram of the described transistor-based stress sensor 10. Here, the first MOS transistor device 11 is rotated by a first angle Φ1 = 90° relative to the normal to the primary plane (e.g., the negative y-axis), and the second MOS transistor device 12 is rotated by a second angle Φ2 = 0° relative to the normal to the primary plane (e.g., the negative y-axis).

[0111] exist Figure 8 The transistor-based stress sensor 10 shown in the simplified equivalent circuit diagram in FIG is designed, based on the arrangement of the individual transistors 1, 2, 3, 4, in particular to determine the difference σ in mechanical stress components acting on the semiconductor substrate 20. XX -σ YY .

[0112] The following describes possible designs for various transistors that can be used in transistor-based stress sensor 10 according to the innovations described herein. Furthermore, all descriptions herein using a + / -45° configuration as an example for MOS transistor arrangements also apply in the same manner to MOS transistor arrangements with a 0° / 90° configuration, and vice versa. Furthermore, all descriptions herein using an n-MOS transistor as an example also apply to p-MOS transistors, and vice versa.

[0113] For example, Figure 9A A transistor-based strain sensor 10 is shown having a first MOS transistor arrangement 11 and a second MOS transistor arrangement 12 , wherein the two MOS transistor arrangements 11 , 12 each have separate transistors 1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B.

[0114] Thus, for example, the first transistor 1 described above can be implemented in two parts, wherein the first transistor 1 has a first transistor part 1A and a second transistor part 1B. In this case, the first transistor part 1A and the second transistor part 1B can share a drain region, wherein, that is, the drain subregion 52A belonging to the first transistor part 1A can be electrically connected to the drain subregion 52B belonging to the second transistor part 1B.

[0115] The same applies to the aforementioned second, third, and fourth transistors 2, 3, 4, which can also be implemented in two parts. In principle, all drain regions (or drain subregions) of the transistors (or transistor parts) of the first MOS transistor arrangement 11 can be connected to one another. Similarly, all drain regions (or drain subregions) of the transistors (or transistor parts) of the second MOS transistor arrangement 12 can be connected to one another.

[0116] Figure 9BA transistor based stress sensor 10 is shown having a similar arrangement of two MOS transistor devices 11, 12. However, one difference is that the individual transistors (or transistor portions) are here arranged in a + / - 45° configuration instead of the 0° / 90° configuration described previously.

[0117] Figure 10 A further conceivable embodiment of a transistor-based stress sensor 10 according to the innovation described herein is shown in FIG. In this embodiment, two transistors are connected to one another, wherein the two transistors share a common drain region.

[0118] For example, the first MOS transistor arrangement 11 may have a fifth MOS transistor 5 (see “drain 15 ”) that shares a common drain region 22 with the first MOS transistor 1 .

[0119] The first MOS transistor arrangement 11 may further include a sixth MOS transistor 6 (see “drain 26 ”) which shares a common drain region 32 with the second MOS transistor 2 .

[0120] The second MOS transistor arrangement 12 may have a seventh MOS transistor 7 (see “drain 37 ”) that shares a common drain region 42 with the third MOS transistor 3 .

[0121] The second MOS transistor arrangement 12 may further include an eighth MOS transistor 8 (see “drain 48 ”) that shares a common drain region 52 with the fourth MOS transistor 4 .

[0122] Figure 11 The first transistor arrangement 11 has the previously described first, second, fifth and sixth transistors 1 , 2 , 5 , 6 . The first transistor 1 and the fifth transistor 5 share a common drain region 15 . The second transistor 2 and the sixth transistor 6 share a common drain region 26 .

[0123] The second transistor arrangement 12 has the previously described third, fourth, seventh and eighth transistors 3, 4, 7, 8. The third transistor 3 and the seventh transistor 7 share a common drain region 37. The fourth transistor 4 and the eighth transistor 8 share a common drain region 48.

[0124] The fourth transistor 4 and the eighth transistor 8 are arranged in the substrate plane so that their current flow directions (from source to drain) each extend at an angle of 90° relative to the normal to the primary plane of the semiconductor substrate 20. The third transistor 3 and the seventh transistor 7 are arranged in the substrate plane so that their current flow directions (from source to drain) each extend at an angle of 270° relative to the normal to the primary plane of the semiconductor substrate 20.

[0125] The first transistor 1 and the fifth transistor 5 are arranged in the substrate plane so that their current flow directions (from source to drain) each extend at an angle of 180° relative to the normal to the primary plane of the semiconductor substrate 20. The second transistor 2 and the sixth transistor 6 are arranged in the substrate plane so that their current flow directions (from source to drain) each extend at an angle of 0° relative to the normal to the primary plane of the semiconductor substrate 20.

[0126] Figure 12 Show Figure 11 1 . Here again, only the MOS transistor arrangements 11, 12 are shown, with their respective individual transistors combined. The two MOS transistor arrangements 11, 12 are arranged here in a 0° / 90° configuration. However, it is also conceivable that the two MOS transistor arrangements 11, 12 could be arranged in a + / -45° configuration.

[0127] In addition to the embodiments discussed so far, cascade circuits with a plurality of transistors are also conceivable. Figure 13 Such a conceivable embodiment is shown with a 0° / 90° configuration, wherein here again a + / −45° configuration is also conceivable in principle.

[0128] Figure 14 shows the associated circuit diagram, and Figure 15 Show Figure 13 FIG. 1 is a corresponding simplified equivalent circuit diagram of a cascade circuit of the first MOS transistor device 11 and the second MOS transistor device 12 .

[0129] According to this embodiment, the first MOS transistor arrangement 11 can have a first transistor cascade circuit N1. This first transistor cascade circuit N1 can in turn have a first transistor 1 as a first base transistor and an additional first cascade transistor 1k (see Figure 14 The first transistor 1 (base transistor) is interconnected with a first cascade transistor 1k in a first cascade circuit N1, wherein the first transistor 1 and the additional first cascade transistor 1k have a common source-drain terminal 11k. The first cascade circuit N1 is arranged in the substrate plane at an angle of 270° relative to the normal to the primary plane of the semiconductor substrate 20.

[0130] The first MOS transistor arrangement 11 may also include a second transistor cascade circuit N2. This second transistor cascade circuit N2 may in turn include a second transistor 2 as a base transistor and an additional second cascade transistor 2k. The second transistor 2 (base transistor) is interconnected with the second cascade transistor 2k in the second cascade circuit N2, wherein the second transistor 2 and the additional second cascade transistor 2k have a common source-drain terminal 22k. The second cascade circuit N2 is arranged in the substrate plane at a 90° angle relative to the normal to the primary plane of the semiconductor substrate 20.

[0131] The second MOS transistor arrangement 12 can in turn include a third transistor cascade circuit N3. This third transistor cascade circuit N3 can include a third transistor 3 as a base transistor and an additional third cascade transistor 3k. The third transistor 3 (base transistor) is interconnected with the third cascade transistor 3k in the third cascade circuit N3, wherein the third transistor 3 and the additional third cascade transistor 3k have a common source-drain terminal 33k. The third cascade circuit N3 is arranged in the substrate plane at an angle of 180° relative to the normal to the primary plane of the semiconductor substrate 20.

[0132] The second MOS transistor arrangement 12 may further include a fourth transistor cascade circuit N4. This fourth transistor cascade circuit N4 may in turn include a fourth transistor 4 as a base transistor and an additional fourth cascade transistor 4k. The fourth transistor 4 (base transistor) is interconnected with the fourth cascade transistor 4k in the fourth cascade circuit N4, wherein the fourth transistor 4 and the additional fourth cascade transistor 4k have a common source-drain terminal 44k. The fourth cascade circuit N4 is arranged in the substrate plane at an angle of 0° relative to the normal to the primary plane of the semiconductor substrate 20.

[0133] The arrangement described so far with the four cascade circuits N1 to N4 can form a closed embodiment of the transistor-based stress sensor 10 .

[0134] exist Figure 13 The embodiment depicted in can optionally also have further cascade circuits N5 to N8.

[0135] For example, the first MOS transistor arrangement 11 may optionally additionally have a fifth transistor cascade circuit N5. This fifth transistor cascade circuit N5 may in turn have a fifth transistor 5 as a base transistor and an additional fifth cascade transistor 5k (see Figure 14The fifth transistor 5 (base transistor) is interconnected with a fifth cascade transistor 5k in the fifth cascade circuit N5, wherein the fifth transistor 5 and the additional fifth cascade transistor 5k have a common source-drain terminal 55k. The fifth cascade circuit N5 is arranged in the substrate plane at an angle of 270° relative to the normal to the primary plane of the semiconductor substrate 20.

[0136] The first MOS transistor arrangement 11 can optionally additionally have a sixth transistor cascade circuit N6. This sixth transistor cascade circuit N6 can in turn have a sixth transistor 6 as a base transistor and an additional sixth cascade transistor 6k (see Figure 14 The sixth transistor 6 (base transistor) is interconnected with a sixth cascade transistor 6k in a sixth cascade circuit N6, wherein the sixth transistor 6 and the additional sixth cascade transistor 6k have a common source-drain terminal 66k. The sixth cascade circuit N6 is arranged in the substrate plane at an angle of 90° to the normal to the primary plane of the semiconductor substrate 20.

[0137] The second MOS transistor arrangement 12 can optionally additionally have a seventh transistor cascade circuit N7. This seventh transistor cascade circuit N7 can in turn have a seventh transistor 7 as a base transistor and an additional seventh cascade transistor 7k (see Figure 14 The seventh transistor 7 (base transistor) is interconnected with a seventh cascade transistor 7k in a seventh cascade circuit N7, wherein the seventh transistor 7 and the additional seventh cascade transistor 7k have a common source-drain terminal 77k. The seventh cascade circuit N7 is arranged in the substrate plane at an angle of 0° relative to the normal to the primary plane of the semiconductor substrate 20.

[0138] The second MOS transistor arrangement 12 may optionally additionally have an eighth transistor cascade circuit N8. This eighth transistor cascade circuit N8 may in turn have an eighth transistor 8 as a base transistor and an additional eighth cascade transistor 8k (see Figure 14 The eighth transistor 8 (base transistor) is interconnected with an eighth cascade transistor 8k in an eighth cascade circuit N8, wherein the eighth transistor 8 and the additional eighth cascade transistor 8k have a common source-drain terminal 88k. The eighth cascade circuit N8 is arranged in the substrate plane at an angle of 180° relative to the normal to the primary plane of the semiconductor substrate 20.

[0139] In the first MOS transistor arrangement 11, the first cascode circuit N1 and the fifth cascode circuit N5 may share a common drain terminal (see "drain 15"). Alternatively or additionally, in the first MOS transistor arrangement 11, the second cascode circuit N2 and the sixth cascode circuit N6 may share a common drain terminal (see "drain 26").

[0140] In the second MOS transistor arrangement 12, the third cascode circuit N3 and the eighth cascode circuit N8 may share a common drain terminal (see "drain 38"). Alternatively or additionally, in the second MOS transistor arrangement 12, the fourth cascode circuit N4 and the seventh cascode circuit N7 may share a common drain terminal (see "drain 47").

[0141] In the first MOS transistor device 11, the first cascode circuit N1 and the fifth cascode circuit N5 can be oriented in the same direction (with respect to their current flow direction I15). In addition, the second cascode circuit N2 and the sixth cascode circuit N6 can be oriented in the same direction (with respect to their current flow direction I26). However, the current flow direction I15 of the first cascode circuit N1 and the fifth cascode circuit N5 can be oriented opposite to the current flow direction I26 of the second cascode circuit N2 and the sixth cascode circuit N6.

[0142] In the second MOS transistor device 12, the third cascode circuit N3 and the eighth cascode circuit N8 can be oriented in the same direction (with respect to their current flow direction I38). In addition, the fourth cascode circuit N4 and the seventh cascode circuit N7 can be oriented in the same direction (with respect to their current flow direction I47). However, the current flow direction I38 of the third cascode circuit N3 and the eighth cascode circuit N8 can be oriented opposite to the current flow direction I47 of the fourth cascode circuit N4 and the seventh cascode circuit N7.

[0143] The current flow directions I38 and I47 of the first MOS transistor device 11 are perpendicular to the current flow directions I15 and I26 of the second MOS transistor device 12 , respectively.

[0144] Figure 15 A simplified equivalent circuit diagram is shown, in which all base transistors are denoted by capital letters 'B' and in which all additional cascode transistors are denoted by capital letters 'K'. The respective common source-drain regions are denoted by capital letters 'SD'.

[0145] Figure 16 Another embodiment of a transistor-based stress sensor 10 is shown, in which a first MOS transistor arrangement 11 and a second MOS transistor arrangement 12 each comprise a cascade circuit with a plurality of transistors. For example, a first transistor 1 is interconnected with a plurality of cascade transistors 1k, with the drain terminals of the individual transistors 1, 1k being interconnected. Similarly, a second transistor 2 can be interconnected with a plurality of cascade transistors 2k, with the drain terminals of the individual transistors 2, 2k likewise being interconnected.

[0146] The same applies to the second MOS transistor arrangement 12. Here, for example, the third transistor 3 can be interconnected with a plurality of cascaded transistors 3k, wherein the drain terminals of the respective transistors 3, 3k are interconnected. Similarly, the fourth transistor 4 can be interconnected with a plurality of cascaded transistors 4k, wherein the drain terminals of the respective transistors 4, 4k are interconnected.

[0147] and Figure 13 Compared to the cascade circuit shown in (where the individual transistors share a common drain region), Figure 16 There are multiple instances of a single drain terminal in the cascade circuit shown in , but these single drain terminals can be interconnected.

[0148] Figure 16 The example shown shows a 0° / 90° configuration. However, it is also conceivable that the two MOS transistor arrangements 11 , 12 can be arranged in a + / −45° configuration.

[0149] As already mentioned at the outset, the transistor-based stress sensor 10 provides a gradient-compensated output signal which is used to determine the mechanical stress component acting on the semiconductor substrate 20 . Figures 17 to 23 A conceivable embodiment of an evaluation circuit 110 is shown, which is designed to determine the corresponding mechanical stress component based on the output signal of the corresponding stress sensor 10 .

[0150] According to these non-limiting embodiments, the evaluation circuit 110 can be designed to compare the gradient-compensated output signal 111 of the transistor-based stress sensor 10 with a reference signal 112 , wherein the deviation from the reference signal 112 defines a measure for the mechanical stress component to be determined.

[0151] The magnitude of the reference signal 112 may substantially correspond to the magnitude of the input signal 114 of the transistor-based stress sensor 10. That is, the input signal 114 and the reference signal (to which the output signal 111 of the stress sensor 110 is compared) may be the same magnitude.

[0152] According to a first conceivable embodiment, the evaluation circuit 110 can be designed to determine the value of the deviation based on the difference between the gradient-compensated output signal 111 and the reference signal 112 .

[0153] According to a second conceivable embodiment, the evaluation circuit 110 can be designed to determine the value of the deviation based on a multiple ratio between the gradient-compensated output signal 111 and the reference signal 112 .

[0154] Figure 17A first embodiment of an evaluation circuit 110 for a transistor-based stress sensor 10 in a + / -45° configuration is shown. As already mentioned, the arrangement of the first MOS transistor device 11 and the second MOS transistor device 12 at an angle of + / -45° in the substrate plane is particularly suitable for determining the mechanical shear stress component σ XY , σ YZ , σ XZ For this purpose, n-channel transistors can be particularly preferably used.

[0155] An input signal 114 with a substantially constant bias voltage is fed into the transistor-based stress sensor 10. The output signal 111 of the transistor-based stress sensor 10 can be compared with a reference signal 112. In this example, the reference signal 112 has a constant voltage of 1V. The constant voltage in the circuit 110 can be adapted to a voltage with a well-defined temperature dependency when it is determined using the bandgap principle. This enables a varying, but well-defined, temperature coefficient of the measured stress voltage (output signal 111), which can be used, for example, to simplify stress compensation circuits, calculations, or algorithms.

[0156] Furthermore, the magnitude of reference signal 112 can be substantially equal to the magnitude of input signal 114 directed into transistor-based stress sensor 10. In this example, output signal 111 deviates by + / - 155 mV relative to reference signal 112. This deviation corresponds to a measure (direction and / or magnitude) of a mechanical stress component acting on semiconductor substrate 20.

[0157] According to this embodiment, the evaluation circuit 110 can therefore be designed to determine the value of the deviation based on the difference between the gradient-compensated output signal 111 and the reference signal 112 (eg + / −155 mV).

[0158] However, it is also conceivable that the evaluation circuit 110 determines the value of the deviation based on the multiple ratio between the gradient-compensated output signal 111 and the reference signal 112 .

[0159] Figure 18 A further embodiment of an evaluation circuit 110 for a transistor-based stress sensor 10 in a + / -45° configuration, in particular for determining a mechanical shear stress component σ XY , σ YZ , σ XZ For this purpose, n-channel transistors can be particularly preferably used.

[0160] An input signal 114 having a substantially constant current is directed to the transistor-based stress sensor 10. An output signal 111 of the transistor-based stress sensor 10 can be compared to a reference signal 112. In this example, the reference signal 112 has a constant current. The constant current used as the input signal 114 or reference signal is relative to the voltage ( Figure 17 ) is better suited because the temperature coefficient can be better adjusted with the aid of a constant current, in order to enable, for example, stress measurements and higher scaling.

[0161] The value of reference signal 112 can be substantially equal to the value of input signal 114 directed into transistor-based stress sensor 10. In this example, the deviation of output signal 111 from reference signal 112 is + / - 15.5%. This deviation corresponds to a measure (direction and / or magnitude) of the mechanical stress component acting on semiconductor substrate 20.

[0162] The output signal 111 and the reference signal 112 of the strain sensor 10 can both be directed to an analog-to-digital converter (ADC) 113. The ADC 113 can be designed to compare the output signal 111 with the reference signal 112 and generate a corresponding digitized output signal 115, which represents the mechanical strain to be detected.

[0163] According to this embodiment, evaluation circuit 110 can therefore be designed to determine the value of the deviation based on a multiple ratio between gradient-compensated output signal 111 and reference signal 112. That is, in this example, the deviation of output signal 111 relative to reference signal 112 can have a multiple ratio of a factor of 1.155, which corresponds to a percentage value of 15.5%.

[0164] However, it is also conceivable that the evaluation circuit 110 ascertains the value of the deviation based on the difference between the gradient-compensated output signal 111 and the reference signal 112 .

[0165] Figure 19 1 shows a schematic equivalent circuit diagram of a transistor-based stress sensor 10 and the corresponding stress dependence of the individual MOS transistor devices 11, 12 in a + / -45° configuration. Figure 19 The first MOS transistor device 11 depicted in the left part of can be oriented in the

[010] direction and Figure 19 The second MOS transistor device 12 depicted in the right portion may be oriented in a

[100] direction.

[0166] The two MOS transistor arrangements 11 , 12 have direction-dependent sensitivities to mechanical stresses. These sensitivities can be determined, for example, based on the resistance change of the respective MOS transistor arrangement 11 , 12 .

[0167] For example, the first MOS transistor device 11 oriented in the

[010] direction has in total the following direction-dependent sensitivities (expressed in % of resistance change):

[0168] δR

[010] =-24.4δ xx -24.4δ yy +155.6δ xy +53.4δ zz .

[0169] That is, in the case where the current flows in the

[010] direction, the total resistance of the first MOS transistor device 11 experiences the stress caused by the mechanical normal stress component σ XX The change in the x-direction of -24.4% per GPa is caused by the mechanical normal stress component σ yy The change in the y direction of -24.4% per GPa is caused by the mechanical normal stress component σ ZZ In addition, due to the mechanical shear stress component σ xy , the total resistance of the first MOS transistor device 11 undergoes a variation of +155.6% per GPa in the x and y directions.

[0170] The second MOS transistor device 12 oriented in the

[100] direction has the following overall direction-dependent sensitivities (expressed in % of resistance change):

[0171] δR

[100] =-24.4δ xx -24.4δ yy -155.6δ xy +53.4δ zz .

[0172] That is, in the case where the current flows in the

[100] direction, the total resistance of the second MOS transistor device 12 experiences the stress caused by the mechanical normal stress component σ XX The change in the x-direction of -24.4% per GPa is caused by the mechanical normal stress component σ yy The change in the y direction of -24.4% per GPa is caused by the mechanical normal stress component σ ZZ In addition, due to the mechanical shear stress component σ xy , the total resistance of the second MOS transistor device 12 experiences a variation of -155.6% per GPa in both the x and y directions.

[0173] If the sum of these two direction-dependent resistance changes δR

[010] +δR

[100] is now formed, then the normal stress component σ XX, σ YY , σ ZZ These normal stress components may occur due to undesirable gradients acting on the semiconductor substrate 20. However, due to the symmetrical arrangement of the first MOS transistor device 11 and the second MOS transistor device 12 relative to each other, these normal stress components cancel out and a gradient-compensated or substantially gradient-free output signal can be obtained. Figure 19 As can be seen in , only the shear stress component σ remains XY Here, the total resistance change is

[0174] δR 总 =155.6σ XY +155.6σ XY =311.2σ XY .

[0175] That is, according to the innovations described herein, the effective stress dependence of such a stress sensor 10 in a + / -45° configuration is approximately

[0176] ~1-311,2% / GPa x(σ XY ).

[0177] Figure 20 A further embodiment of an evaluation circuit 110 for a transistor-based stress sensor 10 is shown. This embodiment corresponds essentially to the embodiment described previously with reference to Figure 17 One difference, however, is that the first MOS transistor device 11 and the second MOS transistor device 12 are not arranged in a + / -45° configuration as before, but in a 0° / 90° configuration. As already mentioned, the arrangement of the first MOS transistor device 11 and the second MOS transistor device 12 in the substrate plane at an angle of 0° / 90° is particularly suitable for determining the mechanical stress component difference σ XX –σ YY For this purpose, p-channel transistors can be particularly preferably used.

[0178] An input signal 114 having a substantially constant bias voltage is directed to the transistor-based stress sensor 10. An output signal 111 of the transistor-based stress sensor 10 can be compared to a reference signal 112. In this example, the reference signal 112 has a constant voltage of 1V. Furthermore, the magnitude of the reference signal 112 can be substantially equal to the magnitude of the input signal 114 directed to the transistor-based stress sensor 10. In this example, the deviation of the output signal 111 from the reference signal 112 is + / - 414 mV. This deviation corresponds to a measure (direction and / or magnitude) of a mechanical stress component acting on the semiconductor substrate 20.

[0179] According to this embodiment, the evaluation circuit 110 can therefore be designed to determine the value of the deviation based on the difference between the gradient-compensated output signal 111 and the reference signal 112 (eg + / −414 mV).

[0180] However, it is also conceivable that the evaluation circuit 110 determines the value of the deviation based on the multiple ratio between the gradient-compensated output signal 111 and the reference signal 112 .

[0181] Figure 21 A further embodiment of an evaluation circuit 110 for a transistor-based strain sensor 10 in a 0° / 90° configuration, in particular for determining a mechanical strain component difference σ XX –σ YY For this purpose, in turn, in particular p-channel transistors can preferably be used.

[0182] An input signal 114 having a substantially constant current is directed into the transistor-based stress sensor 10. An output signal 111 of the transistor-based stress sensor 10 can be compared to a reference signal 112. In this example, the reference signal 112 has a constant current. Furthermore, the magnitude of the reference signal 112 can be substantially equal to the magnitude of the input signal 114 directed into the transistor-based stress sensor 10. In this example, the deviation of the output signal 111 from the reference signal 112 is + / - 41%. This deviation corresponds to a measure (direction and / or magnitude) of a mechanical stress component acting on the semiconductor substrate 20.

[0183] The output signal 111 and the reference signal 112 of the strain sensor 10 can both be directed to an analog-to-digital converter (ADC) 113. The ADC 113 can be designed to compare the output signal 111 with the reference signal 112 and generate a corresponding digitized output signal 115, which represents the mechanical strain to be detected.

[0184] According to this embodiment, evaluation circuit 110 can therefore be designed to determine the value of the deviation based on the multiple ratio between gradient-compensated output signal 111 and reference signal 112. That is, in this example, the deviation of output signal 111 relative to reference signal 112 can have a multiple ratio of a factor of 1.41, which corresponds to a percentage value of 41%.

[0185] However, it is also conceivable that the evaluation circuit 110 ascertains the value of the deviation based on the difference between the gradient-compensated output signal 111 and the reference signal 112 .

[0186] Figure 221 shows a schematic equivalent circuit diagram of a transistor-based stress sensor 10 and the corresponding stress dependence of the individual MOS transistor devices 11, 12 in a 0° / 90° configuration. For example, the first MOS transistor device 11 may be direction, and the second MOS transistor device 12 may be oriented in, for example, a

[110] direction.

[0187] For example, along The directionally oriented first MOS transistor arrangement 11 has in total the following direction-dependent sensitivities (expressed in % of resistance change):

[0188]

[0189] This results in the so-called total stress of the two normal stress components in the x and y directions for the first MOS transistor arrangement 11:

[0190] 2.8% / GPa x(δ xx +δ yy ).

[0191] The so-called differential stress of the two normal stress components in the x and y directions in the first MOS transistor device 11 is

[0192] -276% / GPa x(δ xx -δ yy ).

[0193] In addition, there is a normal stress component along the z direction. The normal stress component is

[0194] 1.1% / GPa x(δ zz ).

[0195] The second MOS transistor device 12 oriented in the

[110] direction has the following direction-dependent sensitivities (expressed in % of resistance change) in total:

[0196] δR

[110] =-66.3δ xx +71.8δ yy -1.1δ zz .

[0197] This results in the so-called total stress of the two normal stress components in the x and y directions for the second MOS transistor arrangement 12:

[0198] 2.8% / GPa x(δ xx +δ yy ).

[0199] The so-called differential stress of the two normal stress components in the x and y directions in the second MOS transistor device 12 is

[0200] +276% / GPa x(δ xx -δ yy ).

[0201] In addition, there is a normal stress component along the z direction. The normal stress component is

[0202] 1.1% / GPa x(δ zz ).

[0203] If we now form the sum of these two direction-dependent resistance changes The total stress (δ xx +δ yy ) and the normal stress component σ ZZ These stress components may occur due to undesired gradients acting on the semiconductor substrate 20. However, due to the symmetrical arrangement of the first MOS transistor device 11 and the second MOS transistor device 12 relative to each other, these stress components cancel out and a gradient-compensated or substantially gradient-free output signal can be obtained. Figure 22 As can be seen in , only the stress component difference (δxx-δyy) remains.

[0204] Therefore, the effective μ of two strain sensors 10 connected in parallel in a 0° / 90° configuration is p Approximately

[0205] ~1+2.8% / GPa x(δ xx +δ yy )+1.1% / GPa x(δ zz ).

[0206] That is, according to the innovations described herein, the effective stress dependence of such a stress sensor 10 in a 0° / 90° configuration is approximately

[0207] ~1-276% / GPa x(δ xx +δ yy ).

[0208] Figure 23 A further embodiment of an evaluation circuit 110 is also shown using a 0° / 90° configuration as an example. The evaluation circuit 110 has a common-mode signal-controlled regulator 59. Here again, the differential voltage of the strain sensor 10 can be measured.

[0209] By means of the regulator 59 controlled by the common-mode signal, a temperature-dependent or constant common-mode signal voltage can be set.

[0210] According to the innovation described herein, the first MOS transistor device 11 can be arranged on the substrate in a point-symmetrical manner with respect to the second MOS transistor device 12. The point of symmetry can be, for example, a midpoint in the middle of the two MOS transistor devices 11, 12.

[0211] Figure 24A One of the previously discussed embodiments is shown again, in which the transistors 1, 2, 3, 4 are always arranged in a star shape around a center point 50. The transistors 1, 2 of the first MOS transistor arrangement 11 are arranged opposite each other in such a way that they lie on a common first line of symmetry 56. The transistors 3, 4 of the second MOS transistor arrangement 12 are also arranged opposite each other in such a way that they lie on a common second line of symmetry 57. The first line of symmetry 56 and the second line of symmetry 57 are perpendicular to each other.

[0212] Figure 24B Another conceivable embodiment is shown, which is significantly more space-saving and, of course, compatible or combinable with all the embodiments of strain sensor 10 described herein. In this embodiment, transistors 1, 2, 3, 4 are oriented relative to one another in a herringbone-like configuration. In other words, only the inner corners of the individual transistors 1, 2, 3, 4 point in the direction of center point 50.

[0213] First transistor 1 of first MOS transistor arrangement 11 is arranged along first axis of symmetry 56A, and second transistor 2 of first MOS transistor arrangement 11 is arranged along second axis of symmetry 56B. First axis of symmetry 56A extends parallel to second axis of symmetry 56B, but is spatially offset.

[0214] The third transistor 3 of the second MOS transistor arrangement 12 is arranged along a third symmetry axis 57A, and the fourth transistor 4 of the second MOS transistor arrangement 12 is arranged along a fourth symmetry axis 57B. The third symmetry axis 57A extends parallel to the fourth symmetry axis 57B, but is spatially offset.

[0215] The axes of symmetry 56A, 56B of the first MOS transistor arrangement 11 are perpendicular to the axes of symmetry 57A, 57B of the second MOS transistor arrangement 12 .

[0216] The innovations described herein also relate to a stress measurement device 90 having at least two transistor-based stress sensors 10 ( 10A, 10B) of the type described herein.

[0217] Figure 25A schematic diagram shows a conceivable embodiment of such a stress measurement device 90 and the possible locations of two or more transistor-based stress sensors 10A, 10B. The stress measurement device 90 has at least one first transistor-based stress sensor and one second transistor-based stress sensor. The transistor-based stress sensors are arranged on or integrated into the semiconductor substrate 20.

[0218] As mentioned at the outset, the present solution relates on the one hand to transistor-based stress sensors in a + / -45° configuration, which are particularly suitable for measuring the mechanical shear stress component σ acting on the semiconductor substrate 20 XY , σ YZ , σ XZ For this purpose, n-MOS transistors can be used in particular. On the other hand, the present solution relates to transistor-based stress sensors in a 0° / 90° configuration, which are particularly suitable for measuring the difference σ of mechanical stress components acting on the semiconductor substrate 20 XX -σ YY For this purpose, in particular p-MOS transistors can be used.

[0219] exist Figure 25 In the schematic diagram of FIG. 1 , a transistor-based stress sensor in a 0° / 90° configuration is identified by reference numeral 10A, while a transistor-based stress sensor in a + / -45° configuration is identified by reference numeral 10B.

[0220] As mentioned at the outset, the stress measurement device 90 includes at least two transistor-based stress sensors. For example, the stress measurement device 90 may include at least two transistor-based stress sensors 10A in a 0° / 90° configuration. Alternatively or additionally, the stress measurement device 90 may include at least two transistor-based stress sensors 10B in a + / -45° configuration. Alternatively or additionally, the stress measurement device 90 may include at least one transistor-based stress sensor 10A in a 0° / 90° configuration and at least one transistor-based stress sensor 10B in a + / -45° configuration.

[0221] The first stress sensor may be arranged in a first substrate region 20A of the semiconductor substrate 20 , which may be, for example, a stress sensor 10A in a 0° / 90° configuration, which is arranged along an outer edge 20A of the semiconductor substrate 20 .

[0222] In conceivable embodiments, one or more further stress sensors 10A may be arranged along one or more further outer edges 20A of the semiconductor substrate 20 in a 0° / 90° configuration, as exemplarily shown in FIG. Figure 25. For example, the first stress sensor 10A1 can be arranged along the first outer edge 20A1 in a 0° / 90° configuration. Alternatively or additionally, the second stress sensor 10A2 can be arranged along the second outer edge 20A2 in a 0° / 90° configuration. Alternatively or additionally, the third stress sensor 10A3 can be arranged along the third outer edge 20A3 in a 0° / 90° configuration. Alternatively or additionally, the fourth stress sensor 10A4 can be arranged along the fourth outer edge 20A4 in a 0° / 90° configuration.

[0223] The stress difference occurs particularly along the outer edge 20A of the semiconductor substrate 20. Therefore, the stress component difference σ along one or more outer edges 20A of the semiconductor substrate 20 is measured. XY , σ YZ , σ XZ The arrangement of the strain sensor 10A in a 0° / 90° configuration is particularly advantageous.

[0224] A second transistor-based stress sensor can be arranged in a second substrate region 20B of the semiconductor substrate 20, which is different from and spatially separated from the first substrate region 20A. For example, this can be a stress sensor 10B in a + / -45° configuration, which is arranged in a corner 20B of the semiconductor substrate 20.

[0225] In conceivable embodiments, one or more further stress sensors 10B may be arranged in a + / - 45° configuration in one or more further corners 20B of the semiconductor substrate 20 , as exemplarily shown in FIG. Figure 25 . For example, the first stress sensor 10B1 can be arranged in the first corner 20B1 in a + / - 45° configuration. Alternatively or additionally, the second stress sensor 10B2 can be arranged in the second corner 20B2 in a + / - 45° configuration. Alternatively or additionally, the third stress sensor 10B3 can be arranged in the third corner 20B3 in a + / - 45° configuration. Alternatively or additionally, the fourth stress sensor 10B4 can be arranged in the fourth corner 20B4 in a + / - 45° configuration.

[0226] Shear stress occurs particularly in the corners 20B of the semiconductor substrate 20. Therefore, the shear stress component σ in one or more corners 20B of the semiconductor substrate 20 is measured. XY ,σ YZ ,σ XZ The arrangement of the strain sensor 10B in a + / - 45° configuration is particularly advantageous.

[0227] A first transistor-based stress sensor of the at least two transistor-based stress sensors 10A, 10B provides a gradient-compensated first output signal for determining a first mechanical stress component acting on the semiconductor substrate 20 .

[0228] The second transistor-based stress sensor of the at least two transistor-based stress sensors 10A, 10B provides a second gradient-compensated output signal for determining a second mechanical stress component acting on the semiconductor substrate 20 .

[0229] The stress measuring device 90 is designed to determine the total mechanical stress acting on the semiconductor substrate 20 based on the gradient-compensated first and second output signals.

[0230] Conventional stress measurement devices typically have only a single stress sensor located in the center of the semiconductor substrate 20. However, the stress measurement device 90 described herein, which has at least two stress sensors 10A, 10B arranged in different substrate regions 20A, 20B, can provide significantly more accurate results.

[0231] For example, a strain sensor 10B may be arranged in one, several, or all corners 20B of the semiconductor substrate 20, wherein each of these strain sensors 10B provides a gradient-compensated output signal as described above. The strain measuring device 90 can then combine all of these individual gradient-compensated output signals to determine the total stress acting on the semiconductor substrate 20, and in this case, in particular, the total stress indicated by the shear stress.

[0232] Alternatively or additionally, a strain sensor 10A may be arranged along one, several, or all outer edges 20A of the semiconductor substrate 20, wherein each of these strain sensors 10A provides a gradient-compensated output signal as described above. The strain measuring device 90 can then combine all of these individual gradient-compensated output signals to determine the total stress acting on the semiconductor substrate 20, and in particular, the stress difference.

[0233] In particular, when stress sensors 10A are arranged in a 0° / 90° configuration along outer edge 20A, it may be advantageous to arrange these stress sensors centrally at the respective outer edge 20A. That is, when considering the total length of outer edge 20A, stress sensors 10A may be arranged halfway along the length of the respective outer edge 20A. Deviations of ±10% to ±20% of half the length (i.e., the center of the outer edge) are tolerable and fall within the scope of the claims.

[0234] In summary, the solution described herein thus proposes one or more transistor-based stress sensors 10. These stress sensors are particularly designed to detect shear-induced stress (with a 0° / 90° configuration of n-MOS transistors) or stress differences (with a ±45° configuration of p-MOS transistors).

[0235] This stress information allows external compensation of the corresponding stress components (for example in a microprocessor) in order to achieve higher precision and improved stability over the entire lifetime of the component mounted on the semiconductor substrate.

[0236] For example, the shear-induced stresses determined by means of the stress sensor 10 can be used in particular to compensate for stress dependencies of quadrature errors in vertical Hall plates (arranged on the same semiconductor substrate 20 ).

[0237] In contrast, the stress difference determined with the aid of stress sensor 10 can be used in particular to compensate for stress dependencies in the oscillator and the band gap, as well as for residual stress dependencies in Hall voltage sensors arranged on the same semiconductor substrate 20 .

[0238] In general, the stress information that can be determined with the aid of the stress sensor 10 can be used to increase the accuracy of the following components:

[0239] Angle sensor based on Hall voltage

[0240] LinHal sensor expansion

[0241] AMR and Hall voltage-based functional safety angle sensors

[0242] 3D sensor derivatives

[0243] Accurate voltage measurement IC (battery monitoring) and bandgap

[0244] Precision oscillator and high-speed interface

[0245] The arrangement of the transistors 1 , 2 , 3 , 4 of the first MOS transistor arrangement 11 and the second MOS transistor arrangement 12 may be mirror-symmetrical, rotationally symmetrical, or point-symmetrical.

[0246] The above embodiments are merely illustrative of the principles of the innovative solutions described herein. It should be understood that modifications and variations of the arrangements and details described herein will be readily apparent to those skilled in the art. It is therefore intended that the solutions described herein be limited solely by the scope of the appended claims and not by the specific details presented herein through the description and illustration of the embodiments.

[0247] Although some aspects are described in conjunction with an apparatus, it should be understood that these aspects also represent descriptions of corresponding methods, and thus blocks or structural elements of the apparatus can also be understood as corresponding method steps or features of method steps. Similarly, aspects described in conjunction with or as method steps also represent descriptions of corresponding blocks, details, or features of the corresponding apparatus.

[0248] Some or all of the method steps can be performed by hardware devices (or using hardware devices), such as microprocessors, programmable computers or electronic circuits. In some embodiments, some or more of the most important method steps can be performed by such devices.

[0249] Depending on the specific implementation requirements, the embodiments can be implemented in hardware or software or at least partially in hardware or at least partially in software. The implementation can be performed using a digital storage medium, such as a floppy disk, DVD, Blu-ray disc, CD, ROM, PROM, EPROM, EEPROM or flash memory, hard disk or other magnetic or optical storage, on which electronically readable control signals are stored, which interact or can interact with a programmable computer system to cause the corresponding method to be performed. Therefore, the digital storage medium can be computer-readable.

[0250] Some exemplary embodiments also include a data carrier having electronically readable control signals, which are capable of interacting with a programmable computer system such that one of the methods described herein is performed.

[0251] Generally, the embodiments can be implemented as a computer program product with a program code, wherein the program code is effective for performing one of the methods when the computer program product runs on a computer.

[0252] The program code can also be stored on a machine-readable carrier, for example.

[0253] Other embodiments include a computer program for performing one of the methods described herein, wherein the computer program is stored on a machine-readable medium. In other words, an embodiment of the method described herein is therefore a computer program having a program code for performing one of the methods described herein when the computer program runs on a computer.

[0254] Therefore, a further embodiment of the methods described herein is a data carrier (or a digital storage medium or a computer-readable medium) on which is recorded the computer program for performing one of the methods described herein. The data carrier or the digital storage medium or the computer-readable medium is typically tangible and / or non-transitory.

[0255] Therefore, another embodiment of the methods described herein is a data stream or a signal sequence representing a computer program for performing one of the methods described herein. The data stream or signal sequence can be configured, for example, to be transmitted via a data communication connection, for example via the Internet.

[0256] A further embodiment comprises a processing device, for example a computer or a programmable logic component, configured or adapted to perform one of the methods described herein.

[0257] A further embodiment comprises a computer on which is installed the computer program for performing one of the methods described herein.

[0258] Another embodiment includes an apparatus or system configured to transmit a computer program for performing at least one of the methods described herein to a receiver. The transmission may be performed electronically or optically, for example. The receiver may be, for example, a computer, a mobile device, a storage device, or the like. The apparatus or system may include, for example, a file server for transmitting the computer program to the receiver.

[0259] In some embodiments, a programmable logic component (e.g., a field programmable gate array, FPGA) can be used to perform some or all of the functions of the methods described herein. In some embodiments, a field programmable gate array can work in conjunction with a microprocessor to perform one of the methods described herein. Generally, in some embodiments, these methods are performed in terms of any hardware device. The hardware device can be general hardware, such as a computer processor (CPU), or hardware dedicated to the method, such as an ASIC.

Claims

1. A transistor-based stress sensor (10) having: A semiconductor substrate (20) having a first MOS transistor device (11) and a second MOS transistor device (12), wherein the first MOS transistor device (11) has a first MOS transistor (1) with a first source-drain channel region (23) and a second MOS transistor (2) with a second source-drain channel region (33), wherein the first MOS transistor (1) and the second MOS transistor (2) are oriented relative to each other such that a current flow direction (24) in the first source-drain channel region (23) is opposite to a current flow direction (34) in the second source-drain channel region (33), and wherein the second MOS transistor device (12) comprises a third MOS transistor (3) with a third source-drain channel region (43) and a fourth MOS transistor (4) with a fourth source-drain channel region (53), wherein the third MOS transistor (3) and the fourth MOS transistor (4) are oriented relative to each other such that a current flow direction (44) in the third source-drain channel region (43) is opposite to a current flow direction (54) in the fourth source-drain channel region (53), wherein the transistor-based stress sensor (10) provides a gradient-compensated output signal for determining at least one mechanical stress component acting on the semiconductor substrate (20), The transistor-based stress sensor (10) is designed to measure only the stress actually acting from the outside on the semiconductor substrate, but not to measure gradient-based effects altogether, wherein the gradient describes a temporally variable stress component.

2. The transistor-based stress sensor (10) according to claim 1, wherein a current flow direction (24) in the first source-drain channel region (23) extends at a first angle (Φ1) relative to a normal to a primary plane of the semiconductor substrate (20), and wherein the current flow direction (44) in the third source-drain channel region (43) extends at a second angle (Φ2) relative to the normal to the primary plane of the semiconductor substrate (20), The first angle (Φ1) and the second angle (Φ2) are perpendicular to each other.

3. The transistor-based stress sensor (10) according to claim 2, wherein the first angle (Φ1) is +45°, and wherein the second angle (Φ2) is -45°, and The transistor-based stress sensor (10) is designed to determine a mechanical shear stress component (σ) acting on the semiconductor substrate (20). XY , σ YZ , σ XZ ).

4. The transistor-based stress sensor (10) according to claim 3, The MOS transistors (1, 2) of the first MOS transistor device (11) and the MOS transistors (3, 4) of the second MOS transistor device (12) are both n-channel type.

5. The transistor-based stress sensor (10) according to claim 2, wherein the first angle (Φ1) is 90°, and wherein the second angle (Φ2) is 0°, and The transistor-based stress sensor (10) is designed to determine differences in mechanical stress components acting on the semiconductor substrate (20).

6. The transistor-based stress sensor (10) according to claim 5, The MOS transistors (1, 2) of the first MOS transistor device (11) and the MOS transistors (3, 4) of the second MOS transistor device (12) are respectively of p-channel type.

7. A transistor-based stress sensor (10) according to any one of claims 1 to 6, The first MOS transistor device (11) is arranged point-symmetrically with the second MOS transistor device (12) in the substrate plane.

8. A transistor-based stress sensor (10) according to any one of claims 1 to 6, wherein the drain terminals (22, 32) of the MOS transistors (1, 2) of the first MOS transistor device (11) are connected to each other, and The drain terminals (42, 52) of the MOS transistors (3, 4) of the second MOS transistor device (12) are connected to each other.

9. A transistor-based stress sensor (10) according to any one of claims 1 to 6, The first MOS transistor device (11) has a fifth MOS transistor (5), the fifth MOS transistor sharing a common drain region (22) with the first MOS transistor (1), and a sixth MOS transistor (6), the sixth MOS transistor sharing a common drain region (32) with the second MOS transistor (2), and The second MOS transistor device (12) has a seventh MOS transistor (7), the seventh MOS transistor sharing a common drain region (42) with the third MOS transistor (3), and An eighth MOS transistor (8), the eighth MOS transistor and the fourth MOS transistor (4) share a common drain region (52).

10. The transistor-based stress sensor (10) according to any one of claims 7, The first MOS transistor (1) and the first cascade transistor (1k) are connected to form a first cascade circuit (N1), The second MOS transistor (2) and the second cascade transistor (2k) are connected to form a second cascade circuit (N2), The third MOS transistor (3) and the third cascade transistor (3k) are connected to form a third cascade circuit (N3), and The fourth MOS transistor (4) and the fourth cascade transistor (4k) are connected to form a fourth cascade circuit (N4).

11. The transistor-based stress sensor (10) according to claim 10, The first cascade circuit (N1) and the fifth cascade circuit (N5) are connected at a common drain terminal (drain15), wherein the second cascade circuit (N2) and the sixth cascade circuit (N6) are connected at a common drain terminal (drain26), wherein the third cascade circuit (N3) is connected to the eighth cascade circuit (N8) at a common drain terminal (drain38), and wherein the fourth cascade circuit (N4) and the seventh cascade circuit (N7) are connected at a common drain terminal (drain47), and The cascade circuits (N1, ..., N8) are arranged in the substrate plane such that The current flow direction (I15) of the first cascade circuit (N1) and the fifth cascade circuit (N5) connected to each other is opposite to the current flow direction (I26) of the second cascade circuit (N2) and the sixth cascade circuit (N6) connected to each other, and The current flow direction (I38) of the third cascade circuit (N3) and the eighth cascade circuit (N8) connected to each other is opposite to the current flow direction (I47) of the fourth cascade circuit (N4) and the seventh cascade circuit (N7) connected to each other.

12. The transistor-based stress sensor (10) according to any one of claims 1 to 6, An evaluation circuit (110) is also provided, which is designed to compare the gradient-compensated output signal (111) of the transistor-based stress sensor (10) with a reference signal (112), wherein a deviation from the reference signal (112) defines a measure for the mechanical stress component to be determined, and The evaluation circuit (110) is designed to: Calculating the value of the deviation based on the difference between the gradient-compensated output signal (111) and the reference signal (112), or The value of the deviation is obtained based on the multiple ratio between the gradient-compensated output signal (111) and the reference signal (112).

13. The transistor-based stress sensor (10) according to claim 12, The reference signal (112) is a reference voltage or a reference current, and the value of the reference signal (112) is the same as the value of the input signal (114) of the transistor-based stress sensor (10).

14. A method for gradient-compensated determination of at least one mechanical stress component acting on a semiconductor substrate (20) by means of a transistor-based stress sensor (10) according to any one of claims 1 to 13, wherein the method comprises the following steps: applying an input signal (114) to the transistor-based stress sensor (10) and tapping a gradient-compensated output signal (111) of the transistor-based stress sensor (10), comparing the gradient-compensated output signal (111) with a reference signal (112), wherein the deviation from the reference signal (112) defines a measure for the mechanical stress component to be determined, and The value of the deviation is determined based on a difference between the gradient-compensated output signal (111) and the reference signal (112), or the value of the deviation is determined based on a multiple ratio between the output signal (111) and the reference signal (112).

15. A program product having a program code for executing the method according to claim 14 when the program is run on a computer.

16. A stress measurement device (90) having at least two transistor-based stress sensors (10A, 10B) according to any one of claims 1 to 13, A first transistor-based stress sensor of at least two of the transistor-based stress sensors (10A, 10B) provides a gradient-compensated first output signal, wherein the gradient-compensated first output signal is used to determine a first mechanical stress component acting on the semiconductor substrate (20), and in, A second transistor-based stress sensor of the at least two transistor-based stress sensors (10A, 10B) provides a gradient-compensated second output signal, wherein the gradient-compensated second output signal is used to determine a second mechanical stress component acting on the semiconductor substrate (20), wherein the first transistor-based stress sensor (10A) is arranged in a first substrate region (20A) of the semiconductor substrate (20), and wherein the second transistor-based stress sensor (10B) is arranged in a second substrate region (20B) of the semiconductor substrate (20) that is different from and spatially separated from the first substrate region (20A), and The stress measuring device (90) is designed to obtain the total mechanical stress acting on the semiconductor substrate (20) based on the first output signal of gradient compensation and the second output signal of gradient compensation.

17. The stress measuring device (90) according to claim 16, wherein the first transistor-based stress sensor (10B1) is arranged in a first corner (20B1) of the semiconductor substrate (20), and wherein the second transistor-based stress sensor (10B2) is arranged in a second corner (20B2) of the semiconductor substrate (20) different from the first corner (20B1), and The first transistor-based stress sensor (10B1) and the second transistor-based stress sensor (10B2) are respectively designed to determine mechanical shear stress components acting in corresponding corners (20B1, 20B2) of the semiconductor substrate (20).

18. The stress measuring device (90) according to claim 16 or 17, wherein the first transistor-based stress sensor (10A1) is arranged along a first outer edge (20A1) of the semiconductor substrate (20), and wherein the second transistor-based stress sensor (10A2) is arranged along a second outer edge (20A2) of the semiconductor substrate (20) different from the first outer edge (20A1), The first transistor-based stress sensor (10A1) and the second transistor-based stress sensor (10A2) are respectively designed to determine a difference in mechanical stress components acting along respective outer edges (20A1, 20A2) of the semiconductor substrate (20).

19. The stress measuring device (90) according to claim 18, wherein the first transistor-based stress sensor (10A1) is arranged over half of the total length of the first outer edge (20A1), and The second transistor-based stress sensor (10A2) is arranged on half of the total length of the second outer edge (20A2).

Images