Intelligent erasing scheme

Abstract

A method of performing an erase operation on a non-volatile storage device is disclosed. The method includes applying a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation, determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse, determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements, and applying the second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

Description

TECHNICAL FIELD

[0001] This application relates to non-volatile memory devices and operations of non-volatile memory devices. BACKGROUND

[0002] This section provides background information to the technology associated with the present disclosure and as such is not necessarily prior art.

[0003] Semiconductor memory devices have become more prevalent in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0004] Charge storage materials, such as floating gates, or charge trapping materials can be used in such memory devices to store charge representative of a data state. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure. One example of a 3D memory structure is a bit cost scalable (BiCS) architecture, which includes a stack of alternating conductive layers and dielectric layers. SUMMARY

[0005] This section provides a general summary of the present disclosure and is not a comprehensive disclosure of its full scope or all of its features and advantages.

[0006] It is an object of the present disclosure to provide a memory device and a method of operating a memory device that addresses and overcomes the disadvantages described herein.

[0007] Accordingly, one aspect of the present disclosure is to provide a method of performing an erase operation on a non-volatile storage device. The method includes applying a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation, determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse, determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements, and applying the second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

[0008] Further, an aspect of the present disclosure is to provide a non-volatile storage device. The non-volatile storage device includes a set of non-volatile storage elements and one or more managing circuits in communication with the set of non-volatile storage elements. The one or more managing circuits are configured to: apply a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation; determine an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determine a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and apply the second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

[0009] Further, an aspect of the present disclosure is to provide another method of performing an erase operation on a non-volatile storage device. The method includes: applying a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements, an erase slope, and an erase verify level; and applying the second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles.

[0010] Other suitable ranges will become apparent from the description provided herein. The description and specific examples in this summary are intended only to provide illustrative purposes and are not intended to be limiting in scope. BRIEF DESCRIPTION OF DRAWINGS

[0011] For a detailed description of example embodiments, reference will now be made to the accompanying drawings in which:

[0012] Figure 1A is a block diagram of an example memory device;

[0013] Figure 1B is a block diagram of an example control circuit including a program circuit, a count circuit, and a determination circuit;

[0014] Figure 2 depicts a block of memory cells in an example two-dimensional configuration of the memory array of FIG. 1;

[0015] Figure 3A depicts a cross-sectional view of an example floating gate memory cell in a NAND string;

[0016] Figure 3B depicts a cross-sectional view of a structure of Figure 3A along line 329;

[0017] Figure 4A A cross-sectional view depicting an example charge-capture memory cell in a NAND string;

[0018] Figure 4B Depicting along line 429 Figure 4A A cross-sectional view of the structure;

[0019] Figure 5A An example block diagram depicting the sensing block SB1 in Figure 1;

[0020] Figure 5B Another example block diagram depicting the sensing block SB1 in Figure 1;

[0021] Figure 6A This is a perspective view of the block set in an example three-dimensional configuration of the memory array in Figure 1;

[0022] Figure 6B Depicting Figure 6A An example cross-sectional view of a portion of one of the blocks;

[0023] Figure 6C Depicting Figure 6B A plot of the diameter of the memory holes in the stack;

[0024] Figure 6D Depicting Figure 6B A close-up view of the stacked area 622;

[0025] Figure 7A Depicting Figure 6B A top view of the stacked example wordline layer WLL0;

[0026] Figure 7B Depicting Figure 6B A top view of the top dielectric layer DL19 in an example of stacking;

[0027] Figure 8A Depicting Figure 7A Example NAND strings in sub-blocks SBa to SBd;

[0028] Figure 8B Another example view depicting the NAND string in the sub-block;

[0029] Figure 8C A top view depicting a stacked example of a layer of letter lines;

[0030] Figure 9 Describe the Vth distribution of memory cells in an example one-way programming operation with four data states;

[0031] Figure 10 Describe the Vth distribution of memory cells in an example one-way programming operation with eight data states;

[0032] Figure 11 Depiction of Vth distribution of memory cells in an example one-pass program operation with sixteen data states;

[0033] Figure 12 Depiction of a method of erasing a non-volatile storage device according to embodiments described herein;

[0034] Figure 13A An example illustration of an erase threshold distribution following the intelligent erase scheme described above with reference to Figure 12

[0035] Figure 13B Providing a close-up view of the upper tail of a threshold voltage distribution of a set of non-volatile storage elements;

[0036] Figure 14 Depiction of another method of erasing a non-volatile storage device according to embodiments described herein. DETAILED DESCRIPTION

[0037] In the following description, numerous specific details are set forth to provide a thorough understanding of the present disclosure. In some examples, well-known or otherwise conventional circuit, structures, and techniques have not been described in detail because such

[0038] In general, the present disclosure relates to non-volatile memory devices of the type that are well suited for use in many applications. Non-volatile memory devices and associated formation methods of the present disclosure will be described in connection with one or more example embodiments. However, the particular example embodiments disclosed are provided merely to sufficiently describe the present inventive concepts, features, advantages, and objectives to permit one of ordinary skill in the art to understand and practice the present disclosure. In particular, the example embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Numerous specific details are set forth, such as examples of specific components, devices, and methods, to provide a thorough understanding of the present embodiments of the present disclosure. One skilled in the relevant art will recognize, however, that the example embodiments can be practiced without the specific details, that the example embodiments can be practiced with the specific details, and that the disclosure is not to be limited to a particular embodiment or a particular application. In some example embodiments, well-known processes, well-known device structures, and well-known techniques are not described in detail.

[0039] ​Various terminology is used to refer to particular system components. Different companies may refer to a component by different names — this document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to..." Also, the term "couple" is intended to mean either an indirect or direct connection. Thus, if a first device couples to a second device, that connection can be through a direct connection, or through an indirect connection via other devices and connections.

[0040] Also, when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the substrate's other layer, or intervening layers can also be present. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under, and can also be present in intervening layers. Also, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.

[0041] Programming operations for a set of memory cells of a memory device generally involve applying a series of program voltages to the memory cells after the memory cells are provided in an erased state. Each program voltage is provided in a program loop, also referred to as a program verify iteration. For example, a program voltage can be applied to a word line connected to a control gate of a memory cell. In one approach, incremental step pulse programming is performed in which the program voltage is increased by a step size in each program loop. A verify operation can be performed after each program voltage to determine whether the memory cell has completed programming. Upon completion of programming of a memory cell, the memory cell can be locked out from further programming while programming of other memory cells continues in subsequent program loops.

[0042] Each memory cell can be associated with a data state according to write data in a program command. Based on its data state, a memory cell will remain in an erased state or programmed to a data state different from the erased state (a programmed data state). For example, in a one bit-per-cell memory device (single level cell (SLC)), there are two data states including an erased state and one higher data state. In a two bit-per-cell memory device (multi-level cell (MLC)), there are four data states including an erased state and three higher data states (referred to as A, B, and C data states (see Figure 9 Figure 10 ​eight data states. In a four-bit per cell memory device (four-level cell (QLC)), there are sixteen data states including an erase state and fifteen higher data states referred to as Er, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F data states (see Table 1 Figure 11

[0043] Upon issuance of a program command, the write data is stored in latches associated with the memory cells. During programming, the latches of the memory cells can be read to determine the data state that the cell will be programmed to. Each programmed data state is associated with a verify voltage, such that when a sensing operation determines that the threshold voltage (Vth) of a memory cell having a given data state is above the associated verify voltage, the memory cell is considered to have completed programming. The sensing operation can determine whether a memory cell has a Vth above the associated verify voltage by applying the associated verify voltage to the control gate and sensing the current through the memory cell. If the current is relatively high, this indicates that the memory cell is in a conductive state such that Vth is less than the control gate voltage. If the current is relatively low, this indicates that the memory cell is in a non-conductive state such that Vth is higher than the control gate voltage.

[0044] The verify voltage used to determine that a memory cell has completed programming can be referred to as a final or lock verify voltage. In some cases, an additional verify voltage can be used to determine that a memory cell is about to complete programming. This additional verify voltage can be referred to as an offset verify voltage, and can be lower than the final verify voltage. When a memory cell is about to complete programming, the programming speed of the memory cell can be reduced, for example, by raising the voltage of the corresponding bit line during one or more subsequent program voltages. For example, in Figure 9 In, a memory cell programmed to the A data state can undergo a verify test at VvAL, the offset verify voltage for the A data state, and VvA, the final verify voltage for the A data state.

[0045] Erasing can be performed across a memory array, individual blocks, or another unit of cells. In one embodiment, a group of memory cells is erased by raising the p-well of the memory cells to an erase voltage for a sufficient period of time. The erase pulse moves the threshold voltage of the memory cells toward (or beyond) an erase target level, which can be lower than 0 volts. In some embodiments, after the erase pulse is applied, an erase verify operation is performed to determine whether the threshold voltage of the memory cells has at least reached the erase target level. The erase pulse and erase verify are repeated with a higher amplitude erase pulse in each cycle until the erase verify passes.​

[0046] Generally, an erase operation can be completed in multiple cycles (e.g., two cycles). For example, an erase voltage (VERA) can be used in a first cycle, and the erase voltage can be increased by a boost voltage (dVERA) and used in a second cycle. The number of cycles implemented in an erase operation can be limited by the time of the erase operation (tERASE). If the number of cycles used in an erase operation is increased, the time to perform the erase operation will increase. A two-pulse erase operation can satisfy the time of the erase operation tERASE. However, over time, especially at end of product life, it can become more difficult to erase some memory devices. In some examples, three cycles can be needed if the second pulse does not pass erase verification.

[0047] To address the above issues, embodiments described herein involve implementation of a smart erase scheme. For example, a smart erase scheme can include performing an erase verify voltage (VCG ERV) scan with bit ignore after a first erase pulse to find an erase upper tail, and determining a second erase pulse based on the erase tail, erase slope, and erase verify level. Some of the benefits provided by embodiments described herein include ensuring that an erase operation will be completed within two erase cycles to comply with tERASE, allowing three cycles in the event the second pulse does not pass erase verification, and better control of erase depth rather than being limited to a quantized boost voltage (e.g., dVERA).

[0048] To help further illustrate the foregoing, a description will now be described Figure 1A . Figure 1A is a block diagram of an example memory device. The memory device 100 can include one or more memory dies 108. The memory die 108 includes a memory structure 126 (e.g., an array of memory cells) of memory cells, control circuitry 110, and read / write circuitry 128. The memory structure 126 is addressable by word lines via a row decoder 124 and by bit lines via a column decoder 132. The read / write circuitry 128 includes a plurality of sense blocks SB1, SB2,... SBp (sense circuitry) and allows pages of memory cells to be read or programmed in parallel. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as the one or more memory dies 108. Commands and data are transferred between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory dies 108 via lines 118.

[0049] As referenced above Figure 1AThe controller 122 is described as included in the same memory device 100 as the one or more memory dies 108. For example, in some embodiments, the memory device can include NAND flash dies positioned adjacent to each other in a column; while, in some embodiments, the memory device can include NAND flash dies stacked on top of each other. Further, in some embodiments, the memory device can include stacked NAND flash dies and a controller as a separate die inside the package.

[0050] The memory structure can be 2D or 3D. The memory structure can include one or more arrays of memory cells, including 3D arrays. The memory structure can include a monolithic three-dimensional memory structure in which multiple levels of memory are formed above (rather than in) a single substrate (e.g., wafer), without an intervening substrate. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical levels of memory cells having active regions disposed above a silicon substrate. The memory structure can be in a non-volatile memory device having circuitry associated with operation of the memory cells, whether the associated circuitry is above the substrate or within the substrate.

[0051] The control circuitry 110 cooperates with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations. A storage region 113 can be set up, for example, for verification parameter settings as described herein.

[0052] The on-chip address decoder 114 provides an address interface between an address interface used by a host or memory controller and the hardware addresses used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. The power control module can include drivers for word lines, SGS and SGD transistors, and source lines. In one approach, a sense block can include a bit line driver. SGS transistors are select gate transistors at the source end of a NAND string, and SGD transistors are select gate transistors at the drain end of a NAND string.

[0053] In some implementations, some of the components can be combined. In various designs, one or more of the components other than the memory structure 126, alone or in combination, can be viewed as at least one control circuit configured to perform the actions described herein. For example, the control circuit can include any one or a combination of: the control circuit 110, the state machine 112, the decoders 114 / 132, the power control module 116, the sense blocks SBb, SB2...SBp, the read / write circuits 128, the controller 122, etc.

[0054] The control circuit can include a program circuit configured to program word lines of a block of memory cells and verify the group of memory cells. The control circuit can also include a count circuit configured to determine a number of memory cells verified to be in a data state. The control circuit can also include a determination circuit configured to determine whether the block is defective based on the number.

[0055] For example, Figure 1B is a block diagram of an example control circuit 150 including a program circuit 151, a count circuit 152, and a determination circuit 153. The program circuit can include software, firmware, and / or hardware. The count circuit can include software, firmware, and / or hardware. The determination circuit can include software, firmware, and / or hardware.

[0056] The off-chip controller 122 can include a processor 122c, storage (memory) such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct for a number of read errors caused by the upper tail of the Vth distribution becoming too high. However, in some cases, there can be uncorrectable errors. The techniques provided herein reduce the likelihood of uncorrectable errors.

[0057] The storage includes code, such as a set of instructions, and the processor is operable to execute the set of instructions to provide the functionality described herein. Alternatively, or in addition, the processor can access code from the storage 126a of the memory structure, such as a reserved area of memory cells in one or more word lines.

[0058] For example, the controller 122 can use code to access, for example, a memory structure for programming, reading, and erase operations. The code can include boot code and control code (e.g., instruction sets). Boot code is software that initializes the controller during a boot or start-up process and enables the controller to access the memory structure. The controller can use the code to control one or more memory structures. Upon power-up, the processor 122c fetches the boot code from the ROM 122a or storage 126a for execution, and the boot code initializes the system components and loads the control code into the RAM 122b. Once the control code is loaded into the RAM, it is executed by the processor. The control code includes drivers to perform basic tasks such as controlling and allocating memory, prioritizing the processing of instructions, and controlling input and output ports.

[0059] In one embodiment, the host is a computing device (e.g., a laptop computer, a desktop computer, a smartphone, a tablet computer, a digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard drives, solid state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host can also include additional system memory, one or more input / output interfaces and / or one or more input / output devices in communication with the one or more processors.

[0060] Other types of non-volatile memory besides NAND flash memory can also be used.

[0061] Semiconductor memory devices include volatile memory devices, such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, and non-volatile memory devices, such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), and other semiconductor elements capable of storing information. Each type of memory device, such as flash memory, can have a different configuration.

[0062] Memory devices can be formed from passive and / or active elements in any combination. As non-limiting examples, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as resistive random access memory (ReRAM) or phase change material, and optionally steering elements, such as diodes or transistors. Further, as non-limiting examples, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric material.

[0063] Multiple memory elements can be configured so that they are connected in series or so that each element can be individually accessed. As a non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND string is an example of a group of series-connected transistors including memory cells and SG transistors.

[0064] A NAND memory array can be configured so that the array is composed of multiple strings of memory, where a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured so that each element can be individually accessed, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0065] Semiconductor memory elements located within and / or above a substrate can be arranged in two-dimensional or three-dimensional form, such as a two-dimensional memory structure or a three-dimensional memory structure.

[0066] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane that extends generally parallel to a major surface of a substrate that supports the memory elements (e.g., in an x-z direction plane). The substrate can be a wafer on or in which layers of memory elements are formed, or can be a carrier substrate that is attached to the memory elements after the memory elements are formed. As a non-limiting example, the substrate can include a semiconductor such as silicon.

[0067] Memory elements can be arranged in a single memory device level, such as an ordered array of multiple rows and / or columns, etc. However, memory elements can be arranged in irregular or non-orthogonal configurations. Memory elements can each have two or more electrodes or contact lines, such as bit lines and word lines.

[0068] Three-dimensional memory arrays are arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y, and z directions, where the z direction is generally perpendicular to the major surfaces of the substrate and the x and y directions are generally parallel to the major surfaces of the substrate).

[0069] As a non-limiting example, a three-dimensional memory structure can be arranged vertically as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending generally perpendicular to the major surfaces of the substrate, i.e., in the y direction), where each column has multiple memory elements. The columns can be arranged, for example, in a two-dimensional configuration in the x-y plane, resulting in a three-dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three-dimensional memory array.

[0070] As a non-limiting example, in a three-dimensional NAND memory array, memory elements can be coupled together to form NAND strings within a single horizontal (e.g., x-y) memory device level. Alternatively, memory elements can be coupled together to form vertical NAND strings that traverse multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned in which some NAND strings contain memory elements in a single memory level, while other strings contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR configurations and ReRAM configurations.

[0071] Generally, in a monolithic three-dimensional memory array, one or more memory device levels are formed over a single substrate. Optionally, a monolithic three-dimensional memory array can also have one or more memory levels that are at least partially within the single substrate. As a non-limiting example, the substrate can comprise a semiconductor such as silicon. In a monolithic three-dimensional array, the layers that make up each memory device level of the array are generally formed on the layers of the underlying memory device levels of the array. However, the layers of adjacent memory device levels of a monolithic three-dimensional memory array can be shared, or have intervening layers between the memory device levels.

[0072] Also, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device having multiple memory levels. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of one another. The substrates can be thinned or removed from the memory device levels prior to stacking, but because the memory device levels are initially formed over separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Further, multiple two-dimensional memory arrays or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0073] Generally, associated circuitry is needed to operate and communicate with memory elements. As non-limiting examples, a memory device can have circuitry for controlling and driving memory elements to implement functions such as programming and reading. Such associated circuitry can be on the same substrate as the memory elements and / or on a separate substrate. For example, a controller for memory read and write operations can be on a separate controller chip and / or on the same substrate as the memory elements.

[0074] Those of skill in the art will recognize that the technology is not limited to the described two-dimensional and three-dimensional example structures, but encompasses all relevant memory structures within the spirit and scope of the technology as described herein and as understood by those of skill in the art.

[0075] Figure 2 A block of memory cells in an example two-dimensional configuration of the memory array 126 of Figure 1 is depicted. The memory array can include many blocks. Each example block 200, 210 includes a plurality of NAND strings and corresponding bit lines, e.g., BL0, BL1,..., which are shared among the blocks. Each NAND string is connected at one end to a drain select gate (SGD), and the control gates of the drain select gates are connected via a common SGD line. The NAND strings are connected at their other end to source select gates, which in turn are connected to a common source line 220. Sixteen word lines, e.g., WL0 to WL15, extend between the source select gates and the drain select gates. In some cases, dummy word lines, which do not contain user data, can also be used in the memory array adjacent to the select gate transistors. Such dummy word lines can protect edge data word lines from certain edge effects.

[0076] One type of non-volatile memory that can be provided in a memory array is floating gate memory. See Figure 3A and 3B Other types of non-volatile memory can also be used. For example, charge trapping memory cells use a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner. See Figure 4A and 4BA three-layer dielectric, composed of silicon oxide, silicon nitride, and silicon oxide (“ONO”), is sandwiched between the conductive control gate and the surface of a semiconductor substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where the electrons are trapped and stored in a finite region. This stored charge then detectably alters the threshold voltage of a portion of the cell channel. The cell is erased by injecting a hot hole into the nitride. Similar cells can be configured in a split-gate configuration, where a doped polysilicon gate extends over a portion of the memory cell channel to form a separate selection transistor.

[0077] In another approach, NROM cells are used. For example, two bits are stored in each NROM cell, where an ONO dielectric layer extends across the channel between the source and drain. The charge of one data bit is located in the dielectric layer adjacent to the drain, and the charge of the other data bit is located in the dielectric layer adjacent to the source. Multi-state data storage is obtained by separately reading the binary states of the spatially separated charge storage regions within the dielectric. Other types of non-volatile memories are also known.

[0078] Figure 3A A cross-sectional view of an example floating-gate memory cell in a NAND string is depicted. Bit lines or NAND string directions enter the page, and word lines direction is from left to right. As an example, word line 324 extends across a NAND string containing corresponding channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and a channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and a channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and a channel region 326. Each memory cell is located in a different corresponding NAND string. A polysilicon inter-dielectric (IPD) layer 328 is also depicted. The control gate is a portion of the word line. Figure 3B The image provides a cross-sectional view along line 329.

[0079] The control gate surrounds the floating gate, thereby increasing the surface contact area between the control gate and the floating gate. This results in a higher IPD capacitance, leading to a higher coupling ratio that makes programming and erasing easier. However, as NAND memory devices scale down, the spacing between adjacent cells becomes smaller, so there is almost no space between two adjacent floating gates for the control gate and IPD. As an alternative, such as Figure 4A and 4BAs shown, planar or flat memory cells have been developed where the control gate is flat or planar; that is, the control gate does not surround the floating gate and its only contact with the charge storage layer is above it. In this case, there is no advantage in having a high floating gate. In fact, it makes the floating gate thinner. Furthermore, the floating gate can be used to store charge, or a thin charge trapping layer can be used to trap charge. This approach avoids the problems of ballistic electron transport, where electrons can travel through the floating gate after tunneling through the tunnel oxide during programming.

[0080] Figure 3B Depicting along line 329 Figure 3A A cross-sectional view of the structure. The NAND string 330 includes SGS transistor 331, example memory cells 300, 333...334 and 335, and SGD transistor 336. As an example of each memory cell, memory cell 300 includes a control gate 302, an IPD layer 328, a floating gate 304, and a tunnel oxide layer 305, and... Figure 3A Consistent. The pathways in the IPD layer of SGS and SGD transistors allow the control gate layer to communicate with the floating gate layer. For example, the control gate and floating gate layer can be polysilicon and the tunnel oxide layer can be silicon oxide. The IPD layer can be, for example, a stack of nitride (N) and oxide (O) in a NONON configuration.

[0081] NAND strings can be formed on a substrate including a p-type substrate region 355, an n-type well 356, and a p-type well 357. n-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type wells. A channel voltage Vch can be directly applied to the channel region of the substrate.

[0082] Figure 4A A cross-sectional view depicting an example charge-trapping memory cell in a NAND string is shown. Viewed in the word line direction of a memory cell that is a 2D example of a memory cell in the memory cell array 126 of FIG1, the memory cell includes a flat control gate and a charge-trapping region. Charge-trapping memory can be used in NOR and NAND flash memory devices. This technology uses an insulator, such as a SiN film, to store electrons, compared to floating-gate MOSFET technology which uses conductors such as doped polysilicon to store electrons. As an example, a word line (WL) 424 extends across a NAND string containing corresponding channel regions 406, 416, and 426. A portion of the word line provides control gates 402, 412, and 422. Below the word line are an IPD layer 428, charge-trapping layers 404, 414, and 421, polysilicon layers 405, 415, and 425, and tunneling layers 409, 407, and 408. Each charge-trapping layer extends continuously in the corresponding NAND string.

[0083] Memory cell 400 includes control gate 402, charge trapping layer 404, polysilicon layer 405, and a portion of channel region 406. Memory cell 410 includes control gate 412, charge trapping layer 414, polysilicon layer 415, and a portion of channel region 416. Memory cell 420 includes control gate 422, charge trapping layer 421, polysilicon layer 425, and a portion of channel region 426.

[0084] A flat control gate is used here instead of a control gate that surrounds a floating gate. One advantage is that the charge trapping layer can be made thinner than a floating gate. In addition, memory cells can be placed closer together.

[0085] Figure 4B A cross-sectional view of the structure along line 429 is depicted. The view shows a NAND string 430 with flat control gates and charge trapping layers. NAND string 430 includes SGS transistor 431, example memory cells 400, 433...434, and 435, and SGD transistor 435. Figure 4A

[0086] A NAND string can be formed on a substrate that includes a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in p-type well 457. Channel voltage Vch can be applied directly to the channel region of the substrate. Memory cell 400 includes control gate 402 and IPD layer 428 over charge trapping layer 404, polysilicon layer 405, tunneling layer 409, and channel region 406.

[0087] For example, the control gate layer can be polysilicon and the tunneling layer can be silicon oxide. The IPD layer can be a stack of high-k dielectrics (such as AlOx or HfOx) that help to increase the coupling ratio between the control gate layer and the charge trapping or charge storage layer. For example, the charge trapping layer can be a mixture of silicon nitride and oxide.

[0088] SGD and SGS transistors have the same configuration as the memory cells, but with longer channel lengths to ensure that the current is turned off in the inhibited NAND string.

[0089] In this example, layers 404, 405, and 409 extend continuously in the NAND string. In another approach, portions of layers 404, 405, and 409 between control gates 402, 412, and 422 can be removed, exposing the top surface of channel 406.

[0090] Figure 5A ​An example block diagram of the sense block SB1 of FIG. 1 is depicted. In one approach, the sense block includes multiple sense circuits. Each sense circuit is associated with a data latch. For example, example sense circuits 550a, 551a, 552a, and 553a are associated with data latches 550b, 551b, 552b, and 553b, respectively. In one approach, different respective sense blocks can be used to sense different subsets of bit lines. This allows the processing load associated with the sense circuits to be divided and handled by respective processors in each sense block. For example, a sense circuit controller 560 in SB1 can communicate with a set of sense circuits and latches. The sense circuit controller can include a pre-charge circuit 561 that provides a voltage to each sense circuit to set a pre-charge voltage. In one possible approach, the voltage is provided to each sense circuit independently, e.g., via a database 503 and a local bus (e.g., LBUS1 or LBUS2) in Figure 5B In another possible approach, a common voltage is provided to each sense circuit at the same time, e.g., via a line 505 in Figure 5B The sense circuit controller can also include a memory 562 and a processor 563. As also mentioned in connection with Figure 2 The memory 562 can store code that can be executed by the processor to perform the functions described herein. These functions can include reading the latches associated with the sense circuits, setting the bit values in the latches, and providing a voltage for setting the pre-charge level in the sense nodes of the sense circuits. Further example details of the sense circuit controller and the sense circuits 550a and 551a are provided below.

[0091] Figure 5B Another example block diagram of the sense block SB1 of FIG. 1 is depicted. The sense circuit controller 560 communicates with multiple sense circuits, including also shown in Figure 5AThe sensing circuit 550a includes a latch 550b, which includes a trip latch 526, an offset verify latch 527, and a data state latch 528. The sensing circuit further includes a voltage clamp 521, such as a transistor, which sets a pre-charge voltage at a sense node 522. A sense node to bit line (BL) switch 523 selectively allows the sense node to communicate with a bit line 525, such as the sense node being electrically connected to the bit line to allow the sense node voltage to decay. The bit line 525 is connected to one or more memory cells, such as memory cell MC1. A voltage clamp 524 can set the voltage on the bit line, such as during a sense operation or during a program voltage. In some cases, a local bus LBUS1 allows the sensing circuit controller to communicate with components in the sensing circuit, such as the latch 550b and voltage clamps. To communicate with the sensing circuit 550a, the sensing circuit controller provides a voltage to a transistor 504 via line 502 to connect LBUS1 with a data bus DBUS 503. The communication can include sending data to and / or receiving data from the sensing circuit.

[0092] For example, the sensing circuit controller can communicate with different sensing circuits in a time-multiplexed manner. In one approach, line 505 can be connected to a voltage clamp in each sensing circuit.

[0093] The sensing circuit 551a includes a latch 551b, which includes a trip latch 546, an offset verify latch 547, and a data state latch 548. A voltage clamp 541 can be used to set a pre-charge voltage at a sense node 542. A sense node to bit line (BL) switch 543 selectively allows the sense node to communicate with a bit line 545, and a voltage clamp 544 can set the voltage on the bit line. The bit line 545 is connected to one or more memory cells, such as memory cell MC2. In some cases, a local bus LBUS2 allows the sensing circuit controller to communicate with components in the sensing circuit, such as the latch 551b and voltage clamps. To communicate with the sensing circuit 551a, the sensing circuit controller provides a voltage to a transistor 506 via line 501 to connect LBUS2 with DBUS.

[0094] The sensing circuit 550a can be a first sensing circuit that includes a first trip latch 526, and the sensing circuit 551a can be a second sensing circuit that includes a second trip latch 546.

[0095] Sensing circuit 550a is an example of a first sensing circuit including a first sense node 522, where the first sensing circuit is associated with a first memory cell MC1 and a first bit line 525. Sensing circuit 551a is an example of a second sensing circuit including a second sense node 542, where the second sensing circuit is associated with a second memory cell MC2 and a second bit line 545.

[0096] Figure 6A A perspective view of a set of blocks 600 in an example three-dimensional configuration of the memory array 126 of FIG. 1. The substrate has example blocks BLKO, BLKI, BLK2, and BLK3 of memory cells (storage elements) and a peripheral region 604 with circuitry for use by the blocks. For example, the circuitry can include voltage drivers 605 that can be connected to control gate layers of the blocks. In one approach, the control gate layers at a common height in a block are commonly driven. The substrate 601 can also carry circuitry below the blocks and one or more lower metal layers patterned along conductive paths to carry signals of the circuitry. The blocks are formed in an intermediate region 602 of the memory device. In an upper region 603 of the memory device, one or more upper metal layers are patterned along conductive paths to carry signals of the circuitry. Each block includes a stacked region of memory cells, with alternating levels of the stack representing word lines. In one possible approach, each block has opposite delaminated sides from which vertical contacts extend upward to the upper metal layers to form connections with the conductive paths. Although four blocks are depicted as examples, two or more blocks extending in the x and / or y directions can be used.

[0097] In one possible approach, the length of the plane in the x direction represents the direction in which the signal path to a word line extends in the one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y direction represents the direction in which the signal path to a bit line extends in the one or more upper metal layers (bit line direction). The z direction represents the height of the memory device.

[0098] Figure 6B An example cross-sectional view of a portion of one of the blocks of Figure 6A The block includes a stack 610 of alternating conductive and dielectric layers. In this example, the conductive layers include two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1 in addition to data word line layers (word lines) WLL0 through WLL10. The dielectric layers are labeled DL0 through DL19. In addition, a region of the stack including NAND strings NS1 and NS2 is depicted. Each NAND string encompasses a memory hole 618 or 619 filled with material forming memory cells adjacent to a word line. In this example, the memory holes are filled with charge trapping material 620. Figure 6D The region of the stack 622 is shown in more detail in

[0099] The stack includes a substrate 611, an insulating film 612 on the substrate, and a portion of a source line SL. NS1 has a source terminal 613 at the bottom 614 of the stack and a drain terminal 615 at the top 616 of the stack. Metal-filled slots 617 and 620 may be periodically provided across the stack as interconnects extending through the stack to connect the source line to a line above the stack. The slots may be used during word line formation and subsequently filled with metal. A portion of a bit line BL0 is also depicted. A conductive via 621 connects the drain terminal 615 to BL0.

[0100] Figure 6C Depicting Figure 6B A plot of the diameter of the memory holes in the stack. The vertical axis is perpendicular to... Figure 6B The stack is aligned and the width (wMH) of memory holes 618 and 619 is depicted, for example, the diameter. Figure 6A Word line layers WLL0 to WLL10 are repeated as examples and are located at corresponding heights z0 to z10 in the stack. In this memory device, the memory vias etched through the stack have extremely high aspect ratios. For example, a depth-to-diameter ratio of approximately 25 to 30 is common. The memory vias may have a circular cross-section. Due to the etching process, the width of the memory vias can vary along the length of the via. Typically, the diameter gradually decreases from the top to the bottom of the memory via. That is, the memory via is tapered and narrows at the bottom of the stack. In some cases, a slight narrowing occurs at the top of the via near the select gate, making the diameter slightly wider before gradually decreasing from the top to the bottom of the memory via.

[0101] Due to the non-uniformity of memory via width, the programming speed, which includes the programming slope and erase speed of the memory cell, can vary based on the memory cell's position along the memory via (e.g., based on the height of the memory cell in the stack). Using smaller diameter memory vias results in a relatively stronger electric field across the tunnel oxide, leading to relatively higher programming and erase speeds. One approach is to define a group of adjacent word lines with similar memory via diameters (e.g., within a defined diameter range) and apply an optimized verification scheme to each word line within a group. Different groups can have different optimized verification schemes.

[0102] Figure 6D Depicting Figure 6BA close-up view of a stack of regions 622. Memory cells are formed at different levels of the stack at the intersection of a word line layer and a memory hole. In this example, SGD transistors 680 and 681 are disposed over dummy memory cells 682 and 683 and data memory cells MC. Multiple layers can be deposited along the sidewalls (SW) of the memory holes 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., a pillar formed of material within a memory hole) can include a charge trapping layer or film 663 (e.g., SiN or other nitride), a tunneling layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word line layer can include a blocking oxide / block high-k material 660, a metal barrier 661, and a conductive metal 662 (e.g., tungsten) as a control gate. For example, control gates 690, 691, 692, 693, and 694 are disposed. In this example, all layers except the metal are disposed in the memory hole. In other approaches, some of the layers can be in the control gate layer. Additional columns are similarly formed in different memory holes. The columns can form columnar active areas (AA) of a NAND string.

[0103] When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge trapping layer and through the tunneling layer. The Vth of the memory cell increases in proportion to the amount of charge stored. During an erase operation, the electrons return to the channel.

[0104] Each of the memory holes can be filled with a plurality of annular layers, including a blocking oxide layer, a charge trapping layer, a tunneling layer, and a channel layer. A core region of each of the memory holes is filled with a body material, and the plurality of annular layers is between the core region and the word lines in each of the memory holes.

[0105] A NAND string can be considered to have a floating body channel, as the length of the channel is not formed on a substrate. Further, the NAND string is provided by a plurality of word line layers in the stack that are above one another, and separated from one another by dielectric layers.

[0106] Figure 7A Depiction Figure 6B A top view of an example word line layer WLL0 of a stack. As mentioned, a 3D memory device can include a stack of alternating conductive and dielectric layers. The conductive layers provide control gates for SG transistors and memory cells. Layers for SG transistors are SG layers and layers for memory cells are word line layers. Further, memory holes are formed in the stack and filled with charge trapping material and channel material. Thus, vertical NAND strings are formed. Source lines are connected to the NAND strings below the stack, and bit lines are connected to the NAND strings above the stack.

[0107] A block BLK in a 3D memory device can be divided into sub-blocks, where each sub-block includes a set of NAND strings with a common SGD control line. For example, see SGD lines / control gates SGD0, SGD1, SGD2, and SGD3 in sub-blocks SBa, SBb, SBc, and SBd, respectively. Sub-blocks SBa, SBb, SBc, and SBd can also be referred to herein as strings of memory cells of a word line. As described, a string of memory cells of a word line can include multiple memory cells that are part of the same sub-block and also disposed in the same word line layer and / or configured to have their control gates biased by and / or with the same word line voltage.

[0108] Further, a word line layer in a block can be divided into zones. Each zone in a respective sub-block can extend between slits that are periodically formed in the stack to process the word line layer during a manufacturing process of the memory device. This processing can include replacing a sacrificial material of the word line layer with metal. Generally, the distance between slits should be relatively small to account for limitations on the distance that an etchant can travel laterally to remove the sacrificial material and that metal can travel to fill the voids that result from the removal of the sacrificial material. For example, the distance between slits can allow for a few rows of memory holes between adjacent slits. The layout of memory holes and slits should also account for limitations on the number of bit lines that can extend across a zone when each bit line is connected to a different memory cell. After processing the word line layer, the slits can optionally be filled with metal to provide interconnects through the stack.

[0109] This figure and other figures are not necessarily drawn to scale. In fact, the zones can be much longer in the x-direction relative to the y-direction to accommodate additional memory holes.

[0110] In this example, there are four rows of memory holes between adjacent slits. Here, a group of memory holes are aligned in the x-direction. Further, the rows of memory holes are in a staggered pattern to increase the density of memory holes. The word line layer or word line is divided into zones WLL0a, WLL0b, WLL0c, and WLL0d that are each connected by a connector 713. In one approach, the last zone of the word line layer in a block can be connected to the first zone of the word line layer in the next block. The connectors are in turn connected to a voltage driver of the word line layer. Zone WLL0a has example memory holes 710 and 711 along line 712. Zone WLL0b has example memory holes 714 and 715. Zone WLL0c has example memory holes 716 and 717. Zone WLL0d has example memory holes 718 and 719. Memory holes are also shown in Figure 7B Each memory hole can be part of a respective NAND string. For example, memory holes 710, 714, 716, and 718 can be part of NAND strings NS0 SBa, NS0 SBb, NS0 SBc, and NS0 SBd, respectively.

[0111] Each circle represents a cross-section of a memory hole at a word line layer or an SG layer. The example circles shown with dashed lines represent memory cells provided by the material in the memory hole and by the adjacent word line layer. For example, memory cells 720 and 721 are in WLL0 a, memory cells 724 and 725 are in WLL0 b, memory cells 726 and 727 are in WLL0 c, and memory cells 728 and 729 are in WLL0 d. These memory cells are at a common height in the stack.

[0112] Metal-filled slits 701, 702, 703, and 704 (e.g., metal interconnects) can be located between and adjacent to the edges of regions WLL0 a through WLL0 d. The metal-filled slits provide a conductive path from the bottom of the stack to the top of the stack. For example, a source line at the bottom of the stack can be connected to a conductive line above the stack, where the conductive line is connected to a voltage driver in a peripheral region of the memory device. For Figure 7A See also Figure 8A .

[0113] Figure 7B A top view of an example top dielectric layer DL19 of the stack of Figure 6B is depicted. The dielectric layer is divided into regions DL19a, DL19 b, DL19 c, and DL19 d. Each region can be connected to a respective voltage driver. This allows a group of memory cells in one region of a word line layer to be programmed simultaneously, where each memory cell is in a respective NAND string connected to a respective bit line. A voltage can be set on each bit line to allow or inhibit programming during each program voltage.

[0114] Region DL19a has example memory holes 710 and 711 along a line 712a that coincides with bit line BL0. Multiple bit lines extend over the memory holes and are connected to the memory holes as indicated by the "X" symbols. BL0 is connected to a group of memory holes including memory holes 711, 715, 717, and 719. Another example bit line BL1 is connected to a group of memory holes including memory holes 710, 714, 716, and 718. Also depicted are metal-filled slits 701, 702, 703, and 704 from Figure 7A of the stack. Bit lines can be numbered in a sequence BL0 through BL23 across the DL19 layer in the -x direction.

[0115] Different subsets of bit lines are connected to cells in different rows. For example, BL0, BL4, BL8, BL12, BL16, and BL20 are connected to cells in the first row of cells at the right edge of each region. BL2, BL6, BL10, BL14, BL18, and BL22 are connected to cells in the adjacent row of cells (next to the first row at the right edge). BL3, BL7, BL11, BL15, BL19, and BL23 are connected to cells in the first row of cells at the left edge of each region. BL1, BL5, BL9, BL13, BL17, and BL21 are connected to cells in the adjacent row of cells (next to the first row at the left edge).

[0116] Figure 8A depicted Figure 7A example NAND strings in sub-blocks SBa to SBd. The sub-blocks are consistent with the structure of Figure 6B The conductive layers in the stack are depicted at the left for reference. Each sub-block includes a plurality of NAND strings, one of which is depicted. For example, SBa includes example NAND string NS0 SBa, SBb includes example NAND string NS0 SBb, SBc includes example NAND string NS0 SBc, and SBd includes example NAND string NS0 SBd.

[0117] In addition, NS0 SBa includes SGS transistors 800 and 801, dummy memory cells 802 and 803, data memory cells 804, 805, 806, 807, 808, 809, 810, 811, 812, 813, and 814, dummy memory cells 815 and 816, and SGD transistors 817 and 818.

[0118] NS0 SBb includes SGS transistors 820 and 821, dummy memory cells 822 and 823, data memory cells 824, 825, 826, 827, 828, 829, 830, 831, 832, 833, and 834, dummy memory cells 835 and 836, and SGD transistors 837 and 838.

[0119] NS0 SBc includes SGS transistors 840 and 841, dummy memory cells 842 and 843, data memory cells 844, 845, 846, 847, 848, 849, 850, 851, 852, 853, and 854, dummy memory cells 855 and 856, and SGD transistors 857 and 858.

[0120] NS0_SBd includes SGS transistors 860 and 861, dummy memory cells 862 and 863, data memory cells 864, 865, 866, 867, 868, 869, 870, 871, 872, 873, and 874, dummy memory cells 875 and 876, and SGD transistors 877 and 878.

[0121] At a given height in the block, a set of memory cells in each sub-block is at a common height. For example, a set of memory cells, including memory cell 804, is among a plurality of memory cells formed along a tapered memory hole in a stack of alternating conductive and dielectric layers. The set of memory cells is at a particular height, z0, in the stack. Another set of memory cells, including memory cell 824, connected to one word line (WLL0) is also at the particular height. In another approach, the set of memory cells, e.g., including memory cell 812, connected to another word line, e.g., WLL8, is at another height (z8) in the stack.

[0122] Figure 8B Another example view of NAND strings in a sub-block is depicted. In this example, the NAND strings include NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd, which have 48 word lines, WL0 to WL47. Each sub-block includes a set of NAND strings that extend in the x-direction and have a common SGD line, e.g., SGD0, SGD1, SGD2, or SGD3. In this simplified example, there is only one SGD transistor and one SGS transistor in each NAND string. The NAND strings NS0_SBa, NS0_SBb, NS0_SBc, and NS0_SBd are in sub-blocks SBa, SBb, SBc, and SBd, respectively. In addition, an example group of word lines G0, G1, and G2 are depicted.

[0123] Figure 8C A schematic diagram of interleaved string architecture 101, 103, 105 (e.g., NAND) of three versions of BiCS memory is generally shown. With reference to string architecture 101, strings are shown in rows 107-0 to 107-7 in architecture 101. Each row is shown as having four ends to strings. The strings can be connected to adjacent strings at the ends (not visible under this view). A first group of rows 107-0 to 107-3 is shown on the left side of dummy row 108. A second group of rows 107-4 to 107-7 is shown on the right side of dummy row 108. Dummy row 108 separates the two groups of rows in the interleaved eight rows. Source line 109 is positioned at the edge of the first group and away from dummy row 108. Source line 110 is positioned at the edge of the second group and away from dummy row 108 and source line 109.

[0124] The interleaved string architecture 103, 105 of BiCS memory is similar to the interleaved string architecture 101, but with additional groups added. Architecture 103 is twice the size of architecture 101 and includes sixteen strings of rows, with each group of four rows separated by dummy rows. Architecture 105 is larger than both architecture 101 and architecture 103. Architecture 105 includes twenty strings of rows, with each group of four rows separated by dummy rows 108.

[0125] These architectures 101, 103, 105 can include a chip under array structure, for example, with control circuitry under a memory array that can include groups of memory strings. With a chip under array structure, the strings can include direct stripe contacts for source lines for read and erase operations.

[0126] Erasing can be performed on an entire memory array, individual blocks or another cell of units. In one implementation, a group of memory cells is erased by raising the p-well of the memory cells to an erase voltage for a sufficient period of time. The erase pulse moves the threshold voltage of the memory cells toward (or beyond) an erase target level, which can be below 0 volts. In some implementations, after the erase pulse is applied, an erase verify operation is performed to determine whether the threshold voltage of the memory cells has reached at least the erase target level. The erase pulse and erase verify are repeated in each cycle using a higher amplitude erase pulse until the erase verify passes.

[0127] Generally, the erase operation can be completed in multiple cycles (e.g., two cycles). For example, an erase voltage (VERA) can be used in a first cycle and the erase voltage can be increased by a boost voltage (dVERA) and used in a second cycle. The number of cycles implemented in the erase operation can be limited by the time of the erase operation (tERASE). If the number of cycles used in the erase operation is increased, the time to perform the erase operation will increase. A two-pulse erase operation can meet the time of the erase operation tERASE. However, over time, especially at end of product life, it can become more difficult to erase some memory devices. In some examples, if the second pulse does not pass the erase verify, three cycles can be needed.

[0128] To address the above concerns, embodiments described herein relate to implementation of a smart erase scheme. For example, a smart erase scheme can include performing an erase verify voltage (VCG ERV) scan with bit ignore after a first erase pulse to find an erase upper tail, and determining a second erase pulse based on the erase tail, erase slope, and erase verify level. Some of the benefits provided by embodiments described herein include ensuring that an erase operation will be completed within two erase cycles to comply with tERASE, allowing for three cycles in the event the second pulse fails erase verify, and preferably controlling erase depth rather than being limited to quantized boost voltages (e.g., dVERA).

[0129] To explore the following in further detail, we will now describe Figure 12 . Figure 12 A method 1200 of erasing a non-volatile storage device in accordance with embodiments described herein is depicted. In some embodiments, method 1200 can be implemented by a controller, control circuit, processor, etc., as described elsewhere herein. As shown in Figure 12 method 1200 begins at step 1202. In step 1202, a first erase voltage pulse is applied to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of an erase operation. For example, with reference to Figure 1A and 1B , control circuit 110 can apply a first erase voltage pulse (VERA) to a set of non-volatile storage elements (e.g., storage device 126a). In some embodiments, control circuit 110 can cooperate with read / write circuit 128 to perform memory operations on memory structure 126. Additionally, in some embodiments, this step can be accomplished by raising the p-well to an erase voltage for a sufficient period of time and grounding the word lines of the selected block while the source lines and bit lines are floating.

[0130] In step 1204, an upper tail of a threshold voltage distribution of the set of non-volatile storage elements is determined after applying the first erase voltage pulse. For example, with continued reference to Figure 1A and 1B, the control circuit 110 can determine an upper tail of a threshold voltage distribution of a set of non-volatile storage elements (e.g., storage devices 126a). More specifically, the control circuit 110 can determine a reference point on the threshold distribution after the first erase pulse in step 1202. The reference point as referred to herein is the "upper tail Vth" because the reference point is generally on the upper end of the Vth distribution. In some embodiments, an erase verify voltage sweep can be used to determine the reference point on the threshold distribution. To help further illustrate, the erase verify level sweep can include first applying a voltage (e.g., 2V) to the word lines (e.g., even word lines, odd word lines, or both even and odd word lines) and one or more NAND strings (e.g., one, two, three, or five NAND strings), and performing a bit-scan operation where a count is determined based on the number of memory cells or NAND strings that store a logical value of "0." If the number of memory cells that store the data state of "0" is less than a threshold amount (e.g., a bit-scan pass fail criterion (e.g., BSPF_EV)), the erase verify voltage (VCG_ERV) is decreased (e.g., 0.5V) and applied to the word lines. The BSPF criterion involves allowing a certain number of failed bits in the operation. This process is repeated until the number of memory cells that store the data state of "0" is greater than or equal to the threshold amount, e.g., the BSPF criterion. To help further illustrate, the following voltage sequence can be applied until the count is greater than or equal to the BSPF criterion: 2V, 1.5V, 1V, 0.5V, 0V, etc. Once the count is equal to or greater than the threshold amount, the applied voltage can serve as the reference point on the threshold distribution and can be used in the calculations described in step 1206.

[0131] In step 1206, a second erase voltage pulse is determined based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements. For example, continuing with the example from Figure 1A and 1B , the control circuit 110 can determine a second erase voltage pulse based on the upper tail of the threshold voltage distribution determined in step 1204. For example, in some embodiments, the second erase voltage pulse can be determined based on the following equation:

[0132]

[0133] In the above equation, the upper tail Vth is determined in step 1204, and the erase slope can be trimmed at the die classification to compensate for die-to-die variations. The erase slope can be fine-tuned for each memory device. The value of the erase slope (e.g., a value between 0.92V and 1.06V) can be programmed into the particular memory device (e.g., a programmable ROM).

[0134] In step 1208, in a second erase cycle of the plurality of erase cycles, a second erase voltage pulse is applied to the set of non-volatile storage elements. For example, continuing with reference to Figure 1A and 1B , the control circuitry 110 can apply a second erase voltage pulse to the set of non-volatile storage elements (e.g., storage 126a). In some embodiments, the control circuitry 110 can cooperate with the read / write circuits 128 to perform memory operations on the memory structure 126. Additionally, in some embodiments, this step can be accomplished by raising the p-well to an erase voltage for a sufficient period of time and grounding the word lines of the selected block while the source lines and bit lines are floating.

[0135] Figure 13A Examples of erase threshold distributions following implementation of the smart erase scheme described above with reference to Figure 12 are provided. In Figure 13A , an erase threshold distribution 1302 is depicted following application of a first erase voltage pulse to the set of non-volatile storage elements (as described in step 1202 of Figure 12 ). Further, in Figure 13A , at 1304, a decrease in an erase verify voltage (VCG ERV) used to determine an upper tail of the threshold voltage distribution of the set of non-volatile storage elements (as described in step 1204 of Figure 12 ) is depicted. Also, in Figure 13A , an erase threshold distribution 1308 is depicted following application of a second erase voltage pulse to the set of non-volatile storage elements (as described in step 1208 of Figure 12 ). The second erase voltage pulse is determined based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements.

[0136] Further, in Figure 13A , 1306 represents an erase verify voltage. In some embodiments, an erase verify operation can be performed to determine whether the threshold voltage of a non-volatile storage element of the set of non-volatile storage elements has reached at least an erase target level. For example, continuing with reference to Figure 1A and 1B, the control circuit 110 can perform an erase verify operation by reading the data of the memory cells based on an erase verify voltage. To help further illustrate, when the read data has a first logic level, e.g., "1", the data of the memory cell can be determined to be a fail bit; when the read data has a second logic level, e.g., "0", the data of the memory cell can be determined to be a pass bit. A fail bit counter included in the memory device 100 can count the fail bits. The verify voltage can be set such that based on the amount of degradation, the number of fail bits is equal to or less than the number of error checking and correction (ECC) bits according to the erase cycles and distribution of the memory cells calculated experimentally during the manufacturing process.

[0137] Figure 13B A close-up view of the upper tail of the threshold voltage distribution of a set of non-volatile storage elements is provided. Specifically, Figure 13B An erase upper tail after a first erase pulse is depicted. Further, Figure 13B A visual depiction of an example of the calculation of the second erase voltage pulse and the relationship between the first erase pulse and the second erase pulse in step 1206 of Figure 12 is provided.

[0138] To help explore this in further detail, a method 1400 of implementing a smart erase scheme according to embodiments described herein will now be described. Figure 14 . Figure 14 A method 1400 of implementing a smart erase scheme according to embodiments described herein is depicted. In some embodiments, the method 1400 can be implemented by a controller, control circuit, processor, etc., as described elsewhere herein. As shown in Figure 14 , the method 1400 begins at step 1402. In step 1402, an erase operation can begin on a non-volatile storage device.

[0139] In Figure 14 , at step 1404, a first erase voltage pulse is applied to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation. As described, with continued reference to Figure 1A and 1B , the control circuit 110 can apply a first erase voltage pulse (VERA) to a set of non-volatile storage elements (e.g., storage device 126a).

[0140] In step 1406, an erase verify voltage (VCG ERV) scan is performed after the application of the first erase voltage pulse. For example, with continued reference to Figure 1A and 1B, the control circuit 110 can perform an erase verify voltage sweep. More specifically, the control circuit 110 can determine a reference point on the threshold distribution after the first erase pulse in step 1402. In some embodiments, an erase verify voltage sweep can be used to determine the reference point on the threshold distribution. For example, an erase verify level sweep can include first applying a voltage (e.g., 2V) to the word lines (e.g., even word lines, odd word lines, or both even and odd word lines) and one or more NAND strings (e.g., one, two, three, or five NAND strings), and performing a bit-scan operation in which a count is determined based on the number of memory cells or NAND strings storing a logical value of "0." A sequence of voltages can be applied until the count is greater than or equal to a BSPF criterion: 2V, 1.5V, 1V, 0.5V, 0V, etc.

[0141] In step 1408, a determination is made as to whether the number of non-volatile storage elements in the set of non-volatile storage elements storing a logical value is greater than or equal to a threshold amount. For example, continuing with reference to Figure 1A and 1B , the control circuit 110 can determine whether the number of memory cells storing a data state of "0" is greater than or equal to a threshold amount (e.g., a bit-scan pass-fail criterion (e.g., BSPF EV)).

[0142] If not greater than or equal to the threshold amount, in step 1410, the erase verify voltage (VCG ERV) is decreased (e.g., by 0.5V) and applied to the word lines. This process is repeated until the number of memory cells storing a data state of "0" is greater than or equal to the threshold amount.

[0143] In step 1412, once the count is equal to or greater than the threshold amount, the applied erase verify voltage can serve as a reference point on the threshold distribution and can be used in step 1414 to calculate a second pulse erase voltage.

[0144] In step 1414, a second erase voltage pulse is determined based on an upper tail of the threshold voltage distribution of the set of non-volatile storage elements. For example, continuing with reference to Figure 1A and 1B , the control circuit 110 can determine a second erase voltage pulse based on the upper tail of the threshold voltage distribution determined in step 1412.

[0145] In step 1416, the second erase voltage pulse is applied to the set of non-volatile storage elements in a second erase cycle of a plurality of erase cycles. For example, continuing with reference to Figure 1A and 1B, the control circuit 110 can apply a second erase voltage pulse to the set of non-volatile storage elements (e.g., storage 126a). In some embodiments, the erase voltage can have a resolution of 0.2V, and once calculated, the second erase voltage can be rounded up to the nearest, maximum erase voltage.

[0146] In step 1418, an erase verify operation is performed. For example, continuing to refer to Figure 1A Figure 1A and 1B , the control circuit 110 can perform the erase verify operation by reading the data of the memory cells based on the erase verify voltage. In step 1420, if the non-volatile storage elements do not pass the erase verify operation, a third erase voltage pulse is applied to the set of non-volatile storage elements in a third erase cycle of the plurality of erase cycles. In some embodiments, the third erase pulse can increase the quantized boost voltage (e.g., dVERA). In step 1422, if the non-volatile storage elements pass the erase verify operation, the erase operation is completed.

[0147] In some embodiments, various parameters for implementing the intelligent erase scheme described herein can be programmed into a particular memory device (e.g., programmable ROM). For example, a first parameter can enable the intelligent erase scheme to be disabled or enabled, a second parameter can allow for selection of even number of word lines, odd number of word lines, or both even and odd number of word lines for the erase verify voltage scan, and a third parameter can allow for selection of one string, two strings, three strings, or five strings for the erase verify voltage scan. Another parameter can include an erase verify voltage offset for starting the erase verify voltage. For example, for TLC, the erase verify voltage can be 0.8V; thus, the starting erase verify voltage can have options of 3.0V, 2.5V, 2.0V, and 1.5V. As another example, for SLC, the starting erase verify voltage can have options of 3.8V, 3.3V, 2.8V, and 2.3V. Additionally, another parameter can enable selection of a step size (e.g., 0.5V, 0.4V, 0.2V, 0.1V, etc.) for the erase verify voltage scan in the erase tail detection. In some embodiments, the bit ignore for the erase tail detection can be shared with the erase verify (e.g., BSPF_EV_MLC).

[0148] The foregoing detailed description of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the application and its practical application to thereby enable others skilled in the art to best utilize the application in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the application is intended to be defined by the claims appended hereto.

Claims

1. A method of performing an erase operation on a non-volatile storage device, comprising: applying a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of the erase operation; determining an upper tail of a threshold voltage distribution of the set of non-volatile storage elements after applying the first erase voltage pulse; determining a second erase voltage pulse based on the upper tail of the threshold voltage distribution of the set of non-volatile storage elements; and applying the second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles, wherein: determining the upper tail of the threshold voltage distribution of the set of non-volatile storage elements includes: applying a first voltage to one or more word lines of the set of non-volatile storage elements; determining a number of non-volatile storage elements of the set of non-volatile storage elements that store a logical value; and determining a reference point on the threshold voltage distribution based on the number of non-volatile storage elements; and determining the second erase voltage pulse includes: determining the second erase voltage pulse based on the reference point on the threshold voltage distribution.

2. The method of claim 1, wherein determining the second erase voltage pulse further includes determining the second erase voltage pulse based on an erase slope.

3. The method of claim 1, wherein determining the second erase voltage pulse further includes determining the second erase voltage pulse based on an erase verify level.

4. The method of claim 1, further comprising: determining whether the number of non-volatile storage elements of the set of non-volatile storage elements that store the logical value is less than a threshold amount; and based on determining that the number of non-volatile storage elements is less than the threshold amount, applying a second voltage to the one or more word lines of the set of non-volatile storage elements, wherein the second voltage is less than the first voltage.

5. The method of claim 4, further comprising: based on determining that the number of non-volatile storage elements is greater than or equal to the threshold amount, calculating the second erase voltage pulse based on the reference point on the threshold voltage distribution.

6. The method of claim 1, further comprising: performing an erase verify operation to determine whether a threshold voltage of a non-volatile storage element of the set of non-volatile storage elements has reached at least an erase target level; and in the event that the non-volatile storage element fails the erase verify operation, applying a third erase voltage pulse to the set of non-volatile storage elements in a third erase cycle of the plurality of erase cycles.

7. A non-volatile storage device, comprising: a set of non-volatile storage elements; and one or more management circuits in communication with the set of non-volatile storage elements and configured to: apply a first erase voltage pulse to a set of non-volatile storage elements in a first erase cycle of a plurality of erase cycles of an erase operation; ​ ​ ​ The upper tail of the threshold voltage distribution of the set of nonvolatile memory elements is determined after the first erase voltage pulse is applied; The second erase voltage pulse is determined based on the upper tail of the threshold voltage distribution of the set of non-volatile memory elements; and In the second erase cycle of the plurality of erase cycles, the second erase voltage pulse is applied to the set of non-volatile memory elements. The one or more management circuits thereon are further configured to: A first voltage is applied to one or more word lines of the set of non-volatile memory elements; Determine the number of non-volatile memory elements storing logic values ​​in the set of non-volatile memory elements; and The reference point on the threshold voltage distribution is determined based on the number of non-volatile memory elements; and The second erase voltage pulse is determined based on the reference point on the threshold voltage distribution.

8. The non-volatile storage device of claim 7, wherein the one or more management circuits are further configured to determine the second erase voltage pulse based on the erase slope.

9. The non-volatile storage device of claim 7, wherein the one or more management circuits are further configured to determine the second erase voltage pulse based on an erase verification level.

10. The non-volatile storage device of claim 7, wherein the one or more management circuits are further configured to: Determine whether the number of non-volatile memory elements storing the logic value in the set of non-volatile memory elements is less than a threshold amount; and A second voltage is applied to one or more word lines of the group of nonvolatile memory elements based on the determination that the number of nonvolatile memory elements is less than the threshold amount, wherein the second voltage is less than the first voltage.

11. The non-volatile storage device of claim 10, wherein the one or more management circuits are further configured to: The second erase voltage pulse is calculated based on a reference point on the threshold voltage distribution, based on the determination that the number of non-volatile memory elements is greater than or equal to the threshold amount.

12. The non-volatile storage device of claim 7, wherein the one or more management circuits are further configured to: Perform an erase verification operation to determine whether the threshold voltage of the non-volatile memory element in the set of non-volatile memory elements has at least reached the erase target level; and If the non-volatile memory element fails the erase verification operation, a third erase voltage pulse is applied to the group of non-volatile memory elements in the third erase cycle of the plurality of erase cycles.

13. A controller for communicating with a set of non-volatile memory elements of a memory device, the controller being configured to: In the first erase cycle of a plurality of erase cycles in an erase operation, a first erase voltage pulse is applied to the set of non-volatile memory elements; The upper tail of the threshold voltage distribution of the set of nonvolatile memory elements is determined after the first erase voltage pulse is applied; The second erase voltage pulse is determined based on the upper tail of the threshold voltage distribution of the set of non-volatile memory elements; and applying a second erase voltage pulse to the set of non-volatile storage elements in a second erase cycle of the plurality of erase cycles, wherein the controller is further configured to: apply a first voltage to one or more word lines of the set of non-volatile storage elements; determine a number of non-volatile storage elements of the set of non-volatile storage elements that store a logical value; determine a reference point on the threshold voltage distribution based on the number of non-volatile storage elements; and determine the second erase voltage pulse based on the reference point on the threshold voltage distribution.

14. The controller of claim 13, wherein the controller is further configured to determine the second erase voltage pulse based on an erase slope.

15. The controller of claim 13, wherein the controller is further configured to determine the second erase voltage pulse based on an erase verify level.

16. The controller of claim 13, wherein the controller is further configured to: determine whether the number of non-volatile storage elements of the set of non-volatile storage elements that store the logical value is less than a threshold amount; and apply a second voltage to the one or more word lines of the set of non-volatile storage elements based on determining that the number of non-volatile storage elements is less than the threshold amount, wherein the second voltage is less than the first voltage.

17. The controller of claim 16, wherein the controller is further configured to: calculate the second erase voltage pulse based on the reference point on the threshold voltage distribution based on determining that the number of non-volatile storage elements is greater than or equal to the threshold amount.

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