Ultra-thin chip and planarization method and application thereof

Abstract

The present invention relates to an ultra-thin chip and a planarization method and application thereof. The planarization method comprises the following steps: providing a chip, the chip comprising a stacked silicon substrate and a functional layer, the edge of the chip warping in the direction of the functional layer; pre-compressing the chip so that the edge of the chip warps in the direction of the silicon substrate; and forming a thin film with a thickness of less than or equal to 5 μm on the surface of the silicon substrate away from the functional layer to obtain a planarized ultra-thin chip. The planarization method can increase the permanent tensile stress introduced by a film of the same thickness, thereby improving the warping degree of the ultra-thin chip on the basis of increasing a smaller thickness, thereby improving the packaging yield and reliability of the ultra-thin chip.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, in particular to an ultra-thin chip and a planarization method and application thereof. Background Art

[0002] Ultra-thin chips have broad application prospects. When the thickness of ultra-thin chips is less than 50μm, they have good flexibility and can be used in flexible electronics. However, as the thickness of ultra-thin chips decreases, their bending stiffness decreases exponentially. At this time, the residual stress introduced by the damaged layer on the back of the ultra-thin chip and the mismatch strain introduced by the functional layer on the front will cause the ultra-thin chip to warp, which will lead to problems such as low packaging yield and poor reliability.

[0003] The damaged layer on the back of the ultra-thin chip can be removed by chemical mechanical polishing process, but the functional layer on the front is the active area of ​​the ultra-thin chip and cannot be removed. Therefore, the traditional method of flattening ultra-thin chips is to deposit a thin film on the back. However, the permanent tensile stress of the film increases with the thickness of the film. Therefore, it is difficult to improve the warping degree of the ultra-thin chip by increasing the thickness slightly. Summary of the invention

[0004] Based on this, it is necessary to provide an ultra-thin chip and its flattening method and application to address the above-mentioned problems. The flattening method can increase the permanent tensile stress introduced by a film of the same thickness, thereby improving the warping degree of the ultra-thin chip on the basis of increasing the thickness less, thereby improving the packaging yield and reliability of the ultra-thin chip.

[0005] The present invention provides a method for planarizing an ultra-thin chip, comprising the following steps:

[0006] Providing a chip, the chip comprising a stacked silicon substrate and a functional layer, wherein an edge of the chip is warped toward the functional layer;

[0007] Pre-compressing the chip so that the edge of the chip is warped toward the silicon substrate; and

[0008] A thin film with a thickness less than or equal to 5 μm is formed on the surface of the silicon substrate away from the functional layer to obtain a planarized ultra-thin chip.

[0009] In one embodiment, when the edge of the chip is warped toward the functional layer, the warping degree is α, and the value range of α is 10 μm-1000 μm.

[0010] In one implementation, when the edge of the chip is warped toward the silicon substrate, the warping degree is β, and the value range of β is 10 μm-1000 μm.

[0011] In one embodiment, the absolute value of the difference between α and β is less than or equal to 100 μm.

[0012] In one embodiment, the step of pre-compressing the chip includes: forming a protective film on the surface of the functional layer away from the silicon substrate, then fixing the chip with the protective film with a clamp, and applying pressure on the surface of the silicon substrate away from the protective film for pre-compression.

[0013] In one embodiment, the material of the thin film is selected from at least one of metal, SiN, SiO2 or polymer materials.

[0014] In one embodiment, the polymer material is selected from at least one of wafer bonding film, polyimide or polyparaxylene.

[0015] In one embodiment, the thickness of the chip is less than or equal to 50 μm.

[0016] An ultra-thin chip is obtained by flattening the chip by the flattening method as described above.

[0017] A flexible electronic device comprises the ultra-thin chip as described above.

[0018] The method for planarizing an ultra-thin chip provided by the present invention introduces temporary compressive stress into the chip by pre-compressing the chip, so that in the step of forming a thin film on the surface of the silicon substrate away from the functional layer, the permanent tensile stress introduced by the thin film of the same thickness is increased, and the tensile stress of the thin film on the back side of the chip is increased, thereby improving the warping degree of the ultra-thin chip on the basis of increasing a small thickness, and realizing the planarization of the ultra-thin chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of a chip with an edge warped toward a functional layer;

[0020] Figure 2 A schematic diagram of a process for planarizing an ultra-thin chip;

[0021] In the figure, 10, chip; 101, silicon substrate; 102, functional layer; 20, thin film; 30, ultra-thin chip. DETAILED DESCRIPTION

[0022] For ease of understanding of the present invention, the present invention will be described more fully below with reference to relevant embodiments. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0024] The ultra-thin chip 30 and its planarization method and application provided by the present invention will be further described below.

[0025] like Figure 1 and Figure 2 As shown, the planarization method of the ultra-thin chip 30 provided by the present invention comprises the following steps:

[0026] S10, providing a chip 10, wherein the chip 10 includes a stacked silicon substrate 101 and a functional layer 102, and an edge of the chip 10 is warped toward the functional layer 102;

[0027] S20, pre-compressing the chip 10 so that the edge of the chip 10 is warped toward the silicon substrate 101; and

[0028] S30 , forming a thin film 20 with a thickness less than or equal to 5 μm on a surface of the silicon substrate 101 away from the functional layer 102 , to obtain a planarized ultra-thin chip 30 .

[0029] It can be understood that the surface of the silicon substrate 101 away from the functional layer 102 is the back side of the chip 10, and the surface of the functional layer 102 away from the silicon substrate 101 is the front side of the chip 10. In one embodiment, there is a damaged layer on the surface of the silicon substrate 101 away from the functional layer 102, and the functional layer 102 includes a stacked device doping layer, an intermediate metal dielectric layer and a passivation layer, and the silicon substrate 101 is bonded to the device doping layer.

[0030] In chip 10, the damaged layer will introduce residual stress, and the formation process of the device doping layer, the intermediate metal dielectric layer and the passivation layer will introduce mismatch strain, such as: lattice mismatch, defects, growth stress, thermal strain, etc.; residual stress and mismatch strain will cause chip 10 to warp.

[0031] In step S10, the silicon substrate 101 is the convex surface of the chip 10, and the functional layer 102 is the concave surface of the chip 10. It should be noted that the definition of the convex surface is: if a section is made at any point on the surface of the convex surface, the surface is always below the section; the definition of the concave surface is: if a section is made at any point on the surface of the concave surface, the surface is always on the upper side of the section.

[0032] The chip 10 is used as a raw material for the planarization method of the ultra-thin chip 30 , and can be purchased or prepared by oneself. In one embodiment, the chip 10 is thinned by back grinding, and the thickness of the chip 10 is less than or equal to 50 μm.

[0033] In one embodiment, the chip 10 is uniaxially warped, that is, of the two mutually perpendicular edges in the in-plane direction of the chip 10, the curvature of one edge is 0, and the curvature of the other edge is greater than 0. At this time, the bending direction is parallel to one edge of the chip 10, and one edge has almost no warping.

[0034] When the edge of the chip 10 is warped toward the functional layer 102 , the warping degree of the chip 10 is α, and the value range of α is 10 μm-1000 μm, and more preferably 500 μm-900 μm.

[0035] In step S20, temporary compressive stress is introduced into the chip 10 by pre-compressing the chip 10, so that in step S30, the permanent tensile stress introduced by the film 20 of the same thickness is increased, thereby improving the warping degree of the ultra-thin chip 30 on the basis of increasing the thickness less, and achieving the flatness of the ultra-thin chip 30.

[0036] It should be noted that, in the chip 10 of step S20, the functional layer 102 is the convex surface of the chip 10, and the silicon substrate 101 is the concave surface of the chip 10; when the edge of the chip 10 is warped toward the silicon substrate 101, the warping degree of the chip 10 is β, and the value range of β is 10μm-1000μm, and further preferably 500μm-900μm.

[0037] It should be noted that the present invention does not impose any particular limitation on the method of pre-compression of the chip 10. In one embodiment, the step of pre-compressing the chip 10 includes: forming a protective film on the surface of the functional layer 102 away from the silicon substrate 101, and then fixing the chip 10 with the protective film with a clamp, and applying pressure on the surface of the silicon substrate 101 away from the protective film for pre-compression. Optionally, the clamp is selected from a concave clamp, and the protective film is adhered to the surface of the concave clamp to achieve fixation and introduce temporary compressive stress at the same time.

[0038] The value of α may be the same as or different from the value of β. In order to better balance the stress and prevent the chip from warping too much in the opposite direction and breaking, in one embodiment, the absolute value of the difference between α and P is less than or equal to 100 μm. Preferably, the absolute value of the difference between α and β is less than or equal to 70 μm. Further preferably, the absolute value of the difference between α and β is less than or equal to 30 μm.

[0039] In one embodiment, before the step of forming a thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102, the surface of the silicon substrate 101 away from the functional layer 102 is polished to remove the damaged layer of the silicon substrate 101. It can be understood that the thickness of the damaged layer is less than the thickness of the silicon substrate 101 in the ultra-thin chip 30.

[0040] In one embodiment, the material of the film 20 is selected from at least one of metal, SiN, SiO2 or polymer materials, wherein polymer materials have better flexibility than other materials and are more conducive to the application of ultra-thin chips 30 in flexible electronics, and polymer materials can be directly bonded to flexible circuit boards during subsequent mounting of ultra-thin chips 30. Therefore, the material of the film 20 is preferably selected from polymer materials. In one embodiment, the polymer material is selected from at least one of chip bonding film (DAF), polyimide or polyparaxylene.

[0041] When the material of the film 20 is selected from metal, the step of forming the film 20 on the surface of the silicon substrate 101 away from the functional layer 102 includes sequentially forming a first metal film 20 and a second metal film 20 on the surface of the silicon substrate 101 away from the functional layer 102. In one embodiment, the material of the first metal film 20 is titanium having high peeling strength with the silicon substrate 101, and the material of the second metal film 20 is selected from at least one of copper, nickel or silver.

[0042] In order to better reduce the warping of the ultra-thin chip 30, in one embodiment, the thickness of the film 20 is calculated based on the large deformation bridge theory or the film substrate system theory. Specifically, the large deformation bridge theory is used to analyze the geometric equations of the system, and the film substrate system theory introduces the mismatch strain into the geometric equations. Finally, the control equation satisfied when the system warping curvature is zero is given by the minimum energy principle.

[0043] In one embodiment, the thin film 20 is formed on a surface of the silicon substrate 101 away from the functional layer 102 by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0044] In one embodiment, after the step of forming the thin film 20 on the surface of the silicon substrate 101 away from the functional layer 102 , the temporary compressive stress is released to obtain the ultra-thin chip 30 .

[0045] The planarization method of the ultra-thin chip 30 provided by the present invention can increase the permanent tensile stress introduced by the film 20 of the same thickness, thereby improving the warping degree of the ultra-thin chip 30 on the basis of increasing the thickness less, thereby improving the packaging yield and reliability of the ultra-thin chip 30.

[0046] The present invention provides an ultra-thin chip 30 , which is obtained by flattening the chip 10 using the flattening method described above.

[0047] The ultra-thin chip 30 provided by the present invention has good flexibility and flatness, and can be well applied to flexible electronics.

[0048] In one embodiment, the thickness of the ultra-thin chip 30 is less than 50 μm, more preferably 20 μm-50 μm.

[0049] In one embodiment, the warpage of the ultra-thin chip 30 is less than or equal to 100 μm, and more preferably 30 μm-70 μm.

[0050] The present invention also provides a flexible electronic device, comprising the ultra-thin chip 30 as described above.

[0051] In one embodiment, the flexible electronics further include a flexible substrate, and the flexible substrate is used to integrate the ultra-thin chip 30 .

[0052] In one embodiment, the material of the flexible substrate is a flexible material including polydimethylsiloxane, aliphatic-aromatic copolyester, hydrogel or biocompatible dressing, which can be determined according to actual needs and is not limited here.

[0053] The flexible electronics provided by the present invention have excellent flexibility and flatness, and can realize large-scale mass production of products, and can be widely used in many fields such as wearable electronic devices, paper-based displays and health monitoring systems.

[0054] Hereinafter, the ultra-thin chip 30 and the planarization method and application thereof will be further described through the following specific embodiments.

[0055] In the planarization method of the ultra-thin chip 30 provided in Examples 1-8 and Comparative Examples 1-4, the ultra-thin chip 30 includes a silicon substrate 101, and a device doping layer, an intermediate metal dielectric layer and a passivation layer stacked on the surface of the silicon substrate 101, wherein the device doping layer, the intermediate metal dielectric layer and the passivation layer together constitute the functional layer 102 of the chip 10, the surface of the silicon substrate 101 away from the functional layer 102 is the back side of the chip 10, and the surface of the functional layer 102 away from the silicon substrate 101 is the front side of the chip 10.

[0056] Example 1

[0057] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0058] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 800 μm.

[0059] DAF is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation bridge theory, the thickness of DAF is calculated to be 5 μm. After the deposition, the DAF is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 is warped toward the functional layer 102, and the warping degree is 100 μm.

[0060] Example 2

[0061] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0062] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 800 μm.

[0063] SiO2 is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Based on the thin film 20 substrate system theory, the thickness of SiO2 is calculated to be 5μm. After the deposition is completed, the adhesive is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30μm is obtained. The edge of the ultra-thin chip 30 is warped toward the functional layer 102, and the warping degree is 200μm.

[0064] Example 3

[0065] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0066] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 800 μm.

[0067] SiN is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Based on the thin film 20 substrate system theory, the thickness of SiN is calculated to be 5 μm. After the deposition is completed, the SiN is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 is warped toward the functional layer 102, and the warping degree is 150 μm.

[0068] Example 4

[0069] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0070] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 800 μm.

[0071] Copper is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Since copper has poor adhesion to the silicon substrate 101 and is easy to fall off, titanium is deposited before copper is deposited. Based on the large deformation bridge theory, the thickness of titanium is calculated to be 0.5 μm and the thickness of copper is 4.5 μm. After the deposition is completed, the adhesive is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 is warped toward the functional layer 102, and the warping degree is 250 μm.

[0072] Example 5

[0073] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0074] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 1600 μm.

[0075] DAF is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation bridge theory, the thickness of DAF is calculated to be 5 μm. After the deposition, the DAF is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 is warped toward the silicon substrate 101, and the warping degree is 300 μm.

[0076] Example 6

[0077] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0078] The front side of chip 10 is temporarily bonded to a protective film, and then the protective film of chip 10 is attached to a concave fixture to introduce temporary compressive stress, so that the functional layer 102 of chip 10 is the convex surface of chip 10, and the silicon substrate 101 of chip 10 is the concave surface of chip 10, with a warpage of 100 μm.

[0079] DAF is selected to be deposited on the surface of the silicon substrate 101 away from the functional layer 102. Based on the large deformation bridge theory, the thickness of DAF is calculated to be 5 μm. After the deposition, the DAF is debonded by ultraviolet light to release the temporary compressive stress, and an ultra-thin chip 30 with a thickness of 30 μm is obtained. The edge of the ultra-thin chip 30 is warped toward the functional layer 102, and the warping degree is 300 μm.

[0080] Comparative Example 1

[0081] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0082] A 5 μm DAF is deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm. The edge of the ultra-thin chip 30 is warped toward the functional layer 102 with a warpage of 400 μm.

[0083] Comparative Example 2

[0084] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0085] 5 μm Siθ2 is deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm. The edge of the ultra-thin chip 30 is warped toward the functional layer 102 with a warping degree of 500 μm.

[0086] Comparative Example 3

[0087] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0088] 5 μm SiN is deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm. The edge of the ultra-thin chip 30 is warped toward the functional layer 102 with a warping degree of 450 μm.

[0089] Comparative Example 4

[0090] A chip 10 is provided. The thickness of the chip 10 is 25 μm and the warpage is 800 μm. The silicon substrate 101 of the chip 10 is the convex surface of the chip 10 , and the functional layer 102 of the chip 10 is the concave surface of the chip 10 .

[0091] 0.5 μm titanium and 4.5 μm copper are sequentially deposited on the surface of the silicon substrate 101 away from the functional layer 102 to obtain an ultra-thin chip 30 with a thickness of 30 μm. The edge of the ultra-thin chip 30 is warped toward the functional layer 102 with a warpage of 550 μm.

[0092] It should be noted that the terms "first" and "second" involved in the present invention are only used to distinguish similar objects, and do not represent a specific order for the objects. "First" and "second" can be interchanged in a specific order or sequence where permitted. It is understandable that the objects distinguished by "first" and "second" can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein.

[0093] The terms used herein are for the purpose of describing specific embodiments only and are not intended to limit the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the term "comprising" is used in this specification, it refers to the presence of features, steps, operations, elements and / or parts, but does not exclude the presence of one or more other features, steps, operations, elements, parts and / or combinations thereof. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and the description includes the occurrence and non-occurrence of the event.

[0094] The embodiments described in the above exemplary embodiments do not represent all embodiments consistent with the present invention. On the contrary, they are only examples of devices and methods consistent with some aspects of the present invention as detailed in the attached claims. The terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusions, so that a process, method, product or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, product or device. In the absence of more restrictions, it is not excluded that there are other identical or equivalent elements in the process, method, product or device including the elements.

[0095] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for planarizing an ultra-thin chip, characterized in that: The following steps are involved: A chip is provided, the chip comprising a stacked silicon substrate and a functional layer, the edge of the chip is warped toward the functional layer, wherein when the edge of the chip is warped toward the functional layer, the warping degree is α, and the value range of α is 10 μm-1000 μm; Pre-compressing the chip so that the edge of the chip warps toward the silicon substrate, wherein when the edge of the chip warps toward the silicon substrate, the warpage is β, the value range of β is 10 μm-1000 μm, and the absolute value of the difference between α and β is less than or equal to 100 μm; and A thin film with a thickness less than or equal to 5 μm is formed on the surface of the silicon substrate away from the functional layer to obtain a planarized ultra-thin chip.

2. The method for planarizing an ultra-thin chip according to claim 1, characterized in that: The value range of α is 500μm-900μm.

3. The method for planarizing an ultra-thin chip according to claim 2, characterized in that: The value range of β is 500μm-900μm.

4. The method for planarizing an ultra-thin chip according to claim 3, characterized in that: The absolute value of the difference between α and β is less than or equal to 70 μm.

5. The method for planarizing an ultra-thin chip according to claim 3, characterized in that: The step of pre-compressing the chip includes: forming a protective film on the surface of the functional layer away from the silicon substrate, fixing the chip with the protective film with a clamp, and applying pressure on the surface of the silicon substrate away from the protective film for pre-compression.

6. The method for planarizing an ultra-thin chip according to any one of claims 1 to 5, characterized in that: The material of the film is selected from at least one of metal, SiN, SiO2 or polymer material.

7. The method for planarizing an ultra-thin chip according to claim 6, characterized in that: The polymer material is selected from at least one of wafer bonding film, polyimide or polyparaxylene.

8. The method for planarizing an ultra-thin chip according to any one of claims 1 to 5, characterized in that: The thickness of the chip is less than or equal to 50 μm.

9. An ultra-thin chip, characterized in that: The chip is flattened by the flattening method according to any one of claims 1 to 8.

10. A flexible electronic device, characterized in that: Comprising the ultra-thin chip as claimed in claim 9.

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