A shielded gate MOSFET device and manufacturing method

Abstract

A structure and manufacturing method of a shielded gate MOSFET device. The present invention relates to power semiconductor devices and provides a better manufacturing process and structure. The process reduces the number of photolithography steps, simplifies the process, and optimizes the performance of the device produced. The process has a unique structure and manufacturing process flow. Compared with traditional structures and processes, it can save several photolithography steps and effectively reduce manufacturing costs.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, in particular to the structure of a shielded gate trench field effect transistor device and a manufacturing method thereof. Background Art

[0002] The following describes the relevant technical background of existing shielded gate trench field effect transistors. It should be noted that the corresponding position words described in this document, such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical", correspond to the relative positions of the reference diagrams. There is no restriction on fixed directions in the specific implementation. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0003] Shielded-gate trench field-effect transistors, a new type of power device, feature low on-resistance and fast switching speeds. However, existing manufacturing methods for this structure require six to eight photolithography steps. For example, the definition of the shield gate electrode, the isolation dielectric layer region, and the formation of the P-body doped region all require the use of a photomask. This results in a relatively high manufacturing cost. Therefore, a cost-saving manufacturing process with fewer photolithography steps is desirable. Summary of the Invention

[0004] In response to the above-mentioned problems of existing shielded gate trench field effect transistor devices, the present invention proposes a shielded gate trench field effect transistor structure and process flow with simple process and low manufacturing cost.

[0005] A method for manufacturing a shielded gate trench field effect transistor device, the manufacturing method comprising the following steps:

[0006] The first step: providing a first conductive type substrate and forming a first conductive type epitaxial layer thereon;

[0007] Step 2: forming a hard mask and a series of trenches on the upper surface of the first conductive type epitaxial layer, namely, first type trenches, second type trenches and third type trenches, wherein the width of the third type trenches is greater than that of the first type trenches and the second type trenches;

[0008] The first type of trench and the second type of trench are in the same trench section, and the third type of trench is located at the outermost periphery of the device and surrounds the first type of trench and the second type of trench;

[0009] The hard mask contains at least one layer of etch-resistant material with a different etch rate than the oxide;

[0010] Step 3: forming a trench insulating layer and a shielding gate electrode in the trench, and then depositing oxide to completely fill the first and second types of trenches and partially fill the third type of trenches;

[0011] Step 4: forming a filling material to fill the third type trench, wherein the filling material is polysilicon, organic polymer, nitride or metal compound;

[0012] Step 5: removing the oxide and filling material above the hard mask to expose the hard mask, and then forming a photoresist on the upper surface of the second type trench and the third type trench and their periphery;

[0013] Step 6: Etch back the oxide to form an inter-electrode isolation layer in the first type of trench;

[0014] Step 7: Etch the hard mask under the protection of photoresist;

[0015] Step 8: removing the photoresist and the filling material deposited in the third type trench;

[0016] Step 9: forming a gate oxide layer on the upper trench sidewall, and then forming a gate electrode;

[0017] Step 10: Use the hard mask as a mask for ion implantation to perform ion implantation;

[0018] During ion implantation, the mask dielectric layer located at the periphery of the trench confines the second conductivity type doped body region formed after ion implantation to the interior of the series of trenches;

[0019] Step 11: forming an oxide dielectric layer on the upper surface of the semiconductor, and then forming a contact hole in the oxide dielectric layer;

[0020] The first type of contact hole is located directly above the second type of trench and extends into the shield gate electrode in the trench; the second type of contact hole is located directly above the first type of trench or the third type of trench and extends into the gate electrode in the trench; the third type of contact hole is located between the trenches and extends into the semiconductor to contact the second conductivity type doped region and the first conductivity type doped source region;

[0021] Step 12: Form upper surface metal and lower surface metal to form a device.

[0022] Furthermore, the method further includes:

[0023] Step 9: Form a gate electrode and make the depth from the gate electrode to the upper surface of the semiconductor between 0.3 and 2 μm;

[0024] Step 11: After forming the oxide dielectric layer, remove the upper surface oxide dielectric layer and expose the upper surface of the semiconductor; then etch the semiconductor to form a contact hole;

[0025] Step 12: Using photolithography, second-type contact holes are formed on the second-type trenches and the third-type trenches, with a portion of the contact holes being located directly above the second-type trenches and extending into the shielding gate electrodes in the trenches; first-type contact holes are located directly above the first-type trenches or the third-type trenches and extending into the gate electrodes in the trenches;

[0026] Then, the upper and lower surface metals are formed, and finally the device is formed.

[0027] Furthermore, the anti-etching material layer in the first step is semiconductor nitride.

[0028] Furthermore, in the fifth step, the oxide and filler material above the hard mask are removed by a chemical mechanical planarization process, and the hard mask is used as a polishing stop layer.

[0029] Furthermore, in the fourth step, the filling material is polysilicon, organic polymer, nitride or metal compound.

[0030] Furthermore, the third type of grooves also include multiple sections of grooves extending outward, and the extended sections of grooves are perpendicular to the third type of grooves.

[0031] Furthermore, the contact hole penetrates through the oxide dielectric layer into the gate electrode in the extension trench, connecting the gate electrode to the upper surface metal.

[0032] Another object of the present invention is to provide a device manufactured by the manufacturing method of the shielded gate trench field effect transistor device.

[0033] The shielded gate trench field effect transistor device proposed in the present invention has a unique structure and manufacturing process flow. Compared with traditional structures and processes, it can save several photolithography steps and effectively reduce manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 A cross-sectional schematic diagram of the second step of the manufacturing process of an embodiment of the present invention.

[0035] Figure 2 FIG. 1 is a partial top view of a trench structure in the second step of a manufacturing process according to an embodiment of the present invention.

[0036] Figure 3 Schematic cross-sectional view of the third step of the manufacturing process of one embodiment of the present invention.

[0037] Figure 4 Schematic cross-sectional view of the fourth step of the manufacturing process of one embodiment of the present invention.

[0038] Figure 5 Schematic cross-sectional view of the fifth step of the manufacturing process of one embodiment of the present invention.

[0039] Figure 6 Schematic cross-sectional view of the sixth step of the manufacturing process of one embodiment of the present invention.

[0040] Figure 7 Schematic cross-sectional view of the seventh step of the manufacturing process of one embodiment of the present invention.

[0041] Figure 8 Schematic cross-sectional view of the eighth step of the manufacturing process of one embodiment of the present invention.

[0042] Figure 9 Schematic cross-sectional view of the ninth step of the manufacturing process of one embodiment of the present invention.

[0043] Figure 10 Schematic cross-sectional view of the tenth step of the manufacturing process of one embodiment of the present invention.

[0044] Figure 11 FIG. 1 is a cross-sectional schematic diagram of the eleventh step of the manufacturing process according to an embodiment of the present invention.

[0045] Figure 12 FIG. 1 is a cross-sectional schematic diagram of the eleventh step of the manufacturing process according to an embodiment of the present invention.

[0046] Figure 13A FIG. 1 is a partial top view of an embodiment of the present invention. The cross-sectional structure of the tangent line AA' is as follows: Figure 12 .

[0047] Figure 13B for Figure 13A The cross-sectional structure of the tangent line BB' in the top view.

[0048] Figure 13C for Figure 13A The cross-sectional structure of the tangent line CC' in the top diagram.

[0049] Figure 14A for Figure 13C Schematic cross-section of the structure in the sixth step of the manufacturing process.

[0050] Figure 14B for Figure 13C Schematic cross-section of the structure in the eighth step of the manufacturing process.

[0051] Figure 15A FIG. 1 is a cross-sectional schematic diagram of the ninth step of the manufacturing process of another embodiment of the present invention.

[0052] Figure 15B FIG. 1 is a cross-sectional schematic diagram of the tenth step of the manufacturing process of another embodiment of the present invention.

[0053] Figure 15C FIG1 is a cross-sectional schematic diagram of the eleventh step of the manufacturing process of another embodiment of the present invention.

[0054] Figure 15D FIG. 1 is a cross-sectional schematic diagram of the twelfth step of the manufacturing process of another embodiment of the present invention.

[0055] Figure 15E FIG. 1 is a cross-sectional schematic diagram of the thirteenth step of the manufacturing process according to another embodiment of the present invention. DETAILED DESCRIPTION

[0056] The present invention is described in detail below with reference to the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P-type (second conductivity type) and N-type (first conductivity type). A P-type conductive semiconductor region can be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, boron (B), aluminum (Al), gallium (Ga), etc. An N-type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be, but are not limited to, phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H + ) etc. In the following description, the heavily doped P-type conductive semiconductor region is marked as P + Region, heavily doped N-type conductive semiconductor region is marked as N + For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally around 1 × 10 19 cm -3 to 1 × 10 21 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0057] The following describes the manufacturing process steps of the shielded gate trench field effect transistor device of the present invention:

[0058] For the first step, please refer to Figure 1 , providing N + A N-type substrate 200 is provided, and an N-type epitaxial layer 201 is formed thereon. +The substrate 200 may be doped with red phosphorus or arsenic, and the N-type epitaxial layer 201 may be doped with phosphorus, with a thickness between 0.5 and 10 μm. The doping concentration of the N-type epitaxial layer 201 may be constant or may vary with depth. In one embodiment, the N-type epitaxial layer 201 is doped with phosphorus at a doping concentration of 1e18 cm -3 to 1e16 cm -3 In another embodiment, the doping concentration is non-uniformly distributed in the N-type epitaxial layer, including a doping concentration of 5e17 cm-1 at the top. -3 to 1e15 cm -3 The lighter area between them and the doping concentration below is 1e17 cm -3 to 1e18 cm -3 The doping concentration above the N-type epitaxial layer is lower, which is conducive to better control of the depth of the P-type body region when forming the P-type body region in the subsequent steps. The doping concentration below is higher to lower the on-resistance, so the boundary is close to the depth of the P-type body region.

[0059] In the second step, a hard mask 301 and a series of trenches located between the hard mask 301 are formed on the upper surface of the epitaxial layer, namely the first type trench 250, the second type trench 251 and the third type trench 252. Figure 1 and Figure 3 As shown, the first type of groove 250 is used to form a conductive area; the second type of groove 251 is used to connect the shielding gate electrode and the upper surface metal layer; the width of the third type of groove 252 is larger than that of the first and second types of grooves, and is used to ensure the breakdown voltage of the device periphery and to connect the gate electrode and the surface metal.

[0060] Figure 2 Shown is a top view of one possible series of trenches used in the device fabrication process. Figure 1 The cross-sectional structure corresponds to Figure 2 The A-A' tangent position of the device. Please refer to Figure 2 , wherein the first type trench 250 and the second type trench 251 are in the same trench section, and the third type trench 252 is located at the outermost periphery and surrounds the first type trench 250 and the second type trench 251. The third type trench 252 may also include multiple sections of outward extensions, which are perpendicular to the third type trench 252 and serve to connect the gate electrode 205 and the upper surface metal 208. Figure 13A and 13B .

[0061] The hard mask 301 at least includes a layer of an etch-resistant material having an etching rate different from that of oxide, wherein the etch-resistant material layer may be a semiconductor nitride.

[0062] The trench formation method may include, but is not limited to, dry etching. In one embodiment, the trench may be formed by thermal ion etching. The etched trench may have a shape that is larger at the top and smaller at the bottom. In another specific embodiment, the width of the trench top surface is 0.2-0.5 μm and the depth is 1.2-3 μm. In yet another specific embodiment, the width of the trench top surface is 0.5-1.5 μm and the depth is 3-6 μm.

[0063] In one embodiment, a dielectric combination layer is first formed on the upper surface of the epitaxial layer: silicon oxide (100-1000A), a hard mask material (1000-4000A), and silicon oxide (2000-3000A); then, photolithography is performed to form a patterned dielectric combination layer; then, the semiconductor is etched to form trenches between the patterned dielectric layer combination layers; after the trenches are formed, the hard mask material is wet-etched to shrink it to the upper surface platform of the semiconductor. Since the upper surface of the hard mask material is protected by the upper oxide layer (silicon oxide), the etching occurs only in the horizontal direction, so that the left and right boundaries of the hard mask material are eventually etched into the upper surface platform of the semiconductor; finally, the oxide layer above the hard mask material is removed to form a hard mask 301.

[0064] In the third step, a trench insulating layer 202 and a shielding gate electrode 203 are formed in the trench; and then an oxide 211 is deposited to completely fill the first and second types of trenches and partially fill the third type of trench 252. Figure 3 shown.

[0065] The trench insulating layer 202 may be an oxide layer, or a combination of an oxide layer and a nitride layer.

[0066] The shielding gate electrode 203 is usually made of polysilicon, and may also be made of metal, metal-semiconductor compound (such as Al, Ti, W, etc.), and a combination thereof.

[0067] In one specific embodiment, the trench insulating layer 202 is an oxide. The oxide layer is first formed by thermal oxidation or chemical vapor deposition to cover the trench sidewalls. Then, a shield gate electrode material is deposited and then etched back to the bottom of the trench to form the shield gate electrode 203. The shield gate electrode 203 is made of polysilicon and is etched back using a wet or dry etch method. The height of the top surface of the shield gate electrode 203 after etching back is 0.4-2.0 μm from the top surface of the semiconductor epitaxial layer 201. After etching back the shield gate electrode 203, oxide is deposited again. The deposition method may include several deposition steps, including a high-density plasma chemical vapor deposition (HDP CVD) process. Because the third-type trench 252 is wider than the first and second-type trenches, the deposition process can be adjusted to ensure that the first and second-type trenches are completely filled while the third-type trench is partially filled.

[0068] In this step, compared with the traditional process, when forming the shielding gate electrode 203, with the corresponding layout improvement, the photolithography process for defining the area of ​​the shielding gate electrode can be eliminated, thereby shortening the process flow and reducing the manufacturing cost.

[0069] In the fourth step, a filling material 401 is formed to fill the third type trench 252, such as Figure 4 shown.

[0070] In a specific embodiment, the filling material 401 may be polysilicon formed by chemical vapor deposition. In addition, the filling material 401 may also be an organic polymer, nitride, metal compound, etc.

[0071] In the fifth step, the oxide 211 and the filling material 401 above the hard mask 301 are removed to expose the hard mask 301, and then a photoresist 402 is formed on the upper surface of the second type trench 251 and the third type trench 252 and their peripheries. Figure 5 shown.

[0072] The method of removing the oxide 211 and the filling material 401 may be etching or chemical mechanical planarization process.

[0073] In one embodiment, the filling material 401 is first etched to a height lower than the hard mask 301 ; and then the oxide 211 is etched to a height lower than the hard mask 301 .

[0074] In another embodiment, a chemical mechanical planarization process is used to remove excess oxide 211 and filler material 401 from the surface of epitaxial layer 201, and hard mask 301 is used as a grinding stop layer, ultimately exposing hard mask 301 on the semiconductor top surface. This chemical mechanical planarization process facilitates a relatively flat wafer surface, facilitating control of subsequent processes such as photolithography and etching.

[0075] Step 6: etch back the oxide 211 to form an inter-electrode isolation layer 204 in the first type trench 250. Figure 6 shown.

[0076] The thickness of the inter-electrode isolation layer 204 formed after etching is 500-5000 Å. In a specific embodiment, a wet etching process is used.

[0077] During the etching process of the inter-electrode isolation layer 204 , the photoresist 402 and the hard mask 301 play a role in preventing lateral etching and protecting oxides in the second type trench 251 and the third type trench 252 .

[0078] In the seventh step, the hard mask 301 is etched under the protection of the photoresist 402 until the hard mask 301 on the first type trench 250 and the second type trench 251 is completely etched away. The hard mask 301 located outside the third type trench 252 is protected by the photoresist 402 and remains above the semiconductor. Figure 7 shown.

[0079] The hard mask 301 may be etched by wet etching. In a specific embodiment, the hard mask 301 is silicon nitride and the etching method is wet etching in a hot phosphoric acid environment.

[0080] In the eighth step, the photoresist 402 and the filling material 401 deposited in the third type trench 252 are removed. Figure 8 shown.

[0081] In the ninth step, a gate oxide layer 210 is formed on the upper sidewall of the trench, and then a gate electrode 205 is formed, as shown in FIG. Figure 9 As shown, the gate electrode 205 in the terminal trench 252 may be smaller in width than the shield gate electrode 203 thereunder.

[0082] The gate oxide layer 210 has a thickness of 200-1000 Å. The gate oxide layer 210 may be formed by thermal oxidation or deposition, or a combination thereof. In one embodiment, the gate oxide layer 210 is formed by wet thermal oxidation at a temperature of 900-1300 degrees.

[0083] In one embodiment, the gate electrode 205 is formed by filling the gate electrode material and etching back. The gate electrode material is usually polysilicon. The etching back method may include chemical planarization and / or dry etching.

[0084] In the tenth step, the hard mask 301 is used as a mask for ion implantation to perform ion implantation, such as Figure 10 shown.

[0085] The ion implantation includes at least one step of P-type ion implantation with an implantation energy of 10keV-200keV. The dopant material implanted may be boron with a dose of 1e12-5e14 cm -3 After the P-type ion implantation, a thermal diffusion process may be performed. In one embodiment, the thermal diffusion temperature is 1000-1150° C. and the time is 10-300 minutes.

[0086] After P-type ion implantation, it is possible to perform a further N + Type ion implantation, with an implantation energy of 5keV-100keV, the doping material may be arsenic, with a dose of 1e13-5e16 cm -3 Between. N +The N type ion implantation may also use the mask dielectric layer 301 as a mask to define the implantation area, or an additional photolithography step may be used to pre-form a patterned photoresist to define the N type ion implantation area. + Type ion implantation area.

[0087] like Figure 10 As shown, during ion implantation, the mask dielectric layer 301 located at the periphery of the trench blocks the P-type ions, and the P-type doped body region 216 formed after the ion implantation is limited to the interior of the series of trenches. Compared with the traditional process, the P-type ions and N-type doped body regions 216 can be omitted at most during ion implantation. + After the ion implantation, the hard mask 301 can be retained or removed.

[0088] In the eleventh step, an oxide dielectric layer 206 is formed on the upper surface of the semiconductor, and then a contact hole 207 is formed on the oxide dielectric layer.

[0089] Oxide dielectric layer 206 is typically composed of oxide and has a thickness of 0.3-1.5 μm. In one embodiment, oxide dielectric layer 206 includes a lower layer of undoped silicon oxide with a thickness of 0.05-1.0 μm and an upper layer of borophosphosilicate glass with a thickness of 0.1-1.5 μm. The formation method of oxide dielectric layer 206 may include oxide deposition and oxide planarization processes.

[0090] A portion of the contact hole 207 is located directly above the second type trench 251 and extends into the shielding gate electrode 203 in the trench. Figure 11 As shown, this is a first-type contact hole. Another portion of the contact hole 207 is located directly above the first-type trench 250 or the third-type trench 252, extending deep into the gate electrode 205 within the trench, representing a second-type contact hole 2071. Yet another portion of the contact hole 207 is located between the trenches and extends deep into the semiconductor, contacting the P-type doped region 216 and the N+-type doped source region, representing a third-type contact hole.

[0091] In a specific embodiment, the contact holes 207 are formed by performing photolithography, using photoresist to define the positions of the contact holes, and then performing dry etching. Each contact hole is used to connect to the upper surface metal 208.

[0092] After etching the contact hole 207, one or more steps of P + Type ion implantation forms a P in the P-type doped body region 216 + Type doped contact region.

[0093] In the twelfth step, the upper surface metal 208 and the lower surface metal 209 are formed to form a device, such as Figure 12 shown.

[0094] The semiconductor top surface metal 208 is typically Al or an Al compound, such as Al / Cu, Al / Si / Cu, and has a thickness of 3-5 μm. Before forming the top surface metal 208, the contact hole 207 may be filled with a diffusion barrier metal. The diffusion barrier metal may be composed of a metal such as Ti or W, or a metal compound thereof such as TiSi or TiN.

[0095] The semiconductor bottom surface metal 220 is usually Ag or Ag compound with a thickness of 0.1-2 μm. Before forming the drain metal 209 under the semiconductor substrate 200, the semiconductor substrate 200 may be thinned to a thickness of 30-200 μm.

[0096] Figure 13A A top view of a possible embodiment of the device of the present invention is shown. Figure 12 The device cross-section structure in Figure 13A In the embodiment, the third type of groove 252 at the outermost portion of the series of grooves includes at least one portion extending outwards, and the extended portion is perpendicular to the third type of groove 252. The cross-sectional structure of the extended portion is as follows: Figure 13B As shown (corresponding to Figure 13A As shown in the figure, the contact hole 207 penetrates into the gate electrode 205 through the oxide dielectric layer 206, connecting the gate electrode 205 with the upper surface metal 208.

[0097] In one embodiment, the structure of the third type of groove 252 surrounding and perpendicular to the first and second types of grooves may be as shown in FIG13C (corresponding to Figure 13A The inner sidewall of the third type trench 252 is a gate oxide layer 210, and the outer sidewall is an oxide layer 211. The oxide layer 211 is thicker than the gate oxide layer 210. The gate oxide layer 210 and the oxide layer 211 isolate the semiconductor epitaxial layer 201 and the gate electrode 205 in the third type trench from each other. The gate electrode 205 has a slightly higher step on the side close to the gate oxide layer 210. Figure 14A and Figure 14B Show the key formation steps of the above structure.

[0098] in Figure 14A Corresponding to the sixth step of the process. Figure 13A As shown in the trench structure, since the inner periphery of the third type trench 252 is connected to the first type trench 250, when the oxide 211 in the first type trench 250 is etched in the sixth step of the process, the oxide 211 in the third type trench (252) will be partially etched from the side, forming the following Figure 14AThe structure shown in FIG. 4 is shown in FIG. 4 , and the etching depth does not exceed the depth of the filling material 401. Next, after the seventh step of removing the hard mask 301 and the eighth step of removing the filling material 401, the structure is shown in FIG. Figure 14B As shown, a step of an oxide layer with a high inner side and a low outer side is formed. After that, a gate oxide layer 210 and a gate electrode 205 are formed in sequence and finally Figure 13C The structure in .

[0099] Figures 15A to 15E The key steps of the process flow of another embodiment of the present invention are shown. In this embodiment, the first eight process steps are consistent with the first embodiment described above, and the following steps are as follows:

[0100] In the ninth step, a gate oxide layer 210 is formed on the upper sidewall of the trench, and then a gate electrode 205 is formed, and the depth from the gate electrode 205 to the upper surface of the semiconductor is between 0.3 and 2 μm. Figure 15A shown.

[0101] In the tenth step, ion implantation is performed using the hard mask 301 as a mask for ion implantation, such as Figure 15B shown.

[0102] In the eleventh step, an oxide dielectric layer 206 is formed on the upper surface of the semiconductor, such as Figure 15C As shown, the oxide dielectric layer 206 has a thickness of 0.3-1.5 μm. The oxide dielectric layer 206 is made of undoped silicon oxide and / or borophosphosilicate glass. The oxide dielectric layer 206 may be formed by oxide deposition, or by thermal oxidation followed by oxide deposition.

[0103] In the twelfth step, the upper oxide dielectric layer 206 is removed and the upper surface of the semiconductor is exposed, such as Figure 15D As shown, the oxide layer may be planarized first and then the oxide is etched.

[0104] In one embodiment, the method for removing the upper oxide dielectric layer 206 is to perform a chemical mechanical planarization process using the hard mask 301 as a grinding stop layer, and then perform oxide etching until the upper surface of the semiconductor is exposed.

[0105] In the thirteenth step, the semiconductor is etched to form a contact hole 230, as shown in FIG. Figure 15E shown.

[0106] The contact hole (230) may be shaped larger at the top and smaller at the bottom. The distance between the bottom of the contact hole (230) and the sidewall of the adjacent trench is between 0.05um and 0.3um. During the semiconductor etching process, the hard mask 301 above the semiconductor can protect the peripheral area of ​​the series of trenches and prevent the area from being etched.

[0107] After etching the contact hole 230, one or more steps of P + Type ion implantation forms a P in the P-type doped body region 216 + Type doped contact region.

[0108] In step 14, using photolithography, contact holes 207 are formed in the second-type trench 251 and the third-type trench 252. A portion of the contact hole 207 is located directly above the second-type trench 251 and extends into the shield gate electrode 203 within the trench. Another portion of the contact hole 207 is located directly above the first-type trench 250 or the third-type trench 252 and extends into the gate electrode 205 within the trench.

[0109] In the fifteenth step, metal is formed on the upper and lower surfaces, and finally the device is formed.

[0110] The shielded-gate trench field-effect transistor described in this invention has a unique manufacturing process flow, structure, and layout. Compared with traditional processes, it can reduce the number of photolithography steps and thus reduce manufacturing costs. It should be noted that the relevant process steps in the above embodiments can be appropriately increased or decreased to achieve the same effect. Persons skilled in the relevant art should recognize that the embodiments of the invention described above are non-limiting but exemplary, and the invention can be implemented in a wider range than the above embodiments.

Claims

1. A method for manufacturing a shielded gate trench field effect transistor device, characterized in that: The manufacturing method comprises the following steps: The first step is to provide a first conductive type substrate (200) and form a first conductive type epitaxial layer (201) thereon; the second step is to form a hard mask (301) and a series of trenches on the upper surface of the first conductive type epitaxial layer (201), which are first type trenches (250), second type trenches (251) and third type trenches (252), respectively, wherein the width of the third type trenches (252) is greater than the widths of the first type trenches (250) and the second type trenches (251); The first type of trench (250) and the second type of trench (251) are in the same trench section, and the third type of trench (252) is located at the outermost periphery of the device and surrounds the first type of trench (250) and the second type of trench (251); The hard mask (301) comprises at least one layer of an etch-resistant material having an etching rate different from that of the oxide; Step 3: forming a trench insulating layer (202) and a shielding gate electrode (203) in the trench, and then depositing an oxide (211) to completely fill the first type of trench (250) and the second type of trench (251), and partially fill the third type of trench (252); Step 4: forming a filling material (401) to fill the third type of groove (252); Step 5: removing the oxide (211) and the filling material (401) above the hard mask (301), exposing the hard mask (301), and then forming a photoresist (402) on the upper surface of the second type trench (251) and the third type trench (252) and their peripheries; Step 6: Under the protection of the photoresist (402) and the hard mask (301), the oxide (211) is etched back to form an inter-electrode isolation layer (204) in the first type of trench (250); when the oxide (211) in the first type of trench (250) is etched, the oxide (211) in the third type of trench (252) surrounding and perpendicular to the first type of trench and the second type of trench will be partially etched from the side; Step 7: etching the hard mask (301) under the protection of the photoresist (402); Step 8: removing the photoresist (402) and the filling material (401) deposited in the third type trench (252), so that the oxide in the third type trench forms a step with a high inner side and a low outer side; Step 9: forming a gate oxide layer (210) on the upper trench sidewall, and then forming a gate electrode (205), wherein the gate electrode in the third type of trench is formed on a step with a high inner side and a low outer side of the oxide; The thickness of the oxide (211) located on the peripheral sidewall of the third type of trench (252) surrounding and perpendicular to the first type of trench and the second type of trench is thicker than the gate oxide layer (210) located on the inner sidewall; Step 10: Using the hard mask (301) as a mask for ion implantation, ion implantation is performed; During ion implantation, the hard mask (301) located at the periphery of the trench confines the second conductive type doped body region (216) formed after the ion implantation to the interior of the series of trenches; Step 11: forming an oxide dielectric layer (206) on the upper surface of the semiconductor, and then forming a first contact hole (207) on the oxide dielectric layer; The first type of contact hole in the first contact hole is located directly above the second type of trench (251) and extends into the shielding gate electrode (203) in the trench; the second type of contact hole in the first contact hole is located directly above the first type of trench (250) or the third type of trench (252) and extends into the gate electrode (205) in the trench; the third type of contact hole in the first contact hole is located between the trenches and extends into the semiconductor, contacting the second conductive type doped body region (216) and the first conductive type doped source region; Step 12: forming an upper surface metal (208) and a lower surface metal (209) to form a device.

2. The method for manufacturing a shielded gate trench field effect transistor device according to claim 1, wherein: The anti-etching material layer in the first step is semiconductor nitride.

3. The method for manufacturing a shielded gate trench field effect transistor device according to claim 1, wherein: In the fifth step, the oxide (211) and the filling material above the hard mask (301) are removed by a chemical mechanical planarization process, and the hard mask (301) is used as a grinding stop layer.

4. The method for manufacturing a shielded gate trench field effect transistor device according to claim 1, wherein: In the fourth step, the filling material (401) is polysilicon, organic polymer, nitride or metal compound.

5. The method for manufacturing a shielded gate trench field effect transistor device according to claim 1, wherein: The third type of groove (252) further includes a plurality of outwardly extending grooves (2521), wherein the extending grooves (2521) are perpendicular to the third type of groove (252).

6. The method for manufacturing a shielded gate trench field effect transistor device according to claim 5, wherein: The first contact hole (207) penetrates into the gate electrode (205) in the extension section trench (2521) through the oxide dielectric layer (206), connecting the gate electrode (205) to the upper surface metal (208).

7. A device manufactured by the method for manufacturing a shielded gate trench field effect transistor device according to any one of claims 1 to 6.

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