Transparent display panel and manufacturing method thereof

Abstract

An embodiment of the present application discloses a transparent display panel and a preparation method thereof: comprising a first substrate and at least two second substrates; the first substrate further comprising a first underlayer, a thin film transistor array layer and a first pad; the thin film transistor array layer is arranged on the first substrate, the first pad is arranged on the thin film transistor array layer, and the thin film transistor array layer includes thin film transistors; at least two second substrates are spliced ​​on the first substrate; the second substrate comprises a second substrate, a pixel unit and a second pad; the pixel unit and the thin film transistor are arranged in an overlapping manner; the use of the overlapping arrangement of the pixel unit and the thin film transistor and the arrangement of the thin film transistor on the first substrate can not only increase the transparent area of ​​the transparent display panel, but also reduce the cost loss of the second substrate caused by the transfer yield problem of the light-emitting diode device.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a transparent display panel and a method for preparing the same. Background Art

[0002] Current display panel splicing technologies primarily involve rigid and flexible panels. These methods present several challenges: The seams between rigid panels are opaque, and when the substrate is transparent, the seams are more noticeable. The backside of the panel is complex, impacting the transparent display.

[0003] During the research and practice of the prior art, the inventors of the present application discovered that, due to the low yield of the existing light-emitting device transfer technology, setting thin-film transistors on the splicing board will increase the loss cost of the splicing board. Summary of the Invention

[0004] The embodiments of the present application provide a transparent display panel, which can increase the transparent area of ​​the transparent display panel, improve the transparency of the transparent display panel, and reduce the loss cost of the transparent display panel.

[0005] An embodiment of the present application provides a transparent display panel, comprising:

[0006] a first substrate; the first substrate further comprising a first substrate, a thin film transistor array layer and a first pad; the thin film transistor array layer is disposed on the first substrate, the first pad is disposed on the thin film transistor array layer, and the thin film transistor array layer includes thin film transistors;

[0007] At least two second substrates, at least two second substrates are spliced ​​on the first substrate; the second substrate includes a second substrate, a pixel unit, and a second pad; the pixel unit is arranged on a side of the second substrate away from the first substrate; the second pad is arranged on a side of the second substrate close to the first substrate; the pixel unit includes at least one light-emitting diode device, and the at least one light-emitting diode device is electrically connected to the second pad; the first pad is bound and connected to the second pad;

[0008] The pixel unit and the thin film transistor are arranged to overlap.

[0009] Optionally, in some embodiments of the present application, the pixel unit is arranged to overlap with the first pad and the second pad respectively.

[0010] Optionally, in some embodiments of the present application, the first substrate further includes a first wiring, wherein the first wiring is connected to the thin film transistor and the first pad;

[0011] The second substrate further includes a second trace, the second trace being connected to the pixel unit and the second pad; the second trace passing through the second substrate;

[0012] The first routing line and the second routing line are arranged to overlap.

[0013] Optionally, in some embodiments of the present application, the distance between any two adjacent pixel units is the same.

[0014] Optionally, in some embodiments of the present application, the transparent display panel further includes a cover plate, and the cover plate is disposed on a side of at least two of the second substrates away from the first substrate.

[0015] Optionally, in some embodiments of the present application, the thin film transistor array layer includes: a semiconductor layer, a first insulating layer, a gate, a second insulating layer, a capacitor metal layer, an interlayer dielectric layer, a source / drain metal layer, a passivation layer and a planarization layer; the semiconductor layer is arranged on the first substrate; the first insulating layer is arranged on the first substrate and covers the semiconductor layer; the gate is arranged on the first insulating layer; the second insulating layer is arranged on the first insulating layer and covers the gate; a capacitor metal layer, the capacitor metal layer is arranged on the second insulating layer; a capacitor is formed between the gate and the capacitor metal layer; the interlayer dielectric layer is arranged on the second insulating layer and covers the capacitor metal layer; the source / drain metal layer is arranged on the interlayer dielectric layer; the source / drain metal layer includes a source and a drain; the source and the drain are electrically connected to the semiconductor layer; the passivation layer is arranged on the interlayer dielectric layer and covers the source / drain metal layer; the planarization layer is arranged on the passivation layer.

[0016] Optionally, in some embodiments of the present application, the first pad includes a first sub-pad and a second sub-pad; the first pad is disposed on the planar layer; and the first sub-pad is electrically connected to the source.

[0017] Optionally, in some embodiments of the present application, the second pad includes a third sub-pad and a fourth sub-pad; the third sub-pad is electrically connected to the first sub-pad; the fourth sub-pad is electrically connected to the second sub-pad; the anode of the light-emitting diode device is electrically connected to the third sub-pad; and the cathode of the light-emitting diode device is electrically connected to the fourth sub-pad.

[0018] Optionally, in some embodiments of the present application, the transparent display panel includes a display area and a border area, the border area is located on at least one side of the display area; the second substrate is arranged in an area of ​​the first substrate corresponding to the display area; the first substrate also includes a gate drive circuit, the gate drive circuit is arranged corresponding to the border area, and is located on both sides of the display area.

[0019] Accordingly, an embodiment of the present application further provides a method for preparing a transparent display panel, comprising the following steps:

[0020] A first substrate is provided; the first substrate further comprises a first underlayer, a thin film transistor array layer and a first pad; the thin film transistor array layer is disposed on the first substrate, the first pad is disposed on the thin film transistor array layer, and the thin film transistor array layer comprises thin film transistors;

[0021] Providing at least two second substrates, the second substrates including a second substrate, a pixel unit, and a second pad; the pixel unit is disposed on a side of the second substrate away from the first substrate; the second pad is disposed on a side of the second substrate close to the first substrate; the pixel unit includes at least one light-emitting diode device, and the at least one light-emitting diode device is electrically connected to the second pad;

[0022] The first substrate and the second substrate are spliced ​​together; the pixel unit and the thin film transistor are arranged in an overlapping manner; and the first pad is bound and connected to the second pad.

[0023] Optionally, in some embodiments of the present application, the step of providing the first substrate includes:

[0024] providing a first substrate;

[0025] forming a semiconductor layer on the first substrate;

[0026] forming a first insulating layer on the first substrate, wherein the first insulating layer covers the semiconductor layer;

[0027] forming a gate on the first insulating layer;

[0028] forming a second insulating layer on the first insulating layer, wherein the second insulating layer covers the gate;

[0029] forming a capacitor metal layer on the second insulating layer;

[0030] forming an interlayer dielectric layer on the second insulating layer, wherein the interlayer dielectric layer covers the capacitor metal layer;

[0031] forming a source-drain metal layer on the interlayer dielectric layer, wherein the source-drain metal layer includes a source electrode and a drain electrode; the semiconductor layer, the gate electrode, the source electrode and the drain electrode form the thin film transistor;

[0032] forming a planar layer on the passivation layer to form the thin film transistor array layer;

[0033] The first pad and the first wiring are formed on the planar layer, and the first pad is connected to the thin film transistor through the first wiring.

[0034] Optionally, in some embodiments of the present application, the step of providing at least two second substrates includes:

[0035] Providing a temporary substrate; forming the second pad on the temporary substrate; the second pad includes a third sub-pad and a fourth sub-pad;

[0036] forming a second substrate on the temporary substrate; the second substrate covers the second pad;

[0037] Transferring the light-emitting diode device to a side of the second substrate away from the first base plate; electrically connecting the first pad to the light-emitting diode device via the second trace; electrically connecting the anode of the light-emitting diode device to the third pad; and electrically connecting the cathode of the light-emitting diode device to the fourth pad;

[0038] The temporary substrate is peeled off to expose the second pad.

[0039] Optionally, in some embodiments of the present application, the step of splicing the first substrate and the second substrate includes:

[0040] Laminating a support plate on the second substrate to form a second substrate module;

[0041] The second substrate module is transferred to the first substrate and is bonded to the first substrate; a gap is formed between the first substrate and the second substrate; the pixel unit and the thin film transistor are overlapped;

[0042] removing the support plate;

[0043] Fill the gap with bonding glue.

[0044] The embodiment of the present application adopts a method of overlapping pixel units and thin film transistors and setting thin film transistors on the first substrate to increase the transparent area of ​​the transparent display panel, improve the transparency of the transparent display panel, and reduce the cost loss caused by the transfer yield problem of the light-emitting diode device on the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 This is a schematic structural diagram of a transparent display panel provided in Example 1 of the present application;

[0047] Figure 2 This is a schematic diagram of the transparent display panel and cover structure provided in Example 1 of the present application;

[0048] Figure 3 is a schematic structural diagram of a transparent display panel provided by another embodiment of the present application;

[0049] Figure 4 1 is a schematic top view of the first substrate and the second substrate provided in an embodiment of the present application;

[0050] Figure 5 This is the method for preparing a transparent display panel provided in Example 2 of the present application;

[0051] Figure 6 This is a schematic diagram of the first substrate structure provided in Example 2 of the present application;

[0052] Figure 7 This is a schematic diagram of the structure of transferring the light-emitting device to the second substrate provided in the second embodiment of the present application;

[0053] Figure 8 This is a schematic diagram of the structure of the peeling temporary substrate and the laminating support plate provided in Example 2 of the present application;

[0054] Figure 9 This is a schematic structural diagram of the second substrate module and the first substrate provided in the second embodiment of the present application;

[0055] Figure 10 This is a structural diagram of the second substrate module and the first substrate provided in the second embodiment of the present application;

[0056] Figure 11 This is a schematic diagram of the structure of the second embodiment of the present application with the support plate removed.

[0057] Explanation of reference numerals: transparent display panel 100, first substrate 10, first underlay 11, thin film transistor array layer 12, thin film transistor 121, semiconductor layer 1211, gate 1212, source / drain metal layer 1213, source 1213a, drain 1213b, first pad 13, first sub-pad 131, second sub-pad 132, first trace 14, capacitor metal layer 15, gate drive circuit 16, first insulating layer 122, second insulating layer 123, interlayer dielectric Layer 124, passivation layer 125, flat layer 126, second substrate 20, second substrate 21, pixel unit 22, light-emitting diode device 221, second pad 23, third sub-pad 231, fourth sub-pad 232, second trace 24, temporary substrate 201, support plate 202, second substrate module 203, conductive adhesive 30, gap 40, bonding adhesive 50, cover plate 60, first insulating layer 110, first sub-substrate 111, second insulating layer 112 and buffer layer 113. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise specified, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; and "inside" and "outside" refer to the outline of the device.

[0059] The embodiments of the present application provide a transparent display panel, which is described in detail below. It should be noted that the order of description of the following embodiments does not limit the preferred order of the embodiments.

[0060] Example 1

[0061] See also Figure 1 and Figure 2An embodiment of the present application provides a transparent display panel 100, comprising: a first substrate 10 and at least two second substrates 20. The first substrate 10 further comprises a first underlay 11, a thin-film transistor array layer 12, and a first pad 13. The thin-film transistor array layer 12 is disposed on the first substrate 11, and the first pad 13 is disposed on the thin-film transistor array layer 12. The thin-film transistor array layer 12 comprises thin-film transistors 121. At least two second substrates 20 are spliced ​​onto the first substrate 10. The second substrate 20 comprises a second substrate 21, a pixel unit 22, and a second pad 23. The pixel unit 22 is disposed on a side of the second substrate 21 away from the first substrate 10. The second pad 23 is disposed on a side of the second substrate 21 closer to the first substrate 10. The pixel unit 22 comprises at least one light-emitting diode device 221, which is electrically connected to the second pad 23. The first pad 13 is bonded to the second pad 23. The pixel unit 22 and the thin-film transistor 121 are disposed in an overlapping manner.

[0062] It can be understood that in this embodiment, the overlapping arrangement of the pixel unit 22 and the thin film transistor 121 can not only increase the transparent area of ​​the transparent display panel 100 and improve the transparency of the transparent display panel 100, but also reduce the area of ​​non-transparent devices and wiring, thereby improving the display effect.

[0063] Furthermore, in existing light-emitting device transfer technology, a daughterboard is used to bind a large number of light-emitting devices. If a light-emitting device fails during the transfer and binding process, the entire daughterboard will be scrapped, resulting in cost losses. Furthermore, during the process of splicing the daughterboard and motherboard, the daughterboard needs to be transferred, which also has the potential to cause daughterboard failures. Therefore, in this embodiment, the thin-film transistor 121 is disposed on the first substrate 10 to reduce losses caused by daughterboard failures during the manufacturing process.

[0064] See also Figure 3 Optionally, in some embodiments, the first substrate 10 may further include a first isolation layer 110, a first sub-substrate 111, a second isolation layer 112, and a buffer layer 113, which are sequentially stacked on the first substrate 11. In this case, the thin film transistor array layer 12 is disposed on the buffer layer 113, which can increase the design space of the first substrate 10 and accommodate more design structures, such as data lines, scan lines, or power lines.

[0065] Optionally, in some embodiments of the present application, the pixel unit 22 is arranged to overlap with the first pad 13 and the second pad 23 respectively.

[0066] It is understandable that in this embodiment, since the pixel unit 22, the first pad 13, and the second pad 23 each affect the light emission effect of the transparent display panel 100, the pixel unit 22 is respectively overlapped with the first pad 13 and the second pad 23, which can reduce the influence of the pixel unit 22, the first pad 13, and the second pad 23 on the transparent display panel 100.

[0067] Optionally, in this embodiment, the first substrate 10 further includes a first trace 14, which is connected to the thin film transistor 121 and the first pad 13. The second substrate 20 further includes a second trace 24, which is connected to the pixel unit 22 and the second pad 23. The second trace 24 extends through the second substrate 21. The first trace 14 and the second trace 24 are arranged to overlap.

[0068] It is understandable that in this embodiment, the first and second traces 14 and 24 each affect the light emitting effect of the transparent display panel 100. The overlapping arrangement of the first and second traces 14 and 24 can reduce the influence of the first and second traces 14 and 24 on the transparent display panel 100.

[0069] Optionally, in this embodiment, the distance between any two adjacent pixel units 22 is the same.

[0070] It can be understood that in this embodiment, the distance between any two adjacent pixel units 22 is the same; that is, in two adjacent second substrates 20, the distance between adjacent pixel units 22 at the gap is the same as the distance between any two adjacent pixel units 22 in the second substrate 20. Such a setting can visually eliminate the seams between the second substrates 20.

[0071] Optionally, in this embodiment, the transparent display panel 100 further includes a cover plate 60 , and the cover plate 60 is disposed on a side of the at least two second substrates 20 away from the first substrate 10 .

[0072] It is understood that in this embodiment, the cover plate 60 is made of glass, which has good light transmittance and wear resistance, can effectively protect the transparent display panel 100 and improve the display effect. In some embodiments, the cover plate 60 is also made of polyester. In some embodiments, the cover plate 60 can also be made of a flexible material, such as polyimide.

[0073] Optionally, in this embodiment, the thin film transistor array layer 12 includes: a semiconductor layer 1211, a first insulating layer 122, a gate electrode 1212, a second insulating layer 123, a capacitor metal layer 15, an interlayer dielectric layer 124, a source / drain metal layer 1213, a passivation layer 125, and a planarization layer 126. The semiconductor layer 1211 is disposed on the first substrate 11. The first insulating layer 122 is disposed on the first substrate 11 and covers the semiconductor layer 1211. The gate electrode 1212 is disposed on the first insulating layer 122. The second insulating layer 123 is disposed on the first insulating layer 122 and covers the gate electrode 1212. The capacitor metal layer 15 is disposed on the second insulating layer 123. A capacitor is formed between the gate electrode 1212 and the capacitor metal layer 15. The interlayer dielectric layer 124 is disposed on the second insulating layer 123 and covers the capacitor metal layer 15. The source / drain metal layer 1213 is disposed on the interlayer dielectric layer 124. The source / drain metal layer 1213 includes a source electrode 1213a and a drain electrode 1213b. The source electrode 1213a and the drain electrode 1213b are electrically connected to the semiconductor layer 1211. The passivation layer 125 is disposed on the interlayer dielectric layer 124 and covers the source / drain metal layer 1213. The planarization layer 126 is disposed on the passivation layer 125.

[0074] It is understood that in this embodiment, the capacitor formed between the gate 1212 and the capacitor metal layer 15 can save design space on the first substrate 10 and accommodate more structural designs on the first substrate 10. By forming a capacitor between the gate 1212 and the capacitor metal layer 15, the gate 1212 and the capacitor metal layer 15 form an overlapping structure, reducing the impact of the capacitor metal layer 15 on the light output effect.

[0075] Optionally, in some embodiments of the present application, the first pad 13 includes a first sub-pad 131 and a second sub-pad 132. The first pad 13 is disposed on the planar layer 126. The first sub-pad 131 is electrically connected to the source electrode 1213a.

[0076] It is understandable that, in this embodiment, disposing the first pad 13 on the flat layer 126 can facilitate exposing the first pad 13 from the first substrate 10 , thereby facilitating subsequent binding of the first pad 13 and the second pad 23 .

[0077] Optionally, in some embodiments of the present application, the second pad 23 includes a third sub-pad 231 and a fourth sub-pad 232. The third sub-pad 231 is electrically connected to the first sub-pad 131. The fourth sub-pad 232 is electrically connected to the second sub-pad 132. The anode of the light-emitting diode device 221 is electrically connected to the third sub-pad 231. The cathode of the light-emitting diode device 221 is electrically connected to the fourth sub-pad 232.

[0078] It can be understood that, in this embodiment, the first pads 13 and the second pads 23 correspond one to one, which can improve the firmness of the first pads 13 and the second pads 23.

[0079] See also Figure 4 Optionally, in some embodiments of the present application, the transparent display panel 100 includes a display area and a border area, and the border area is located on at least one side of the display area; the second substrate 20 is arranged in the area of ​​the first substrate 10 corresponding to the display area; the first substrate 10 also includes a gate drive circuit 16, which is arranged corresponding to the border area and is located on both sides of the display area.

[0080] It can be understood that in this embodiment, the gate drive circuit 16 is arranged in the frame area of ​​the first substrate 10 to reduce the area of ​​the display area occupied by the gate drive circuit 16, thereby avoiding the gate drive circuit 16 being arranged in the display area. Since the gate drive circuit 16 is not light-transmissive, arranging the gate drive circuit 16 in the frame area of ​​the first substrate 10 can improve the integrity of the display area.

[0081] Example 2

[0082] See also Figure 5 , this embodiment also provides a method for preparing a display screen.

[0083] The method for preparing a display screen comprises the following steps:

[0084] Step B1: Provide a first substrate 10. The first substrate 10 further includes a first underlayer 11, a thin film transistor array layer 12, and a first pad 13. The thin film transistor array layer 12 is disposed on the first underlayer 11, and the first pad 13 is disposed on the thin film transistor array layer 12. The thin film transistor array layer 12 includes thin film transistors 121.

[0085] Step B2: Provide at least two second substrates 20. The second substrates 20 include a second substrate 21, a pixel unit 22, and a second pad 23. The pixel unit 22 is disposed on a side of the second substrate 21 away from the first substrate 10. The second pad 23 is disposed on a side of the second substrate 21 closer to the first substrate 10. The pixel unit 22 includes at least one light-emitting diode device 221, which is electrically connected to the second pad 23.

[0086] Step B3: splice the first substrate 10 and the second substrate 20. The pixel unit 22 and the thin film transistor 121 are overlapped. The first pad 13 and the second pad 23 are bonded and connected.

[0087] See also Figure 6 , the preparation method of the display screen is described in detail below:

[0088] In step B1, the step of providing a first substrate 10 includes:

[0089] Step B10: Provide a first substrate 11. In this step, first substrate 11 can be a flexible substrate or a rigid substrate, and can include one of glass, silicon, silicon dioxide, polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene diphthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, polyimide, or polyurethane. The process then proceeds to Step B11.

[0090] In step B11, a semiconductor layer 1211 is formed on the first substrate 11. The semiconductor layer 1211 can be formed of single crystal silicon, polycrystalline silicon or an oxide semiconductor. The oxide semiconductor can include oxides based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn) or indium (In) and their composite oxides (such as indium gallium zinc oxide (InGaZnO4), indium zinc oxide (Zn-In-O), zinc tin oxide (Zn-Sn-O), indium gallium oxide (In-Ga-O), indium tin oxide (In-Sn-O), indium zirconium oxide (In-Zr-O), indium zirconium zinc oxide (In-Zr-Zn-O), indium zirconium tin oxide (In-Zr-Sn-O), indium zirconium gallium oxide (In-Zr-Ga-O), indium aluminum oxide (In-Al-O), One of indium zinc aluminum oxide (In-Zn-Al-O), indium tin aluminum oxide (In-Sn-Al-O), indium aluminum gallium oxide (In-Al-Ga-O), indium tantalum oxide (In-Ta-O), indium tantalum zinc oxide (In-Ta-Zn-O), indium tantalum tin oxide (In-Ta-Sn-O), indium tantalum gallium oxide (In-Ta-Ga-O), indium germanium oxide (In-Ge-O), indium germanium zinc oxide (In-Ge-Zn-O), indium germanium tin oxide (In-Ge-Sn-O), indium germanium gallium oxide (In-Ge-Ga-O), titanium indium zinc oxide (Ti-In-Zn-O), and hafnium indium zinc oxide (Hf-In-Zn-O). Then, the process proceeds to step B12.

[0091] In step B12, a first insulating layer 122 is formed on the first substrate 11, covering the semiconductor layer 1211. The material of the first insulating layer 122 can include at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and an organic photoresist. The process then proceeds to step B13.

[0092] Step B13, forming a gate 1212 on the first insulating layer 122;

[0093] In step B14, a second insulating layer 123 is formed on the first insulating layer 122. The second insulating layer 123 covers the gate 1212. The material of the second insulating layer 123 can include at least one of silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, titanium oxide, and an organic photoresist. The process then proceeds to step B15.

[0094] In step B15, a capacitor metal layer 15 is formed on the second insulating layer 123. The capacitor metal layer 15 overlaps the gate 1212, which saves design space on the first substrate 10, allows for more structural designs on the first substrate 10, and reduces the impact of the capacitor metal layer 15 on light extraction. The process then proceeds to step B16.

[0095] In step B16, an interlayer dielectric layer 124 is formed on the second insulating layer 123. The interlayer dielectric layer 124 covers the capacitor metal layer 15. Then, the process proceeds to step B17.

[0096] In step B17, a source / drain metal layer 1213 is formed on the interlayer dielectric layer 124. The source / drain metal layer 1213 includes a source electrode 1213a and a drain electrode 1213b. The semiconductor layer 1211, the gate electrode 1212, the source electrode 1213a, and the drain electrode 1213b form the thin film transistor 121. The process then proceeds to step B18.

[0097] In step B18, a planarization layer 126 is formed on the passivation layer 125 to form the thin film transistor array layer 12. Then, the process proceeds to step B19.

[0098] In step B19, a first pad 13 and a first trace 14 are formed on the planar layer 126. The first pad 13 is connected to the thin film transistor 121 via the first trace 14. Then, the process proceeds to step B2.

[0099] See also Figure 7 In step B2, the step of providing at least two second substrates 20 includes:

[0100] In step B21, a temporary substrate 201 is provided. A second pad 23 is formed on the temporary substrate 201. The second pad 23 includes a third sub-pad 231 and a fourth sub-pad 232. The process then proceeds to step B22.

[0101] In step B22, a second substrate 21 is formed on the temporary substrate 201. Second substrate 21 covers second pads 23. Second substrate 21 is a flexible substrate and may include one of polyethylene, polypropylene, polystyrene, polylactic acid, polyethylene diphthalate, polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyethersulfone, aromatic fluorotoluene containing polyarylate, polycyclic olefin, and polyimide. The process then proceeds to step B23.

[0102] In step B23, the LED device 221 is transferred to the side of the second substrate 21 facing away from the first base plate 10. The first pad 13 is electrically connected to the LED device 221 via the second trace 24. The anode of the LED device 221 is electrically connected to the third pad. The cathode of the LED device 221 is electrically connected to the fourth pad. The process then proceeds to step B24.

[0103] See also Figure 8 In step B24, the temporary substrate 201 is peeled off to expose the second pad 23. In this step, the process of peeling off the temporary substrate 201 includes laser lift-off. Then, the process proceeds to step B3.

[0104] See also Figure 2 、 Figure 4 and Figure 9 In step B3, the step of splicing the first substrate 10 and the second substrate 20 includes:

[0105] In step B31, a support plate 202 is attached to the second substrate 20 to form a second substrate 20 module. Since the second substrate 20 is in a soft state after being peeled off from the temporary substrate 201, the support plate 202 plays a supporting role. Then, the process proceeds to step B32.

[0106] See also Figure 10 , step B32, transfer the second substrate 20 module to the first substrate 10, and bind it to the first substrate 10. There is a gap 40 between the first substrate 10 and the second substrate 20. The pixel unit 22 and the thin film transistor 121 are arranged in an overlapping manner. In this step, the first pad 13 and the second pad 23 are bound and connected by the conductive adhesive 30, and an electrical connection is formed between the first substrate 10 and the second substrate 20. In this step, the pixel unit 22 and the thin film transistor 121 are arranged in an overlapping manner, which can reduce the influence of the pixel unit 22 and the thin film transistor 121 on the light output effect. Then proceed to step B33.

[0107] See also Figure 11 , step B33, remove the support plate 202. Then proceed to step B34.

[0108] Step B34: Fill the gap 40 with bonding glue 50 .

[0109] This completes the method for preparing the transparent display panel 100 according to the embodiment of the present application.

[0110] The above is a detailed introduction to a transparent display panel and a preparation method provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A transparent display panel, characterized in that: include: a first substrate; The first substrate further includes a first substrate, a thin film transistor array layer and a first pad; the thin film transistor array layer is provided on the first substrate, the first pad is provided on the thin film transistor array layer, and the thin film transistor array layer includes thin film transistors; At least two second substrates, at least two second substrates are spliced ​​on the first substrate; the second substrate includes a second substrate, a pixel unit, and a second pad; the pixel unit is arranged on a side of the second substrate away from the first substrate; the second pad is arranged on a side of the second substrate close to the first substrate; the pixel unit includes at least one light-emitting diode device, and the at least one light-emitting diode device is electrically connected to the second pad; the first pad is bound and connected to the second pad; The pixel unit and the thin film transistor are arranged to overlap.

2. The transparent display panel according to claim 1, wherein: The pixel units are respectively overlapped with the first pad and the second pad.

3. The transparent display panel according to claim 2, wherein: The first substrate further includes a first wiring, wherein the first wiring is connected to the thin film transistor and the first pad; The second substrate further includes a second trace, the second trace being connected to the pixel unit and the second pad; the second trace passing through the second substrate; The first routing line and the second routing line are arranged to overlap.

4. The transparent display panel according to claim 1, wherein: The distance between any two adjacent pixel units is the same.

5. The transparent display panel according to claim 1, wherein: The display panel further includes a cover plate, which is disposed on a side of at least two of the second substrates away from the first substrate.

6. The transparent display panel according to claim 1, wherein: The thin film transistor array layer includes: a semiconductor layer, a first insulating layer, a gate, a second insulating layer, a capacitor metal layer, an interlayer dielectric layer, a source-drain metal layer, a passivation layer and a planarization layer; the semiconductor layer is arranged on the first substrate; the first insulating layer is arranged on the first substrate and covers the semiconductor layer; the gate is arranged on the first insulating layer; the second insulating layer is arranged on the first insulating layer and covers the gate; a capacitor metal layer, the capacitor metal layer is arranged on the second insulating layer; a capacitor is formed between the gate and the capacitor metal layer; the interlayer dielectric layer is arranged on the second insulating layer and covers the capacitor metal layer; the source-drain metal layer is arranged on the interlayer dielectric layer; the source-drain metal layer includes a source and a drain; the source and the drain are electrically connected to the semiconductor layer; the passivation layer is arranged on the interlayer dielectric layer and covers the source-drain metal layer; the planarization layer is arranged on the passivation layer.

7. The transparent display panel according to claim 6, wherein: The first pad includes a first sub-pad and a second sub-pad; the first pad is disposed on the planar layer; and the first sub-pad is electrically connected to the source.

8. The transparent display panel according to claim 7, wherein: The second pad includes a third sub-pad and a fourth sub-pad; the third sub-pad is electrically connected to the first sub-pad; the fourth sub-pad is electrically connected to the second sub-pad; the anode of the light-emitting diode device is electrically connected to the third sub-pad; and the cathode of the light-emitting diode device is electrically connected to the fourth sub-pad.

9. The transparent display panel according to claim 1, wherein: The display panel includes a display area and a frame area, and the frame area is located on at least one side of the display area; the second substrate is arranged in an area of ​​the first substrate corresponding to the display area; the first substrate also includes a gate drive circuit, which is arranged corresponding to the frame area and is located on both sides of the display area.

10. A method for preparing a transparent display panel, characterized in that: The following steps are involved: A first substrate is provided; the first substrate further comprises a first underlayer, a thin film transistor array layer and a first pad; the thin film transistor array layer is disposed on the first substrate, the first pad is disposed on the thin film transistor array layer, and the thin film transistor array layer comprises thin film transistors; Providing at least two second substrates, the second substrates including a second substrate, a pixel unit, and a second pad; the pixel unit is disposed on a side of the second substrate away from the first substrate; the second pad is disposed on a side of the second substrate close to the first substrate; the pixel unit includes at least one light-emitting diode device, and the at least one light-emitting diode device is electrically connected to the second pad; The first substrate and the second substrate are spliced ​​together; the pixel unit and the thin film transistor are arranged in an overlapping manner; and the first pad is bound and connected to the second pad.

11. The method for preparing a transparent display panel according to claim 10, wherein: The step of providing the first substrate includes: providing a first substrate; forming a semiconductor layer on the first substrate; forming a first insulating layer on the first substrate, wherein the first insulating layer covers the semiconductor layer; forming a gate on the first insulating layer; forming a second insulating layer on the first insulating layer, wherein the second insulating layer covers the gate; forming a capacitor metal layer on the second insulating layer; forming an interlayer dielectric layer on the second insulating layer, wherein the interlayer dielectric layer covers the capacitor metal layer; forming a source-drain metal layer on the interlayer dielectric layer, wherein the source-drain metal layer includes a source electrode and a drain electrode; the semiconductor layer, the gate electrode, the source electrode and the drain electrode form the thin film transistor; forming a planar layer on the passivation layer to form the thin film transistor array layer, wherein the passivation layer is disposed on the interlayer dielectric layer; The first pad and the first wiring are formed on the planar layer, and the first pad is connected to the thin film transistor through the first wiring.

12. The method for preparing a transparent display panel according to claim 11, wherein: The step of providing at least two second substrates comprises: Providing a temporary substrate; forming the second pad on the temporary substrate; the second pad includes a third sub-pad and a fourth sub-pad; forming a second substrate on the temporary substrate; the second substrate covers the second pad; The light-emitting diode device is transferred to a side of the second substrate away from the first base plate; the second pad is electrically connected to the light-emitting diode device through a second trace; the anode of the light-emitting diode device is electrically connected to the third sub-pad; and the cathode of the light-emitting diode device is electrically connected to the fourth sub-pad; The temporary substrate is peeled off to expose the second pad.

13. The method for preparing a transparent display panel according to claim 12, wherein: The step of splicing the first substrate and the second substrate includes: Laminating a support plate on the second substrate to form a second substrate module; The second substrate module is transferred to the first substrate and is bonded to the first substrate; a gap is formed between the first substrate and the second substrate; the pixel unit and the thin film transistor are overlapped; removing the support plate; Fill the gap with bonding glue.

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