Intelligent heat-detecting chip based on novel silicon carbide mosfet structure and layout structure thereof

Abstract

The application discloses an intelligent heat measuring chip based on a novel silicon carbide MOSFET structure and a layout structure thereof, and the chip comprises a source electrode, a gate electrode, a cathode, a gate oxide layer, a first N+ injection area, a first P+ injection area, a second P+ injection area, a second P-well area, a first P-well area, a second N+ injection area, an N-epitaxial area, an N+ substrate area, a drain electrode, a passivation layer, a source electrode contact, an N+ source area and a drain electrode contact. The application can integrate a PIN diode in the silicon carbide MOSFET structure, and the PIN diode can be used for monitoring the temperature of the chip in real time, so that the reliability of the device can be improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to an intelligent heat measuring chip based on a novel silicon carbide MOSFET structure and a layout structure thereof. BACKGROUND

[0002] In recent years, as a representative of the third generation of semiconductor materials, silicon carbide (SiC) has advantages such as high breakdown field strength, high saturated electron drift rate and high thermal conductivity, and has become an ideal choice for power semiconductor devices for high-voltage, high-frequency and high-temperature applications. Based on its excellent physical and electrical properties, silicon carbide materials have received extensive attention from the industry, and SiC MOSFET is a representative power device.

[0003] However, SiC MOSFET works under large current conditions, and the heat generated is significant, which will affect its reliability. The silicon carbide MOSFET devices in the prior art still cannot overcome the adverse effects of temperature changes. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides an intelligent heat measuring chip based on a novel silicon carbide MOSFET structure and a layout structure thereof. The technical problem to be solved by the application is realized through the following technical scheme:

[0005] The application discloses an intelligent heat measuring chip based on a novel silicon carbide MOSFET structure, which comprises a source electrode (1), a gate electrode (2), a cathode electrode (3), a gate oxide layer (4), a first N+ injection area (5), a first P+ injection area (6), a second P+ injection area (7), a second P- well area (8), a first P- well area (9), a second N+ injection area (10), an N- epitaxial area (11), an N+ substrate area (12), a drain electrode (13), a passivation layer (14), a source electrode contact (15), an N+ source area (16) and a drain electrode contact (17), wherein the drain electrode contact (17) is located above the drain electrode (13), the N+ substrate area (12) is located above the drain electrode contact (17), the N- epitaxial area (11) is located above the N+ substrate area (12), the first P- well area (9) comprises a left first P- well area and a right first P- well area, the left first P- well area is embedded above the left side of the N- epitaxial area (11), the right first P- well area is embedded above the right side of the N- epitaxial area (11), the left first P- well area is sequentially embedded with the first P+ injection area (6) and the first N+ injection area (5) from left to right above the left first P- well area, the right first P- well area is sequentially embedded with the N+ source area (16) and the first P+ injection area (6) from left to right above the right first P- well area, the second P- well area (8) and the second N+ injection area (10) are located in the middle of the left first P- well area and the right first P- well area and are sequentially embedded above the N- epitaxial area (11) from left to right, the second P+ injection area (7) is embedded above the second P- well area (8), the gate oxide layer (4) is located above the second P- well area (8), the first P- well area (9) and the second N+ injection area (10), the source electrode contact (15) is located on both sides of the gate oxide layer (4), the passivation layer (14) is located above the gate oxide layer (4), the source electrode (1) comprises a first source level, a second source level and a third source level, the source electrode (1) structure comprises a vertical part and a horizontal part, wherein the width of the horizontal part is greater than the width of the vertical part, the vertical parts of the first source level and the second source level are respectively embedded on both sides of the passivation layer (14), the horizontal parts of the first source level and the second source level are located above the passivation layer (14), and the vertical parts of the first source level and the second source level are respectively located above the source electrode contact (15), the vertical parts of the cathode electrode (3) and the third source level are sequentially embedded in the gate oxide layer (4) and the passivation layer (14) from left to right, the cathode electrode (3) is located above the second P- well area (8), the third source level is located above the second N+ injection area (10), and the cathode electrode (3) and the third source level are located between the first source level and the second source level, the gate electrode (2) comprises a first gate electrode and a second gate electrode, the first gate electrode is located above the gate oxide layer (4), is embedded below the passivation layer (14) and is located between the first source level and the cathode electrode (3).The second gate is located above the gate oxide layer (4), embedded below the passivation layer (14), and between the second source level and the third source level; the source electrode (1), the cathode electrode (3), the second P+ injection area (7), the second P- well area (8), the second N+ injection area (10) and the N- epitaxial area (11) constitute a PIN diode cell; the source electrode (1), the gate electrode (2), the gate oxide layer (4), the first N+ injection area (5), the first P+ injection area (6), the first P- well area (9), the N- epitaxial area (11), the N+ substrate area (12), the drain electrode (13) and the N+ source area (16) constitute a MOSFET cell area.

[0006] In an embodiment of the present application, the interface of the source electrode (1), the first P+ injection area (6), the first N+ injection area (5) and the second N+ injection area (10) is an ohmic contact.

[0007] In an embodiment of the present application, the interface of the cathode electrode (3) and the second P+ injection area (7) is an ohmic contact.

[0008] The present application has the following beneficial effects:

[0009] The present application can integrate a PIN diode in a silicon carbide MOSFET structure, and can improve the reliability of the device by monitoring the temperature of the chip in real time through the PIN diode.

[0010] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a schematic diagram of an intelligent heat measuring chip structure based on a new type of silicon carbide MOSFET structure according to an embodiment of the present application;

[0012] Figure 2 is a layout structure schematic diagram of an intelligent heat measuring chip based on a new type of silicon carbide MOSFET structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0013] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0014] Embodiment One

[0015] Please refer to Figure 1 , Figure 1The application provides a smart heat measuring chip structure based on a novel silicon carbide MOSFET structure.

[0016] The drain contact (17) is located above the drain (13).

[0017] The N+ substrate region (12) is located above the drain contact (17).

[0018] The N- epitaxial region (11) is located above the N+ substrate region (12).

[0019] The first P- well region (9) comprises a left first P- well region and a right first P- well region.

[0020] The left first P- well region is embedded above the left side of the N- epitaxial region (11).

[0021] The right first P- well region is embedded above the right side of the N- epitaxial region (11).

[0022] The left first P- well region is embedded above the left side of the N- epitaxial region (11).

[0023] The right first P- well region is embedded above the right side of the N- epitaxial region (11).

[0024] The second P- well region (8) and the second N+ injection region (10) are located in the middle of the left first P- well region and the right first P- well region and are embedded above the N- epitaxial region (11) from left to right.

[0025] The second P+ injection region (7) is embedded above the second P- well region (8).

[0026] The gate oxide layer (4) is located above the second P- well region (8), the first P- well region (9) and the second N+ injection region (10).

[0027] The source contact (15) is located on both sides of the gate oxide layer (4).

[0028] The passivation layer (14) is located above the gate oxide layer (4).

[0029] The source electrode (1) comprises a first source level, a second source level and a third source level.

[0030] The source level (1) structure comprises a vertical part and a horizontal part, wherein the width of the horizontal part is greater than the width of the vertical part.

[0031] The vertical parts of the first source level and the second source level are embedded on both sides of the passivation layer (14) respectively, and the horizontal parts are above the passivation layer (14); and the vertical parts of the first source level and the second source level are above the source contact (15) respectively.

[0032] The vertical parts of the cathode (3) and the third source level are embedded in the gate oxide layer (4) and the passivation layer (14) from left to right in sequence.

[0033] The cathode (3) is above the second P-well region (8), and the third source level is above the second N+ implant region (10); and the cathode (3) and the third source level are between the first source level and the second source level.

[0034] The gate electrode (2) comprises a first gate electrode and a second gate electrode.

[0035] The first gate electrode is above the gate oxide layer (4), embedded below the passivation layer (14), and between the first source level and the cathode (3).

[0036] The second gate electrode is above the gate oxide layer (4), embedded below the passivation layer (14), and between the second source level and the third source level.

[0037] Optionally, the source electrode (1), the cathode (3), the second P+ implant region (7), the second P-well region (8), the second N+ implant region (10) and the N- epitaxial region (11) constitute a PIN diode cell.

[0038] It should be noted that the PIN diode cells of the present application are uniformly distributed in the middle of the source electrode, strictly monitor the source electrode temperature, and are connected to the cathode, and the PIN diode cell spacing is the same as the MOSFET cell spacing.

[0039] Optionally, the source electrode (1), the gate electrode (2), the gate oxide layer (4), the first N+ implant region (5), the first P+ implant region (6), the first P-well region (9), the N- epitaxial region (11), the N+ substrate region (12), the drain electrode (13) and the N+ source region (16) constitute a MOSFET cell region.

[0040] Optionally, the interface between the source electrode (1), the first P+ implant region (6), the first N+ implant region (5) and the second N+ implant region (10) is an ohmic contact.

[0041] Optionally, the interface between the cathode (3) and the second P+ implant region (7) is an ohmic contact.

[0042] Optionally, the first P- well region (9) has a depth of 1 μm-1.2 μm and a width of 6.1 μm-6.5 μm, and the first P- well region (9) is uniformly doped with a doping concentration of 5x10 16 cm -3 .

[0043] Optionally, the second P- well region (8) has a depth of 1 μm-1.2 μm and a width of 1.8 μm-2.2 μm, and the second P- well region (8) is uniformly doped with a doping concentration of 5x10 16 cm -3 .

[0044] Optionally, the first P- well region (9) and the second P- well region (8) have the same depth.

[0045] Optionally, the first N+ implant region (5) has a depth of 0.2 μm-0.4 μm, a width of 1.7 μm-2 μm, and a doping concentration of 1x10 19 -1x10 20 cm -3 .

[0046] Optionally, the second N+ implant region (10) has a depth of 0.2 μm-0.4 μm, a width of 1.7 μm-2 μm, and a doping concentration of 1x10 19 -1x10 20 cm -3 .

[0047] Optionally, the first P+ implant region (6) has a depth of 0.2 μm-0.4 μm, a doping concentration of 1x10 19 -1x10 20 cm -3 , and a width of 1.4 μm-1.6 μm.

[0048] Optionally, the second P+ implant region (7) has a depth of 0.2 μm-0.4 μm, a doping concentration of 1x10 19 -1x10 20 cm -3 , and a width of 1.4 μm-1.6 μm.

[0049] Optionally, the first P+ implant region (6) and the second P+ implant region (7) have the same depth and doping concentration.

[0050] Optionally, the interval between the second P-well region (8) and the first P-well region (9) is less than or equal to 4 μm.

[0051] It should be noted that, through experiments, it is verified that the interval between the first P-well region and the second P-well region is preferably 1.2 μm.

[0052] Optionally, the interval between the second P-well region (8) and the second N+ injection region (10) is 0.8 μm; and the interval between the second N+ injection region (10) and the first P-well region (9) is 0.5 μm.

[0053] Referring to Figure 1 , the interface between the cathode and the second P+ injection region is ohmic contact, which can make the applied voltage of the cathode fall on the second P-well region; similarly, the interface between the source and the second N+ injection region is ohmic contact, which can make the voltage of the source fall on the N-epitaxial layer. At this time, the second P-well region and the N-epitaxial layer constitute a PIN diode integrated in the intelligent heat measuring chip of the silicon carbide MOSFET structure. Further, according to the forward conduction characteristic of the PIN diode, it is known that, under the same forward voltage, the forward conduction current density of high temperature shows a decreasing trend. Since under the condition of low doping, the increase of temperature will intensify the vibration of crystal lattice atoms, increase the scattering probability of majority carrier electrons, and reduce the mobility and conductivity, thereby reducing the current. That is, the present application can monitor the temperature according to the current change of the PIN diode.

[0054] In summary, the present application can integrate the PIN diode and the silicon carbide MOSFET in the chip, utilize the influence of temperature on the forward I-V characteristic of the diode, and through the current flowing through the PIN diode, the chip temperature can be effectively monitored in real time, so that the temperature of the internal cell of the silicon carbide MOSFET device can be calculated by the technical personnel, and timely control and protection can be performed, thereby improving the reliability of the device.

[0055] Embodiment Two

[0056] Referring to Figure 2 , Figure 2 is a layout structure schematic diagram of an intelligent heat measuring chip based on a new type of silicon carbide MOSFET structure provided by the embodiment of the present application, and the layout structure comprises:

[0057] a MOSFET cell region (18), a gate electrode region (19), a cell of a PIN diode (20), a source electrode region (21), and a cathode region (22).

[0058] Referring to Figure 2The PIN diode cells are evenly distributed in the middle of the source, and the interval of the cells in the X, Y and Z directions is consistent with the interval of the MOSFET cells, so that the local breakdown of the device is effectively prevented, and the breakdown voltage of the device is improved. Meanwhile, the uniform distribution of the PIN diode can effectively monitor the temperature of the source, prevent the device from being damaged due to the excessively high temperature, and improve the reliability of the device.

[0059] Embodiment three

[0060] The embodiment three of the present application provides a preparation method of an intelligent heat measuring chip based on a novel silicon carbide MOSFET structure, and the method comprises the following steps:

[0061] Step a: forming an N- epitaxial region on an N+ substrate region by epitaxial growth.

[0062] Step b: sequentially performing initial oxidation, photolithography and field region boron ion implantation on the N- epitaxial layer to form a first P well region and a second P well region, i.e. well region formation.

[0063] Step c: performing Si3N4 deposition and photolithography to form an active region; performing field oxidation, photolithography and again field oxidation to perform gate oxidation; and opening voltage adjustment to grow a gate oxide layer.

[0064] Step d: performing polysilicon deposition, etching a gate of the MOSFET, phosphorus ion implantation and promotion by using photoresist as a mask to form a first N+ implantation region and a second N+ implantation region; and performing boron ion implantation to form a first P+ implantation region and a second P+ implantation region.

[0065] Step e: performing phosphorus silicon glass deposition, photolithography, hole etching, phosphorus silicon glass deposition and reflow.

[0066] Step f: sequentially performing aluminum evaporation, photolithography, aluminum etching, photolithography, back metalization and passivation hole etching to obtain the intelligent heat measuring chip based on the novel silicon carbide MOSFET structure.

[0067] In conclusion, the present application can integrate PIN diodes and silicon carbide MOSFETs in a chip, utilize the influence of the temperature of the diode on the forward I-V characteristic, and effectively monitor the temperature of the chip in real time through the current flowing through the PIN diode, so that the temperature of the internal cells of the silicon carbide MOSFET device can be calculated by the technical personnel for timely control and protection, and the reliability of the device can be improved.

[0068] In the description of the present application, it is to be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like are based on the orientations or positional relationships shown in the drawings, and are merely intended to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated thereby must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0069] In addition, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated thereby. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0070] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of a first feature to a second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of a first feature to a second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. "Under", "below" and "underneath" of a first feature to a second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0071] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0072] Although the application has been described in connection with specific embodiments thereof, it will be understood that it is capable of further modifications and this application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended to cover and embrace all adaptations or modifications of the application. The terminology used herein for the purpose of describing particular embodiments is not intended to be limiting of the application. This application is intended to cover all such modifications and alternatives within the scope of the application including combinations of aspects of the application with other items not described.

[0073] The above description is further detailed in connection with specific preferred embodiments of the application, and it is not to be construed that the specific implementation of the application is limited to these descriptions. For those skilled in the art, without departing from the concept of the application, a number of simple deductions or substitutions can be made, and all of them shall be regarded as falling within the protection scope of the application.

Claims

1. An intelligent heat-detecting chip based on a novel silicon carbide MOSFET structure, characterized in that, The chip comprises: a source electrode (1), a gate electrode (2), a cathode electrode (3), a gate oxide layer (4), a first N+ injection region (5), a first P+ injection region (6), a second P+ injection region (7), a second P- well region (8), a first P- well region (9), a second N+ injection region (10), an N- epitaxial region (11), an N+ substrate region (12), a drain electrode (13), a passivation layer (14), a source electrode contact (15), an N+ source region (16), and a drain electrode contact (17); wherein, the drain electrode contact (17) is located above the drain electrode (13); the N+ substrate region (12) is located above the drain electrode contact (17); the N- epitaxial region (11) is located above the N+ substrate region (12); the first P- well region (9) comprises a left first P- well region and a right first P- well region; the left first P- well region is embedded above the left side of the N- epitaxial region (11); the right first P- well region is embedded above the right side of the N- epitaxial region (11); a first P+ injection region (6) and a first N+ injection region (5) are sequentially embedded above the left first P- well region from left to right; an N+ source region (16) and a first P+ injection region (6) are sequentially embedded above the right first P- well region from left to right; the second P- well region (8) and the second N+ injection region (10) are located in the middle of the left first P- well region and the right first P- well region, and are sequentially embedded above the N- epitaxial region (11) from left to right; the second P+ injection region (7) is embedded above the second P- well region (8); the gate oxide layer (4) is located above the second P- well region (8), the first P- well region (9), and the second N+ injection region (10); the source electrode contact (15) is located on both sides of the gate oxide layer (4); the passivation layer (14) is located above the gate oxide layer (4); the source electrode (1) comprises a first source electrode, a second source electrode, and a third source electrode; the source electrode (1) structure comprises a vertical part and a horizontal part, wherein the width of the horizontal part is greater than the width of the vertical part; the vertical parts of the first source electrode and the second source electrode are respectively embedded on both sides of the passivation layer (14), and the horizontal parts thereof are located above the passivation layer (14); and the vertical parts of the first source electrode and the second source electrode are respectively located above the source electrode contact (15); the vertical parts of the cathode electrode (3) and the third source electrode are sequentially embedded in the gate oxide layer (4) and the passivation layer (14) from left to right; the cathode electrode (3) is located above the second P- well region (8), and the third source electrode is located above the second N+ injection region (10); and the cathode electrode (3) and the third source electrode are located between the first source electrode and the second source electrode; the gate electrode (2) comprises a first gate electrode and a second gate electrode; the first gate electrode is located above the gate oxide layer (4), is embedded below the passivation layer (14), and is located between the first source electrode and the cathode electrode (3); The second gate is located above the gate oxide layer (4), embedded below the passivation layer (14), and between the second source and the third source; The source (1), the cathode (3), the second P+ implantation region (7), the second P- well region (8), the second N+ implantation region (10) and the N- epitaxial region (11) constitute a PIN diode cell; The source (1), the gate (2), the gate oxide layer (4), the first N+ implantation region (5), the first P+ implantation region (6), the first P- well region (9), the N- epitaxial region (11), the N+ substrate region (12), the drain (13) and the N+ source region (16) constitute a MOSFET cell region.

2. The chip of claim 1, wherein The interface of the source (1), the first P+ implantation region (6), the first N+ implantation region (5) and the second N+ implantation region (10) is ohmic contact.

3. The chip of claim 1, wherein The interface of the cathode (3) and the second P+ implantation region (7) is ohmic contact.

4. The chip of claim 1, wherein The depth of the first P-well region (9) is 1-1.2 μm, the width is 6.1-6.5 μm, the first P-well region (9) is uniformly doped, the doping concentration is 5x1016-5x1017 cm-3. 16 -3 ;​ The depth of the second P-well region (8) is 1-1.2 μm, the width is 1.8-2.2 μm, the second P-well region (8) is uniformly doped, the doping concentration is 5x1018-1x1019 cm-3. 16 cm -3 ; The depth of the first P- well region (9) and the second P- well region (8) is consistent.

5. The chip of claim 1, wherein, The first N+ implantation region (5) has a depth of 0.2-0.4 μm, a width of 1.7-2 μm, and a doping concentration of 1 x 1019-1 x 1020cm-3. 19 -1 x 1018cm-3 20 cm -3 ; The second N+ implantation region (10) has a depth of 0.2-0.4 μm, a width of 1.7-2 μm, and a doping concentration of 1 x 1019-1 x 1020cm-3. 19 -1 x 1019 20 cm -3 .

6. The chip of claim 1, wherein The first P+ injection region (6) has a depth of 0.2-0.4 μm, a doping concentration of 1x1018-1x1019 cm-3, and a width of 1.4-1.6 μm. 19 -1x1018 20 cm -3 -1x1019 cm-3. -1x1018 The second P+ injection region (7) has a depth of 0.2-0.4 μm, a doping concentration of 1x1019 cm-3, and a width of 1.4-1.6 μm. 19 -1x1019 cm-3 20 cm -3 -1x1019 cm-3 The depth and doping concentration of the first P+ implantation region (6) and the second P+ implantation region (7) are consistent.

7. The chip of claim 1, wherein The spacing between the second P- well region (8) and the first P- well region (9) is less than or equal to 4μm.

8. The chip of claim 1, wherein, The spacing between the second P- well region (8) and the second N+ implantation region (10) is 0.8μm; The spacing between the second N+ implantation region (10) and the first P- well region (9) is 0.5μm.

9. A layout structure of an intelligent heat-detecting chip based on a novel silicon carbide MOSFET structure according to claim 1, characterized in that, The layout structure comprises: The MOSFET cell region (18), the gate electrode region (19), the PIN diode cell (20), the source electrode region (21) and the cathode region (22).

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