A GaN FET half-bridge crosstalk suppression circuit

Abstract

The present invention belongs to the field of electronic circuit technology, and specifically relates to a GaN FET half-bridge crosstalk suppression circuit. The present invention provides a GaN half-bridge crosstalk suppression circuit that utilizes active devices to achieve crosstalk suppression and prevents GaN bridge arm crosstalk from causing GaN bridge arm break-through or device breakdown. The suppression effect is significant, and the correct switching on and off of GaN devices can be ensured.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic circuits, and in particular relates to a GaN FET half-bridge crosstalk suppression circuit. Background Art

[0002] Power electronic converters are currently moving towards higher power density. To improve converter power density, switching frequency should be increased to reduce the size of passive components. Wide-bandgap devices, such as gallium nitride (GaN) transistors, are well-suited for this application. Compared to Si devices like Si MOSFETs, GaN transistors offer lower gate charge Qg, zero gate-drain recovery charge Qrr, lower on-state resistance Rds(on), lower threshold voltage, and lower minimum allowable gate-source voltage. This allows for faster switching and reduced switching and conduction losses. They are expected to replace traditional Si MOSFETs and become the solution for future high-performance power systems. The advantages of GaN devices are particularly evident in high-voltage systems above 400V, enabling higher switching frequencies and power density, significantly improving system conversion efficiency, and are particularly well-suited to the trend toward miniaturization of power modules.

[0003] However, due to the presence of various parasitic parameters in GaN transistor circuits, high-frequency crosstalk may be generated in the gate voltage, collector-emitter voltage, or collector current when GaN switches at a specific operating point. This will cause rapid voltage changes at the switching node, and undesirable positive voltage spikes or negative voltage spikes will appear on the gate-source voltage of its auxiliary switch. When the GaN transistor switches, the positive voltage spike may exceed the threshold voltage Vth, resulting in false turn-on. When a negative voltage spike occurs, the superposition of the negative voltage spike and the negative voltage may exceed the minimum allowable gate-source voltage of the GaN transistor, resulting in gate breakdown. At the same time, these crosstalk spikes will cause interference to other electronic circuits, including their gate drivers, which may lead to incorrect GaN control. In particular, bridge structure applications are severely affected by crosstalk problems.

[0004] To resolve the above contradictions, many crosstalk suppression drive circuits have been proposed. A complete crosstalk suppression drive circuit includes a gate driver and a gate drive power supply (GDPS). Common methods include the following:

[0005] 1. Reduce the switching speed of the switches that cause crosstalk. Increasing the on / off gate resistors in parallel with the external gate-source capacitors can reduce the switching speed. However, this will increase switching losses.

[0006] 2. Enhance the noise immunity of switches subject to crosstalk. Connecting an external gate-source capacitor in parallel can reduce the magnitude of voltage spikes, but this also introduces additional switching losses. Adding auxiliary circuitry or changing the gate resistor can provide a low-impedance path, thereby reducing both positive and negative voltage spikes.

[0007] 3. Given that the GaN switching process requires gates with varying drive capabilities, a separate charge and discharge path technology is proposed. For the Buck half-bridge circuit topology, bootstrap technology is used to power the high-side drive circuit, and a high-speed, low-power, and highly reliable level shifter circuit is designed to achieve this level shift. Summary of the Invention

[0008] The purpose of the present invention is to propose a new GaN crosstalk suppression circuit based on the crosstalk characteristics of GaN devices, which uses active devices to achieve crosstalk elimination and prevent the breakdown of switching tubes caused by bridge arm crosstalk.

[0009] The technical solution of the present invention is:

[0010] A GaN FET half-bridge crosstalk suppression circuit is connected between the gate and source of a GaN device of a GaN synchronous buck circuit, comprising a first GaN switch tube, a second GaN switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a capacitor, a first inductor, a second inductor, a first triode, a second triode, a third triode, a fourth triode, a first diode, a second diode, a third diode, a fourth diode, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first voltage source, a second voltage source, a third voltage source, and a fourth voltage source; wherein the drain of the first GaN switch tube is connected to the positive electrode of the bus voltage through the first inductor, and the gate thereof is connected to the positive electrode of the first switch tube through the first resistor, the second resistor, and the second diode in sequence. The source and the drain of the second switching tube; the fifth resistor is connected in parallel between the third diode and the first resistor; the drain of the first switching tube is connected to the positive end of the first voltage source, and the gate thereof is connected to the first control signal; the source of the second switching tube is connected to the negative end of the second voltage source, and the gate thereof is connected to the second control signal; the negative end of the first voltage source and the positive end of the second voltage source are connected to the source of the first GaN switching tube, the drain of the second GaN switching tube, and one end of the second inductor; the collector of the first transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the source of the first switching tube, the source of the second switching tube, one end of the third resistor, one end of the fourth resistor, and the emitter of the second transistor; the other end of the third resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the connection point of the first resistor and the second resistor, and the emitter of the second transistor; the base of the second transistor is connected to the other end of the fourth resistor;

[0011] The gate of the second GaN switching tube is connected to the source of the third switching tube and the drain of the fourth switching tube through the sixth resistor, the seventh resistor and the fourth diode in sequence; the tenth resistor is connected in parallel across the third diode and the fifth resistor; the drain of the third switching tube is connected to the positive terminal of the third voltage source, and its gate is connected to the third control signal; the source of the fourth switching tube is connected to the negative terminal of the fourth voltage source, and its gate is connected to the fourth control signal; the negative terminal of the third voltage source and the positive terminal of the fourth voltage source are connected to the source of the second GaN switching tube and the negative terminal of the bus voltage; the collector of the third transistor is connected to the cathode of the second diode, the anode of the second diode is connected to the source of the third switching tube, the source of the fourth switching tube, one end of the eighth resistor, one end of the ninth resistor, and the emitter of the fourth transistor; the other end of the eighth resistor is connected to the base of the third transistor, the emitter of the third transistor is connected to the connecting point of the sixth resistor and the seventh resistor, and the emitter of the fourth transistor; the base of the fourth transistor is connected to the other end of the ninth resistor;

[0012] The other end of the second inductor is connected to a parallel circuit consisting of a capacitor and an eleventh resistor to form an output end connected to the gate of the GaN device.

[0013] The working cycle of the GaN FET half-bridge crosstalk suppression circuit is divided into four stages, such as Figure 2 As shown, they are:

[0014] Phase 1: The first control signal and the fourth control signal are at high level, and the second control signal and the third control signal are at low level;

[0015] Second stage: the first control signal and the third control signal are at low level, and the second control signal and the fourth control signal are at high level;

[0016] The third stage: the first control signal and the fourth control signal are at a low level, and the second control signal and the third control signal are at a high level;

[0017] Phase 4: the second control signal and the third control signal are at a low level, and the first control signal and the fourth control signal are at a high level.

[0018] The beneficial effect of the present invention is that the present invention provides a GaN half-bridge crosstalk suppression circuit, which uses active devices to achieve crosstalk suppression and prevents the GaN bridge arm from being directly connected or the device from being broken down due to the bridge arm crosstalk. The suppression effect is obvious and can well ensure the correct opening and closing of the GaN device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the structure of the GaN half-bridge crosstalk suppression circuit in an embodiment of the present invention;

[0020] Figure 2 This is the on-off waveform of the auxiliary switch;

[0021] Figure 3 This is the working flow diagram of the auxiliary switch;

[0022] Figure 4 shows the equivalent circuit diagrams of each stage of turn-on and turn-off, where (a) is the equivalent circuit diagram before time t0, (b) is the equivalent circuit diagram from t0 to t1, (c) is the equivalent circuit diagram from t1 to t2, and (d) is the equivalent circuit diagram from t2 to t3.

[0023] Figure 5 is the V of the lower tube Q2 without the crosstalk suppression circuit gs Waveform graph;

[0024] Figure 6 The V of the lower tube Q2 with the crosstalk suppression circuit added gs Waveform graph. DETAILED DESCRIPTION

[0025] The present invention is described in detail below with reference to the accompanying drawings and simulation examples;

[0026] This embodiment provides a GaN half-bridge crosstalk suppression circuit, which is used in a half-bridge circuit, for example Figure 1 As shown, it includes: an active auxiliary drive circuit and a GaN synchronous BUCK test circuit. The active auxiliary drive circuit is used to clamp the gate-source voltage of the GaN FET at the turn-off voltage during the crosstalk generation process, thereby reducing the gate-source voltage spike of the GaN FET during the switching process. The GaN synchronous BUCK test circuit includes an upper and lower half-bridge composed of two GaNs and various parasitic parameters of the circuit. Since the synchronous BUCK circuit has a simple structure and crosstalk also exists between the two switching tubes, this circuit is used to analyze the working principle of the crosstalk suppression circuit. The advantage of the proposed crosstalk suppression circuit is that the crosstalk suppression effect is obvious.

[0027] The GaN synchronous BUCK test circuit includes: upper and lower GaN devices Q1, Q2, and a DC bus voltage V dc , GaN's gate-source parasitic capacitance C gs , gate-drain parasitic capacitance C gd , drain-source parasitic capacitance C ds , GaN gate inductance L g ( Figure 1 (not shown), source inductance L s ( Figure 1 (not shown), leakage inductance L d ( Figure 1 (not shown), is the gate input resistance R g , power circuit parasitic inductance L1, C j is the junction capacitance of the diode ( Figure 1 Not shown), load inductor L0, output capacitor and output resistor Co and R o .

[0028] The active auxiliary driving circuit includes: an auxiliary NPN transistor T 1H , auxiliary PNP transistor T 2H , clamping diode D1, current limiting resistors R1, R2, drive resistor R H (correspond Figure 1 Medium R hon and R hoff ) and auxiliary switch S 1H and S 2H Q1 turns on and off the voltage control source V 1H and V 2H Wherein, the auxiliary NPN or PNP transistor T 1H and T 2H No external control signal is required, and the transistor can be turned on by simply providing a forward bias voltage to the emitter junction of the transistor. 1H The base is connected to the current limiting resistor R1, and the emitter is connected to the gate input resistor R of the GaN g The collector is connected to the clamping diode D1. 2H The base is connected to the current limiting resistor R2, and the emitter is connected to the gate input resistor R of the GaN g Connect the collector to the off voltage source V 2H The current limiting resistors R1 and R2 are connected to the driving resistor R H The auxiliary switch S 1H and S 2H It consists of an active control power supply and a MOSFET switching device.

[0029] The crosstalk suppression circuit works according to the following principles: Figure 3 :When the crosstalk is turned off, the driving resistor R H The voltage on T 2H The emitter junction is forward biased, T 2H Turn on and T 1H At the same time, Q1 and Q2 commutate, and the drain-source voltage V ds2 Drop, Q2's parasitic capacitance C gd2 Discharge, discharge current flows through C gd2 Flowing through the parasitic capacitance C gs2 and R L , R L The voltage of T 1L The emitter junction is forward biased, T 2L The emitter junction is reverse biased, T 1L Turn on while T 2L- is always in the cut-off state. At the same time, diode D2 is subjected to the forward voltage and turns on, thus clamping the gate-source voltage of Q2 at V 2L .

[0030] The working principle of the GaN crosstalk suppression circuit of the present invention is explained below in conjunction with the equivalent working circuit of the GaN half-bridge crosstalk circuit shown in FIG4 , specifically as follows:

[0031] (1) t o Before time t, the equivalent circuit of the circuit is shown in Figure 4 (a). Q1 is in the on state, Q2 is in the off state, and the load current flows through the channel of Q1. There is no current flowing in the drive circuit, so the voltages on RH and RL in the drive circuit are zero, T 1H 、T 2H 、T 1L and T 2L The emitter junction voltage is zero, all four transistors are in the cut-off state, and the auxiliary unit does not work.

[0032] (2) t0-t1 stage: The equivalent circuit of the circuit is shown in Figure 4 (b). During the shutdown process of Q1, R H Voltage on

[0033] Make T 2H The emitter junction is forward biased, T 2H Turn on and T 1H At the same time, Q1 and Q2 commutate, and the drain-source voltage V ds2 Drop, Q2's parasitic capacitance C gd2 Discharge, discharge current flows through C gd2 Flowing through the parasitic capacitance C gs2 and R L , R L The voltage of T 1L The emitter junction is forward biased, T 2L The emitter junction is reverse biased, T 1L Turn on while T 2L - is always in the cut-off state. At the same time, diode D2 is subjected to the forward voltage and turns on, thus clamping the gate-source voltage of Q2 at V 2L .

[0034] (3) t1-t2 stage: The equivalent circuit diagram of the circuit is shown in Figure 4 (c). At t1, Q2 begins to conduct, the anti-parallel diode of Q2 and the channel of Q2 commutate, driving the resistor R L (correspond Figure 1 Medium R lon and R loff ) makes the voltage across T 1L The reflection junction is forward biased, T 2L The emitter junction is reverse biased. Therefore, T 1Lconduction, T 2L However, since D2 is in the cut-off state due to the reverse voltage, D2 and T 1L The branch circuit is in an open circuit state. The auxiliary unit does not function during this process.

[0035] (4) t2-t3 stage: The equivalent circuit diagram of the circuit is shown in Figure 4 (d). At t2, Q2 starts to turn off, driving the resistor R L The voltage on T 2L The emitter junction is forward biased, T 2L Q1 turns on, and Q2 turns off quickly. After that, Q1 starts to turn on. During the conduction of Q1, the parasitic diodes of Q1 and Q2 commutate. When the drain-source voltage V ds2 When the parasitic capacitance C gd2 Charging, the charging current flows through C gd2 and R L , R L The voltage on T 2L The emitter junction is forward biased, T 2L turns on, clamping the gate-source voltage of Q2 to V 2L .

[0036] In order to compare the crosstalk suppression effect of the present invention in the half-bridge circuit, this embodiment is based on Cadence simulation software. The GaN device model adopts the EPC2051 model provided by EPC. The Schottky diode D2 in the auxiliary drive circuit adopts the 1N5819HW-7-F model. The auxiliary PNP transistor S 1H The ZXTP25100BFHTA model is used. The MOSFET device in the auxiliary switch is the RQ5E040AJ model. Comparing and analyzing with a traditional circuit without crosstalk suppression, the simulation model of this embodiment has a load inductor L0 of 220uH, a load resistor R0 of 20Ω, a filter capacitor C0 of 330uF, and a DC input voltage of 100V. All parasitic parameters of the GaN devices in the circuit are based on the datasheet data. The following bridge arm is an example: the high-level input V 1H 5V, low level input V 2H is 0V, driving resistor R H 、R L The resistors R1, R2, R3 and R4 are 120Ω. Figure 5 、 Figure 6As shown in the waveforms, without the crosstalk suppression circuit, the lower arm GaN gate-source positive crosstalk voltage spike can reach 2.6V and the negative crosstalk voltage spike can reach -6V due to crosstalk, with large oscillations both during turn-on and turn-off. When the crosstalk suppression circuit of the present invention is applied, the positive and negative crosstalk between the GaN gate and source almost completely disappears, the oscillations decrease, and the electromagnetic interference phenomenon is alleviated. However, the disadvantage is that a certain switching speed is sacrificed. However, according to simulation, the switching speed remains at the MHz level, so the impact is limited.

Claims

1. A GaN FET half-bridge crosstalk suppression circuit connected between the gate and source of a GaN device in a GaN synchronous buck circuit, characterized in that: The invention comprises a first GaN switch tube, a second GaN switch tube, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a capacitor, a first inductor, a second inductor, a first transistor, a second transistor, a third transistor, a fourth transistor, a first diode, a second diode, a third diode, a fourth diode, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a first voltage source, a second voltage source, a third voltage source and a fourth voltage source; wherein the drain of the first GaN switch tube is connected to the positive electrode of the bus voltage through the first inductor, and the gate thereof is connected to the source of the first switch tube and the drain of the second switch tube through the first resistor, the second resistor and the second diode in sequence; the fifth transistor The resistor is connected in parallel across the second diode and the second resistor; the drain of the first switching tube is connected to the positive end of the first voltage source, and the gate thereof is connected to the first control signal; the source of the second switching tube is connected to the negative end of the second voltage source, and the gate thereof is connected to the second control signal; the negative end of the first voltage source and the positive end of the second voltage source are connected to the source of the first GaN switching tube, the drain of the second GaN switching tube, and one end of the second inductor; the collector of the first transistor is connected to the cathode of the first diode, the anode of the first diode is connected to the source of the second switching tube, one end of the third resistor, one end of the fourth resistor, and the collector of the second transistor; the other end of the third resistor is connected to the base of the first transistor, the emitter of the first transistor is connected to the connection point of the first resistor and the second resistor, and the emitter of the second transistor; the base of the second transistor is connected to the other end of the fourth resistor; The gate of the second GaN switching tube is connected to the source of the third switching tube and the drain of the fourth switching tube through the sixth resistor, the seventh resistor and the fourth diode in sequence; the tenth resistor is connected in parallel across the fourth diode and the seventh resistor; the drain of the third switching tube is connected to the positive terminal of the third voltage source, and its gate is connected to the third control signal; the source of the fourth switching tube is connected to the negative terminal of the fourth voltage source, and its gate is connected to the fourth control signal; the negative terminal of the third voltage source and the positive terminal of the fourth voltage source are connected to the source of the second GaN switching tube and the negative terminal of the bus voltage; the collector of the third transistor is connected to the negative terminal of the third diode, and the anode of the third diode is connected to the source of the fourth switching tube, one end of the eighth resistor, one end of the ninth resistor, and the collector of the fourth transistor; the other end of the eighth resistor is connected to the base of the third transistor, the emitter of the third transistor is connected to the connecting point of the sixth resistor and the seventh resistor, and the emitter of the fourth transistor; the base of the fourth transistor is connected to the other end of the ninth resistor; The other end of the second inductor is connected to a parallel circuit consisting of a capacitor and an eleventh resistor to form an output end connected to the gate of the GaN device.

2. A GaN FET half-bridge crosstalk suppression circuit according to claim 1, characterized in that: The circuit's working cycle is divided into four stages: Phase 1: The first control signal and the fourth control signal are at high level, and the second control signal and the third control signal are at low level; Second stage: the first control signal and the third control signal are at low level, and the second control signal and the fourth control signal are at high level; The third stage: the first control signal and the fourth control signal are at a low level, and the second control signal and the third control signal are at a high level; Phase 4: the second control signal and the third control signal are at a low level, and the first control signal and the fourth control signal are at a high level.

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