A control circuit for bit line leakage current, sensitive amplifier and memory

Abstract

The present invention discloses a control circuit of a bit line leakage current, a sensitive amplifier and a memory, comprising a memory array composed of 8T SRAM memory cells and a four-input sensitive amplifier with a symmetrical structure, wherein two pairs of transmission tubes of the memory array are respectively connected to a main bit line pair and a sub-bit line pair; a main bit line and a sub-bit line connected to a storage node on the same side in a column of memory cells are respectively connected to an input end on both sides of the four-input sensitive amplifier, wherein: the input end of one side connected to the sub-bit line in the four-input sensitive amplifier is connected to another main bit line, and the input end of one side connected to the main bit line is connected to another sub-bit line. The circuit structure can detect and compensate for the bit line leakage current in real time without adding more control signals; when the bit line leakage current is large, the correct data can still be read out, and the performance is very stable.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a control circuit for a bit line leakage current, a sensitive amplifier and a memory. Background Art

[0002] As CMOS (Complementary Metal Oxide Semiconductor) process technology is scaled down, CMOS circuits have improved performance while reducing area. The reduction in process also reduces the power supply voltage, so it is necessary to reduce the threshold voltage of the transistor to maintain the high performance of the transistor. However, the reduction in threshold voltage will lead to an increase in subthreshold leakage current. The increased leakage current will have a serious impact on the operation of static random-access memory (SRAM), especially the read operation. The leakage current on the bit line will cause the read operation time to be extended, and even cause read data errors.

[0003] In order to alleviate or eliminate the impact caused by the bit line leakage current, the prior art proposes the following solutions:

[0004] like Figure 1 The circuit structure of the self-compared bit-line pairs in the prior art is shown in the figure. The working principle of the circuit structure of the self-compared bit-line pairs is as follows: an auxiliary bit line is added on both sides of the bit lines BL and BLB, and the bit lines and the auxiliary bit lines are connected to the four inputs of a four-input sense amplifier. Two PMOS tubes control the connection between the bit lines and the auxiliary bit lines respectively. When the voltage of the bit line decreases due to the leakage current, the voltage of the auxiliary bit line also decreases and remains the same as the bit line voltage. The voltage drop of one side of the bit line caused by the leakage current will reduce the discharge speed of the node on that side of the sense amplifier, while the voltage of the auxiliary bit line on the other side compensates for this discharge speed. This circuit structure compensates for the voltage drop of the bit line caused by the leakage current very well, but the disadvantage is that this compensation is not real-time and does not take into account the leakage current of the bit line after the word line WL is turned on, which affects the accuracy of the compensation.

[0005] like Figure 2The circuit structure of X-Calibration in the prior art is shown. The working principle of the X-Calibration circuit structure is as follows: a capacitor is connected in series to the bit line, and the bit line connection relationship is changed by an additional PMOS tube, and the drop in the bit line voltage caused by the leakage current is recorded on the capacitor, and then the voltage recorded on the capacitor is used to compensate for the change in the bit line voltage caused by the leakage current. However, the disadvantage of this circuit structure is that the charging and discharging time of the series capacitor will reduce the read operation speed, and two normally open PMOS tubes need to be connected to the bit line to generate current to ensure the stability of the voltage, which will greatly increase the reading time and power consumption. Summary of the invention

[0006] The purpose of the present invention is to provide a control circuit for a bit line leakage current, a sensitive amplifier and a memory, wherein the circuit structure can detect and compensate for the bit line leakage current in real time without adding more control signals; when the bit line leakage current is large, the correct data can still be read out, and the performance is very stable.

[0007] The objective of the present invention is achieved through the following technical solutions:

[0008] A control circuit for a bit line leakage current, a sense amplifier and a memory, the control circuit comprising a memory array consisting of 8TSRAM memory cells and a four-input sense amplifier with a symmetrical structure, wherein:

[0009] The two pairs of transmission tubes of the storage array are respectively connected to the main bit line pair and the sub bit line pair; wherein the main bit line pair includes the main bit lines BLM and BLMB; the sub bit line pair includes the sub bit lines BLN and BLNB;

[0010] A main bit line BLM and a sub bit line BLNB connected to the storage nodes on the same side in a column of memory cells are respectively connected to an input terminal on both sides of the four-input sense amplifier, wherein:

[0011] The input end of the four-input sense amplifier connected to the sub-bit line BLNB is connected to another main bit line BLMB, and the input end of the four-input sense amplifier connected to the main bit line BLM is connected to another sub-bit line BLN;

[0012] When there is leakage current on one of the main bit lines in the main bit line pair, the secondary bit line in the secondary bit line pair connected to the storage node on the same side as the main bit line also generates an equal amount of leakage current; therefore, when the four-input sensitive amplifier reads data, the voltage drop caused by the leakage current of the bit line on one side can be compensated in real time on the other side, thereby reading the correct data and realizing the control of the bit line leakage current.

[0013] It can be seen from the technical solution provided by the present invention that the above circuit structure can detect and compensate for the bit line leakage current in real time without adding more control signals; when the bit line leakage current is large, the correct data can still be read out, with very stable performance, and under different bit line leakage currents, the time for reading data changes very little, thereby improving the performance of the circuit read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0015] Figure 1 The circuit structure of the Self-compared bit-line pairs in the prior art;

[0016] Figure 2 It is the circuit structure of X-Calibration in the prior art;

[0017] Figure 3 A schematic diagram of the structure of a control circuit for a bit line leakage current, a sense amplifier and a memory according to an embodiment of the present invention;

[0018] Figure 4 Schematic diagram of the structure of the 8T SRAM storage unit according to an embodiment of the present invention;

[0019] Figure 5 Schematic diagram of the structure of a four-input sensitive amplifier according to an embodiment of the present invention;

[0020] Figure 6 A timing waveform diagram of a circuit structure provided by an embodiment of the present invention;

[0021] Figure 7 The diagram is a read time diagram of a conventional SRAM circuit (hereinafter referred to as CONV) using a conventional SA in a 55nm CMOS process and a circuit provided by an embodiment of the present invention under different bit line leakage current conditions;

[0022] Figure 8 A comparison diagram of the maximum bit line leakage current that a conventional SRAM circuit using a conventional SA under a 55nm CMOS process and a circuit provided by an embodiment of the present invention can withstand under different process angles;

[0023] Fig. 9The figure is a comparison diagram of the time required to read data under different process angles for a conventional SRAM circuit using conventional SA in a 55nm CMOS process and a circuit provided by an embodiment of the present invention when there is a maximum leakage current on the bit line. DETAILED DESCRIPTION

[0024] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] like Figure 3 FIG. 1 is a schematic diagram of a control circuit structure of a bit line leakage current, a sense amplifier and a memory according to an embodiment of the present invention. The control circuit includes a storage array composed of 8T SRAM storage cells and a four-input sense amplifier ( Figure 3 SA_4IN in , where:

[0026] The two pairs of transmission tubes of the storage array are respectively connected to the main bit line pair and the sub bit line pair; wherein the main bit line pair includes the main bit lines BLM and BLMB; the sub bit line pair includes the sub bit lines BLN and BLNB;

[0027] A main bit line BLM and a sub bit line BLNB connected to the storage nodes on the same side in a column of memory cells are respectively connected to an input terminal on both sides of the four-input sense amplifier, wherein:

[0028] The input end of the four-input sense amplifier connected to the sub-bit line BLNB is connected to another main bit line BLMB, and the input end of the four-input sense amplifier connected to the main bit line BLM is connected to another sub-bit line BLN;

[0029] When there is leakage current on one of the main bit lines in the main bit line pair, the secondary bit line in the secondary bit line pair connected to the storage node on the same side as the main bit line also generates an equal amount of leakage current; therefore, when the four-input sensitive amplifier reads data, the voltage drop caused by the leakage current of the bit line on one side can be compensated in real time on the other side, thereby reading the correct data and realizing the control of the bit line leakage current.

[0030] like Figure 4 FIG. 1 is a schematic diagram of the structure of the 8T SRAM storage unit according to an embodiment of the present invention. The 8T SRAM storage unit in the storage array is composed of 2 PMOS transistors and 6 NMOS transistors, the 2 PMOS transistors are marked as P0 and P1, and the 6 NMOS transistors are marked as N0 to N5, wherein:

[0031] The gate of the PMOS tube P0 is connected to the gate of the NMOS tube N2, and the source is connected to the power supply VDD;

[0032] The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N3, and the source is connected to VDD;

[0033] The gate of the NMOS tube N0 is connected to the word line WL, the drain is connected to the main bit line BLM, and the source is connected to the drain of the PMOS tube P0, the drain of the NMOS tube N2, the gate of the PMOS tube P1, the gate of the NMOS tube N3 and the source of the NMOS tube N5 respectively;

[0034] The gate of the NMOS transistor N1 is connected to the word line WL, the drain is connected to another main bit line BLMB, and the source is respectively connected to the gate of the PMOS transistor P0, the drain of the PMOS transistor P1, the gate of the NMOS transistor N2, the drain of the NMOS transistor N3, and the source of the NMOS transistor N4;

[0035] The gate of the NMOS tube N2 is respectively connected to the gate of the PMOS tube P0, the drain of the PMOS tube P1, the source of the NMOS tube N1, the drain of the NMOS tube N3 and the source of the NMOS tube N4, and the source is connected to the ground VSS;

[0036] The gate of the NMOS tube N3 is respectively connected to the drain of the PMOS tube P0, the gate of the PMOS tube P1, the source of the NMOS tube N0, the drain of the NMOS tube N2 and the source of the NMOS tube N5, and the source is connected to VSS;

[0037] The gate of the NMOS tube N4 is connected to VSS, and the drain is connected to the auxiliary bit line BLN;

[0038] The gate of the NMOS transistor N5 is connected to VSS, and the drain is connected to another sub-bit line BLNB.

[0039] like Figure 5 FIG. 1 is a schematic diagram of the structure of a four-input sensitive amplifier according to an embodiment of the present invention. The four-input sensitive amplifier is composed of four PMOS tubes and seven NMOS tubes. The four PMOS tubes are marked as P0 to P3, and the seven NMOS tubes are marked as N0 to N6. In particular,

[0040] The gate of the PMOS tube P0 is connected to the pre-charge signal PRE, and the source is connected to the power supply VDD;

[0041] The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N0, and the source is connected to VDD;

[0042] The gate of the PMOS tube P2 is connected to the gate of the NMOS tube N1, and the source is connected to VDD;

[0043] The gate of the PMOS tube P3 is connected to the pre-charge signal PRE, and the source is respectively connected to the source of the PMOS tube P0, the source of the PMOS tube P1, the source of the PMOS tube P2 and VDD;

[0044] The gate of the NMOS tube N0 is respectively connected to the gate of the PMOS tube P1, the drain of the PMOS tube P2, the drain of the PMOS tube P3 and the drain of the NMOS tube N1, and the drain is respectively connected to the drain of the PMOS tube P0, the drain of the PMOS tube P1, the gate of the PMOS tube P2 and the gate of the NMOS tube N1;

[0045] The gate of the NMOS tube N1 is respectively connected to the drain of the PMOS tube P0, the drain of the PMOS tube P1, the gate of the PMOS tube P2 and the drain of the NMOS tube N0, and the drain is respectively connected to the gate of the PMOS tube P1, the drain of the PMOS tube P2, the drain of the PMOS tube P3 and the gate of the NMOS tube N0;

[0046] The gate of the NMOS tube N2 is connected to the main bit line BLM, and the drain is connected to the source of the NMOS tube N0 and the drain of the NMOS tube N3;

[0047] The gate of the NMOS tube N3 is connected to the auxiliary bit line BLN, and the drain is connected to the source of the NMOS tube NO and the drain of the NMOS tube N2;

[0048] The gate of the NMOS tube N4 is connected to another secondary bit line BLNB, and the drain is connected to the source of the NMOS tube N1 and the drain of the NMOS tube N5;

[0049] The gate of the NMOS transistor N5 is connected to another main bit line BLMB, and the drain is connected to the source of the NMOS transistor N1 and the drain of the NMOS transistor N4;

[0050] The gate of the NMOS tube N6 is connected to the enable signal SAEN, the drain is respectively connected to the source of the NMOS tube N2, the source of the NMOS tube N3, the source of the NMOS tube N4 and the source of the NMOS tube N5, and the source is connected to the ground VSS.

[0051] In a specific implementation, based on the structure of the control circuit:

[0052] At the beginning of the read operation, the main bit lines BLM and BLMB, as well as the sub-bit lines BLN and BLNB are precharged to the power supply VDD. Since there is leakage current on the main bit line BLM, it is set to I leakage0 , the voltage V of the main bit line BLM BLM From VDD down to VDD-ΔV1, ΔV1 is the leakage current I leakage0 The voltage V of the main bit line BLM caused by BLMAt the same time, since the secondary bit line BLNB and the main bit line BLM are connected to the storage node on the same side, the leakage current on the secondary bit line BLNB is equal to the leakage current on the main bit line BLM, both of which are I leakage0 , so the voltage V BLNB It also drops from VDD to VDD-ΔV1, that is, V BLM =V BLNB ;

[0053] On the other hand, since there is leakage current on the main bit line BLMB, let I leakage1 , the voltage of the main bit line BLMB is V BLMB From VDD down to VDD-ΔV2, ΔV2 is the leakage current I leakage1 The voltage V of the main bit line BLMB caused by BLMB At the same time, since the secondary bit line BLN and the main bit line BLMB are connected to the storage node on the same side, the leakage current on the secondary bit line BLN is equal to the leakage current on the main bit line BLMB, both of which are I leakage1 Therefore, the voltage V BLN It also drops from VDD to VDD-ΔV2, that is, V BLMB =V BLN ;

[0054] like Figure 6 FIG. 1 is a timing waveform diagram of the circuit structure provided by an embodiment of the present invention, wherein PRE is a precharge signal, WL is a word line signal, and SAEN is an enable signal of a four-input sense amplifier (SA_4IN). After the word line WL is turned on, if the data stored in the storage node Q is "0", there is a bit line discharge current I on the main bit line BLM. cell0 , resulting in the voltage V BLM The voltage V BLNB unchanged, so V BLM <V BLNB , V BLMB =V BLN; Since the main bit line BLM and the sub-bit line BLN are connected to the two input ports on the left side of the four-input sense amplifier, and the main bit line BLNB and the sub-bit line BLMB are connected to the two input ports on the right side of the four-input sense amplifier, and because the input ports on both sides of the four-input sense amplifier are symmetrical, when the enable signal SAEN is turned on, the discharge speed of the output node OUT of the four-input sense amplifier will be greater than the discharge speed of the output node OUTB, wherein the output node OUT and the output node OUTB are both pre-charged to VDD in the pre-charge stage; the voltage of the output node OUT quickly drops to 0, while the voltage of the output node OUTB will remain at VDD, thereby generating an output signal and completing data reading;

[0055] If the data stored in the storage node Q is "1", there is a bit line discharge current I on the main bit line BLMB cell1 , resulting in the voltage V BLMB The voltage V BLN unchanged, so V BLMB <V BLN , V BLM =V BLNB Therefore, when the enable signal SAEN is turned on, the discharge speed of the output node OUT of the four-input sensitive amplifier will be lower than the discharge speed of the output node OUTB, the voltage of the output node OUTB will drop quickly to 0, and the voltage of the output node OUT will remain at VDD, thereby generating an output signal and completing data reading.

[0056] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0057] In order to more clearly demonstrate the technical solution and the technical effects provided by the present invention, the performance of the circuit structure provided by the embodiment of the present invention is compared with the traditional SRAM and SA circuits in conjunction with the accompanying drawings. The specific contents are as follows:

[0058] (1) Figure 7 FIG. 1 is a read time diagram of a conventional SRAM circuit (hereinafter referred to as CONV) using a conventional SA in a 55nm CMOS process and a circuit provided by an embodiment of the present invention under different bit line leakage current conditions. Figure 7It can be seen that under the simulation conditions of 1.2V power supply voltage, TT process angle, and 25°C, the results show that when the leakage current is relatively small, the reading time of the traditional SRAM circuit using the traditional SA is slightly shorter than the circuit structure provided in the embodiment of the present invention. However, when the leakage current increases to about 10uA, the reading time of the traditional SRAM circuit using the traditional SA is longer than the circuit structure provided in the embodiment of the present invention, and when the leakage current further increases, the reading time of the traditional SRAM structure will increase rapidly, while the reading time of the circuit structure provided in the embodiment of the present invention remains basically unchanged, and even shows a decreasing trend. In the case of the same leakage current, the reading time of the traditional SRAM structure is much longer than the reading time of the circuit structure provided in the embodiment of the present invention.

[0059] (2) Figure 8 The figure shows a comparison of the maximum bit line leakage current that a traditional SRAM circuit using traditional SA under 55nm CMOS process and the circuit provided by the embodiment of the present invention can withstand at different process angles. Since the circuit structure provided by the embodiment of the present invention can read correct data when there is any leakage current of the main bit line, in the actual circuit, excessive leakage current will also cause read damage to the storage node data. Therefore, when testing the maximum main bit line leakage current that the circuit structure can withstand at different process angles, the maximum main bit line leakage current that the circuit structure can withstand without read damage is taken. Figure 8 It can be seen that under the simulation conditions of 1.2V power supply voltage and 25°C, the circuit structure provided by the embodiment of the present invention has improved ability to withstand bit line leakage current compared with the traditional SRAM circuit at different process angles. The greatest improvement is at the SS process angle, where the circuit structure's ability to withstand leakage current increases by 156.6%.

[0060] (3) Fig. 9 The figure shows a comparison of the time required to read data under different process angles when there is a maximum leakage current on the bit line for a traditional SRAM circuit using a traditional SA under a 55nm CMOS process and a circuit provided by an embodiment of the present invention. Among them, under the ss process angle, the bit line leakage currents of CONV and the structure are 22.4uA and 57.49uA respectively; under the tt process angle, the bit line leakage currents of CONV and the structure are 34.71uA and 56.68uA respectively; under the ff process angle, the bit line leakage currents of CONV and the structure are 50.42uA and 63.15uA respectively. Fig. 9It can be seen that: under the simulation conditions of 1.2V power supply voltage and 25°C, at different process angles, when there is a maximum leakage current on the bit line, the time for reading data in the circuit structure provided by the embodiment of the present invention is greatly reduced compared with the traditional SRAM circuit, and the reading time is reduced by up to 81.2%.

[0061] (4) As shown in Table 1 below, under the simulation conditions of 1.2V power supply voltage, TT process angle, and 25°C, the data output of SA_4IN when reading Q node data under different main bit line leakage and different storage data provided by the circuit of the embodiment of the present invention is shown:

[0062] Table 1

[0063] Main bit line leakage comparison Q and QB nodes store data SA_4INOUT Output Data BLM leak is large (0,1) 0 0 BLM leak is large (1,0) 1 1 BLMB leaks a lot (0,1) 0 0 BLMB leaks a lot (1,0) 1 1

[0064] It can be seen from Table 1 that under the simulation conditions of 1.2V power supply voltage, TT process angle, and 25°C, the results show that when the leakage current on the main bit line BLM is larger than that on the main bit line BLMB, if the storage node Q is "0", the output OUT of SA_4IN is 0, and the circuit output data is "0"; if the storage node Q is "1", the output OUT of SA_4IN is 1, and the circuit output data is "1". When the leakage current on the main bit line BLMB is larger than that on the main bit line BLM, if the storage node Q is "0", the output OUT of SA_4IN is 0, and the circuit output data is "0"; if the storage node Q is "1", the output OUT of SA_4IN is 1, and the circuit output data is "1".

[0065] In summary, the control circuit provided in the embodiment of the present invention can effectively resist the influence caused by the bit line leakage current. Compared with the traditional SRAM circuit structure, it can significantly reduce the time for reading data and improve the speed of SRAM reading operation; and improve the ability of SRAM to resist the bit line leakage current, avoiding the problem of reading erroneous data caused by leakage current during the reading operation of traditional SRAM, and improving the stability of SRAM reading data.

[0066] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A control circuit for a bit line leakage current, a sense amplifier and a memory, characterized in that: The control circuit includes a storage array consisting of 8T SRAM storage cells and a four-input sense amplifier with a symmetrical structure, wherein: The two pairs of transmission tubes of the storage array are respectively connected to the main bit line pair and the sub bit line pair; wherein the main bit line pair includes the main bit lines BLM and BLMB; the sub bit line pair includes the sub bit lines BLN and BLNB; A main bit line BLM and a sub bit line BLNB connected to the storage nodes on the same side in a column of memory cells are respectively connected to an input terminal on both sides of the four-input sense amplifier, wherein: The input end of the four-input sense amplifier connected to the sub-bit line BLNB is connected to another main bit line BLMB, and the input end of the four-input sense amplifier connected to the main bit line BLM is connected to another sub-bit line BLN; When there is leakage current on one of the main bit lines in the main bit line pair, the sub-bit line in the sub-bit line pair connected to the storage node on the same side as the main bit line also generates an equal amount of leakage current; therefore, when the four-input sense amplifier reads data, the voltage drop caused by the leakage current of the bit line on one side can be compensated in real time on the other side, thereby reading out the correct data, and realizing the control of the leakage current of the bit line; The 8T SRAM storage unit in the storage array is composed of 2 PMOS tubes and 6 NMOS tubes, the 2 PMOS tubes are marked as P0 and P1, and the 6 NMOS tubes are marked as N0 to N5, wherein: The gate of the PMOS tube P0 is connected to the gate of the NMOS tube N2, and the source is connected to the power supply VDD; The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N3, and the source is connected to VDD; The gate of the NMOS tube N0 is connected to the word line WL, the drain is connected to the main bit line BLM, and the source is connected to the drain of the PMOS tube P0, the drain of the NMOS tube N2, the gate of the PMOS tube P1, the gate of the NMOS tube N3 and the source of the NMOS tube N5 respectively; The gate of the NMOS transistor N1 is connected to the word line WL, the drain is connected to another main bit line BLMB, and the source is respectively connected to the gate of the PMOS transistor P0, the drain of the PMOS transistor P1, the gate of the NMOS transistor N2, the drain of the NMOS transistor N3, and the source of the NMOS transistor N4; The gate of the NMOS tube N2 is respectively connected to the gate of the PMOS tube P0, the drain of the PMOS tube P1, the source of the NMOS tube N1, the drain of the NMOS tube N3 and the source of the NMOS tube N4, and the source is connected to the ground VSS; The gate of the NMOS tube N3 is respectively connected to the drain of the PMOS tube P0, the gate of the PMOS tube P1, the source of the NMOS tube N0, the drain of the NMOS tube N2 and the source of the NMOS tube N5, and the source is connected to VSS; The gate of the NMOS tube N4 is connected to VSS, and the drain is connected to the auxiliary bit line BLN; The gate of the NMOS tube N5 is connected to VSS, and the drain is connected to another secondary bit line BLNB; The four-input sensitive amplifier is composed of 4 PMOS tubes and 7 NMOS tubes, the 4 PMOS tubes are marked as P0 to P3, and the 7 NMOS tubes are marked as N0 to N6, wherein: The gate of the PMOS tube P0 is connected to the pre-charge signal PRE, and the source is connected to the power supply VDD; The gate of the PMOS tube P1 is connected to the gate of the NMOS tube N0, and the source is connected to VDD; The gate of the PMOS tube P2 is connected to the gate of the NMOS tube N1, and the source is connected to VDD; The gate of the PMOS tube P3 is connected to the pre-charge signal PRE, and the source is respectively connected to the source of the PMOS tube P0, the source of the PMOS tube P1, the source of the PMOS tube P2 and VDD; The gate of the NMOS tube N0 is respectively connected to the gate of the PMOS tube P1, the drain of the PMOS tube P2, the drain of the PMOS tube P3 and the drain of the NMOS tube N1, and the drain is respectively connected to the drain of the PMOS tube P0, the drain of the PMOS tube P1, the gate of the PMOS tube P2 and the gate of the NMOS tube N1; The gate of the NMOS tube N1 is respectively connected to the drain of the PMOS tube P0, the drain of the PMOS tube P1, the gate of the PMOS tube P2 and the drain of the NMOS tube N0, and the drain is respectively connected to the gate of the PMOS tube P1, the drain of the PMOS tube P2, the drain of the PMOS tube P3 and the gate of the NMOS tube N0; The gate of the NMOS tube N2 is connected to the main bit line BLM, and the drain is connected to the source of the NMOS tube N0 and the drain of the NMOS tube N3; The gate of the NMOS tube N3 is connected to the auxiliary bit line BLN, and the drain is connected to the source of the NMOS tube N0 and the drain of the NMOS tube N2; The gate of the NMOS tube N4 is connected to another secondary bit line BLNB, and the drain is connected to the source of the NMOS tube N1 and the drain of the NMOS tube N5; The gate of the NMOS transistor N5 is connected to another main bit line BLMB, and the drain is connected to the source of the NMOS transistor N1 and the drain of the NMOS transistor N4; The gate of the NMOS tube N6 is connected to the enable signal SAEN, the drain is respectively connected to the source of the NMOS tube N2, the source of the NMOS tube N3, the source of the NMOS tube N4 and the source of the NMOS tube N5, and the source is connected to the ground VSS.

2. The control circuit of the bit line leakage current, the sense amplifier and the memory according to claim 1, characterized in that: Based on the structure of the control circuit: At the beginning of the read operation, the main bit lines BLM and BLMB, as well as the sub-bit lines BLN and BLNB are precharged to the power supply VDD. Since there is leakage current on the main bit line BLM, it is set to I leakaqe0 , the voltage V of the main bit line BLM BLM From VDD down to VDD-ΔV1, ΔV1 is the leakage current I leakage0 The voltage V of the main bit line BLM caused by BLM At the same time, since the secondary bit line BLNB and the main bit line BLM are connected to the storage node on the same side, the leakage current on the secondary bit line BLNB is equal to the leakage current on the main bit line BLM, both of which are I leakage0 , so the voltage V BLNB It also drops from VDD to VDD-ΔV1, that is, V BLM =V BLNB ; On the other hand, since there is leakage current on the main bit line BLMB, let I leakage1 , the voltage of the main bit line BLMB is V BLMB From VDD down to VDD-ΔV2, ΔV2 is the leakage current I leakage1 The voltage V of the main bit line BLMB caused by BLMB At the same time, since the secondary bit line BLN and the main bit line BLMB are connected to the storage node on the same side, the leakage current on the secondary bit line BLN is equal to the leakage current on the main bit line BLMB, both of which are I leakage1 Therefore, the voltage V BLN It also drops from VDD to VDD-ΔV2, that is, V BLMB =V BLN ; After the word line WL is turned on, if the data stored in the storage node Q is "0", there is a bit line discharge current I on the main bit line BLM cell0 , resulting in the voltage V BLM The voltage V BLNB unchanged, so V BLM <V BLNB , V BLMB =V BLN ; Since the main bit line BLM and the sub-bit line BLN are connected to the two input ports on the left side of the four-input sense amplifier, and the main bit line BLNB and the sub-bit line BLMB are connected to the two input ports on the right side of the four-input sense amplifier, and because the input ports on both sides of the four-input sense amplifier are symmetrical, when the enable signal SAEN is turned on, the discharge speed of the output node OUT of the four-input sense amplifier will be greater than the discharge speed of the output node OUTB, wherein the output node OUT and the output node OUTB are both pre-charged to VDD in the pre-charge stage; the voltage of the output node OUT quickly drops to 0, while the voltage of the output node OUTB will remain at VDD, thereby generating an output signal and completing data reading; If the data stored in the storage node Q is "1", there is a bit line discharge current I on the main bit line BLMB cell1 , resulting in the voltage V BLMB The voltage V BLN unchanged, so V BLMB <V BLN , V BLM =V BLNB Therefore, when the enable signal SAEN is turned on, the discharge speed of the output node OUT of the four-input sensitive amplifier will be lower than the discharge speed of the output node OUTB, the voltage of the output node OUTB will drop quickly to 0, and the voltage of the output node OUT will remain at VDD, thereby generating an output signal and completing data reading.

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