Semiconductor device and continuous readout method

Abstract

The present invention provides a semiconductor device and a continuous reading method for improving the existing continuous reading. The flash memory of the present invention includes: a NAND type memory cell array, an input-output circuit, an ECC circuit, a controller, a word line selection circuit, a page buffer / reading circuit, and a column selection circuit. When the controller performs continuous reading of a page, the first 1 / 2 page of the selected page is read from the memory cell array, and independently the second 1 / 2 page of the selected page is read from the memory cell array, and the data of the 1 / 2 page read out is continuously outputted in synchronization with a clock signal.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device and a continuous reading method of a NAND type flash memory. Background Art

[0002] NAND flash memories are sometimes equipped with a continuous read function (burst read function) for continuously reading multiple pages in response to external commands. The page buffer / read circuit includes, for example, two latches, and during the continuous read operation, one latch holds the data read from the array while the other latch can output the data held by the other latch (such as Patent Document 1, Patent Document 2, Patent Document 3, etc.). Patent Document 4 discloses a read method for further speeding up continuous read.

[0003] [Prior art literature]

[0004] [Patent Document]

[0005] [Patent Document 1] Japanese Patent No. 5323170

[0006] [Patent Document 2] Japanese Patent No. 5667143

[0007] [Patent Document 3] US Patent Application US2014 / 0104947A1

[0008] [Patent Document 4] Japanese Patent No. 6744950 Summary of the invention

[0009] Figure 1 The schematic structure of a NAND type flash memory equipped with an on-chip error checking and correction (ECC) function is shown. The flash memory includes: a memory cell array 10 including a NAND string, a page buffer / readout circuit 20, a data transfer circuit 30, a data transfer circuit 32, an error detection and correction circuit (hereinafter referred to as an ECC circuit) 40, and an input-output circuit 50. The page buffer / readout circuit 20 includes two latches L1 and L2 (one latch is, for example, 4KB) for holding read data or input data to be programmed, and the latches L1 and L2 include a first cache C0 and a second cache C1 (one cache is, for example, 2KB), respectively.

[0010] Figure 2The timing diagram disclosed in Patent Document 4 when performing continuous reading of multiple pages is shown. First, the array reading of page P0 is performed, and the data of page P0 is maintained in the first cache C0 and the second cache C1 (P0C0, P0C1) of latch L1. Next, the data of the first cache C0 and the second cache C1 of latch L1 are transferred to the first cache C0 and the second cache C1 of latch L2, and the data of the first cache C0 and the second cache C1 are subjected to ECC decoding operation in the ECC circuit 40. When an error is detected, the data of the first cache C0 and the second cache C1 of latch L2 are corrected.

[0011] In the continuous reading, the row address counter is automatically incremented, and the next page P1 is read, and the read data is transferred to the first cache C0 and the second cache C1 of the latch L1. During this period, the data of the first cache C0 of the latch L2 is transferred to the input-output circuit 50, and the data held by the input-output circuit 50 is output synchronously with the external clock signal ExCLK supplied from the outside. Then, the data of the second cache C1 of the latch L2 is output from the input-output circuit 50 synchronously with the external clock signal ExCLK, and during this period, the data of the first cache C0 of the latch L1 is transferred to the latch L2, and the ECC circuit 40 performs ECC processing.

[0012] During the period when the data of the second cache C1 of latch L1 is transmitted to latch L2 and the data of the first cache C0 of latch L2 is output from the input-output circuit 50, the data of the second cache C1 of latch L2 is processed by ECC, and then, during the period when the data of the second cache C1 of latch L2 is output from the input-output circuit 50, the next page P2 is read out from the array and transmitted to the first cache C0 and the second cache C1 of latch L1, and the data of the first cache C0 is transmitted to latch L2 for ECC processing.

[0013] The continuous readout using latches L1 and L2 actually starts from the array readout of page P2. The start timing of the array readout of page P2 is not the time point when the data of page P1 is transferred from latch L1 to latch L2, but the time point when the data of page P1 of the first cache C0 of latch L1 is transferred to latch L2 earlier. Even if the timing of the array readout of page P2 is advanced, the array readout actually takes a certain amount of time. Therefore, at the time point when the data of page P2 read out from the array is transferred to latch L1, if a high-speed external clock signal ExCLK is used for the speed of continuous readout, the data of page P1 is transferred from latch L1 to latch L2.

[0014] The array read time tARRAY is defined by the start and end timings of the array read. The end timing of the array read of page P2 is the start timing of the array read of the next page P3. When pages P2, P3, P4, ... are read successively, the array read time tARRAY is also continuous.

[0015] Here, array readout is performed using an internal clock signal at a determined timing, while data output is performed based on an external clock signal ExCLK that is asynchronous with the internal clock signal. Figure 2 The constraints of the continuous readout are expressed by equation (1). tARRAY and tECC are constant times, and tDOUT is defined by the frequency of the external clock signal ExCLK.

[0016] tARRAY<tDOUT(1 page)

[0017] tECC<tDOUT(1 / 2 page)…(1)

[0018] As long as the following constraints are met, that is, the time tDOUT to output one page of data is greater than the array read time tARRAY, and the time tDOUT to output 1 / 2 page of data is greater than the ECC processing time tECC, then it can be achieved. Figure 2 The continuous readout is accelerated. Figure 2 The following situation is illustrated in the figure: compared with the page P2 array read time tARRAY, the total output time tDOUT, which is the time for outputting the second cache data of page P0 and the time for outputting the first cache data of page P1, is larger. The page P2 array read time tARRAY is from the time point when the first cache C0 data of page P1 starts to be transferred from latch L1 to latch L2 to the time point when the first cache C0 data of the next page P2 starts to be transferred from latch L1 to latch L2; compared with the time tECC for ECC processing of the first cache C0 data of latch L2, the time tDOUT for outputting the second cache C1 data of latch L2 is larger.

[0019] However, changing the start timing of array reading creates another timing constraint. Assuming that the user uses a slow external clock signal ExCLK, at the time when the data read from the array is transmitted to latch L1, latch L1 retains the data of the previous page due to the slow frequency of the external clock signal ExCLK, and the data of the previous page in latch L1 is destroyed by the next page of data read from the array.

[0020] Formula (2) represents a constraint for preventing such data destruction from occurring.

[0021] tDOUT(1 / 2 page)<tARRAY…(2)

[0022] Formula (3) is derived from formula (1) and formula (2).

[0023] tARRAY<tDOUT<tARRAY×2…(3)

[0024] In order to use an external clock signal ExCLK having a frequency lower than the minimum frequency specified by equation (3), the conventional flash memory prepares a status register and performs a control operation such as Figure 2 The high-speed continuous reading as shown, or the continuous reading in which the array reading is performed after the data held in the latch L1 is transferred to the latch L2, is switched. Figure 3 An example of a status register is shown in FIG. 1. The setting value "1" corresponds to the use of the high-speed external clock signal ExCLK and is used in the continuous reading. Figure 2 The array readout starts at the timing shown, and the setting value "0" corresponds to the use of the low-speed external clock signal ExCLK, and the array readout starts at the continuous readout timing. The setting value of the status register can be rewritten from the outside. The user can input the rewrite command from the outside and the address "XXh" of the status register to change the setting value of the status register.

[0025] This conventional flash memory can realize high-speed continuous reading by maximizing the frequency of the external clock signal ExCLK. On the other hand, there is a restriction on the minimum value of the frequency of the external clock signal ExCLK. In order to use such a low frequency, a circuit for switching the timing of starting the state register or array reading is required. Furthermore, the user must set the operation of the state register, which is complicated.

[0026] In addition, in the case of continuous reading, array reading is performed in data output, and when input / output (IO) noise overlaps with the current of array reading at the timing of a certain operation, a large peak current Icc is generated. The input / output circuit 50 includes, for example, a parallel / serial conversion circuit connected to m flip-flops, and converts m-bit parallel data into serial data in synchronization with an external clock signal ExCLK and outputs it from an external terminal. On the other hand, in continuous reading, a large current flows in order to precharge the bit line, and as the size of one page increases, a correspondingly large current is consumed.

[0027] The array readout is performed synchronously with the internal clock signal InCLK generated by the internal clock generator, but the internal clock signal InCLK is asynchronous with the external clock signal ExCLK. When the edges of the two clock signals overlap or approach each other in time, a large peak current Icc is generated due to the action synchronized with the clock signal. The large peak current Icc temporarily drops the internal supply voltage or generates noise, thereby delaying the circuit action or making the action unstable. Therefore, the peak current Icc is reduced as much as possible.

[0028] The continuous reading method of a page of a NAND flash memory of the present invention includes: a first reading step, reading out 1 / 2 page of first data from a first storage cell array, and holding the read first data in a first holding circuit; a second reading step, reading out 1 / 2 page of second data from a second storage cell array at a timing different from that of the first storage cell array, and holding the read second data in a second holding circuit; a first output step, outputting the first data synchronously with a clock signal; and a second output step, continuously outputting the second data after outputting the first data synchronously with the clock signal.

[0029] The continuous reading method further includes: a first transmission step of transmitting the first data held in the first holding circuit to the third holding circuit; and a second transmission step of transmitting the second data held in the second holding circuit to the fourth holding circuit, after the first transmission step, the first data of the next page read out by the first reading step is held in the first holding circuit, and after the second transmission step, the second data of the next page read out by the second reading step is held in the second holding circuit. The continuous reading method further includes: a first ECC step of performing error detection and correction on the first data held in the third holding circuit; and a second ECC step of performing error detection and correction on the second data held in the fourth holding circuit. During the period of outputting the first data held in the third holding circuit by the first output step, the second ECC step performs error detection and correction on the second data of the next page held in the fourth holding circuit, and during the period of outputting the second data held in the fourth holding circuit by the second output step, the first ECC step performs error detection and correction on the first data of the next page held in the third holding circuit. The first readout step reads out the first data of the first two pages in response to the first data held in the third holding circuit being outputted in the first output step, and the second readout step reads out the second data of the first two pages in response to the second data held in the fourth holding circuit being outputted in the second output step. The first output step and the second output step continuously and alternately output the first data and the second data from each of the plurality of external terminals.

[0030] The method for continuously reading pages of a NAND flash memory of the present invention also includes: a reading step, in which the array reading of the first 1 / 2 page and the array reading of the second 1 / 2 page are performed independently from the memory cell array; a holding step, in which the first data of the 1 / 2 page read out of the first array is held in a first holding circuit, and the second data of the 1 / 2 page read out of the second array is held in a second holding circuit; and an output step, in which the reading step and the holding step are performed by reading out multiple pages, and the first data and the second data are output alternately in synchronization with a clock signal.

[0031] The semiconductor device of the present invention includes: a first array readout unit that reads out data from a first NAND type memory cell array; a second array readout unit that reads out data from a second NAND type memory cell array; a first holding unit that holds the data read out by the first readout unit; a second holding unit that holds the data read out by the second readout unit; an output unit that can output the data held by the first holding unit and the second holding unit in synchronization with a clock signal; and a control unit that controls the readout action. When the control unit controls the continuous reading of pages, the first array readout unit reads out the first data of 1 / 2 page, the second array readout unit reads out the second data of 1 / 2 page, and the output unit continuously outputs the first data and the second data alternately.

[0032] In one embodiment of the present invention, the first holding component includes: a first latch, which holds the first data read by the first array read-out component; and a second latch, which holds the first data transmitted from the first latch, and after the first data is transmitted from the first latch to the second latch, the first data of 1 / 2 page of the next page read by the first array read-out component is held in the first latch, and the second holding component includes: a first latch, which holds the second data read by the second array read-out component; and a second latch, which holds the second data transmitted from the first latch, and after the second data is transmitted from the first latch to the second latch, the second data of 1 / 2 page of the next page read by the second array read-out component is held in the first latch.

[0033] The semiconductor device also includes an error detection and correction unit for performing data error detection and correction, and the error detection and correction unit performs error detection and correction on the first data or the second data held in the second latch of the first holding unit and the second holding unit. During the period when the output unit outputs the first data held in the second latch of the first holding unit, the error detection and correction unit performs error detection and correction on the second data of the next page held in the second latch of the second holding unit, and during the period when the output unit outputs the second data held in the second latch of the second holding unit, the error detection and correction unit performs error detection and correction on the first data of the next page held in the second latch of the first holding unit. The first array readout unit responds to the first data held in the second latch of the first holding unit output by the output unit to read out the first data of 1 / 2 page of the first two pages, and the second array readout unit responds to the second data held in the second latch of the second holding unit output by the output unit to read out the second data of 1 / 2 page of the first two pages. The first memory cell array and the second memory cell array can be formed on the same chip. Or the first memory cell array and the second memory cell array are formed on different chips respectively. The output unit continuously and alternately outputs the first data and the second data from each of the plurality of external terminals.

[0034] The reading method of the NAND flash memory of the present invention includes the following steps: receiving a command; determining whether it is a normal page read or a continuous read of multiple pages based on the command; when it is determined to be a normal page read, simultaneously accessing the first storage cell array and the second storage cell array, reading one page of data from the first storage cell array and the second storage cell array, and maintaining the read data in the first holding circuit and the second holding circuit; and when it is determined to be a continuous read of multiple pages, separately accessing the first storage cell array and the second storage cell array, reading 1 / 2 page of first data from the first storage cell array, maintaining the read first data in the first holding circuit, reading the remaining 1 / 2 page of second data from the second storage cell array, and maintaining the read second data in the second holding circuit.

[0035] The semiconductor device of the present invention also includes: a control unit that determines whether it is a normal page read or a continuous read of multiple pages based on the received command. When it is determined to be a normal page read, one page of data is read from the first storage cell array and the second storage cell array at the same time, and the first holding unit and the second holding unit hold the read data. When it is determined to be a continuous read of multiple pages, 1 / 2 page of first data is read from the first storage cell array, and the first holding unit holds the read first data. Then, the remaining 1 / 2 page of second data is read from the second storage cell array, and the second holding unit holds the read second data.

[0036] According to the present invention, when continuously reading pages, the reading of 1 / 2 page from the first memory cell array and the reading of 1 / 2 page from the second memory cell array are performed independently, so that the continuous reading of pages can be performed without being restricted by the frequency of the clock signal. Furthermore, by reading in 1 / 2 pages, the peak current during array reading can be reduced, thereby improving the reliability of circuit operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram showing a conventional NAND type flash memory;

[0038] Figure 2 This is a timing diagram for continuous reading in an existing NAND flash memory;

[0039] Figure 3 is a diagram representing the existing state register;

[0040] Figure 4 is a block diagram showing the structure of a NAND flash memory according to an embodiment of the present invention;

[0041] Figure 5 is a circuit diagram showing a NAND string of the present embodiment;

[0042] Figure 6 is a structural diagram showing a bit line selection circuit of the present embodiment;

[0043] Figure 7 is a diagram showing the structure of a page buffer / readout circuit of the present embodiment;

[0044] Figure 8 is a diagram schematically illustrating the continuous readout action of this embodiment;

[0045] Fig. 9 is a timing diagram when a continuous read operation is performed in the flash memory of this embodiment;

[0046] FIG. 10(A) is a diagram showing the structure of a flash memory according to a variation of the embodiment of the present invention, and FIG. 10(B) is a diagram showing its internal structure.

[0047] [Explanation of Symbols]

[0048] 10, 110_1, 110_2, 340_1: storage cell array

[0049] 20, 170_1, 170_2: Page buffer / readout circuit

[0050] 30, 32: Data transmission circuit

[0051] 40, 130: ECC circuit

[0052] 50, 120, 370_1, 370_2: Input and output circuits

[0053] 100, 100B: Flash memory

[0054] 140: Address register

[0055] 150, 360_1, 360_2: Controller

[0056] 160_1, 160_2: word line selection circuit

[0057] 180_1, 180_2: Column selection circuit

[0058] 190: Internal voltage generation circuit

[0059] 200_1: Bit line selection circuit

[0060] 210: Decision circuit

[0061] 220_1, 220_2: Transmission circuit

[0062] 300_1, 300_2: Chip

[0063] 310_1, 320_2: Internal solder pads

[0064] 320: Internal wiring

[0065] 330: External terminal

[0066] 350_1: Peripheral circuit

[0067] 380: Main computer

[0068] BLCD1, BLCD2, BLCLAMP, BLCN, BLPRE, BLSe, BLSo, CACHE, DTG, EQ, REG, RESET2, VG: transistors

[0069] BLK(0), BLK(1), ..., BLK(m-1): storage blocks

[0070] BLS, SLR1, SLR2, SLS1, SLS2: Node

[0071] C0: First cache

[0072] C1: Second cache

[0073] ExCLK: external clock signal

[0074] GBLe: Even bit lines

[0075] GBLo: odd bit line

[0076] L1, L2: latch

[0077] MC0, MC1, MC2, ..., MC63: storage unit

[0078] NU: NAND string

[0079] P0, P1, P2, P3, P4: Page

[0080] SGD, SGS: select gate lines

[0081] SL: Source Line

[0082] SNS: Readout Node

[0083] tARRAY: array readout time

[0084] tDOUT, tDout: output time

[0085] tECC: Time for ECC processing

[0086] V1, V2: voltage supply nodes

[0087] Vers: Erase voltage

[0088] VIRPWR: Virtual Power

[0089] Vpass: pass voltage

[0090] Vpgm: write voltage (programming voltage)

[0091] Vread: read pass voltage

[0092] WL0, WL1, WL2, ..., WL31: word lines DETAILED DESCRIPTION

[0093] Figure 41 is a structural diagram of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes a memory cell array 110_1 and a memory cell array 110_2, which are arranged in a matrix with a plurality of memory cells; an input / output circuit 120, which is connected to an external input / output terminal and responds to an external clock signal ExCLK and outputs read data to the outside or imports data input from the outside; an ECC circuit 130, which performs error detection and correction of data to be programmed or data to be read; an address register 140, which receives address data via the input / output circuit 120; a controller 150, which controls each unit based on command data received via the input / output circuit 120 or control signals applied to external terminals; and a word line 130. The page buffer / readout circuit 170_1 and the page buffer / readout circuit 170_2 hold the data read out from the memory cell array 110_1 and the memory cell array 110_2, or hold the data to be programmed into the array; the column selection circuit 180_1 and the column selection circuit 180_2 decode the column address information Ay from the address register 140, and select the bit line of the page buffer / readout circuit 170_1 and the page buffer / readout circuit 170_2 based on the decoding result; and the internal voltage generation circuit 190 generates various voltages (write voltage Vpgm, pass voltage Vpass, read pass voltage Vread, erase voltage Vers, etc.) required for reading, programming and erasing data.

[0094] The flash memory 100 of the present embodiment includes two memory cell arrays 110_1 and 110_2 that can operate independently, two word line selection circuits 160_1 and 160_2, two page buffer / readout circuits 170_1 and 170_2, and two column selection circuits 180_1 and 180_2. The controller 150 controls the reading, programming, erasing, and other operations of the memory cell arrays 110_1 and 110_2 through the word line selection circuits 160_1 and 160_2, the page buffer / readout circuits 170_1 and 170_2, and the column selection circuits 180_1 and 180_2. The word line selection circuit 160_1, the word line selection circuit 160_2, the page buffer / readout circuit 170_1, the page buffer / readout circuit 170_2, and the column selection circuit 180_1, the column selection circuit 180_2. The memory cell array 110_1, the memory cell array 110_2, the word line selection circuit 160_1, the word line selection circuit 160_2, the page buffer / readout circuit 170_1, the page buffer / readout circuit 170_2, and the column selection circuit 180_1, the column selection circuit 180_2 share a common structure, so in the following description, only one of them will be described.

[0095] The memory cell array 110_1 has, for example, m memory blocks BLK(0), BLK(1), ..., BLK(m-1) arranged along the column direction. A plurality of NAND strings NU are formed in one memory block, and a NAND string is formed by connecting a plurality of memory cells in series. Figure 5 As shown, a NAND string NU includes a plurality of memory cells MCi (i=0, 1, ..., 63) connected in series, a bit line side selection transistor, and a source line side selection transistor. The drain of the bit line side selection transistor is connected to a corresponding global bit line GBL, and the source of the source line side selection transistor is connected to a common source line SL. The control gate of the memory cell MCi is connected to the word line WLi, and the gates of the bit line side selection transistor and the source line side selection transistor are respectively connected to the selection gate line SGD and the selection gate line SGS. The word line selection circuit 160_1 drives the bit line side selection transistor and the source line side selection transistor via the selection gate line SGD and the selection gate line SGS based on the row address information Ax to select a block or a word.

[0096] The NAND string NU can be formed on the substrate surface in two dimensions or three dimensions. In addition, the NAND string NU can also include a dummy cell between the bit line side selection transistor and the memory cell and / or between the source line side selection transistor and the memory cell.

[0097] exist Figure 6 The structure of the bit line selection circuit is shown in FIG. Figure 6As an example, one page buffer / readout circuit 170_1 shared by one even bit line GBLe and one odd bit line GBLo, and a bit line selection circuit 200_1 connected thereto are shown.

[0098] The bit line selection circuit 200_1 includes: a transistor BLSe for selecting an even bit line GBLe, a transistor BLSo for selecting an odd bit line GBLo, a transistor YBLe for connecting a virtual power supply VIRPWR to the even bit line GBLe, and a transistor YBLo for connecting a virtual power supply VIRPWR to the odd bit line GBLo. A NAND string is connected between the even bit line GBLe and the source line SL, and a NAND string is connected between the odd bit line GBLo and the source line SL. For example, in a read operation, a shielded read is performed, and when the even bit line GBLe is selected, the odd bit line GBLo is not selected, and when the odd bit line GBLo is selected, the even bit line GBLe is not selected. The non-selected bit line is connected to the ground (Ground, GND) level via the virtual power supply VIRPWR.

[0099] Figure 7 Show Figure 6 The structure of a page buffer / readout circuit 170_1 is shown. For convenience, the signal applied to the gate of the transistor represents the transistor. The page buffer / readout circuit 170 includes two latches L1 and L2, and a transfer gate (transistor CACHE) is connected between the latch L1 and the latch L2. By turning on the transfer gate, bidirectional data transfer from the latch L1 to the latch L2 or from the latch L2 to the latch L1 can be performed.

[0100] The latch L1 includes a pair of cross-coupled inverters, a node SLR1 of the latch L1 is connected to the common source / drain (S / D) of the transistor BLCD1 and the transistor DTG, and a node SLS1 is connected to the determination circuit 210. The determination circuit 210 determines, for example, whether the program verification (Program Verify) or the erase verification is qualified. When the node SLR1 is selectively charged to Vdd by the self-voltage supply node V2 or the node SLR1 is selectively discharged to GND during the program verification, the transistor DTG is turned on. Furthermore, the latch L1 can short-circuit the node SLR1 and the node SLS1 through the transistor EQ.

[0101] Nodes SLR1 and SLS1 of latch L1 are connected to nodes SLS2 and SLR2 of latch L2 via transistor CACHE, respectively. Node SLR2 of latch L2 is connected to read node SNS via transistor BLCD2, and node SLS2 is connected to transistor RESET2. When latch L2 is reset, transistor RESET2 is turned on.

[0102] A transistor VG and a transistor REG are connected in series between the voltage supply node V2 and the read node SNS, and the gate of the transistor VG is connected to the S / D of the transistor DTG. The voltage supply node V1 is connected to the read node SNS via the transistor BLPRE. A transistor BLCN and a transistor BLCLAMP are connected in series between the read node SNS and the node BLS of the bit line selection circuit 200.

[0103] The word line selection circuit 160_1 and the column selection circuit 180_1 select a read start position of data in a page according to the row address information Ax and the column address information Ay, or automatically read data from the beginning of the page without using the row address information Ax and the column address information Ay. Furthermore, the word line selection circuit 160_1 and the column selection circuit 180_1 may include a row address counter and a column address counter that increment the row address information Ax and the column address information Ay in response to a clock signal.

[0104] When the data held in the latch L2 of the page buffer / readout circuit 170_1 is output, the column selection circuit 180_1 selects n-bit data from the data held in the latch L2. The selected n-bit data is input to the n differential sense amplifiers as differential data of the node SLS2 and the node SLR2, and the n differential sense amplifiers output the read n-bit data to the internal data bus with a width of n bits.

[0105] The data output from the n-bit width internal data bus is selectively supplied to the ECC circuit 130 or the input / output circuit 120 via the transmission circuit. The ECC circuit 130 performs error detection and correction on the data supplied via the internal data bus. The input / output circuit 120 includes, for example, a parallel / serial conversion circuit directly connected to a plurality of flip-flops, and the parallel / serial conversion circuit converts the data input in parallel from the internal data bus into serial data in synchronization with the external clock signal ExCLK, and supplies the converted data to an external terminal. The external terminal may be, for example, ×1, ×2, ×4, or ×8.

[0106] In the read operation of the flash memory, a positive voltage is applied to the bit line, a voltage (e.g., 0V) is applied to the selected word line, a pass voltage Vpass (e.g., 4.5V) is applied to the non-selected word line, a positive voltage (e.g., 4.5V) is applied to the selected gate line SGD and the selected gate line SGS, the bit line side selection transistor and the source line side selection transistor are turned on, and 0V is applied to the common source line. In the programming operation, a high voltage programming voltage Vpgm (15V to 20V) is applied to the selected word line, an intermediate potential (e.g., 10V) is applied to the non-selected word line, the bit line side selection transistor is turned on, the source line side selection transistor is turned off, and a potential corresponding to the data "0" or "1" is supplied to the bit line. In the erase operation, 0V is applied to the selected word line in the block, a high voltage (e.g., 20V) is applied to the P well, and the data is erased in units of blocks by extracting electrons from the floating gate to the substrate.

[0107] In the normal read operation, program operation, and erase operation of the flash memory 100, the controller 150 controls the operation of the two memory cell arrays 110_1 and 110_2 as if they were one memory cell array. When the flash memory 100 receives a normal page read command and address from the host computer, the command is identified by the controller 150, and under the control of the controller 150, the word line selection circuits 160_1 and 160_2 simultaneously select the word lines of the same row of the memory cell arrays 110_1 and 110_2 based on the row address information Ax. That is, the selection of the word line of the memory cell array 110_1 corresponds to the reading of 1 / 2 page data, and the selection of the word line of the memory cell array 110_2 corresponds to the reading of 1 / 2 page data. As a result, the selection of the word line by the word line selection circuits 160_1 and 160_2 corresponds to the reading of one page of data.

[0108] When performing a read operation, first, the selected bit line (for example, the even bit line) is precharged from the voltage supply node V1 of the page buffer / read circuit 170_1 and the page buffer / read circuit 170_2 via the transistor BLPRE. Next, the word line of the memory cell array 110_1 and the memory cell array 110_2 is selected, and the voltage of the selected bit line is discharged according to the storage state of the selected memory cell. Next, the potential generated in the read node SNS is transmitted to the latch L1, and thus the array read is completed.

[0109] Next, the continuous read operation of the flash memory will be described. In the continuous read operation, unlike a normal page read, the controller 150 controls the timing of array reads of the memory cell array 110_1 and the memory cell array 110_2 separately.

[0110] When receiving a continuous read command and an address via the input / output circuit 120, the controller 150 recognizes the command and controls continuous reading of a plurality of pages from the start page to the end page. The continuous reading ends with a command or when a designated page is read.

[0111] Figure 8 Schematic diagram for explaining the continuous reading operation of this embodiment. Figure 1 As shown, one page of data is read out from the memory cell array at one time, and the read data is simultaneously transmitted to the first cache C0 and the second cache C1 of the latch L1, but in the continuous reading of the flash memory 100, 1 / 2 page of data is read out from the memory cell array 110_1 and the memory cell array 110_2 at different timings, and the read data is transmitted to the first cache C0 and the second cache C1 of the latch L1 at different timings.

[0112] Specifically, the first 1 / 2 page of data of a certain page is read out from the memory cell array 110_1, and the read data is transferred to the first cache C0 of the latch L1 and held therein. After the memory cell array 110_1 is read out, the second 1 / 2 page of a certain page is read out from the memory cell array 110_2, and the read data is transferred to the second cache C1 of the latch L1 and held therein.

[0113] Next, the data held in the first cache C0 and the second cache C1 of the latch L1 are transferred to the first cache C0 and the second cache C1 of the latch L2 and held therein. The data held in the first cache C0 of the latch L2 is transferred to the ECC circuit 130 through the transfer circuit 220_1, where data error detection and correction are performed, and then transferred to the input-output circuit 120 through the transfer circuit 220_1, where it is output synchronously with the external clock signal ExCLK. During the processing by the ECC circuit 130, the data of the first 1 / 2 page of the next page is read out, and the data is held in the first cache C0 of the latch L1.

[0114] The data of the response latch L2 is transmitted to the input-output circuit 120 and the data of the first cache C0 of the latch L1 is transmitted to the first cache C0 of the latch L2, and the data of the first 1 / 2 page of the next page (the first two pages from the output page) is read out from the memory cell array 110_1, and the data is transmitted to the first cache C0 of the latch L1.

[0115] The memory cell array 110_2 is read out in the same manner as the memory cell array 110_1. The controller 150 controls the timing of the array read out of the memory cell array 110_2 so that after the data of the first cache C0 of the latch L2 is output synchronously with the external clock signal ExCLK, the data of the second cache C1 of the latch L2 is continuously output synchronously with the external clock signal ExCLK.

[0116] Fig. 9 This is a specific timing diagram of the continuous read action based on the present embodiment. The area indicated by the dotted line in the figure indicates the state of release of latches L1 and L2. Even if rewritten, the data will not be destroyed. The readout of page P0 and page P1 is the same as the normal page readout, and page P0 and page P1 are read out from the memory cell array 110_1 and the memory cell array 110_2 at the same time. Continuous reading starts from page P2. When the output (input-output circuit 120) of the data of page P0 held in the first cache C0 of latch L2 is completed, in response to this, the data of page P1 of the first cache C0 of latch L1 is transferred to the first cache C0 of latch L2, and the data of the first 1 / 2 page of page P2 is read out from the memory cell array 110_1, which is transferred to the first cache C0 of latch L1 and held therein. The data transfer time from latch L1 to latch L2 is much shorter than the time required for array readout, and therefore latch L1 is released at the time when the array readout data is transferred to latch L1.

[0117] Next, in the output of the data of page P0 held in the second cache C1 of latch L2, the data of page P1 held in the first cache C0 of latch L2 is subjected to ECC processing. When the output of the data of page P0 held in the second cache C1 of latch L2 is completed, in response thereto, the data of page P1 of the second cache C1 of latch L1 is transferred to the second cache C1 of latch L2, and the data of the last 1 / 2 page of page P2 is read out from the memory cell array 110_2, which is transferred to the second cache C1 of latch L1 and held therein. Thereafter, the continuous reading of pages is performed in the same manner.

[0118] As a constraint for performing continuous reading, equation (4) needs to be satisfied.

[0119] tECC(1 / 2 page)<tDout(1 / 2 page)…(4)

[0120] tDout is determined by the frequency of the external clock signal ExCLK. In order to reduce tECC, the ECC circuit 130 may include a plurality of ECC circuits, and the plurality of ECC circuits may perform data error detection and correction in parallel.

[0121] Thus, in the continuous reading of the present embodiment, 1 / 2 page data is read from the memory cell array 110_1 and the memory cell array 110_2 at different timings. After the data of the first cache C0 of the latch L2 is output, the 1 / 2 page data read from the memory cell array 110_1 is transferred to the first cache C0 of the latch L1, and after the data of the second cache C1 of the latch L2 is output, the 1 / 2 page data read from the memory cell array 110_2 is transferred to the second cache C1 of the latch L1. Thus, the data retained in the latch L1 is prevented from being destroyed by the data read from the memory cell array due to the slow frequency of the external clock signal ExCLK in the conventional continuous reading operation, and the continuous reading of the page can be performed without being restricted by the frequency of the external clock signal ExCLK. In addition, it is not necessary to prepare a status register as in the conventional method, and the user does not need to switch the timing of array reading.

[0122] Furthermore, in the continuous readout of the present embodiment, the peak current during array readout can be reduced. In the conventional array readout, the bit lines of one page are precharged, thereby generating a large peak current. The memory cell array 110_1 and the memory cell array 110_2 are operated at separate timings to precharge the bit lines of 1 / 2 page, thereby reducing the peak current. As a result, the supply voltage inside the chip can be stabilized, and the reliability of the circuit operation can be improved.

[0123] Next, a modified example of the embodiment of the present invention is described. In the previous embodiment, the two arrays are formed on the same chip in a manner that the operations of the memory cell array 110_1 and the memory cell array 110_2 are functionally separated, but in this modified example, as shown in FIG. 10(A), the flash memory 100B includes two chips 300_1 and 300_2 in a manner that the two memory cell arrays are physically separated. The two chips 300_1 and 300_2 can be stacked or arranged in parallel. The internal pads 310_1 for multiple inputs and outputs formed on the chip 300_1 are electrically connected to the corresponding external terminals 330 for inputs and outputs via the internal wiring 320, and similarly, the internal pads 320_2 for multiple inputs and outputs formed on the chip 300_2 are electrically connected to the corresponding external terminals 330 for inputs and outputs via the internal wiring 320.

[0124] FIG10(B) is a block diagram showing the internal structure of each chip. Chip 300_1 includes: a memory cell array 340_1, which is formed with a plurality of NAND strings; a peripheral circuit 350_1, which is formed with a word line selection circuit or a page buffer / readout circuit, etc.; a controller 360_1, which controls the operation of chip 300_1; and an input / output circuit 370_1, which is connected to an internal pad 310_1. Another chip 300_2 has the same structure as chip 300_1.

[0125] The chips 300_1 and 300_2 are connected to the host computer 380 via the external terminal 330. The commands (read, program, erase, etc.) and addresses output from the host computer 380 are input to the chips 300_1 and 300_2 in a common manner via the external terminal 330. When the commands and addresses to be read continuously are input from the host computer 380, the controllers 360_1 and 360_2 are operated as follows. Fig. 9 As shown in the timing diagram shown in FIG. 1 , the control of continuous reading is performed in each chip 300_1 and chip 300_2. The controller 360_1 reads the first 1 / 2 page and outputs the read data from the external terminal 330 via the input / output circuit 370_1, and the controller 360_2 reads the last 1 / 2 page and outputs the read data from the external terminal 330 via the input / output circuit 370_2. In this way, the continuously read data of multiple pages are output from the external terminal 330.

[0126] Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the specific embodiments, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims.

Claims

1. A continuous read method, which is similar to a continuous read method for pages of a non-volatile flash memory, comprising: A first reading step of reading out first data of a 1 / 2 page from a first memory cell array and holding the read first data in a first holding circuit of a first holding unit; A second reading step of reading out second data of 1 / 2 page from the second memory cell array at a timing different from that of the first memory cell array, and holding the read second data in a second holding circuit of the second holding unit; a first output step of outputting first data in synchronization with a clock signal; and a second output step of outputting the second data continuously after outputting the first data in synchronization with the clock signal, The first holding component includes the first holding circuit and the third holding circuit, the second holding component includes the second holding circuit and the fourth holding circuit, and the first holding component and the second holding component are independent structures. During the period in which the first data held in the third holding circuit is outputted by the first outputting step, the second error detection and correction step performs error detection and correction on the second data of the next page held in the fourth holding circuit, The first error detection and correction step performs error detection and correction on the first data of the next page held in the third holding circuit while the second data held in the fourth holding circuit is outputted in the second output step.

2. The continuous readout method according to claim 1, further comprising: A first transmission step of transmitting the first data held in the first holding circuit to the third holding circuit; as well as a second transmission step, transmitting the second data held in the second holding circuit to the fourth holding circuit; After the first transfer step, the first data of the next 1 / 2 page read out in the first readout step is held in the first holding circuit. After the second transfer step, the second data of the next 1 / 2 page read out in the second readout step is held in the second holding circuit. a first error detection and correction step of performing error detection and correction on the first data held in the third holding circuit; and The second error detection and correction step performs error detection and correction on the second data held in the fourth holding circuit.

3. The continuous readout method according to claim 1, wherein: The first readout step reads out the first data of the first two pages in response to the first data held in the third holding circuit being outputted in the first output step, and the second readout step reads out the second data of the first two pages in response to the second data held in the fourth holding circuit being outputted in the second output step, wherein: The first output step and the second output step are to alternately and continuously output the first data and the second data from each of the plurality of external terminals.

4. A continuous read method, which is similar to a continuous read method for pages of a non-volatile flash memory, comprising: A readout step of independently reading out the first 1 / 2 page and the last 1 / 2 page of the memory cell array; A holding step of holding the first data of 1 / 2 page read out by the first array in a first holding circuit of the first holding unit, and holding the second data of 1 / 2 page read out by the second array in a second holding circuit of the second holding unit; as well as an output step, performing the reading step and the holding step by reading out a plurality of pages, and outputting the first data and the second data alternately in synchronization with a clock signal, The first holding component includes the first holding circuit and the third holding circuit, the second holding component includes the second holding circuit and the fourth holding circuit, and the first holding component and the second holding component are independent structures. During the period when the first data held in the third holding circuit is output, error detection and correction are performed on the second data of the next page held in the fourth holding circuit, During the period in which the second data held in the fourth holding circuit is output, error detection and correction are performed on the first data of the next page held in the third holding circuit.

5. A semiconductor device comprising: A first array reading unit reads data from a first NAND type memory cell array; A second array reading unit reads data from a second NAND type memory cell array; a first holding unit for holding the data read out by the first array reading unit; a second holding unit for holding the data read out by the second array reading unit; an output unit capable of outputting the data held by the first holding unit and the second holding unit in synchronization with a clock signal; and Control unit, which controls the reading action. When the control unit controls the continuous reading of pages, the first array reading unit reads out the first data of 1 / 2 page, the second array reading unit reads out the second data of 1 / 2 page, and the output unit continuously outputs the first data and the second data alternately. The first holding component and the second holding component are independent structures. The semiconductor device further includes an error detection and correction unit for performing error detection and correction of data, wherein the error detection and correction unit performs error detection and correction on the first data or the second data held in the second latch of the first holding unit and the second holding unit. The error detection and correction unit performs error detection and correction on the second data of the next page held in the second latch of the second holding unit while the output unit outputs the first data held in the second latch of the first holding unit. The error detection and correction unit performs error detection and correction on first data of a next page held in the second latch of the first holding unit while the output unit outputs the second data held in the second latch of the second holding unit.

6. The semiconductor device according to claim 5, wherein: The first holding unit includes: a first latch for holding the first data read by the first array read unit; and a second latch for holding the first data transmitted from the first latch, wherein after the first data is transmitted from the first latch to the second latch, the first data of the next page of 1 / 2 page read by the first array read unit is held in the first latch. The second holding unit includes: a first latch, which holds the second data read by the second array read-out unit; and a second latch, which holds the second data transmitted from the first latch. After the second data is transmitted from the first latch to the second latch, the second data of the next page of 1 / 2 page read by the second array read-out unit is held in the first latch.

7. The semiconductor device according to claim 5, wherein: The first array read-out unit responds to the first data held in the second latch of the first holding unit being output by the output unit to read out the first data of 1 / 2 page of the first two pages, and the second array read-out unit responds to the second data held in the second latch of the second holding unit being output by the output unit to read out the second data of 1 / 2 page of the first two pages.

8. The semiconductor device according to claim 5, wherein: The first memory cell array and the second memory cell array are formed on the same chip, or the first memory cell array and the second memory cell array are formed on different chips.

9. The semiconductor device according to claim 5, wherein: The output unit continuously and alternately outputs the first data and the second data from each of a plurality of external terminals.

10. The semiconductor device according to claim 5, wherein The control unit controls the read operation of the first memory cell array and the second memory cell array. The control unit determines whether it is a normal page read or a continuous read of multiple pages based on the received command. When it is determined to be a normal page read, one page of data is read from the first storage cell array and the second storage cell array at the same time, and the first holding unit and the second holding unit hold the read data. When it is determined to be a continuous read of multiple pages, 1 / 2 page of first data is read from the first storage cell array, and the first holding unit holds the read first data. Then, the remaining 1 / 2 page of second data is read from the second storage cell array, and the second holding unit holds the read second data.

11. A readout method, which is a readout method of a NAND flash memory, comprising the following steps: Receive commands; Based on the command, determining whether it is normal page reading or continuous reading of a plurality of pages; When it is determined that the page is read normally, the first memory cell array and the second memory cell array are accessed simultaneously, one page of data is read from the first memory cell array and the second memory cell array, and the read data is held in the first holding circuit and the second holding circuit; and When it is determined that a plurality of pages are read continuously, the first memory cell array and the second memory cell array are accessed separately, 1 / 2 page of first data is read from the first memory cell array, and the read first data is held in a first holding circuit of a first holding unit, and the remaining 1 / 2 page of second data is read from the second memory cell array, and the read second data is held in a second holding circuit of a second holding unit, The first holding component includes the first holding circuit, the second holding component includes the second holding circuit, and the first holding component and the second holding component are independent structures.

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