A permanent self-destructable ATD circuit module

Abstract

The present invention relates to an ATD circuit module capable of permanent self-destruction, and belongs to the field of chip data security technology. The ATD circuit module is integrated inside an SRAM chip, and includes an abnormality detection unit, a boost power supply unit, and an ATD logic unit. Among them, the abnormality detection unit is used to detect threatening operations on the SRAM chip; the boost power supply unit serves as a backup power supply for the abnormality detection unit and the ATD logic unit, and provides a high voltage signal for the ATD logic unit; the ATD logic unit contains an electronic fuse, which can be blown after receiving a high voltage signal, so that the ATD logic unit completely loses its working ability. The present invention can permanently self-destruct the SRAM chip after detecting that the SRAM is subjected to a threatening operation, thereby improving the security of the internal data of the SRAM.

Description

Technical Field

[0001] The invention belongs to the technical field of chip data security, and in particular relates to an ATD circuit module capable of permanent self-destruction. Background Art

[0002] Currently, the internal ATD (Address Translate Detector) module of large-capacity SRAM chips is used as the "interface" control module, which is responsible for the SRAM internal data writing and reading functions.

[0003] In order to protect data security and prevent illegal reading of chip data, one method is to cut off the power supply of the SRAM chip after detecting unauthorized illegal access to prevent attackers from stealing data.

[0004] However, due to the data residue problem in the existing SRAM chip technology, the information stored before power failure can be partially restored through the aging imprint method. This is because when a certain storage unit in the SRAM storage unit array stores fixed data for a long time, the two symmetrical MOS tubes will experience different degrees of BTI (Bias Temperature Instability) aging effects, resulting in permanent threshold voltage mismatch, resulting in a certain probability (about 10% to 20%) of reading the power-on initial value opposite to the original storage value after the unit is powered on. The user's usage traces are recorded invisibly through this physical level method. Therefore, the method of cutting off the SRAM power supply still has the security risk of data being read out.

[0005] Another way to protect chip data security is to set up an anti-attack detection and control circuit and a self-built power supply unit in the SRAM chip. When the anti-attack detection and control circuit detects a threat, it erases or rewrites the data in the SRAM. However, the disadvantage of this method is that the chip circuit system is relatively complex, there are many control signals, and the use of an additional power supply unit leads to large area overhead and power consumption. At the same time, after the SRAM is in standby for a long time, the anti-attack detection and control circuit will lose its detection function.

[0006] In order to prevent data from being illegally read from the SRAM chip, there is currently a technology for chip security reinforcement, which mainly targets the problem of anti-aging stamping and increases the number of transistors used in each storage unit. However, this also increases the signal ports of the SRAM chip, consumes a lot of chip area and power consumption, and the chip manufacturing cost will also increase. Summary of the invention

[0007] In view of the above deficiencies in the prior art, the present invention aims to provide an ATD circuit module that can permanently self-destruct. Starting from the ATD module inside the SRAM chip, by providing an ATD circuit module with a self-destruct function, the data security of the SRAM chip is improved, and at the same time, the problems of high power consumption and high manufacturing cost of the existing chips with security reinforcement function are solved.

[0008] A permanently self-destructible ATD circuit module comprises: an abnormality detection unit, a boost power supply unit and an ATD logic unit; wherein:

[0009] The abnormality detection unit provides an enable signal to the boost energy supply unit after detecting an abnormal signal when the SRAM chip is attacked;

[0010] The boost power supply unit provides a backup power supply for the abnormality detection module and the ATD logic module, and outputs a high voltage signal to the ATD logic module after receiving the enable signal;

[0011] The ATD logic unit is used to generate an ATD digital pulse signal, and after receiving the high voltage signal, it makes the ATD digital pulse signal invalid.

[0012] Furthermore, the abnormal signal includes abnormal voltage fluctuation, current fluctuation, temperature fluctuation and / or access signal fluctuation inside the chip.

[0013] Furthermore, the boost energy supply unit includes a charge pump, which is used to generate the high voltage signal.

[0014] Furthermore, the boost power supply unit includes a capacitor, which is electrically connected to the power port, and the capacitor serves as the backup power supply for the abnormality detection unit and the ATD logic unit.

[0015] Furthermore, the disabling of the ATD digital pulse signal includes narrowing, eliminating or fixing the pulse width of the ATD digital pulse signal to a fixed level.

[0016] Further, the ATD logic unit includes an electronic fuse, a weak pull-up circuit and at least one strong pull-down circuit; wherein the electronic fuse is located between the weak pull-up circuit and the at least one strong pull-down circuit, or the electronic fuse is located at the generation and output end of the ATD digital pulse signal.

[0017] Furthermore, the weak pull-up circuit is a PMOS transistor circuit; the gate of the PMOS transistor is connected to a chip select signal, and the chip select signal is connected to a read-write logic control circuit inside the SRAM chip; the source of the PMOS transistor is connected to a power supply; and the drain of the PMOS transistor is connected to a first end of an electronic fuse or a common source of the strong pull-down circuit.

[0018] Furthermore, the strong pull-down circuit is a circuit of multiple NMOS transistors; the gates of the multiple NMOS transistors are respectively connected to the address signal lines inside the SRAM chip; the common drains of the multiple NMOS transistors are grounded; and the common source of the multiple NMOS transistors is connected to the second end of the electronic fuse or the drain of the PMOS transistor.

[0019] Furthermore, the electronic fuse also has a third terminal for receiving the high voltage signal.

[0020] Furthermore, an SRAM chip includes an ATD circuit module capable of permanent self-destruction.

[0021] The beneficial effects of the present invention are as follows:

[0022] Since the ATD circuit module is also needed as the "interface" for reading data when illegally reading the internal data of the SRAM chip, the present invention sets an ATD circuit module with a self-destruction function in the chip. When the chip is illegally read, the "interface" of the internal storage array is automatically destroyed, making it impossible for the attacker to read data from the chip, thereby improving the overall security of the SRAM chip. The invention has a simple structure and has the function of permanent data destruction, while solving the problem of high power consumption and high chip manufacturing cost of traditional SRAM chips with security reinforcement function. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are only used to illustrate specific embodiments and are not considered to limit the present invention. In the entire drawings, the same reference symbols represent the same components. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0024] Figure 1 A structural diagram of an ATD circuit module capable of permanent self-destruction provided by one embodiment of the present invention;

[0025] Figure 2 ATD logic unit principle of an ATD circuit module capable of permanent self-destruction provided by an embodiment of the present invention Figure 1 ;

[0026] Figure 3ATD logic unit principle of an ATD circuit module capable of permanent self-destruction provided by an embodiment of the present invention Figure 2 ;

[0027] Figure 4 A timing diagram of a voltage fluctuation threat of an ATD circuit module capable of permanent self-destruction provided by an embodiment of the present invention;

[0028] Figure 5 A schematic diagram of an SRAM chip containing an ATD circuit module capable of permanent self-destruction provided in accordance with an embodiment of the present invention.

[0029] Reference numerals

[0030] 1. Abnormal detection unit; 2. Boost power supply unit; 3. ATD logic unit. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to describe the principles of the present invention, but it should be understood that these descriptions are only exemplary and are not intended to limit the scope of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field should fall within the scope of protection of the present invention.

[0032] In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts disclosed in the present invention. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0033] Embodiments of the invention

[0034] Traditional SRAM chips (static random access memory) use a global static design method, in which the operation of the memory is started by control signals such as address jumps, and no other dedicated control units are required. As a result, any jump of any input signal such as data or address bus will pass through subsequent circuits in sequence. Therefore, the fully static circuit implementation method will bring a lot of area and power consumption to the design of large-capacity SRAM.

[0035] The large-capacity SRAM chip uses the ATD (Address Translate Detector) module as the "interface" control module, which is responsible for the SRAM internal data writing and reading functions.

[0036] The working principle of the ATD module is: when the external input control signal of the SRAM chip, such as the chip select / read / write enable signal or the address signal, changes, it will immediately trigger the ATD module inside the SRAM chip to generate an ATD digital pulse signal. This pulse signal controls the sensitive amplifier and other modules inside the SRAM to complete the read and write functions of the SRAM storage cell array. Therefore, there is no need to wait for the synchronous clock signal, which greatly improves the operating speed of the circuit and realizes the asynchronous working mode of the SRAM chip.

[0037] A specific embodiment of the present invention discloses an ATD circuit module capable of permanent self-destruction. The ATD circuit module can lose its data interface function after detecting that an SRAM is subjected to illegal operation, so that the SRAM chip cannot perform normal data read and write operations and thus becomes permanently ineffective.

[0038] Figure 1 The structure diagram of the ATD circuit module that can permanently self-destruct is provided in this embodiment. Figure 1 As shown, the ATD circuit module includes an abnormality detection unit 1, a boost energy supply unit 2 and an ATD logic unit 3.

[0039] The abnormality detection unit 1 includes an abnormality detection circuit; the abnormality detection circuit is used to detect the threat signal of the SRAM chip and control the output enable signal; the threat signal includes abnormal voltage fluctuation, current fluctuation, temperature fluctuation and access signal fluctuation inside the chip; when the abnormality detection circuit detects the threat signal, it is determined that the SRAM chip is under threat attack, and the enable signal is changed from a low level to a high level, and output to the boost power supply unit 2 to start the self-destruction process.

[0040] The boost power supply unit 2 is used to provide a backup power supply to the abnormality detection unit 1 and the ATD logic unit 3, and to provide a high voltage to the ATD logic unit 3 for blowing the efuse electronic fuse. The boost power supply unit 2 includes a charge pump and a capacitor. On the one hand, the capacitor stores energy extracted from the power port as a backup power supply for the abnormality detection unit 1 and the ATD logic unit 3; on the other hand, after receiving the enable signal output by the abnormality detection unit 1, a high voltage signal is generated through the charge pump structure and output to the ATD logic unit 3, which is used to provide a blowing voltage for the efuse electronic fuse.

[0041] The ATD logic unit 3 includes an electronic fuse, a weak pull-up circuit and a strong pull-down circuit, which are used to control the read and write operations of the SRAM, and can blow the internal efuse electronic fuse after receiving a high voltage signal from the boost power supply unit 2, so that the ATD circuit module completely loses its working ability.

[0042] More specifically, the efuse electronic fuse is an electronic fuse that presents a low resistance state under normal working conditions. When receiving a signal of high voltage or high current density, the fuse blows and presents a high resistance state, and the original path becomes an open circuit.

[0043] Figure 2 and Figure 3 There are two optional circuit schematics for the ATD logic unit provided in this embodiment, each of which includes 1 efuse electronic fuse, n NMOS tubes and 1 PMOS tube, where n is the number of address signal lines of the SRAM chip.

[0044] like Figure 2 and Figure 3 As shown, the strong pull-down circuit includes a circuit composed of n NMOS tubes.

[0045] More specifically, n NMOS tubes are connected in a strong pull-down manner in the circuit, wherein the gate of each NMOS tube is connected to the address signal bus inside the chip. Under normal working conditions, the address signal bus generates an ATD digital pulse signal through n NMOS tubes, and the ATD digital pulse signal is used to drive the sensitive amplifier and precharge module in the SRAM chip.

[0046] In the weak pull-up circuit, the PMOS tube is connected in the circuit in a weak pull-up manner, and the chip select signal is connected to the gate of the PMOS tube; the chip select signal is controlled by the read-write logic control module inside the SRAM chip.

[0047] Under normal circumstances, the on-off of NMOS and PMOS can be controlled by controlling the address signal bus and the chip selection signal, so that the ATD logic unit can controllably output the ATD digital pulse signal.

[0048] Alternatively, if Figure 2 As shown, the two poles of the efuse electronic fuse are connected to the drain of the PMOS and the common source of the NMOS respectively, and the high voltage end is connected to the high voltage signal from the boost power supply unit. When the efuse electronic fuse receives the high voltage output by the boost power supply unit, it will melt and form a short circuit in the current path, making the pulse width of the ATD digital pulse signal output by the ATD logic unit narrow, disappear or be a fixed level. After the ATD logic unit fails, the SRAM chip fails because it cannot read and write data normally.

[0049] Optionally, another ATD logic unit schematic diagram of this embodiment is as follows: Figure 3 As shown, Figure 2 Compared with the circuit schematic shown, Figure 3 Only the installation position of the efuse electronic fuse in the circuit is changed.

[0050] like Figure 3As shown, the efuse electronic fuse is connected in series to the output end of the ATD digital pulse signal, and the high voltage end is electrically connected to the high voltage signal from the boost power supply unit. When the efuse electronic fuse receives the high voltage output by the boost power supply unit, it will melt and form a short circuit in the current path, so that the pulse width of the ATD digital pulse signal output by the ATD logic unit becomes narrower, disappears or is a fixed level. After the ATD logic unit fails, the SRAM chip fails because it cannot read and write data normally.

[0051] Figure 5 Schematic diagram of an SRAM chip containing an ATD circuit module capable of permanent self-destruction provided in this embodiment.

[0052] like Figure 5 As shown, the SRAM chip mainly includes a read-write logic control module, a sense amplifier, an address signal bus, a data input and output port, a row decoder, a column decoder, an SRAM storage cell array, a precharge module and an ATD circuit module.

[0053] More specifically:

[0054] The read / write logic control module is electrically connected to the data input / output port and is also electrically connected to the chip select signal input terminal of the SRAM chip;

[0055] The data input and output ports are electrically connected to the read-write logic control module and the sense amplifier, respectively, and are electrically connected to the data signal input terminal of the SRAM chip;

[0056] The sense amplifier is electrically connected to the data input and output ports and the column decoder respectively;

[0057] The column decoder is electrically connected to the address signal bus, the sense amplifier and the SRAM storage cell array respectively;

[0058] The address signal bus is electrically connected to the column decoder and the row decoder respectively, and is electrically connected to the address signal input terminal of the SRAM chip;

[0059] The row decoder is electrically connected to the address signal bus and the SRAM storage cell array respectively;

[0060] The SRAM storage cell array is electrically connected to the precharge module, the column decoder and the row decoder respectively.

[0061] The ATD circuit module is integrated into the SRAM chip, including:

[0062] The chip select signal terminal of the ATD logic unit in the ATD circuit module is electrically connected to the read-write logic control module inside the SRAM chip and is controlled by the chip select signal input terminal of the SRAM chip;

[0063] The address signal terminal of the ATD logic unit in the ATD circuit module is electrically connected to the address signal bus of the SRAM chip and is controlled by the address signal input terminal of the SRAM chip;

[0064] The ATD digital pulse signal end of the ATD logic unit in the ATD circuit module is electrically connected to the pre-charge module and the sensitive amplifier in the SRAM chip respectively. When the ATD digital pulse signal end normally sends out a digital pulse signal, it can control the pre-charge module and the sensitive amplifier to work normally, thereby enabling data reading and writing operations on the SRAM chip.

[0065] Taking the detection of voltage fluctuation threat as an example, combined with Figure 4 The timing diagram shown is used to illustrate the working process and timing of the ATD circuit module of this embodiment.

[0066] Figure 4 A timing diagram of the ATD circuit module capable of permanent self-destruction provided in this embodiment when a voltage fluctuation threat is detected.

[0067] like Figure 4 As shown, when the abnormal detection unit detects a threat signal of abnormal voltage fluctuation, the abnormal detection unit changes the enable signal from a low level to a high level and outputs it to the boost power supply unit; when the boost power supply unit detects that the enable signal jumps to a high level, after a fault-tolerant hesitation period, if the enable signal still remains at a high level, the boost power supply unit sets the output high voltage signal from a low level to a high level, so that the high voltage end of the efuse electronic fuse inside the ATD logic unit is loaded with a high level, and after a fuse time, the efuse electronic fuse is blown, and thereafter the ATD digital pulse signal continues to output a low level, the sensitive amplifier and pre-charge module in the SRAM chip fail and cannot be read normally, and the SRAM completes self-destruction.

[0068] The present invention provides an ATD circuit module capable of permanent self-destruction. Starting from the ATD module inside an SRAM chip, by providing an ATD security module with a self-destruction function, the data security of the SRAM chip is greatly improved. Meanwhile, the module has a simple structure and a permanent data destruction function, thereby solving the problems of high power consumption and high manufacturing cost of existing chips with security reinforcement functions.

[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be covered within the protection scope of the present invention.

Claims

1. A permanently self-destructible ATD circuit module, characterized in that: include: Abnormal detection unit, boost power supply unit and ATD logic unit; wherein, The abnormality detection unit provides an enable signal to the boost energy supply unit after detecting an abnormal signal when the SRAM chip is attacked; The boost power supply unit provides a backup power supply for the abnormality detection unit and the ATD logic module, and outputs a high voltage signal to the ATD logic module after receiving the enable signal; The ATD logic unit is used to generate an ATD digital pulse signal, and after receiving the high voltage signal, the ATD digital pulse signal is invalidated; The said making the ATD digital pulse signal ineffective includes making the pulse width of the ATD digital pulse signal narrow, disappear or become a fixed level; The ATD logic unit includes an electronic fuse, a weak pull-up circuit and at least one strong pull-down circuit; wherein the electronic fuse is located between the weak pull-up circuit and the at least one strong pull-down circuit, or the electronic fuse is located at the generation and output end of the ATD digital pulse signal.

2. The ATD circuit module capable of permanent self-destruction according to claim 1, characterized in that: The abnormal signal includes abnormal voltage fluctuation, current fluctuation, temperature fluctuation and / or access signal fluctuation inside the chip.

3. The ATD circuit module capable of permanent self-destruction according to claim 2, characterized in that: The boost power supply unit includes a charge pump, which is used to generate the high voltage signal.

4. The ATD circuit module capable of permanent self-destruction according to claim 3, characterized in that: The boost power supply unit includes a capacitor, which is electrically connected to the power port and serves as the backup power supply for the abnormality detection unit and the ATD logic unit.

5. The ATD circuit module capable of permanent self-destruction according to claim 1, characterized in that: The weak pull-up circuit is a PMOS transistor circuit; the gate of the PMOS transistor is connected to a chip select signal, and the chip select signal is connected to a read-write logic control circuit inside the SRAM chip; the source of the PMOS transistor is connected to a power supply; the drain of the PMOS transistor is connected to a first end of an electronic fuse or a common source of the strong pull-down circuit.

6. The ATD circuit module capable of permanent self-destruction according to claim 5, characterized in that: The strong pull-down circuit is a circuit of multiple NMOS transistors; the gates of the multiple NMOS transistors are respectively connected to the address signal lines inside the SRAM chip; the common drains of the multiple NMOS transistors are grounded; and the common sources of the multiple NMOS transistors are connected to the second end of the electronic fuse or the drain of the PMOS transistor.

7. The ATD circuit module capable of permanent self-destruction according to claim 6, characterized in that: The electronic fuse also has a third terminal for receiving the high voltage signal.

8. An SRAM chip comprising the ATD circuit module capable of permanent self-destruction according to any one of claims 1 to 7.

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