Memory device and method of manufacturing the same

Abstract

The present invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate and an electronic fuse structure. The substrate includes an array area and an electronic fuse area, and the electronic fuse area of ​​the substrate has an electronic fuse groove. The electronic fuse structure includes a first gate oxide layer, a plurality of doped regions, a dummy buried word line and an electronic fuse gate. The first gate oxide layer is formed on the surface of the electronic fuse groove. These doped regions are respectively formed in the substrate on opposite sides outside the electronic fuse groove and are in contact with the first gate oxide layer. The dummy buried word line is formed on the first gate oxide layer. The electronic fuse gate is formed on the dummy buried word line and is in contact with the first gate oxide layer. The dummy buried word line is electrically isolated from the electronic fuse gate.

Description

Technical Field

[0001] The invention relates to a memory device, and more particularly to a memory device with an electronic fuse structure and a manufacturing method thereof. Background Art

[0002] As electronic products become increasingly miniaturized, there is a demand for memory devices to be increasingly miniaturized. However, as memory devices become increasingly miniaturized, it becomes more difficult to improve the reliability and yield of memory devices.

[0003] For example, in a known dynamic random access memory (DRAM), an electronic fuse (eFuse) is usually formed between an array area and a peripheral area. An electronic fuse generally includes two conductive structures and a dielectric layer (e.g., a gate oxide layer) located between the two conductive structures. When a write operation is performed, a high bias is applied to the two conductive structures to cause the dielectric layer to break down, thereby forming a permanent conductive path in the dielectric layer. As the location where the dielectric layer breaks down is different, the current value that can be read from the electronic fuse structure is also different. As the length of the path connecting the location where the dielectric layer breaks down to the two conductive structures decreases, the resistance value read from the electronic fuse structure can be reduced, and the distribution of the resistance value read can be made more concentrated. In this way, it will be beneficial to improve the yield and reliability of the memory device. However, in the prior art, the location where the dielectric layer breaks down is random and difficult to control, and therefore, it is not conducive to improving the yield and reliability of the memory device.

[0004] Therefore, in the art, there is still a need for a memory device with high yield and high reliability and a method for forming the same. Summary of the invention

[0005] The embodiments of the present invention provide a memory device and a manufacturing method thereof, which can improve the resistance value and resistance value distribution of an electronic fuse structure, thereby improving the performance and yield rate of the memory device.

[0006] An embodiment of the present invention discloses a memory device, comprising: a substrate, wherein the substrate comprises an array region and an electronic fuse region, and an electronic fuse groove is provided in the electronic fuse region of the substrate; and an electronic fuse structure, comprising: a first gate oxide layer, conformally formed on the surface of the electronic fuse groove; a plurality of doped regions, respectively formed in the substrate on opposite sides outside the electronic fuse groove, wherein the doped regions are in contact with the first gate oxide layer; a dummy buried word line, formed on the first gate oxide layer; and an electronic fuse gate, formed on the dummy buried word line and in contact with the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the electronic fuse gate.

[0007] An embodiment of the present invention discloses a method for manufacturing a memory device, comprising: providing a substrate, wherein the substrate includes an array area and an electronic fuse area; forming an electronic fuse structure in the electronic fuse area of ​​the substrate, wherein forming the electronic fuse structure comprises: forming an electronic fuse groove in the electronic fuse area of ​​the substrate; forming a first gate oxide layer on the surface of the electronic fuse groove; forming a dummy buried word line on the first gate oxide; forming a plurality of doped regions in the substrate on opposite sides outside the electronic fuse groove, wherein the doped regions are in contact with the first gate oxide layer; and forming an electronic fuse gate on the dummy buried word line and in contact with the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the electronic fuse gate.

[0008] In the memory device provided by the embodiment of the present invention, by arranging the virtual buried word line and the insulating filling layer below the electronic fuse gate, the thickness of the electronic fuse gate can be controlled within a suitable range. Therefore, the resistance value and resistance value distribution of the electronic fuse structure can be improved. In this way, the performance and yield rate of the memory device can be improved. Furthermore, in the manufacturing method of the memory device provided by the embodiment of the present invention, the first half of the process of the electronic fuse area can be integrated with the process of the array area, and the second half of the process of the electronic fuse area can be integrated with the processes of the array area and the peripheral area at the same time. Therefore, the production cost and the complexity of the process can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0010] Figures 1A to 1F Schematic cross-sectional views of an array region and an electronic fuse region at various stages of a process according to some embodiments of the present invention.

[0011] Figures 2A to 2GSchematic cross-sectional views of electronic fuse structures at various stages of the process according to some embodiments of the present invention.

[0012] Figure 3 Schematic cross-sectional view of the array region of some embodiments of the present invention.

[0013] Figure 4 Schematic cross-sectional view of the peripheral area of ​​some embodiments of the present invention.

[0014] Figure Number:

[0015] 10: array area 129: patterned photoresist layer

[0016] 20: electronic fuse area 130: second insulating layer

[0017] 30: peripheral area 132: conductive layer

[0018] 100: electronic fuse structure 134: metal silicide layer

[0019] 102: substrate 136: source / drain contact structure

[0020] 103: first insulating layer 140: bit line contact structure

[0021] 104: gate oxide layer 145: second trench (word line trench)

[0022] 105: hard mask layer 150: gate structure

[0023] 105': hard mask pattern 155: third trench (electronic fuse trench)

[0024] 106: buried word line 165: electronic fuse gate accommodation space

[0025] 106': dummy buried word line 165A: opening

[0026] 106A: first conductive layer 165B: accommodation space

[0027] 106B: second conductive layer 175: opening

[0028] 107: mask pattern 185: source / drain contact hole

[0029] 108: doping region (source / drain structure) D1: thickness

[0030] 109: first sacrificial layer D2: depth

[0031] 110: insulation filling layer H1: first thickness

[0032] 111: second sacrificial layer H2: second thickness

[0033] 112: gate oxide layer P1: first spacing

[0034] 114: hard mask layer P2: second spacing

[0035] 115: first groove T1: thickness

[0036] 116: patterned photoresist layer W1: first width

[0037] 120: electronic fuse gate W2: second width

[0038] 122: metal silicide layer W3: third width (groove width)

[0039] 124: metal layer W4: fourth width

[0040] 126: Cover layer W5: Fifth width

[0041] 128: Hard mask layer DETAILED DESCRIPTION

[0042] In order to make the above and other purposes, features and advantages of the present invention more clearly understood, the following is a detailed description of the preferred embodiments with the accompanying drawings. Furthermore, repeated reference symbols and / or words may be used in different examples of the present invention. These repeated symbols or words are for the purpose of simplification and clarity, and are not used to limit the relationship between the various embodiments and / or the appearance structures.

[0043] Here, the terms "about" and "approximately" generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The quantities given here are approximate quantities, which means that the meaning of "about" and "approximately" can still be implied in the absence of specific instructions.

[0044] The present invention provides a memory device and a method for manufacturing the same. Figures 1A to 1F Schematic cross-sectional views of the array region 10 and the electronic fuse region 20 at various stages of the process in some embodiments of the present invention. It should be noted that the "electronic fuse structure" in this specification can be an electronic fuse structure that electrically insulates two conductive structures from each other by applying a voltage, or an anti-fuse structure that electrically connects two conductive structures to each other by applying a voltage.

[0045] Please refer to Figure 1A , a first insulating layer 103 and a hard mask layer 105 are formed on the substrate 102 . Then, a mask pattern 107 is formed on the hard mask layer 105 . Thereafter, a first sacrificial layer 109 is conformally formed on the mask pattern 107 .

[0046] The material of the substrate 102 may include silicon, a silicon-containing semiconductor, silicon on insulator (SOI), other suitable materials or a combination of the above materials. In the present embodiment, the substrate 102 is a silicon substrate. In some embodiments, a shallow trench isolation structure may be formed in the substrate 102. In some embodiments, other structures may also be formed in the substrate 102. For example, a p-type well, an n-type well or a conductive region may be formed in the substrate 102 by an implantation process. In order to simplify the description, the above-mentioned shallow trench isolation structure and other structures are not shown in the drawings, and the structures in the substrate 102 and the methods for forming them are not described in detail here. The material of the first insulating layer 103 may include oxides, nitrides, oxynitrides, carbides, other suitable insulating materials or a combination of the above. In the present embodiment, the first insulating layer 103 is silicon oxide formed by thermal oxidation.

[0047] The material of the hard mask layer 105 may include polysilicon, oxide, nitride, oxynitride, carbon-based materials (e.g., diamond-like carbon film), other suitable insulating materials, or a combination thereof. In the present embodiment, the hard mask layer 105 is a diamond-like carbon film. The material of the mask pattern 107 may include polysilicon, oxide, nitride, oxynitride, carbon-based materials (e.g., diamond-like carbon film), photoresist, other suitable mask materials, or a combination thereof. In order to have etching selectivity in the subsequent etching process, the material of the hard mask layer 105 may be different from the material of the mask pattern 107. In the present embodiment, the mask pattern 107 is silicon oxycarbide. The hard mask layer 105 and the mask pattern 107 may each independently be a single-layer structure formed of a single material or a multi-layer structure formed of a plurality of different materials.

[0048] The material of the first sacrificial layer 109 may include oxide, nitride, oxynitride or a combination thereof. In the present embodiment, the first sacrificial layer 109 is silicon oxide. The first sacrificial layer 109 may be formed by a suitable deposition process, for example, a chemical vapor deposition process, an atomic layer deposition process or a combination thereof.

[0049] Please still refer to Figure 1A In the array region 10, adjacent mask patterns 107 have a first pitch P1, and in the electronic fuse region 20, adjacent mask patterns 107 have a second pitch P2 that is smaller than the first pitch P1. Therefore, when the first sacrificial layer 109 fills the gaps between the mask patterns 107 in the electronic fuse region 20, the gaps between the mask patterns 107 in the array region 10 are not yet filled. That is, in the array region 10, the first sacrificial layer 109 forms a first trench 115 between adjacent mask patterns 107.

[0050] Please refer to Figure 1B, multiple etching processes may be performed to pattern the hard mask layer 105 to form multiple hard mask patterns 105'. In more detail, first, a first etching process is performed to partially remove the first sacrificial layer 109, so that the top surface of the mask pattern 107 is exposed, and the partially removed first sacrificial layer 109 forms a spacer on the sidewall of the mask pattern 107 in the array region 10. In addition, after the first etching process, in the array region 10, the top surface of the hard mask layer 105 located at the bottom of the first trench 115 is exposed; in the electronic fuse region 20, the top surface of the hard mask layer 105 located between the mask patterns 107 is not exposed, but is still covered by the first sacrificial layer 109. Next, a second etching process is performed to remove the mask pattern 107 and retain the first sacrificial layer 109. Next, the hard mask layer 105 is subjected to a third etching process using the first sacrificial layer 109 as an etching mask to transfer the pattern of the first sacrificial layer 109 to the hard mask layer 105. After the third etching process, in the array region 10, the hard mask pattern 105' has a first width W1, and in the electronic fuse region 20, the hard mask pattern 105' has a second width W2 greater than the first width W1.

[0051] The first etching process, the second etching process, and the third etching process may each independently include an anisotropic etching process. In order to form a pattern of the first sacrificial layer 109 for transfer to the hard mask layer 105, in the first etching process, the removal rate of the first sacrificial layer 109 may be much greater than the removal rate of the mask pattern 107 and the removal rate of the hard mask layer 105, and in the second etching process, the removal rate of the mask pattern 107 may be much greater than the removal rate of the first sacrificial layer 109.

[0052] Please refer to Figure 1C , a second sacrificial layer 111 is formed to cover the hard mask pattern 105' to fill the gap between adjacent hard mask patterns 105'. Then, the second sacrificial layer 111 is etched back to expose the top surface of the hard mask pattern 105'. The material and formation method of the second sacrificial layer 111 may be the same as or similar to the material and formation method of the first sacrificial layer 109, and will not be described in detail here. In the present embodiment, the second sacrificial layer 111 is silicon oxide and is formed by chemical vapor deposition.

[0053] Please refer to Figure 1D , a fourth etching process is performed to remove the hard mask pattern 105', and the second sacrificial layer 111 is retained to form a pattern formed by the second sacrificial layer 111. The fourth etching process may include an anisotropic etching process. In order to selectively remove the hard mask pattern 105', in the fourth etching process, the removal rate of the hard mask pattern 105' may be much greater than the removal rate of the second sacrificial layer 111.

[0054] Please refer to Figure 1E , using the second sacrificial layer 111 as an etching mask, a fifth etching process is performed on the substrate 102 and the first insulating layer 103 to form a plurality of second trenches 145 having a first width W1 in the array region 10 in the substrate 102, and a plurality of third trenches 155 having a second width W2 in the electronic fuse region 20 in the substrate 102. The fifth etching process may include an anisotropic etching process. In the second trenches 145, buried word lines 106 (shown in FIG. 1 ) are subsequently formed. Figure 1F Therefore, in this specification, the second trench 145 is also referred to as the “word line trench 145”. On the other hand, in the third trench 155, an electronic fuse structure (shown in FIG. 1 ) will be formed later. Figure 2G ). Therefore, in this specification, the third trench 155 is also referred to as “electronic fuse trench 155”.

[0055] To simplify the diagram, Figure 1F Only one word line trench 145 in the array region 10 and one electronic fuse trench 155 in the electronic fuse region 20 are shown. Figure 1F , a gate oxide layer 104 is conformally formed on the substrate 102, and the surfaces of the word line trench 145 and the electronic fuse trench 155 have the gate oxide layer 104. In the present embodiment, the gate oxide layer 104 is silicon oxide formed by a thermal oxidation method. Next, a first conductive layer 106A is conformally formed on the gate oxide layer 104. Next, a second conductive layer 106B is formed in the word line trench 145 and the electronic fuse trench 155 where the first conductive layer 106A has been formed. The top surfaces of the first conductive layer 106A and the second conductive layer 106B are lower than the top surface of the substrate 102.

[0056] The material of the first conductive layer 106A may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials or combinations thereof. The material of the second conductive layer 106B may include tungsten, aluminum, copper, gold, silver, alloys thereof, other suitable metal materials or combinations thereof. The first conductive layer 106A and the second conductive layer 106B may be independently formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, other suitable deposition processes or combinations thereof. In the present embodiment, the first conductive layer 106A is titanium nitride, and the second conductive layer 106B is tungsten. In some embodiments, the first conductive layer 106A and the second conductive layer 106B located in the word line trench 145 may be collectively referred to as "buried word line 106". Furthermore, the first conductive layer 106A and the second conductive layer 106B located in the electronic fuse trench 155 may be collectively referred to as "dummy buried word line 106'" to indicate that they are not electrically connected to other components.

[0057] Please refer to Figure 1F, the width of the electronic fuse trench 155 (i.e., the second width W2) is greater than the width of the word line trench 145 (i.e., the first width W1). Therefore, after the second conductive layer 106B fills up the word line trench 145, the top surface of the second conductive layer 106B in the word line trench 145 is higher than the top surface of the second conductive layer 106B in the electronic fuse trench 155. Then, the first conductive layer 106A and the second conductive layer 106B may be partially removed (e.g., by an etch-back process), so that the buried word line 106 in the word line trench 145 has a first thickness H1, and the dummy buried word line 106' in the electronic fuse trench 155 has a second thickness H2 that is less than the first thickness H1. In other words, the top surface of the buried word line 106 is higher than the top surface of the dummy buried word line 106'.

[0058] Please still refer to Figure 1F , filling insulating materials into the word line trench 145 and the electronic fuse trench 155 where the buried word line 106 and the dummy buried word line 106' are formed respectively. Then, the excess insulating material is removed by a planarization process (e.g., a chemical mechanical polishing process) to form an insulating filling layer 110 on the buried word line 106 and the dummy buried word line 106'. In the present embodiment, the planarization process also removes the gate oxide layer 104 located on the top surface of the substrate 102 to expose the top surface of the substrate 102. The material of the insulating filling layer 110 may include oxide, nitride, oxynitride, other suitable insulating materials or a combination thereof. In the present embodiment, the insulating filling layer 110 is silicon nitride.

[0059] Next, an implantation process is performed on the substrate 102 to form doped regions 108 in the substrate 102 on two opposite sides outside the word line trench 145, and doped regions 108 are formed in the substrate 102 on two opposite sides outside the electronic fuse trench 155. For simplicity of description, the doped regions 108 may also be referred to as “source / drain structures 108” in this specification.

[0060] Figure 2A to Figure 2G Schematic cross-sectional views of the electronic fuse structure 100 at various stages of the process of some embodiments of the present invention. Figure 2A to Figure 2G Only one electronic fuse structure 100 located in the electronic fuse region 20 is shown. Figure 2A , in the formation of Figure 1FAfter the structure shown, a gate oxide layer 112, a hard mask layer 114, and a patterned photoresist layer 116 are sequentially formed on the substrate 102. The patterned photoresist layer 116 has an opening 165A. The position of the opening 165A corresponds to the position of the electronic fuse trench 155. The material and formation method of the gate oxide layer 112 can be the same as or similar to the material and formation method of the gate oxide layer 104. The material and formation method of the hard mask layer 114 can be the same as or similar to the material and formation method of the hard mask layer 105. The material of the patterned photoresist layer 116 can be a known photoresist material.

[0061] Please refer to Figure 2B , using the patterned photoresist layer 116 as an etching mask, a sixth etching process is performed on the hard mask layer 105 and the second dielectric layer 112 to transfer the pattern of the opening 165A to the second dielectric layer 112. The sixth etching process may include an anisotropic etching process. Then, a seventh etching process is performed to partially remove the insulating filling layer 110 to form the electronic fuse gate accommodating space 165. Figure 2B As shown, the electronic fuse gate accommodating space 165 is located on the insulating filling layer 110 from which the first thickness D1 is removed, and includes an opening 165A and an accommodating space 165B having the first thickness D1 that are interconnected. The seventh etching process may include an isotropic etching process or an anisotropic etching process. During the seventh etching process, the removal rate of the insulating filling layer 110 is much greater than the removal rate of the first insulating layer 103 and the removal rate of the second dielectric layer 112. In this way, after partially removing the insulating filling layer 110, the gate oxide layer 104 and the gate oxide layer 112 can still be retained.

[0062] Please refer to Figure 2C , fill the electronic fuse gate accommodating space 165 with conductive material. Then, a planarization process is performed to remove excess conductive material to form the electronic fuse gate 120 in the electronic fuse gate accommodating space 165. The electronic fuse gate 120 is formed on the insulating filling layer 110 and is in contact with the gate oxide layer 104 and the gate oxide layer 112. The material of the electronic fuse gate 120 may include doped polysilicon, other suitable conductive materials, or a combination thereof. In the present embodiment, the material of the electronic fuse gate 120 is doped polysilicon.

[0063] In the present embodiment, the top surface of the electronic fuse gate 120 may be flush with the top surface of the gate oxide layer 112 and higher than the top surface of the doped region 108. In this way, it is beneficial to subsequently form a flat metal silicide layer 122. In other embodiments, an etch-back process (e.g., dry etching or wet etching) may be performed to remove excess conductive material, so that the top surface of the electronic fuse gate 120 may be lower than the top surface of the gate oxide layer 112 and flush with the top surface of the doped region. In this way, it is beneficial to reduce the operating voltage of the electronic fuse structure 100.

[0064] Please refer to Figure 2D , a metal silicide layer 122, a metal layer 124, a cap layer 126, a hard mask layer 128 and a patterned photoresist layer 129 are sequentially formed on the gate oxide layer 112 and the electronic fuse gate 120. The position of the patterned photoresist layer 129 corresponds to the position of the electronic fuse gate 120. The material of the metal silicide layer 122 may include a silicide of a metal (e.g., cobalt, tungsten, nickel, or a combination thereof). The material of the metal layer 124 may include cobalt, tungsten, nickel, other suitable metals, or a combination thereof. The material of the cap layer 126 may include an oxide, a nitride, a nitride oxide, other suitable insulating materials, or a combination thereof. In the present embodiment, the cap layer 126 is silicon nitride. The metal silicide layer 122, the metal layer 124 and the cap layer 126 may be independently formed by a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, other suitable deposition processes, or a combination thereof. The material and forming method of the hard mask layer 128 may be the same as or similar to the material and forming method of the hard mask layer 105. The material of the patterned photoresist layer 129 may be a known photoresist material.

[0065] Please refer to Figure 2E , an eighth etching process is performed using the patterned photoresist layer 129 as an etching mask to pattern the gate oxide layer 112, the metal silicide layer 122, the metal layer 124 and the cap layer 126, and remove the hard mask layer 128. The eighth etching process may include an anisotropic etching process. After the eighth etching process, the remaining gate oxide layer 112, the metal silicide layer 122, the metal layer 124 and the cap layer 126 are formed on the electronic fuse trench, and their positions correspond to the positions of the electronic fuse trenches. Furthermore, after the eighth etching process, the top surfaces of the substrate 102 and the source / drain structure 108 are exposed.

[0066] Please refer to Figure 2F, forming a second insulating layer 130 on the substrate 102. The top surface of the second insulating layer 130 may be coplanar with the top surface of the cap layer 126. The material of the second insulating layer 130 may include oxide, nitride, oxynitride, carbide, other suitable insulating materials or a combination thereof. In the present embodiment, the second insulating layer 130 is spin on glass (SOG). Next, a ninth etching process is performed to form an opening 175 in the cap layer 126 and to form a source / drain contact hole 185 in the second insulating layer 130. The opening 175 exposes the metal layer 124, and the source / drain contact hole 185 exposes the source / drain structure 108. The ninth etching process may include an anisotropic etching process. Furthermore, in order to ensure that the metal layer 124 and / or the source / drain structure 108 can be exposed, in some embodiments, the ninth etching process may be over etching.

[0067] Please refer to Figure 2G , fill the conductive material into the opening 175 and the source / drain contact hole 185. Then, a planarization process is performed to remove excess conductive material to form a conductive layer 132 in the opening 175, and a source / drain contact structure 136 is formed in the source / drain contact hole 185 to complete the electronic fuse structure 100. In the present embodiment, after the conductive material is filled into the source / drain contact hole 185, a heating process may be performed to form a metal silicide layer 134 between the source / drain contact structure 136 and the source / drain structure 108. The materials of the conductive layer 132 and the source / drain contact structure 136 may be the same as or similar to the material of the metal layer 124. The material of the metal silicide layer 134 may be the same as or similar to the material of the metal silicide layer 122. The electronic fuse gate 120 may be electrically connected to an external device through the metal silicide layer 122, the metal layer 124, and the conductive layer 132. Therefore, in this specification, the metal silicide layer 122 , the metal layer 124 , and the conductive layer 132 may be collectively referred to as an “electronic fuse contact structure”.

[0068] The width of the conductive layer 132 may be less than or equal to the width of the metal layer 124. In the present embodiment, the width of the conductive layer 132 is less than the width of the metal layer 124, thereby reducing the risk of short circuit between the metal layer 124 and the source / drain contact structure 136, thereby improving the yield of the memory device. In other embodiments, the width of the conductive layer 132 is equal to the width of the metal layer 124, thereby reducing the resistance value of the electronic fuse contact structure, thereby improving the performance of the memory device.

[0069] In such Figure 2G After the above-mentioned related processes are completed, other known processes may be performed to complete the memory device. In order to simplify the description, other known processes will not be described in detail here.

[0070] Figure 3 Schematic cross-sectional view of the array region 10 according to some embodiments of the present invention. Figure 4 Schematic cross-sectional view of the peripheral region 30 of some embodiments of the present invention. In some embodiments, the peripheral region 30 surrounds the array region 10, and the electronic fuse region 20 is located at the junction of the array region 10 and the peripheral region 30. In other embodiments, the array region 10, the electronic fuse region 20 and the peripheral region 30 can be arranged in any suitable arrangement according to design requirements. Figure 2G After the above-mentioned related processes are completed, the cross-sectional profiles of the array region 10, the electronic fuse region 20 and the peripheral region 30 are respectively shown in Figure 3 , Figure 2G and Figure 4 .

[0071] In the manufacturing method of the memory device provided in the present embodiment, the first half of the process of the electronic fuse region 20 can be integrated with the process of the array region 10, and the second half of the process of the electronic fuse region 20 can be integrated with the processes of the array region 10 and the peripheral region 30 at the same time. Therefore, the production cost and the complexity of the process can be reduced.

[0072] For more details, please refer to Figures 1A to 1F , the word line groove 145 located in the array area 10 and the electronic fuse groove 155 located in the electronic fuse area 20 are formed simultaneously in the same process, and the buried word line 106 located in the array area 10 and the dummy buried word line 106' located in the electronic fuse area 20 are formed simultaneously in the same process. In the known technology, in order to form an electronic fuse structure with a suitable size, an additional mask layer is usually used to shield the electronic fuse area when performing the process in the array area or the peripheral area. In other words, the process formulas of the array area, the electronic fuse area and the peripheral area are independent of each other. Therefore, the process complexity and production cost of the known technology are very high. In the manufacturing method of the memory device provided in the present embodiment, word line grooves 145 and electronic fuse grooves 155 with different widths can be formed simultaneously. In other words, in the case Figures 1A to 1F In the above process, the first half of the process of the electronic fuse area 20 can be integrated with the process of the array area 10. In this way, the process complexity and production cost can be reduced.

[0073] In some embodiments, Figures 1A to 1F In the above process, the peripheral region 30 is not affected (for example, the peripheral region 30 may be covered by a mask layer). Figures 1A to 1F The peripheral area 30 is not shown.

[0074] On the other hand, in Figure 2AIn the process described above, in the array region 10, the patterned photoresist layer 116 has openings (not shown) between adjacent buried word lines 106, and in the peripheral region 30, the patterned photoresist layer 116 has no openings. It should be noted that in the array region 10, the openings of the patterned photoresist layer 116 are not located directly above the buried word lines 106. Therefore, the electronic fuse gate 120 is not formed in the word line trench 145. Figure 2B In the process described above, in the array region 10, a bit line contact trench is formed between adjacent buried word lines 106. Figure 2C In the above process, in the array region 10, the conductive material filled into the bit line contact trench forms the bit line contact structure 140, and in the peripheral region 30, a conductive material layer is formed on the gate oxide layer 112. Figure 2D In the process described above, in the array region 10, the position of the patterned photoresist layer 129 corresponds to the position of the bit line contact structure 140, and in the peripheral region 30, the position of the patterned photoresist layer 129 corresponds to the position of the gate structure 150 to be formed subsequently. Figure 2E In the process described above, in the array region 10, a stacked structure including a metal silicide layer 122, a metal layer 124, and a cap layer 126 is formed on the bit line contact structure 140. In this step, the conductive material layer located in the peripheral region 30 is patterned to form a gate structure 150. Therefore, in the peripheral region 30, a stacked structure including a gate oxide layer 112, a gate structure 150, a metal silicide layer 122, a metal layer 124, and a cap layer 126 is formed on the substrate 102. Figure 2F In the above process, in the array region 10, no opening is formed in the second insulating layer 130. In this step, similar to the electronic fuse region 20, in the peripheral region 30, an opening is formed in the cap layer 126, and source / drain contact holes are formed in the second insulating layer 130. Figure 2G In the above process, the array region 10 is not affected (for example, the array region 10 may be covered by a mask layer), thus forming the following Figure 3 In this step, similar to the electronic fuse region 20, in the peripheral region 30, a conductive layer 132 is formed in the cap layer 126, a source / drain contact structure 136 is formed in the source / drain contact hole, and a metal silicide layer 134 is formed between the source / drain contact structure 136 and the source / drain structure 108. In some embodiments, the source / drain structure 108 located in the peripheral region 30 may be formed as follows: Figure 1F In some other embodiments, the source / drain structure 108 located in the peripheral region 30 may be formed in the following manner: Figure 2E The above process is followed by an additional implantation process.

[0075] The gate structure 150 located in the peripheral region 30 can be electrically connected to an external device through the metal silicide layer 122, the metal layer 124 and the conductive layer 132. Therefore, in this specification, the metal silicide layer 122, the metal layer 124 and the conductive layer 132 above the gate structure 150 located in the peripheral region 30 can also be collectively referred to as a “gate contact structure”.

[0076] As described above, according to the manufacturing method of the memory device provided in this embodiment, the bit line contact structure 140 and the electronic fuse gate 120 can be formed simultaneously in the array region 10 and the electronic fuse region 20, and the electronic fuse contact structure and the gate contact structure can be formed simultaneously in the electronic fuse region 20 and the peripheral region 30. In other words, in the case of Figures 2A to 2G In the above process, the latter half of the process of the electronic fuse region 20 can be integrated with the processes of the array region 10 and the peripheral region 30. In this way, the process complexity and production cost can be further reduced.

[0077] Some embodiments of the present invention provide a memory device. Figure 2G , Figure 3 and Figure 4 , the memory device includes a substrate 102, and the substrate 102 includes an array region 10, an electronic fuse region 20 and a peripheral region 30. Figure 1F and Figure 2G As shown, in the electronic fuse region 20, the memory device includes an electronic fuse structure 100. The electronic fuse structure 100 includes a gate oxide layer 104, a dummy buried word line 106' and an insulating filling layer 110 configured in an electronic fuse trench 155, and the gate oxide layer 104 is conformally formed on the surface of the electronic fuse trench 155, the dummy buried word line 106' is formed on the gate oxide layer 104, and the insulating filling layer 110 is formed on the dummy buried word line 106'. The electronic fuse trench 155 is formed in the substrate 102. The electronic fuse structure 100 also includes a gate oxide layer 112, a plurality of doped regions 108 and an electronic fuse gate 120. The gate oxide layer 112 has an opening 165A (indicated at Figure 2B The electronic fuse gate 120 is formed in the electronic fuse trench 155 and is located on the insulating filling layer 110 and is in contact with the gate oxide layer 104. The electronic fuse gate 120 is formed in the electronic fuse trench 155 and is located on the insulating filling layer 110 and is in contact with the gate oxide layer 104 and the gate oxide layer 112. The insulating filling layer 110 is configured to electrically isolate the electronic fuse gate 102 from the dummy buried word line 106'. In the present embodiment, the electronic fuse gate 120 is also formed in the opening 165A of the gate oxide layer 112, and the top surface of the electronic fuse gate 120 is coplanar with the top surface of the gate oxide layer 112.

[0078] The electronic fuse structure 100 further includes an electronic fuse contact structure formed on the electronic fuse gate 120. The electronic fuse contact structure includes a metal silicide layer 122, a metal layer 124, and a conductive layer 132 sequentially formed on the electronic fuse gate 120. In one embodiment, the conductive layer 132 is disposed in the opening of the cap layer 126, and the metal silicide layer 122 and the metal layer 124 are further extended and disposed on the gate oxide layer 112.

[0079] In order to facilitate the miniaturization of the device, the narrower the width of the word line groove 145, the better. However, the critical dimension of the patterning step for forming the opening 165A needs to be larger than the critical dimension of the word line groove 145 to reduce the operating voltage of the electronic fuse structure. If the width of the electronic fuse groove 155 is the same as the width of the word line groove 145, the width of the electronic fuse groove 155 will be smaller than the width of the opening 165. In this case, the conductive material filled in the electronic fuse gate accommodating space 165 is likely to remain on the top surface of the doped region 108, thereby causing a short circuit. In this way, the yield of the memory device will be reduced. On the other hand, if the width of the electronic fuse groove 155 is too small, it will be difficult to align the electronic fuse groove 155 and the opening 165A when forming the opening 165A. In this way, the impedance of the electronic fuse gate 120 will increase, and it may even be unable to contact the gate oxide layer 104, thereby causing the electronic fuse structure 100 to fail to work.

[0080] Please refer to Figure 1F In one embodiment, the ratio W2 / W1 of the second width W2 to the first width W1 is 2.0-5.0, which can facilitate the integration of the second half of the process of the electronic fuse area 20 with the processes of the array area 10 and the peripheral area 30, and can reduce or avoid the above-mentioned problems.

[0081] Please refer to Figure 2B After the gate oxide layer 104 is formed, the opening width of the electronic fuse trench 155 is the third width W3, and the third width W3 is greater than the fourth width W4 of the opening 165A. Therefore, the opening 165A of the gate oxide layer 112 is smaller than the bottom width of the electronic fuse gate 120 (i.e., the third width W3). In some embodiments, the protrusion width of the gate oxide layer 112 is defined as ((W3-W4) / 2), and the protrusion width is 5%-45% of the bottom width of the electronic fuse gate 120 (i.e., the third width W3). That is, the ratio of the fourth width W4 to the third width W3 is 0.1-0.9, which can help to concentrate the location where the breakdown occurs in the gate oxide layer 104.

[0082] Please refer to Figure 2GIn this embodiment, the width of the gate oxide layer 112 (ie, the fifth width W5) is greater than the thickness T1 of the gate oxide layer 104. Therefore, when the electronic fuse structure 100 is written, the gate oxide layer 104 is more likely to be broken down than the gate oxide layer 112.

[0083] On the other hand, Figure 2C As shown, in this embodiment, an electronic fuse gate 120 is disposed above the dummy buried word line 106' and the insulating filling layer 110. Therefore, the location where the breakdown occurs can be controlled to be located at the gate oxide layer 104 between the electronic fuse gate 120 and the source / drain structure 108. In this embodiment, the resistance value read from the electronic fuse structure can be reduced, and the distribution of the read resistance value can be made more concentrated. In this way, it will be beneficial to improve the yield and reliability of the memory device.

[0084] Please refer to Figure 2B and Figure 2C , the contact thickness between the electronic fuse gate 120 and the gate oxide layer 104 is a first thickness D1, the doped region 108 has a depth D2, and the thickness D1 is less than the depth D2. In order to effectively concentrate the location where the breakdown occurs and thus improve the resistance distribution of the electronic fuse structure, in some embodiments, the ratio D2 / D1 of the depth D2 to the first thickness D1 is 1.5-5.0.

[0085] In summary, in the memory device provided by the embodiment of the present invention, by setting the electronic fuse gate above the virtual buried word line and the insulating filling layer, the position where the gate oxide layer breaks down can be controlled within a specific range. Therefore, the resistance value and resistance value distribution of the electronic fuse structure can be improved. In this way, the performance and yield of the memory device can be improved. Furthermore, in the manufacturing method of the memory device provided by the embodiment of the present invention, the first half of the process of the electronic fuse area can be integrated with the process of the array area, and the second half of the process of the electronic fuse area can be integrated with the processes of the array area and the peripheral area at the same time. Therefore, the production cost and process complexity can be reduced.

[0086] Although the present invention has been disclosed as above with several preferred embodiments, they are not intended to limit the present invention. Any person with ordinary knowledge in the technical field may make any changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope defined by the claims.

Claims

1. A memory device, characterized in that: include: A substrate, wherein the substrate includes an array region and an electronic fuse region, and the electronic fuse region of the substrate has an electronic fuse trench; as well as An electronic fuse structure, comprising: a first gate oxide layer conformally formed on a surface of the electronic fuse trench; a plurality of doped regions, respectively formed in the substrate at two opposite sides outside the electronic fuse trench, wherein the plurality of doped regions are in contact with the first gate oxide layer; a dummy buried word line formed on the first gate oxide layer; and An electronic fuse gate is formed on the dummy buried word line and contacts the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the electronic fuse gate.

2. The memory device according to claim 1, wherein: The electronic fuse structure further includes an insulating filling layer disposed between the dummy buried word line and the electronic fuse gate, the contact thickness between the electronic fuse gate and the first gate oxide layer is a first thickness D1, and each of the plurality of doped regions has a depth D2 greater than the first thickness D1.

3. The memory device according to claim 2, wherein: A ratio D2 / D1 of the depth D2 to the first thickness D1 is 1.5-5.

0.

4. The memory device according to claim 1, wherein: The array region of the substrate has a word line groove, and further includes: a buried word line formed in the word line trench, wherein a top surface of the buried word line is higher than a top surface of the dummy buried word line, The word line trench has a first width W1, the electronic fuse trench has a second width W2, and a ratio W2 / W1 of the second width W2 to the first width W1 is 2.0-5.

0.

5. The memory device according to claim 1, wherein: The invention also includes a second gate oxide layer formed on the substrate, wherein the second gate oxide layer has an opening, the opening exposes the electronic fuse gate, and a width of the opening is smaller than a bottom width of the electronic fuse gate.

6. The memory device according to claim 5, characterized in that A ratio of the width of the opening to the bottom width of the e-fuse gate is 0.1 to 0.

9.

7. The memory device according to claim 5, wherein: A top surface of the electronic fuse gate is lower than or flush with a top surface of the second gate oxide layer.

8. The memory device according to claim 7, wherein: A top surface of the electronic fuse gate is higher than or flush with a top surface of each doping region.

9. The memory device according to claim 1, wherein: Also includes: an electronic fuse contact structure electrically connected to the electronic fuse gate, the electronic fuse contact structure comprising: a metal silicide layer formed on the electronic fuse gate; a metal layer formed on the metal silicide layer; and A conductive layer is formed on the metal layer, wherein a width of the conductive layer is less than or equal to a width of the metal layer.

10. A method for manufacturing a memory device, characterized in that: include: Providing a substrate, wherein the substrate includes an array region and an electronic fuse region; and An electronic fuse structure is formed in the electronic fuse region of the substrate, wherein forming the electronic fuse structure comprises: forming an electronic fuse trench in the electronic fuse region of the substrate; forming a first gate oxide layer on a surface of the electronic fuse trench; forming a dummy buried word line on the first gate oxide layer; forming a plurality of doped regions in the substrate at two opposite sides outside the electronic fuse trench, respectively, wherein the plurality of doped regions are in contact with the first gate oxide layer; and An electronic fuse gate is formed on the dummy buried word line and in contact with the first gate oxide layer, wherein the dummy buried word line is electrically isolated from the electronic fuse gate.

11. The method for manufacturing a memory device according to claim 10, wherein: Forming the electronic fuse structure further includes: After forming the dummy buried word line, forming an insulating filling layer on the dummy buried word line to electrically isolate the dummy buried word line from the electronic fuse gate. The contact thickness between the electronic fuse gate and the first gate oxide layer is a first thickness D1, and each doped region has a depth D2 greater than the first thickness D1.

12. The method for manufacturing a memory device according to claim 11, wherein: Also includes: After forming the insulating filling layer and before forming the electronic fuse gate, forming a second gate oxide layer on the substrate and the insulating filling layer; patterning the second gate oxide layer so that the second gate oxide layer has an opening; as well as The insulating filling layer is partially removed to reduce the first thickness of the insulating filling layer, so as to form an accommodating space in the electronic fuse groove that is interconnected with the opening. Wherein, forming the electronic fuse gate on the dummy buried word line includes forming the electronic fuse gate in the accommodating space, The opening exposes the electronic fuse gate, and a width of the opening is smaller than a bottom width of the electronic fuse gate.

13. The method for manufacturing a memory device according to claim 10, wherein: Also includes: forming a metal silicide layer on the electronic fuse gate; forming a metal layer on the metal silicide layer; forming a capping layer on the metal layer; patterning the metal silicide layer, the metal layer and the cap layer; forming an insulating layer on the substrate, and making the insulating layer coplanar with the cover layer; performing an etching process to form an opening in the cap layer, wherein the opening exposes the metal layer; as well as A conductive layer is formed in the opening, wherein a width of the conductive layer is less than or equal to a width of the metal layer, and wherein the metal silicide layer, the metal layer and the conductive layer constitute an electronic fuse contact structure.

14. The method for manufacturing a memory device according to claim 10, wherein: Also includes: forming a word line trench in the array region of the substrate, wherein the word line trench is formed simultaneously with the electronic fuse trench; as well as A buried word line is formed in the word line trench, wherein the buried word line and the dummy buried word line are formed simultaneously.

15. The method for manufacturing a memory device according to claim 14, wherein: The word line trench has a first width W1 , the electronic fuse trench has a second width W2 , and a ratio W2 / W1 of the second width W2 to the first width W1 is 2.0-5.

0.

16. The method for manufacturing a memory device according to claim 13, wherein: Also includes: forming a gate structure in a peripheral region of the substrate; as well as A gate contact structure is formed on the gate structure, wherein the gate contact structure and the electronic fuse contact structure are formed simultaneously.

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