Array substrate and manufacturing method thereof and display panel

Abstract

The present application is applicable to the field of display technology, and proposes an array substrate, including a base substrate, the base substrate including a first surface and a second surface arranged opposite to each other, and a plurality of through holes penetrating the first surface and the second surface are provided on the base substrate; the array substrate also includes a display circuit, which is arranged on the first surface, and the display circuit includes a signal line connected to a driving circuit and a thin film transistor connected to the signal line; the signal line has a proximal end close to the driving circuit and a distal end away from the driving circuit; an auxiliary circuit is arranged on the second surface and connected to the driving circuit, the impedance of the back circuit is less than the impedance of the signal line, and the back circuit is also connected to at least one thin film transistor arranged at the distal end of the signal line through a through hole. The present application also proposes a method for manufacturing an array substrate and a display panel. The present application solves the problem of abnormal screen display caused by signal attenuation of metal signal lines.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular relates to an array substrate and a manufacturing method thereof, and a display panel. Background Art

[0002] With the development of optoelectronic display technology and semiconductor manufacturing technology, Thin Film Transistor-Liquid Crystal Display (TFT-LCD) has become the mainstream technology of flat panel display with its advantages of lightness, energy saving, high display quality, and mature and stable manufacturing process. It is widely used in home appliances, computers, transportation, medical and other fields. TFT-LCD mainly includes an array substrate and a color filter (CF) substrate, as well as a liquid crystal layer (LCL) disposed between the array substrate and the color filter substrate. The array substrate is the core part of the display panel, and metal signal lines, TFT devices and pixel patterns are made on the array substrate.

[0003] As liquid crystal display technology matures, people have put forward higher requirements for liquid crystal displays, including high resolution, large size, high refresh rate, etc. Due to the impedance of the metal signal line on the array substrate, the signal will gradually attenuate when it is transmitted from one end of the metal signal line to the end. As the size of the panel increases, this attenuation is gradually amplified, resulting in a large difference in the signal between the near end and the end of the signal line, which in turn causes abnormal display of the panel. Summary of the invention

[0004] The present application provides an array substrate and a manufacturing method thereof, and a display panel, which at least solve the problem of abnormal picture display caused by signal attenuation of metal signal lines.

[0005] An embodiment of a first aspect of the present application provides an array substrate, comprising:

[0006] A substrate, comprising a first surface and a second surface arranged opposite to each other, wherein the substrate is provided with a plurality of through holes penetrating the first surface and the second surface;

[0007] A display circuit is provided on the first surface, wherein the display circuit comprises a signal line connected to a driving circuit and a thin film transistor connected to the signal line; the signal line has a proximal end close to the driving circuit and a distal end far away from the driving circuit;

[0008] An auxiliary circuit is arranged on the second surface and connected to the driving circuit. The impedance of the auxiliary circuit is smaller than the impedance of the signal line. The auxiliary circuit is also connected to at least one thin film transistor arranged at the far end of the signal line through the through hole.

[0009] In some embodiments, the driving circuit includes a gate driving unit and a data driving unit, the signal line includes a scan line connected to the gate driving unit and extending in a row direction and a data line connected to the data driving unit and extending in a column direction; at least one thin film transistor disposed at a remote end of the scan line is a first remote thin film transistor, and at least one thin film transistor disposed at a remote end of the signal line is a second remote thin film transistor;

[0010] The auxiliary circuit includes a plurality of back scan lines and a plurality of back data lines, each of the back scan lines connects the gate driving unit and at least one of the first remote thin film transistors in a row, and each of the back data lines connects the data driving unit and at least one of the second remote thin film transistors in a column.

[0011] In some embodiments, the display circuit includes at least two partitions, the scan lines and the data lines in each partition are independently connected to the drive circuit, and each partition is provided with at least one column of the first remote thin film transistors and at least one row of the second remote thin film transistors.

[0012] In some embodiments, the thin film transistor includes a gate disposed on the first surface, an active layer disposed on the gate, and a source and a drain disposed on the active layer; the second remote thin film transistor further includes a signal pad disposed on the first surface and electrically connected to the source;

[0013] The plurality of through holes on the substrate include a first through hole and a second through hole, the first through hole exposing the gate of the first remote thin film transistor, and the second through hole exposing the signal pad;

[0014] The back scan line is connected to the gate of the remote thin film transistor through the first through hole, and the back data line is connected to the signal pad of the remote thin film transistor through the second through hole.

[0015] In some embodiments, the array substrate further includes a first protection layer disposed between the back scan line and the back data line, and the first protection layer is provided with a via hole corresponding to and connected to the second through hole.

[0016] In some embodiments, the back scan line and the back data line are both made of transparent conductive film material, the line width of the back scan line is greater than the line width of the scan line, and the line width of the back data line is greater than the line width of the signal line.

[0017] In some embodiments, the thickness of the back scan line and the back data line ranges from The line widths of the back scan lines and the back data lines are greater than 30 μm to 50 μm.

[0018] The second aspect of the present application provides a method for manufacturing an array substrate, including:

[0019] Providing a substrate substrate, the substrate substrate comprising a first surface and a second surface disposed opposite to each other;

[0020] A display circuit is fabricated on the first surface, wherein the display circuit includes a signal line and a thin film transistor connected to the signal line; the signal line has a proximal end close to a driving circuit and a distal end far away from the driving circuit;

[0021] Making a plurality of through holes penetrating the first surface and the second surface on the base substrate, each of the through holes being arranged corresponding to one of the thin film transistors arranged at the far end of the signal line;

[0022] An auxiliary circuit is fabricated on the second surface, wherein the impedance of the auxiliary circuit is smaller than the impedance of the signal line, and the auxiliary circuit is connected to the thin film transistor disposed at the far end of the signal line through the through hole.

[0023] In some embodiments, the signal line includes a scan line for connecting a gate driving unit and a data line for connecting a data driving unit; at least one thin film transistor disposed at a remote end of the scan line is a first remote thin film transistor, and at least one thin film transistor disposed at a remote end of the signal line is a second remote thin film transistor;

[0024] Producing an auxiliary circuit on the second surface of the base substrate, comprising:

[0025] Depositing a first transparent conductive film layer on the second surface, and patterning the first transparent conductive film layer into a plurality of back scan lines, wherein the plurality of back scan lines are connected to corresponding first remote thin film transistors through some of the through holes;

[0026] Depositing a first protective layer on the second surface, and opening a plurality of via holes on the first protective layer by patterning, wherein the plurality of via holes are arranged correspondingly to and connected with the remaining through holes;

[0027] A second transparent conductive film layer is deposited on the first protective layer, and the second transparent conductive film layer is patterned to form a plurality of back data lines, and the back data lines are connected to the second remote thin film transistor through the via holes and the through holes.

[0028] An embodiment of a third aspect of the present application provides a display panel, including:

[0029] The array substrate as described in the first aspect;

[0030] an opposite substrate, arranged opposite to the array substrate; and

[0031] The liquid crystal layer is arranged between the array substrate and the opposite substrate.

[0032] The above-mentioned array substrate includes a base substrate, a display circuit arranged on the first surface of the base substrate, and an auxiliary circuit arranged on the second surface of the base substrate. The display circuit includes a signal line and a thin film transistor; the auxiliary circuit is connected to a driving circuit and at least one thin film transistor arranged at the far end of the signal line. Therefore, the auxiliary circuit can independently provide a signal to at least one thin film transistor at the far end of the signal line. The above-mentioned array substrate and display panel solve the problem of display abnormality caused by signal attenuation of the signal line and improve the display quality.

[0033] The manufacturing method of the above-mentioned array substrate first makes a display circuit on the first surface of the base substrate, and makes an auxiliary circuit on the second surface of the base substrate. The auxiliary circuit connects the thin film transistor at the far end of the signal line through the through hole on the base substrate. In this way, the auxiliary circuit can independently provide a signal to at least one thin film transistor at the far end of the signal line, thereby solving the problem of display abnormality caused by signal attenuation of the signal line and improving the display quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0035] Figure 1 is a schematic structural diagram of an array substrate provided in the first embodiment of the present application;

[0036] Figure 2 is a schematic structural diagram of a display area of ​​an array substrate provided in the first embodiment of the present application;

[0037] Figure 3 yes Figure 2 An enlarged schematic diagram of part A of the array substrate shown;

[0038] Figure 4 yes Figure 2 A cross-sectional view of the array substrate along line BB is shown;

[0039] Figure 5 yes Figure 3 The cross-sectional view of the array substrate along line CC is shown;

[0040] Figure 6 is a flow chart of a method for manufacturing an array substrate provided in a second embodiment of the present application;

[0041] Figure 7 It is a schematic diagram of the process of manufacturing a display circuit in the method for manufacturing an array substrate provided in an embodiment of the present application;

[0042] Figure 8 is a schematic diagram of the steps of making a through hole on a substrate provided in an embodiment of the present application;

[0043] Fig. 9 It is a schematic diagram of manufacturing a backside scanning line on a substrate provided in an embodiment of the present application;

[0044] Fig.10 It is a schematic diagram of manufacturing a first protective layer on a substrate provided in an embodiment of the present application;

[0045] Fig.11 It is a schematic diagram of manufacturing a backside data line on a substrate provided by an embodiment of the present application;

[0046] Fig.12 It is a schematic diagram of the structure of a display panel provided in the third embodiment of the present application.

[0047] The meanings of the marks in the figure are:

[0048] 100, array substrate; 10, base substrate; 11, first surface; 12, second surface; 13, through hole; 131, first through hole; 132, second through hole; 20, display circuit; 201, partition; 21, signal line; 211, scan line; 212, data line; 22, thin film transistor; 22a, first remote thin film transistor; 22b, second remote thin film transistor; 221, gate; 222, active layer; 2221, semiconductor Active layer; 2222, ohmic contact layer; 223, source; 224, drain; 225, signal pad; 23, gate insulating layer; 24, passivation layer; 25, pixel electrode; 30, auxiliary circuit; 31, back scan line; 32, back data line; 33, first protective layer; 331, via; 34, second protective layer; 41, gate drive unit; 42, data drive unit; 1, display panel; 200, opposite substrate; 300, liquid crystal layer. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings, i.e., embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0050] It should be understood that the terms "length", "width", "upper", "lower", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In order to illustrate the technical solution described in this application, the following is a description with reference to specific drawings and embodiments.

[0053] First embodiment

[0054] The first embodiment of the first aspect of the present application provides an array substrate. Figures 1 to 5 The array substrate 100 includes a base substrate 10 , a display circuit 20 and an auxiliary circuit 30 disposed on the base substrate 10 .

[0055] The base substrate 10 includes a first surface 11 and a second surface 12 that are opposite to each other. A plurality of through holes 13 penetrating the first surface 11 and the second surface 12 are disposed on the base substrate 10 .

[0056] The display circuit 20 is disposed on the first surface 11, and includes a signal line 21 connected to the driving circuit and a thin film transistor (TFT) 22 connected to the signal line 21. The display circuit 20 is used to transmit a driving signal provided by the driving circuit to the thin film transistor 22, so as to control the on and off of the thin film transistor 22 and provide a preset voltage to the thin film transistor 22. The signal line 21 has a proximal end close to the driving circuit and a distal end far away from the driving circuit.

[0057] It can be understood that the base substrate 10 is provided with a plurality of signal lines 21, each signal line 21 is respectively along Figure 1 The signal lines 21 are extended in the X direction (row direction) or the Y direction (column direction) as shown, and each signal line 21 is connected to a plurality of thin film transistors 22 in the same row or column.

[0058] Optionally, the driving circuit may be disposed on the array substrate 100 , for example, directly manufactured on the base substrate 10 or disposed on the base substrate 10 by binding.

[0059] The auxiliary circuit 30 is disposed on the second surface 12 and connected to the driving circuit. The impedance of the auxiliary circuit 30 is less than the impedance of the signal line 21. The auxiliary circuit 30 is also connected to at least one thin film transistor 22 disposed at the far end of the signal line 21 through the through hole 13, so that the auxiliary circuit 30 can provide an independent driving signal to the thin film transistor 22 at the far end of the signal line 21. For example, the auxiliary circuit 30 connects the last thin film transistor 22 at the far end of each signal line 21 (a thin film transistor 22 farthest from the driving circuit), or the auxiliary circuit 30 connects the last 2 to 5 thin film transistors 22 at the far end of the signal line 21. Since the auxiliary circuit 30 is disposed on the side of the base substrate 10 away from the display circuit 20, the auxiliary circuit 30 will not affect the routing of the display circuit 20.

[0060] The driving principle of the above-mentioned array substrate 100 is as follows: the display circuit 20 connects the driving circuit and the thin film transistor 22, and the display circuit 20 can transmit the voltage signal provided by the driving circuit to multiple thin film transistors 22; from the proximal end to the distal end of the signal line 21, the signal transmitted by the signal line 21 gradually attenuates; since at least one thin film transistor 22 arranged at the distal end of the signal line 21 is also connected to the auxiliary circuit 30, and the auxiliary circuit 30 is also connected to the driving circuit, therefore, the auxiliary circuit 30 can independently provide a signal to at least one thin film transistor 22 at the distal end of the signal line 21, thereby solving the problem of abnormal picture display caused by signal attenuation of the metal signal line; at the same time, the above-mentioned array substrate 100 can be applied to large-size display panels without splicing multiple display panels, thereby solving the problem of splicing gaps.

[0061] The above-mentioned array substrate 100 includes a base substrate 10, a display circuit 20 arranged on a first surface 11 of the base substrate 10, and an auxiliary circuit 30 arranged on a second surface 12 of the base substrate 10. The display circuit 20 includes a signal line 21 and a thin film transistor 22; the auxiliary circuit 30 is connected to a driving circuit and at least one thin film transistor 22 arranged at the far end of the signal line 21. Therefore, the auxiliary circuit 30 can independently provide a signal to at least one thin film transistor 22 at the far end of the signal line 21, thereby solving the problem of display abnormality of the display panel caused by signal attenuation of the signal line 21, improving the display quality, and eliminating the need to splice multiple display panels, thereby solving the problem of splicing gaps in large-size panels.

[0062] like Figure 1 and Figure 2As shown, the driving circuit includes a gate driving unit 41 and a data driving unit 42, and the signal line 21 includes a scanning line 211 connected to the gate driving unit 41 and extending in the row direction and a data line 212 connected to the data driving unit 42 and extending in the column direction; at least one thin film transistor 22 arranged at the far end of the scanning line 211 is a first far-end thin film transistor 22a, and at least one thin film transistor 22 arranged at the far end of the signal line 21 is a second far-end thin film transistor 22b.

[0063] The auxiliary circuit 30 may be connected to at least one of the first remote thin film transistor 22 a and the second remote thin film transistor 22 b to solve the attenuation problem of the scan line 211 and / or the data line 212 .

[0064] For example, the array substrate 100 includes M scan lines 211, the auxiliary circuit 30 includes M back scan lines 31, and each back scan line 31 is connected to one or more first remote thin film transistors 22a at the remote end of the corresponding scan line 211; for another example, the array substrate 100 includes N signal lines 21, the auxiliary circuit 30 includes N back data lines 32, and each back data line 32 is connected to one or more second remote thin film transistors 22b at the remote end of the corresponding signal line 21.

[0065] In some embodiments, the auxiliary circuit 30 includes a plurality of back scan lines 31 and a plurality of back data lines 32, each back scan line 31 connects the gate driving unit 41 and at least one first remote thin film transistor 22a in a row, and each back data line 32 connects the data driving unit 42 and at least one second remote thin film transistor 22b in a column. In this way, the auxiliary circuit 30 can solve the attenuation problem of the scan line 211 and the signal line 21 at the same time.

[0066] In some embodiments, Figure 1 and Figure 2 As shown, the display circuit 20 includes at least two partitions 201 , and each partition 201 is provided with at least one column of first remote thin film transistors 22 a and at least one row of second remote thin film transistors 22 b .

[0067] Figure 2 The display area of ​​an array substrate 100 is schematically shown. In this embodiment, the display circuit 20 includes four partitions 201. The scan lines 211 and the data lines 212 in each partition are independently connected to the driving circuit, that is, the scan lines 211 in each partition 201 are connected to the gate driving unit 41 and a row of thin film transistors 22 in the partition 201, and the data lines 212 in each partition 201 are connected to the data driving unit 42 and a column of thin film transistors 22 in the partition 201.

[0068] Therefore, at least one column of first remote thin film transistors 22a and at least one row of second remote thin film transistors 22b are provided in each partition 201. Accordingly, the auxiliary circuit 30 includes a plurality of back scan lines 31 and a plurality of back data lines 32 corresponding to each partition 201. Figure 1 As shown, the last column of thin film transistors 22 away from the gate driving unit 41 in each partition 201 is a first remote thin film transistor 22a, and the last row of thin film transistors 22 away from the data driving unit 42 in each partition 201 is a second remote thin film transistor 22b. It can be understood that the last multiple columns (for example, 1 to 5 columns) of thin film transistors 22 away from the gate driving unit 41 in each partition 201 can be further used as the first remote thin film transistors 22a connected to the back scan line 31, and the last multiple rows (for example, 1 to 5 rows) of thin film transistors 22 away from the data driving unit 42 in each partition 201 can be used as the second remote thin film transistors 22b connected to the back data line 32.

[0069] By adopting the above technical solution, the display line 20 is set to multiple partitions 201, which can further reduce the signal attenuation and display distortion problems of the scan line 211 and the data line 212; the above array substrate 100 is suitable for large-size display panels and does not need to adopt a spliced ​​display screen solution.

[0070] Figures 3 to 5 The thin film transistor 22 at the intersection of the last row of scan lines 211 and the last column of data lines 212 in each partition 201 is shown. The thin film transistor 22 also serves as the first remote thin film transistor 22a and the second remote thin film transistor 22b. Therefore, the thin film transistor 22 is connected to the back scan line 31 and the back data line 32 at the same time. Please refer to Figure 1 For example, a partition 201 includes only one column of first remote thin film transistors 22a and one row of second remote thin film transistors 22b. Except for the thin film transistors 22 at the intersection of the last row of scan lines 211 and the last column of data lines 212, the remaining first remote thin film transistors 22a are only connected to the back scan lines 31, and the remaining second remote thin film transistors 22b are only connected to the back data lines 32.

[0071] Please also refer to Figures 3 to 5 The thin film transistor 22 includes a gate electrode 221 disposed on the first surface 11, an active layer 222 disposed on the gate electrode 221, and a source electrode 223 and a drain electrode 224 disposed on the active layer 222; the second remote thin film transistor 22b also includes a signal pad 225 disposed on the first surface 11 and electrically connected to the source electrode 223.

[0072] Optionally, the active layer 222 includes a semiconductor active layer 2221 and an ohmic contact layer 2222 which are stacked.

[0073] The plurality of through holes 13 on the base substrate 10 include a first through hole 131 and a second through hole 132 , wherein the first through hole 131 exposes the gate 221 of the first remote thin film transistor 22 a , and the second through hole 132 exposes the signal pad 225 ;

[0074] The back scan line 31 is connected to the gate electrode 221 of the first remote thin film transistor 22 a through the first through hole 131 , and the back data line 32 is connected to the signal pad 225 of the second remote thin film transistor 22 b through the second through hole 132 .

[0075] By adopting the above technical solution, the back scan line 31 can be connected to the first remote thin film transistor 22a through the first through hole 131 to independently drive the first remote thin film transistor 22a; the back data line 32 can be connected to the second remote thin film transistor 22b through the second through hole 132 to independently drive the second remote thin film transistor 22b.

[0076] like Figure 5 As shown, the array substrate 100 further includes a gate insulating layer 23 disposed above the gate electrode 221, a passivation layer 24 disposed above the source electrode 223 and the drain electrode 224, and a pixel electrode 25 disposed above the passivation layer 24 and connected to the drain electrode 224 through a connecting hole 13 on the passivation layer 24. In order to dispose the signal pad 225 on the first surface 11, a third through hole is disposed on the gate insulating layer 23, and the signal pad 225 is disposed in the third through hole and connected to the source electrode 223.

[0077] In some embodiments, the array substrate 100 further includes a first protective layer 33 disposed between the back scan line 31 and the back data line 32, and a via hole 331 corresponding to and connected to the second through hole 132 is opened on the first protective layer 33. The first protective layer 33 plays an insulating role between the back scan line 31 and the back data line 32; the back data line 32 can be connected to the signal pad 225 in the second remote thin film transistor 22b through the via hole 331 on the first protective layer 33 and the second through hole 132 on the base substrate 10.

[0078] Optionally, the array substrate 100 further includes a second protective layer 34 covering the back data lines 32 , so that the first protective layer 33 and the second protective layer 34 can protect the back scan lines and the back data lines 32 from being scratched.

[0079] In some embodiments, the back scan line 31 and the back data line 32 are both made of transparent conductive film material, such as ITO (transparent indium tin oxide). In this way, the back scan line 31 and the back data line 32 will not block light, thereby avoiding reducing the light transmittance of the display panel; and the back scan line 31 and the back data line 32 can both obtain lower impedance.

[0080] Furthermore, the line width of the back scan line 31 is greater than the line width of the scan line 211, and the line width of the back data line 32 is greater than the line width of the signal line 21. In this way, the impedance of the back scan line 31 can be further made smaller than the impedance of the scan line 211, and the impedance of the back data line 32 can be further made smaller than the impedance of the signal line 21.

[0081] In order to make the impedance of the auxiliary circuit 30 smaller than the impedance of the signal line 21, optionally, the line width of the back scan line 31 is larger than the line width of the scan line 211, and the line width of the back data line 32 is larger than the line width of the back data line 32, so that the impedance of the back scan line 31 and the back data line 32 is smaller. It can be understood that the impedance of the auxiliary circuit 30 can also be adjusted by adjusting the material of the back scan line 31 and the back data line 32 to achieve the impedance of the auxiliary circuit 30 is smaller than the impedance of the signal line 21. Optionally, the line width of the back scan line 31 and the back data line 32 depends on the pixel size, the line width of the scan line 211 and the data line 212 is about one tenth to one twentieth of the pixel width, and the line width of the back scan line 31 and the back data line 32 can be slightly smaller than the pixel width at most, so that the impedance of the back scan line and the back data line 32 is much smaller than the scan line 211 and the data line 212.

[0082] In some embodiments, the thickness range of the back scan line 31 and the back data line 32 is (Angstrom), the line width of the back scan line 31 and the back data line 32 is greater than 30μm, and further, the line width of the back scan line 31 and the back data line 32 can be greater than 50μm. In this way, it can be ensured that the back scan line 31 and the back data line 32 have a lower impedance. It can be understood that the range of the line width of the back scan line 31 and the back data line 32 is not limited to this, as long as it is greater than the scan line 211 and the data line 212 and less than the pixel width.

[0083] Optionally, the diameter of the first through hole 131 is greater than 3 times the line width of the scan line 211 and smaller than the diameter of the gate 221 in the first remote thin film transistor 22a, and the diameter of the second through hole 132 is greater than 3 times the line width of the signal line 21 and smaller than the diameter of the signal pad 225 in the second remote thin film transistor 22b.

[0084] Second embodiment

[0085] The second embodiment of the second aspect of the present application provides a method for manufacturing an array substrate. Figures 1 to 6, the manufacturing method of the array substrate includes the following steps.

[0086] Step S110: providing a base substrate 10 , wherein the base substrate 10 comprises a first surface 11 and a second surface 12 arranged opposite to each other.

[0087] The base substrate 10 may be a transparent glass substrate, but is not limited thereto.

[0088] Step S120 : manufacturing the display circuit 20 on the first surface 11 .

[0089] The display circuit 20 includes a signal line 21 and a thin film transistor 22 connected to the signal line 21 ; the signal line 21 has a proximal end close to the driving circuit and a distal end far away from the driving circuit.

[0090] Specifically, the signal line 21 includes a scan line 211 for connecting to the gate driving unit 41 and a data line 212 for connecting to the data driving unit 42; at least one thin film transistor 22 disposed at the far end of the scan line 211 is a first far-end thin film transistor 22a, and at least one thin film transistor 22 disposed at the far end of the signal line 21 is a second far-end thin film transistor 22b.

[0091] Step S130 : manufacturing a plurality of through holes 13 penetrating the first surface 11 and the second surface 12 on the base substrate 10 .

[0092] Each through hole 13 is provided corresponding to a thin film transistor 22 provided at the far end of the signal line 21. Specifically, each through hole 13 is provided corresponding to a first far end thin film transistor 22a and a second far end thin film transistor 22b. There is no unique method for making the through hole 13. For example, if the base substrate 10 is a glass substrate, the through hole 13 is made by a hydrofluoric acid etching method; if the base substrate 10 is a flexible substrate, the through hole 13 is made by a laser opening method. It is understood that the glass substrate and the flexible substrate may also use other methods to make the through hole 13, without limitation thereto.

[0093] Step S140 : manufacturing an auxiliary circuit 30 on the second surface 12 , wherein the auxiliary circuit 30 is connected to the thin film transistor 22 disposed at the far end of the signal line 21 through the through hole 13 .

[0094] The impedance of the auxiliary line 30 is smaller than the impedance of the signal line 21 .

[0095] After the auxiliary circuit 30 is fabricated on the second surface 12 , the auxiliary circuit 30 is connected to the thin film transistor 22 at the far end of the signal line 21 through the through hole 13 , that is, the auxiliary circuit 30 is connected to the first far end thin film transistor 22 a or the second far end thin film transistor 22 b through the through hole 13 .

[0096] The manufacturing method of the above-mentioned array substrate 100 first makes a display circuit 20 on the first surface 11 of the base substrate 10, and makes an auxiliary circuit 30 on the second surface 12 of the base substrate 10. The auxiliary circuit 30 connects the thin film transistor 22 at the far end of the signal line through the through hole 13 on the base substrate 10. In this way, the auxiliary circuit 30 can independently provide a signal to at least one thin film transistor 22 at the far end of the signal line 21, thereby solving the problem of display abnormality of the display panel caused by signal attenuation of the signal line 21, improving the display quality, and eliminating the need to splice multiple display panels, thereby solving the problem of splicing gaps in large-size panels.

[0097] Figures 7 to 11 Taking the thin film transistor 22 at the intersection of the last row of scan lines 211 and the last column of data lines 212 as an example, the manufacturing process of the array substrate is illustrated.

[0098] Please refer to Figure 7 , step S120 includes the following sub-steps.

[0099] like Figure 7 As shown in (a), first, a gate electrode 221 is manufactured on a base substrate 10 .

[0100] Specifically, the first metal layer (M1) is deposited by physical vapor deposition. The material of the first metal layer can be a metal such as Cu, Al, Mo, or a composite layer structure of multiple metals. The material of the first metal layer has good electrical conductivity, good adhesion to the substrate 10, and a simple patterning method. After the first metal layer is deposited, the first metal layer is patterned by a yellow light process (coating, exposure, development, etching, and degumming) to form a scanning line 211 and a gate 221. The thickness of the gate 221 can be

[0101] like Figure 7 As shown in (b), a gate insulating layer 23 is formed above the base substrate 10 and the gate 221.

[0102] Specifically, the gate insulating layer 23 is deposited by chemical vapor deposition, and the material of the gate insulating layer 23 can be SiO 2 or SiN X , thickness controlled at Then, the photoresist is spin-coated, and the photoresist is exposed and developed through a designed mask plate to form a third through hole in the gate insulating layer 23 .

[0103] like Figure 7 As shown in FIG. 5( c ), an active layer 222 is formed on the gate insulating layer 23 .

[0104] Specifically, on the basis of the gate insulating layer 23, a semiconductor active layer 2221 and an ohmic contact layer 2222 are deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and then the semiconductor active layer 2221 and the ohmic contact layer 2222 are patterned by a yellow light process (coating, exposure, development, etching, and degumming). Among them, the material of the semiconductor active layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), metal oxide semiconductor materials, etc. Amorphous silicon (a-Si) and polycrystalline silicon (p-Si) are usually deposited by chemical vapor deposition (CVD) to prepare thin films, and metal oxide semiconductor materials are usually deposited by physical vapor deposition (PVD) to prepare thin films. The thickness of the semiconductor active layer is controlled to be 200 Å / s. The purpose of the ohmic contact layer is to ensure good ohmic contact between the semiconductor active layer and the source and drain electrodes 224 and reduce impedance. It is mainly formed by doping a-Si / p-Si with phosphorus to form an N-type conductor. Its thickness is controlled to be

[0105] like Figure 7 As shown in (d), a source electrode 223 and a drain electrode 224 are fabricated on the active layer 222 .

[0106] Specifically, the second metal layer (M2) is deposited by physical vapor deposition technology, and its thickness is controlled within The second metal layer is patterned by a photolithography process (coating, exposure, development, etching, and de-bonding) to obtain a source electrode 223 and a drain electrode 224 . In this step, the source electrode 223 is deposited on the base substrate 10 through a third through hole in the gate insulating layer 23 to form a signal pad 225 .

[0107] like Figure 7 As shown in (e), a passivation layer 24 is formed on the source electrode 223 and the drain electrode 224.

[0108] Specifically, the passivation layer 24 is deposited by chemical vapor deposition. The passivation layer 24 serves as an upper protective layer. The material of the passivation layer 24 can be SiO 2 or SiN X , thickness controlled at After the passivation layer 24 is deposited, a via hole is provided in the passivation layer 24 to expose a portion of the drain electrode 224 .

[0109] like Figure 7 As shown in FIG. 5( f ), a pixel electrode 25 is formed on the passivation layer 24 .

[0110] Specifically, a transparent conductive layer is deposited on a whole surface through a physical or chemical vapor deposition process, and the material of the transparent conductive layer is, for example, ITO; then, the transparent conductive layer is patterned through photoresist coating, exposure, development, etching and other techniques to obtain a pixel electrode 25, and the pixel electrode 25 is electrically connected to the drain 224.

[0111] Please refer to Figure 7 and Figure 8 Step S130 specifically includes: opening holes at positions of the base substrate 10 corresponding to the gate electrode 221 of the first remote thin film transistor 22a and the signal pad 225 of the second remote thin film transistor 22b to obtain the first through hole 131 and the second through hole 132.

[0112] In some embodiments, step S140 of manufacturing the auxiliary circuit 30 on the second surface 12 of the base substrate 10 includes the following sub-steps.

[0113] First, if Fig. 9 As shown, a first transparent conductive film layer is deposited on the second surface 12 and patterned to form a plurality of back scan lines 31 ; the plurality of back scan lines 31 are connected to corresponding first remote thin film transistors 22 a through some through holes 13 .

[0114] Specifically, a first transparent conductive layer thin film is deposited on the back of the substrate by physical or chemical vapor deposition process, and then the transparent conductive layer is patterned by photoresist coating, exposure, development, etching and other technologies to obtain the back scanning line 31, and connected to the gate 221 of the first remote thin film transistor 22a through the first through hole 131. The first transparent conductive layer thin film can be made of ITO, and the thickness is controlled to be To ensure a low impedance, the line width of the back scan line 314 may be greater than 30 μm.

[0115] Then, if Fig.10 As shown, a first protective layer 33 is deposited on the second surface 12 , and a plurality of via holes 331 are opened on the first protective layer 33 by patterning. The plurality of via holes 331 are arranged correspondingly and connected with the remaining through holes 13 .

[0116] Specifically, a first protective layer 33 is deposited by chemical vapor deposition, and then patterned by photoresist coating, exposure, development, etching and other techniques. The first protective layer 33 may be made of SiO 2 or SiN X , thickness controlled at

[0117] Then, if Fig.11 As shown, a second transparent conductive film layer is deposited on the first protective layer 33 and patterned to form a plurality of back data lines 32 . The back data lines 32 are connected to the second remote thin film transistor 22 b through the vias 331 and the through holes 13 .

[0118] Specifically, a second transparent conductive layer is deposited on the back of the substrate by physical or chemical vapor deposition process, and then the second transparent conductive layer is patterned by photoresist coating, exposure, development, etching and other techniques to obtain the back data line 32, and connected to the signal pad 225 through the via hole 331 and the second through hole 132; the second transparent conductive layer can be made of ITO, and the thickness is controlled to be To ensure a low impedance, the line width of the back data line 32 may be greater than 30 μm.

[0119] Next, a second protective layer 34 is deposited by chemical vapor deposition, and then patterned by photoresist coating, exposure, development, etching and other techniques. The material of the second protective layer 34 can be SiO 2 or SiN X , thickness controlled at The second protection layer 34 covers the back data line 32 to protect the back data line 32 .

[0120] Third embodiment

[0121] The third embodiment of the third aspect of the present application provides a display panel. Fig.12 The display panel 1 includes an array substrate 100 as in the first aspect, an opposing substrate 200 arranged opposite to the array substrate 100, and a liquid crystal layer 300 arranged between the array substrate 100 and the opposing substrate 200, wherein the opposing substrate 200 may be a color filter substrate provided with a color filter film, but is not limited thereto. For example, the color filter film may also be provided on the array substrate 100.

[0122] The display panel 1 solves the problems of abnormal picture display and splicing gaps caused by signal attenuation of metal signal lines.

[0123] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An array substrate, comprising a base substrate, wherein the base substrate comprises a first surface and a second surface arranged opposite to each other, characterized in that: The base substrate is provided with a plurality of through holes penetrating the first surface and the second surface; The array substrate further includes: A display circuit is provided on the first surface, wherein the display circuit comprises a signal line connected to a driving circuit and a thin film transistor connected to the signal line; the signal line has a proximal end close to the driving circuit and a distal end far away from the driving circuit; An auxiliary circuit is arranged on the second surface and connected to the driving circuit. The auxiliary circuit is arranged on a side of the base substrate away from the display circuit. The impedance of the auxiliary circuit is smaller than the impedance of the signal line. The auxiliary circuit is also connected to at least one thin film transistor arranged at the far end of the signal line through the through hole. The auxiliary circuit can provide an independent driving signal to the thin film transistor at the far end of the signal line.

2. The array substrate according to claim 1, wherein: The driving circuit includes a gate driving unit and a data driving unit, the signal line includes a scanning line connected to the gate driving unit and extending in a row direction, and a data line connected to the data driving unit and extending in a column direction; at least one thin film transistor disposed at a remote end of the scanning line is a first remote thin film transistor, and at least one thin film transistor disposed at a remote end of the data line is a second remote thin film transistor; The auxiliary circuit includes a plurality of back scan lines and a plurality of back data lines, each of the back scan lines connects the gate driving unit and at least one of the first remote thin film transistors in a row, and each of the back data lines connects the data driving unit and at least one of the second remote thin film transistors in a column.

3. The array substrate according to claim 2, wherein: The display circuit includes at least two partitions, the scan lines and the data lines in each partition are independently connected to the drive circuit, and each partition is provided with at least one column of the first remote thin film transistors and at least one row of the second remote thin film transistors.

4. The array substrate according to claim 2 or 3, characterized in that: The thin film transistor includes a gate disposed on the first surface, an active layer disposed on the gate, and a source and a drain disposed on the active layer; the second remote thin film transistor also includes a signal pad disposed on the first surface and electrically connected to the source; The plurality of through holes on the substrate include a first through hole and a second through hole, the first through hole exposing the gate of the first remote thin film transistor, and the second through hole exposing the signal pad; The back scan line is connected to the gate of the remote thin film transistor through the first through hole, and the back data line is connected to the signal pad of the remote thin film transistor through the second through hole.

5. The array substrate according to claim 4, wherein: The array substrate further includes a first protection layer disposed between the back scan line and the back data line, and the first protection layer is provided with a via hole corresponding to and communicating with the second through hole.

6. The array substrate according to claim 2 or 3, characterized in that: The back scan line and the back data line are both made of transparent conductive film material, the line width of the back scan line is greater than the line width of the scan line, and the line width of the back data line is greater than the line width of the signal line.

7. The array substrate according to claim 6, wherein: The thickness range of the back scan line and the back data line is The line widths of the back scan lines and the back data lines are greater than 30 μm to 50 μm.

8. A method for manufacturing an array substrate, characterized in that: include: Providing a substrate substrate, the substrate substrate comprising a first surface and a second surface disposed opposite to each other; A display circuit is fabricated on the first surface, wherein the display circuit includes a signal line and a thin film transistor connected to the signal line; the signal line has a proximal end close to a driving circuit and a distal end far away from the driving circuit; Making a plurality of through holes penetrating the first surface and the second surface on the base substrate, each of the through holes being arranged corresponding to one of the thin film transistors arranged at the far end of the signal line; An auxiliary circuit is fabricated on the second surface, wherein the impedance of the auxiliary circuit is smaller than the impedance of the signal line, the auxiliary circuit is connected to the thin film transistor at the far end of the signal line through the through hole, and the auxiliary circuit is disposed on a side of the base substrate away from the display circuit, and the auxiliary circuit can provide an independent driving signal to the thin film transistor at the far end of the signal line.

9. The method for manufacturing an array substrate according to claim 8, wherein: The signal line includes a scan line for connecting a gate driving unit and a data line for connecting a data driving unit; at least one thin film transistor disposed at a remote end of the scan line is a first remote thin film transistor, and at least one thin film transistor disposed at a remote end of the data line is a second remote thin film transistor; Producing an auxiliary circuit on the second surface of the base substrate, comprising: Depositing a first transparent conductive film layer on the second surface, and patterning the first transparent conductive film layer into a plurality of back scan lines, wherein the plurality of back scan lines are connected to corresponding first remote thin film transistors through some of the through holes; Depositing a first protective layer on the second surface, and opening a plurality of via holes on the first protective layer by patterning, wherein the plurality of via holes are arranged correspondingly to and connected with the remaining through holes; A second transparent conductive film layer is deposited on the first protective layer, and the second transparent conductive film layer is patterned to form a plurality of back data lines, and the back data lines are connected to the second remote thin film transistor through the via holes and the through holes.

10. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 7; an opposite substrate, arranged opposite to the array substrate; and The liquid crystal layer is arranged between the array substrate and the opposite substrate.

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