Orthogonal frequency division circuit and its working method, latch of CMOS structure

Abstract

An orthogonal frequency division circuit and its working method, and a latch of CMOS structure, wherein the orthogonal frequency division circuit comprises: a first latch and a second latch, wherein the first latch and the second latch both comprise a first pseudo inversion latch, a second pseudo inversion latch and a bistable circuit, wherein the first pseudo inversion latch comprises a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, and the second pseudo inversion latch comprises a second PMOS transistor, a second CMOS transistor and a second NMOS transistor. Since the first latch and the second latch both comprise a CMOS structure, the orthogonal frequency division circuit can have high integration, low power consumption during operation and low cost.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an orthogonal frequency division circuit and a working method thereof, and a latch with a CMOS structure. Background Art

[0002] Orthogonal four-phase frequency division circuits are widely used in high-speed serial circuits. Compared with the structure using differential clocks, the structure using orthogonal four-phase frequency division circuits has a higher energy efficiency ratio.

[0003] In the existing orthogonal frequency division circuit, two current mode logic latches (Current Mode Logic latch, hereinafter referred to as CML latches) are usually used to realize the function of orthogonal four-phase frequency division.

[0004] However, when the orthogonal frequency division circuit is working, since the power supply voltage terminal and the ground terminal are turned on in the circuit of the CML latch, the current of the orthogonal frequency division circuit is large and the power consumption is also large. At the same time, due to the high-frequency working environment, the restriction on the resistance in the circuit of the CML latch is large, that is, it is necessary to use a resistor with a very small resistance value, resulting in the resistor occupying a large area in the integrated circuit, resulting in poor integration of the orthogonal frequency division circuit. In addition, since the circuit of the CML latch needs to use devices such as current mirrors and resistors, on the one hand, the device of the current mirror occupies a large area, resulting in poor integration of the orthogonal frequency division circuit, and on the other hand, the use of devices such as current mirrors and resistors will also result in high cost of the orthogonal frequency division circuit. Summary of the invention

[0005] The technical problem solved by the present invention is to provide an orthogonal frequency division circuit and its working method, and a latch with a CMOS structure, so that the orthogonal frequency division circuit has high integration, low power consumption during operation, and low cost.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides an orthogonal frequency division circuit, including: a first latch, the first latch has a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a first clock terminal and a second clock terminal, the first clock terminal and the second clock terminal are used to input an inverted clock signal; a second latch, the second latch has a third input terminal, a fourth input terminal, a third output terminal, a fourth output terminal, and a third clock terminal and a fourth clock terminal, the third clock terminal and the fourth clock terminal are used to input an inverted clock signal, and the clock signal input to the first clock terminal and the third clock terminal is inverted; the first latch and the second latch both include a first pseudo-inverting latch, a second pseudo-inverting latch and a bistable circuit, the first pseudo-inverting latch includes a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, the second pseudo-inverting latch includes a second PMOS transistor, a second CMOS transistor and a second NMOS transistor, wherein the drain of the first CMOS transistor is connected to the first PMOS transistor, the source of the first CMOS transistor is connected to the first NMOS transistor, the drain of the second CMOS transistor is connected to the second PMOS transistor, the source of the second CMOS transistor is connected to the second NMOS transistor, the two ends of the bistable circuit are respectively connected to the output end of the first CMOS transistor and the output end of the second CMOS transistor, and, in the circuit of the first latch, the two ends of the bistable circuit are also coupled to the first output end and the second output end, respectively, and in the circuit of the second latch, the two ends of the bistable circuit are also coupled to the third output end and the fourth output end, respectively; a first signal node connected to the first input end and the fourth output end; a second signal node connected to the second input end and the third output end; a third signal node connected to the first output end and the third input end; a fourth signal node connected to the second output end and the fourth input end.

[0007] Optionally, in the circuit of the first latch, the drain terminal of the first CMOS transistor is coupled to the first clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the second clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the first input terminal, the output terminal of the first CMOS transistor is coupled to the first output terminal, the drain terminal of the second CMOS transistor is coupled to the first clock terminal through the second PMOS transistor, the source terminal of the second CMOS transistor is coupled to the second clock terminal through the second NMOS transistor, the input terminal of the second CMOS transistor is coupled to the second input terminal, and the output terminal of the second CMOS transistor is coupled to the second output terminal.

[0008] Optionally, in the circuit of the second latch, the drain terminal of the first CMOS transistor is coupled to the third clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the fourth clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the third input terminal, the output terminal of the first CMOS transistor is coupled to the third output terminal, the drain terminal of the second CMOS transistor is coupled to the third clock terminal through the second PMOS transistor, the source terminal of the second CMOS transistor is coupled to the fourth clock terminal through the second NMOS transistor, the input terminal of the second CMOS transistor is coupled to the fourth input terminal, and the output terminal of the second CMOS transistor is coupled to the fourth output terminal.

[0009] Optionally, in the circuit of the first latch, the drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the first clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the first clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the second clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the second clock terminal.

[0010] Optionally, in the circuit of the second latch, the drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the third clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the third clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the fourth clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the fourth clock terminal.

[0011] Optionally, the first CMOS transistor includes: a third PMOS transistor, the gate of the third PMOS transistor is connected to the input end of the first CMOS transistor, the source end of the third PMOS transistor is connected to the output end of the first CMOS transistor, and the drain end of the third PMOS transistor is connected to the drain end of the first CMOS transistor; a third NMOS transistor, the gate of the third NMOS transistor is connected to the input end of the first CMOS transistor, the source end of the third NMOS transistor is connected to the output end of the first CMOS transistor, and the drain end of the third NMOS transistor is connected to the source end of the first CMOS transistor.

[0012] Optionally, the second CMOS transistor includes: a fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the input end of the second CMOS transistor, the source end of the fourth PMOS transistor is connected to the output end of the second CMOS transistor, and the drain end of the fourth PMOS transistor is connected to the drain end of the second CMOS transistor; a fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the input end of the second CMOS transistor, the source end of the fourth NMOS transistor is connected to the output end of the second CMOS transistor, and the drain end of the fourth NMOS transistor is connected to the source end of the second CMOS transistor.

[0013] Optionally, the bistable circuit includes: a first inverter and a second inverter; in the circuit of the first latch, the input end of the first inverter is coupled to the first output end, the output end of the first inverter is coupled to the second output end, the output end of the second inverter is coupled to the first output end, and the input end of the second inverter is coupled to the second output end; in the circuit of the second latch, the input end of the first inverter is coupled to the third output end, the output end of the first inverter is coupled to the fourth output end, the output end of the second inverter is coupled to the third output end, and the input end of the second inverter is coupled to the fourth output end.

[0014] Correspondingly, the technical solution of the present invention also provides a latch of a CMOS structure, wherein the latch of the CMOS structure has a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a first clock terminal and a second clock terminal, wherein the first clock terminal and the second clock terminal are used to input an inverted clock signal, and the latch of the CMOS structure comprises: a first pseudo inverting latch, wherein the first pseudo inverting latch comprises a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, wherein the drain terminal of the first CMOS transistor is coupled to the first clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the second clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the first input terminal, and the first The output end of the CMOS transistor is coupled to the first output end; a second pseudo inverting latch, the second pseudo inverting latch includes a second PMOS transistor, a second CMOS transistor and a second NMOS transistor, the drain end of the second CMOS transistor is coupled to the first clock end through the second PMOS transistor, the source end of the second CMOS transistor is coupled to the second clock end through the second NMOS transistor, the input end of the second CMOS transistor is coupled to the second input end, and the output end of the second CMOS transistor is coupled to the second output end; a bistable circuit, two ends of the bistable circuit are respectively connected to the output end of the first CMOS transistor and the output end of the second CMOS transistor, and the two ends of the bistable circuit are also respectively coupled to the first output end and the second output end.

[0015] Optionally, the drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the first clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the first clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the second clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the second clock terminal.

[0016] Optionally, the first CMOS transistor includes: a third PMOS transistor, the gate of the third PMOS transistor is connected to the input end of the first CMOS transistor, the source end of the third PMOS transistor is connected to the output end of the first CMOS transistor, and the drain end of the third PMOS transistor is connected to the drain end of the first CMOS transistor; a third NMOS transistor, the gate of the third NMOS transistor is connected to the input end of the first CMOS transistor, the source end of the third NMOS transistor is connected to the output end of the first CMOS transistor, and the drain end of the third NMOS transistor is connected to the source end of the first CMOS transistor.

[0017] Optionally, the second CMOS transistor includes: a fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to the input end of the second CMOS transistor, the source end of the fourth PMOS transistor is connected to the output end of the second CMOS transistor, and the drain end of the fourth PMOS transistor is connected to the drain end of the second CMOS transistor; a fourth NMOS transistor, the gate of the fourth NMOS transistor is connected to the input end of the second CMOS transistor, the source end of the fourth NMOS transistor is connected to the output end of the second CMOS transistor, and the drain end of the fourth NMOS transistor is connected to the source end of the second CMOS transistor.

[0018] Optionally, the bistable circuit includes: a first inverter, an input end of the first inverter is coupled to the first output end, and an output end of the first inverter is coupled to the second output end; a second inverter, an output end of the second inverter is coupled to the first output end, and an input end of the second inverter is coupled to the second output end.

[0019] Correspondingly, the technical solution of the present invention also provides a working method based on the above-mentioned orthogonal frequency division circuit, including: inputting a first clock signal at the first clock end and the fourth clock end, inputting a second clock signal at the second clock end and the third clock end, the first clock signal and the second clock signal are inverted, and the first clock signal and the second clock signal have a period T; inputting a first input signal at the first input end, inputting a second input signal at the second input end, and the first input signal and the second input signal are inverted; the first signal node outputs a first signal; the second signal node outputs a second signal, the first signal and the second signal are inverted, and the first signal and the second signal have a period of 2T; the third signal node outputs a third signal; the fourth signal node outputs a fourth signal, the third signal and the fourth signal are inverted, the third signal and the fourth signal have a period of 2T, and there is a phase difference of T / 2 between the first signal and the third signal.

[0020] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0021] In the orthogonal frequency division circuit provided by the technical solution of the present invention, since the first latch and the second latch both include a first pseudo-inverting latch, a second pseudo-inverting latch and a bistable circuit, and the first pseudo-inverting latch includes a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, and the second pseudo-inverting latch includes a second PMOS transistor, a second CMOS transistor and a second NMOS transistor, therefore, while realizing orthogonal 4-phase frequency division, the orthogonal frequency division circuit not only has low power consumption during operation, but also occupies a small area in the integrated circuit, so that the integrated circuit has a higher degree of integration, and at the same time, the cost of the orthogonal frequency division circuit is low. Specifically, since the first pseudo-inverting latch includes a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, and the second pseudo-inverting latch includes a second PMOS transistor, a second CMOS transistor and a second NMOS transistor, therefore, the opening and closing of the MOS transistors in the first latch and the second latch can be controlled by the movement of a small amount of carriers, so that the orthogonal frequency division circuit consumes little power during operation. Moreover, since the opening and closing of the MOS transistors in the first latch and the second latch are controlled by the movement of a small amount of carriers, there is no need to use resistors and current mirrors in the first latch and the second latch. Therefore, the orthogonal frequency division circuit occupies a small area in the integrated circuit, making the integrated circuit more integrated, and the cost of the orthogonal frequency division circuit is also low. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a circuit structure diagram of an orthogonal frequency division circuit according to an embodiment of the present invention;

[0023] Figure 2 yes Figure 1 A schematic diagram of the circuit structure of the first latch in;

[0024] Figure 3 yes Figure 1 A schematic diagram of the circuit structure of the second latch in;

[0025] Figure 4 4 is a timing diagram of an orthogonal frequency division circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] As described in the background technology, when the orthogonal frequency division circuit is working, since the power supply voltage terminal and the ground terminal are turned on in the circuit of the CML latch, the current of the orthogonal frequency division circuit is large and the power consumption is also large. At the same time, due to the high-frequency working environment, the restriction on the resistance in the circuit of the CML latch is large, that is, it is necessary to use a resistor with a very small resistance value, resulting in the resistor occupying a large area in the integrated circuit, resulting in poor integration of the orthogonal frequency division circuit. In addition, since the circuit of the CML latch needs to use devices such as current mirrors and resistors, on the one hand, the device of the current mirror occupies a large area, resulting in poor integration of the orthogonal frequency division circuit, and on the other hand, the use of devices such as current mirrors and resistors will also result in high cost of the orthogonal frequency division circuit.

[0027] In order to solve the above technical problems, the technical solution of the present invention provides an orthogonal frequency division circuit and its working method, and a latch of a CMOS structure, wherein the orthogonal frequency division circuit includes a first latch and a second latch. Since the first latch and the second latch both include a CMOS structure, the orthogonal frequency division circuit can have high integration, low power consumption during operation, and low cost.

[0028] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 1 is a schematic diagram of the circuit structure of an orthogonal frequency division circuit according to an embodiment of the present invention, Figure 2 yes Figure 1 The circuit structure diagram of the first latch in FIG. Figure 3 yes Figure 1 Schematic diagram of the circuit structure of the second latch in .

[0030] Please refer to Figures 1 to 3, the orthogonal frequency division circuit includes: a first latch, the first latch having a first input terminal IN1, a second input terminal IN2, a first output terminal ON1, a second output terminal ON2, and a first clock terminal CK1 and a second clock terminal CK2, the first clock terminal CK1 and the second clock terminal CK2 are used to input an inverted clock signal; a second latch, the second latch having a third input terminal IN3, a fourth input terminal IN4, a third output terminal ON3, a fourth output terminal ON4, and a third clock terminal CK3 and a fourth clock terminal CK4, the third clock terminal CK3 and the fourth clock terminal CK4 are used to input an inverted clock signal, and the clock signal input to the first clock terminal CK1 and the third clock terminal CK3 is inverted; a first signal node S1 connected to the first input terminal IN1 and the fourth output terminal ON4; a second signal node S2 connected to the second input terminal IN2 and the third output terminal ON3; a third signal node S3 connected to the first output terminal ON1 and the third input terminal IN3; a fourth signal node S4 connected to the second output terminal ON2 and the fourth input terminal IN4.

[0031] Specifically, the first latch and the second latch each include a first pseudo inversion latch, a second pseudo inversion latch and a bistable circuit.

[0032] The first pseudo inversion latch includes a first PMOS transistor PM1, a first CMOS transistor CM1, and a first NMOS transistor NM1.

[0033] The second pseudo inversion latch includes a second PMOS transistor PM2 , a second CMOS transistor CM2 , and a second NMOS transistor NM1 .

[0034] The drain end of the first CMOS transistor CM1 is connected to the first PMOS transistor PM1, the source end of the first CMOS transistor CM1 is connected to the first NMOS transistor NM1, the drain end of the second CMOS transistor CM2 is connected to the second PMOS transistor PM2, the source end of the second CMOS transistor CM2 is connected to the second NMOS transistor NM2, and the two ends of the bistable circuit are respectively connected to the output end of the first CMOS transistor CM1 and the output end of the second CMOS transistor CM2.

[0035] In the circuit of the first latch, two ends of the bistable circuit are respectively coupled to the first output terminal ON1 and the second output terminal ON2. In the circuit of the second latch, two ends of the bistable circuit are respectively coupled to the third output terminal ON3 and the fourth output terminal ON4.

[0036] Since the first latch and the second latch both include a first pseudo-inverting latch, a second pseudo-inverting latch and a bistable circuit, and the first pseudo-inverting latch includes a first PMOS transistor PM1, a first CMOS transistor CM1 and a first NMOS transistor NM1, and the second pseudo-inverting latch includes a second PMOS transistor PM2, a second CMOS transistor CM2 and a second NMOS transistor NM2, therefore, while realizing orthogonal 4-phase frequency division, the orthogonal frequency division circuit not only consumes less power during operation, but also occupies a smaller area in the integrated circuit, so that the integrated circuit has a higher degree of integration, and at the same time, the cost of the orthogonal frequency division circuit is low. Specifically, since the first pseudo-inverting latch includes a first PMOS transistor PM1, a first CMOS transistor CM1 and a first NMOS transistor NM1, and the second pseudo-inverting latch includes a second PMOS transistor PM2, a second CMOS transistor CM2 and a second NMOS transistor NM2, therefore, the opening and closing of the MOS transistors in the first latch and the second latch can be controlled by the movement of a small amount of carriers, so that the orthogonal frequency division circuit consumes less power during operation. Moreover, since the opening and closing of the MOS transistors in the first latch and the second latch are controlled by the movement of a small amount of carriers, there is no need to use resistors and current mirrors in the first latch and the second latch. Therefore, the orthogonal frequency division circuit occupies a small area in the integrated circuit, making the integrated circuit more integrated, and the cost of the orthogonal frequency division circuit is also low.

[0037] The circuit structures of the first latch and the second latch are described in detail below with reference to the accompanying drawings.

[0038] Please combine Figure 1 refer to Figure 2 In the circuit of the first latch, the output end of the first CMOS transistor CM1 is coupled to the node Q2, the output end of the second CMOS transistor CM2 is coupled to the node Q4, one end of the bistable circuit is coupled to the node D1, the other end of the bistable circuit is coupled to the node D2, and the node Q2 is coupled to the node D1, and the node Q4 is coupled to the node D2.

[0039] Therefore, in the circuit of the first latch, two ends of the bistable circuit are connected to the output end of the first CMOS transistor CM1 and the output end of the second CMOS transistor CM2 respectively.

[0040] In this embodiment, in the circuit of the first latch, the drain terminal of the first CMOS transistor CM1 is coupled to the first clock terminal CK1 through the first PMOS transistor PM1, the source terminal of the first CMOS transistor CM1 is coupled to the second clock terminal CK2 through the first NMOS transistor NM1, the input terminal of the first CMOS transistor CM1 is coupled to the first input terminal IN1, the output terminal of the first CMOS transistor CM1 is coupled to the first output terminal ON1, the drain terminal of the second CMOS transistor CM2 is coupled to the first clock terminal CK1 through the second PMOS transistor PM2, the source terminal of the second CMOS transistor CM2 is coupled to the second clock terminal CK2 through the second NMOS transistor NM2, the input terminal of the second CMOS transistor CM2 is coupled to the second input terminal IN2, and the output terminal of the second CMOS transistor CM2 is coupled to the second output terminal ON2.

[0041] Specifically, in the present embodiment, in the circuit of the first latch, the drain terminal of the first PMOS transistor PM1 is connected to the power supply voltage VDD, the source terminal of the first PMOS transistor PM1 is connected to the drain terminal of the first CMOS transistor CM1, the gate terminal of the first PMOS transistor PM1 is coupled to the first clock terminal CK1, the drain terminal of the second PMOS transistor PM2 is connected to the power supply voltage VDD, the source terminal of the second PMOS transistor PM2 is connected to the drain terminal of the second CMOS transistor CM2, the gate terminal of the second PMOS transistor PM2 is coupled to the first clock terminal CK1, the drain terminal of the first NMOS transistor NM1 is grounded to VSS, the source terminal of the first NMOS transistor NM1 is connected to the source terminal of the first CMOS transistor CM1, the gate terminal of the first NMOS transistor NM1 is coupled to the second clock terminal CK2, the drain terminal of the second NMOS transistor NM2 is grounded to VSS, the source terminal of the second NMOS transistor NM2 is connected to the source terminal of the second CMOS transistor CM2, and the gate terminal of the second NMOS transistor NM2 is coupled to the second clock terminal CK2.

[0042] In this embodiment, in the circuit of the first latch, the first CMOS transistor CM1 includes: a third PMOS transistor PM3, the gate of the third PMOS transistor PM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third PMOS transistor PM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third PMOS transistor PM3 is connected to the drain end of the first CMOS transistor CM1; a third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third NMOS transistor NM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third NMOS transistor NM3 is connected to the source end of the first CMOS transistor CM1.

[0043] Specifically, in the circuit of the first latch, the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are coupled to the node Q1, and the source of the third PMOS transistor PM3 and the source of the third NMOS transistor NM3 are coupled to the node Q2.

[0044] In this embodiment, in the circuit of the first latch, the second CMOS transistor CM2 includes: a fourth PMOS transistor PM4, the gate of the fourth PMOS transistor PM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth PMOS transistor PM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth PMOS transistor PM4 is connected to the drain end of the second CMOS transistor CM2; a fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth NMOS transistor NM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth NMOS transistor NM4 is connected to the source end of the second CMOS transistor CM2.

[0045] Specifically, in the circuit of the first latch, the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are coupled to the node Q3, and the source of the fourth PMOS transistor PM4 and the source of the fourth NMOS transistor NM4 are coupled to the node Q4.

[0046] In this embodiment, in the circuit of the first latch, two ends of the bistable circuit are coupled to the first output end ON1 and the second output end ON2 respectively.

[0047] Specifically, one end of the bistable circuit is coupled to the first output end ON1 through a node D1 , and the other end of the bistable circuit is coupled to the second output end ON2 through a node D2 .

[0048] In this embodiment, in the circuit of the first latch, the bistable circuit includes: a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is coupled to the first output end ON1, the output end of the first inverter INV1 is coupled to the second output end ON2, the output end of the second inverter INV2 is coupled to the first output end ON1, and the input end of the second inverter INV2 is coupled to the second output end ON2.

[0049] Specifically, in the circuit of the first latch, the input end of the first inverter INV1 and the output end of the second inverter INV2 are coupled to the node D1, so that the input end of the first inverter INV1 is coupled to the first output end ON1, and the output end of the second inverter INV2 is coupled to the first output end ON1. The output end of the first inverter INV1 and the input end of the second inverter INV2 are coupled to the node D2, so that the output end of the first inverter INV1 is coupled to the second output end ON2, and the input end of the second inverter INV2 is coupled to the second output end ON2.

[0050] Please combine Figure 1 refer to Figure 3 Similarly, in the circuit of the second latch, the output end of the first CMOS transistor CM1 is coupled to the node Q2, the output end of the second CMOS transistor CM2 is coupled to the node Q4, one end of the bistable circuit is coupled to the node D1, the other end of the bistable circuit is coupled to the node D2, and the node Q2 is coupled to the node D1, and the node Q4 is coupled to the node D2.

[0051] Therefore, in the circuit of the second latch, two ends of the bistable circuit are connected to the output end of the first CMOS transistor CM1 and the output end of the second CMOS transistor CM2 respectively.

[0052] In this embodiment, in the circuit of the second latch, the drain terminal of the first CMOS transistor CM1 is coupled to the third clock terminal CK3 through the first PMOS transistor PM1, the source terminal of the first CMOS transistor CM1 is coupled to the fourth clock terminal CK4 through the first NMOS transistor NM1, the input terminal of the first CMOS transistor CM1 is coupled to the third input terminal IN3, the output terminal of the first CMOS transistor CM1 is coupled to the third output terminal ON3, the drain terminal of the second CMOS transistor CM2 is coupled to the third clock terminal CK3 through the second PMOS transistor PM2, the source terminal of the second CMOS transistor CM2 is coupled to the fourth clock terminal CK4 through the second NMOS transistor NM2, the input terminal of the second CMOS transistor CM2 is coupled to the fourth input terminal IN4, and the output terminal of the second CMOS transistor CM2 is coupled to the fourth output terminal ON4.

[0053] Specifically, in the present embodiment, in the circuit of the second latch, the drain terminal of the first PMOS transistor PM1 is connected to the power supply voltage VDD, the source terminal of the first PMOS transistor PM1 is connected to the drain terminal of the first CMOS transistor CM1, the gate terminal of the first PMOS transistor PM1 is coupled to the third clock terminal CK3, the drain terminal of the second PMOS transistor PM2 is connected to the power supply voltage VDD, the source terminal of the second PMOS transistor PM2 is connected to the drain terminal of the second CMOS transistor CM2, the gate terminal of the second PMOS transistor PM2 is coupled to the third clock terminal CK3, the drain terminal of the first NMOS transistor NM1 is grounded to VSS, the source terminal of the first NMOS transistor NM1 is connected to the source terminal of the first CMOS transistor CM1, the gate terminal of the first NMOS transistor NM1 is coupled to the fourth clock terminal CK4, the drain terminal of the second NMOS transistor NM2 is grounded to VSS, the source terminal of the second NMOS transistor NM2 is connected to the source terminal of the second CMOS transistor CM2, and the gate terminal of the second NMOS transistor NM2 is coupled to the fourth clock terminal CK4.

[0054] Similarly, in the circuit of the second latch, the first CMOS transistor CM1 includes: a third PMOS transistor PM3, the gate of the third PMOS transistor PM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third PMOS transistor PM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third PMOS transistor PM3 is connected to the drain end of the first CMOS transistor CM1; a third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third NMOS transistor NM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third NMOS transistor NM3 is connected to the source end of the first CMOS transistor CM1.

[0055] Specifically, in the circuit of the second latch, the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are coupled to the node Q1, and the source of the third PMOS transistor PM3 and the source of the third NMOS transistor NM3 are coupled to the node Q2.

[0056] Similarly, in the circuit of the second latch, the second CMOS transistor CM2 includes: a fourth PMOS transistor PM4, the gate of the fourth PMOS transistor PM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth PMOS transistor PM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth PMOS transistor PM4 is connected to the drain end of the second CMOS transistor CM2; a fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth NMOS transistor NM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth NMOS transistor NM4 is connected to the source end of the second CMOS transistor CM2.

[0057] Specifically, in the circuit of the second latch, the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are coupled to the node Q3, and the source of the fourth PMOS transistor PM4 and the source of the fourth NMOS transistor NM4 are coupled to the node Q4.

[0058] In this embodiment, in the circuit of the second latch, two ends of the bistable circuit are coupled to the third output terminal ON3 and the fourth output terminal ON4 respectively.

[0059] Specifically, one end of the bistable circuit is coupled to the third output end ON3 via the node D1 , and the other end of the bistable circuit is coupled to the fourth output end ON4 via the node D2 .

[0060] Similarly, in the circuit of the second latch, the bistable circuit includes: a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is coupled to the third output end ON3, the output end of the first inverter INV1 is coupled to the fourth output end ON4, the output end of the second inverter INV2 is coupled to the third output end ON3, and the input end of the second inverter INV2 is coupled to the fourth output end ON4.

[0061] Specifically, in the circuit of the second latch, the input end of the first inverter INV1 and the output end of the second inverter INV2 are coupled to the node D1, so that the input end of the first inverter INV1 is coupled to the third output end ON3, and the output end of the second inverter INV2 is coupled to the third output end ON3. The output end of the first inverter INV1 and the input end of the second inverter INV2 are coupled to the node D2, so that the output end of the first inverter INV1 is coupled to the fourth output end ON4, and the input end of the second inverter INV2 is coupled to the fourth output end ON4.

[0062] Since during the operation of the orthogonal frequency division circuit, there is no conduction between the power supply voltage VDD and the ground terminal VSS, but the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, the second NMOS transistor NM2, the first CMOS transistor CM1 and the second CMOS transistor CM2 in the first latch and the second latch are controlled to be turned on and off through the movement of a small amount of carriers to achieve orthogonal four-phase frequency division. Therefore, the orthogonal frequency division circuit consumes little power during operation.

[0063] Moreover, since the first latch and the second latch are controlled by the movement of a small amount of carriers, there is no need to use resistors and current mirrors in the first latch and the second latch. Therefore, the orthogonal frequency division circuit occupies a small area in the integrated circuit, making the integrated circuit more integrated, and the cost of the orthogonal frequency division circuit is also lower.

[0064] Accordingly, an embodiment of the present invention further provides a latch of a CMOS structure for the above-mentioned orthogonal frequency division circuit, please continue to refer to Figure 2 The latch of the CMOS structure has a first input terminal IN1, a second input terminal IN2, a first output terminal ON1, a second output terminal ON2, and a first clock terminal CK1 and a second clock terminal CK2, wherein the first clock terminal CK1 and the second clock terminal CK2 are used to input an inverted clock signal.

[0065] Furthermore, the latch of the CMOS structure includes: a first pseudo-inversion latch, which includes a first PMOS transistor PM1, a first CMOS transistor CM1 and a first NMOS transistor NM1, a drain end of the first CMOS transistor CM1 is coupled to the first clock end CK1 through the first PMOS transistor PM1, a source end of the first CMOS transistor CM1 is coupled to the second clock end CK2 through the first NMOS transistor NM1, an input end of the first CMOS transistor CM1 is coupled to the first input end IN1, and an output end of the first CMOS transistor CM1 is coupled to the first output end ON1.

[0066] The latch of the CMOS structure also includes: a second pseudo-inversion latch, which includes a second PMOS transistor PM2, a second CMOS transistor CM2 and a second NMOS transistor NM2, the drain end of the second CMOS transistor CM2 is coupled to the first clock end CK1 through the second PMOS transistor PM2, the source end of the second CMOS transistor CM2 is coupled to the second clock end CK2 through the second NMOS transistor NM2, the input end of the second CMOS transistor CM2 is coupled to the second input end IN2, and the output end of the second CMOS transistor CM2 is coupled to the second output end ON2.

[0067] The latch of the CMOS structure further includes: a bistable circuit, two ends of which are respectively connected to the output end of the first CMOS transistor CM1 and the output end of the second CMOS transistor CM2, and two ends of the bistable circuit are also respectively coupled to the first output end ON1 and the second output end ON2.

[0068] Specifically, in this embodiment, the output end of the first CMOS transistor CM1 is coupled to the node Q2, the output end of the second CMOS transistor CM2 is coupled to the node Q4, one end of the bistable circuit is coupled to the node D1, the other end of the bistable circuit is coupled to the node D2, and the node Q2 is coupled to the node D1, and the node Q4 is coupled to the node D2.

[0069] Thus, two ends of the bistable circuit are connected to the output end of the first CMOS transistor CM1 and the output end of the second CMOS transistor CM2 respectively.

[0070] Specifically, in the present embodiment, the drain terminal of the first PMOS transistor PM1 is connected to the power supply voltage VDD, the source terminal of the first PMOS transistor PM1 is connected to the drain terminal of the first CMOS transistor CM1, and the gate terminal of the first PMOS transistor PM1 is coupled to the first clock terminal CK1; the drain terminal of the second PMOS transistor PM2 is connected to the power supply voltage VDD, the source terminal of the second PMOS transistor PM2 is connected to the drain terminal of the second CMOS transistor CM2, and the gate terminal of the second PMOS transistor PM2 is coupled to the first clock terminal CK1; the drain terminal of the first NMOS transistor NM1 is connected to the ground VSS, the source terminal of the first NMOS transistor NM1 is connected to the source terminal of the first CMOS transistor CM1, and the gate terminal of the first NMOS transistor NM1 is coupled to the second clock terminal CK2; the drain terminal of the second NMOS transistor NM2 is connected to the ground VSS, the source terminal of the second NMOS transistor NM2 is connected to the source terminal of the second CMOS transistor CM2, and the gate terminal of the second NMOS transistor NM2 is coupled to the second clock terminal CK2.

[0071] In this embodiment, the first CMOS transistor CM1 includes: a third PMOS transistor PM3, the gate of the third PMOS transistor PM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third PMOS transistor PM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third PMOS transistor PM3 is connected to the drain end of the first CMOS transistor CM1; a third NMOS transistor NM3, the gate of the third NMOS transistor NM3 is connected to the input end of the first CMOS transistor CM1, the source end of the third NMOS transistor NM3 is connected to the output end of the first CMOS transistor CM1, and the drain end of the third NMOS transistor NM3 is connected to the source end of the first CMOS transistor CM1.

[0072] Specifically, in the latch circuit of the CMOS structure, the gate of the third PMOS transistor PM3 and the gate of the third NMOS transistor NM3 are coupled to the node Q1, and the source of the third PMOS transistor PM3 and the source of the third NMOS transistor NM3 are coupled to the node Q2.

[0073] In this embodiment, the second CMOS transistor CM2 includes: a fourth PMOS transistor PM4, the gate of the fourth PMOS transistor PM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth PMOS transistor PM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth PMOS transistor PM4 is connected to the drain end of the second CMOS transistor CM2; a fourth NMOS transistor NM4, the gate of the fourth NMOS transistor NM4 is connected to the input end of the second CMOS transistor CM2, the source end of the fourth NMOS transistor NM4 is connected to the output end of the second CMOS transistor CM2, and the drain end of the fourth NMOS transistor NM4 is connected to the source end of the second CMOS transistor CM2.

[0074] Specifically, in the circuit of the latch with the CMOS structure, the gate of the fourth PMOS transistor PM4 and the gate of the fourth NMOS transistor NM4 are coupled to the node Q3, and the source of the fourth PMOS transistor PM4 and the source of the fourth NMOS transistor NM4 are coupled to the node Q4.

[0075] Specifically, one end of the bistable circuit is coupled to the first output end ON1 through a node D1 , and the other end of the bistable circuit is coupled to the second output end ON2 through a node D2 .

[0076] In this embodiment, in the circuit of the latch of the CMOS structure, the bistable circuit includes: a first inverter INV1 and a second inverter INV2, the input end of the first inverter INV1 is coupled to the first output end ON1, the output end of the first inverter INV1 is coupled to the second output end ON2, the output end of the second inverter INV2 is coupled to the first output end ON1, and the input end of the second inverter INV2 is coupled to the second output end ON2.

[0077] Specifically, in the circuit of the latch of the CMOS structure, the input end of the first inverter INV1 and the output end of the second inverter INV2 are coupled to the node D1, so that the input end of the first inverter INV1 is coupled to the first output end ON1, and the output end of the second inverter INV2 is coupled to the first output end ON1. The output end of the first inverter INV1 and the input end of the second inverter INV2 are coupled to the node D2, so that the output end of the first inverter INV1 is coupled to the second output end ON2, and the input end of the second inverter INV2 is coupled to the second output end ON2.

[0078] Figure 4 4 is a timing diagram of an orthogonal frequency division circuit according to an embodiment of the present invention.

[0079] Correspondingly, an embodiment of the present invention further provides a working method based on the above-mentioned orthogonal frequency division circuit. Figures 1 to 3 refer to Figure 4 ,include:

[0080] A first clock signal clk is input into the first clock terminal CK1 and the fourth clock terminal CK4, and a second clock signal clkb is input into the second clock terminal CK2 and the third clock terminal CK3, wherein the first clock signal clk and the second clock signal clkb are inverted, and the first clock signal clk and the second clock signal clkb have a period T;

[0081] A first input signal is input into the first input terminal IN1, and a second input signal is input into the second input terminal IN2, wherein the first input signal and the second input signal are inverted;

[0082] The first signal node S1 outputs a first signal;

[0083] The second signal node S2 outputs a second signal, the first signal and the second signal are inverted, and the first signal and the second signal have a period of 2T;

[0084] The third signal node S3 outputs a third signal;

[0085] The fourth signal node S4 outputs a fourth signal, the third signal and the fourth signal are inverted, the third signal and the fourth signal have a period of 2T, and there is a phase difference of T / 2 between the first signal and the third signal.

[0086] Specifically, when a signal "0" is input to the first clock terminal CK1 and the fourth clock terminal CK4, and a signal "1" is input to the second clock terminal CK2 and the third clock terminal CK3, in the circuit of the first latch, the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 are all turned on. On the contrary, in the circuit of the second latch, the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 are all turned off.

[0087] At this time, the second latch is in a latched state.

[0088] At this time, if a signal "0" is input to the first input terminal IN1, and a signal "1" is input to the second input terminal IN2, in the circuit of the first latch, the third PMOS transistor PM3 is turned on, the fourth PMOS transistor PM4 is turned on, the third NMOS transistor NM3 is turned off, and the fourth NMOS transistor NM4 is turned off. Thus, the first signal node S1 outputs a signal "0", the second signal node S4 outputs a signal "1", the third signal node S3 outputs a signal "1", and the fourth signal node S4 outputs a signal "0".

[0089] At this time, if a signal "1" is input to the first input terminal IN1, and a signal "0" is input to the second input terminal IN2, in the circuit of the first latch, the third PMOS transistor PM3 is turned off, the fourth PMOS transistor PM4 is turned off, the third NMOS transistor NM3 is turned on, and the fourth NMOS transistor NM4 is turned on. Thus, the first signal node S1 outputs a signal "1", the second signal node S4 outputs a signal "0", the third signal node S3 outputs a signal "0", and the fourth signal node S4 outputs a signal "1".

[0090] When a signal "1" is input to the first clock terminal CK1 and the fourth clock terminal CK4, and a signal "0" is input to the second clock terminal CK2 and the third clock terminal CK3, in the circuit of the second latch, the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 are all turned on. On the contrary, in the circuit of the first latch, the first PMOS transistor PM1, the second PMOS transistor PM2, the first NMOS transistor NM1, and the second NMOS transistor NM2 are all turned off.

[0091] At this time, the first latch is in a latched state.

[0092] If the third signal node S3 outputs a signal "1" and the fourth signal node S4 outputs a signal "0", a signal "1" is input to the third input terminal IN3, and a signal "0" is input to the fourth input terminal IN4. At this time, in the circuit of the second latch, the third PMOS transistor PM3 is turned off, the fourth PMOS transistor PM4 is turned off, the third NMOS transistor NM3 is turned on, and the fourth NMOS transistor NM4 is turned on. Thus, the first signal node S1 outputs a signal "1", and the second signal node S4 outputs a signal "0".

[0093] If the third signal node S3 outputs a signal "0" and the fourth signal node S4 outputs a signal "1", a signal "0" is input to the third input terminal IN3, and a signal "1" is input to the fourth input terminal IN4. At this time, in the circuit of the second latch, the third PMOS transistor PM3 is turned on and off, the fourth PMOS transistor PM4 is turned on, the third NMOS transistor NM3 is turned off, and the fourth NMOS transistor NM4 is turned off. Thus, the first signal node S1 outputs a signal "0", and the second signal node S4 outputs a signal "1".

[0094] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An orthogonal frequency division circuit, characterized in that: include: A first latch, wherein the first latch has a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a first clock terminal and a second clock terminal, wherein the first clock terminal and the second clock terminal are used to input an inverted clock signal; a second latch, the second latch having a third input terminal, a fourth input terminal, a third output terminal, a fourth output terminal, and a third clock terminal and a fourth clock terminal, the third clock terminal and the fourth clock terminal are used to input an inverted clock signal, and the clock signals input to the first clock terminal and the third clock terminal are inverted; The first latch and the second latch both include a first pseudo inversion latch, a second pseudo inversion latch and a bistable circuit, the first pseudo inversion latch includes a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, the second pseudo inversion latch includes a second PMOS transistor, a second CMOS transistor and a second NMOS transistor, wherein the drain of the first CMOS transistor is connected to the first PMOS transistor, the source of the first CMOS transistor is connected to the first NMOS transistor, the drain of the second CMOS transistor is connected to the second PMOS transistor, the source of the second CMOS transistor is connected to the second NMOS transistor, the two ends of the bistable circuit are respectively connected to the output end of the first CMOS transistor and the output end of the second CMOS transistor, and, in the circuit of the first latch, the two ends of the bistable circuit are also coupled to the first output end and the second output end, respectively, and in the circuit of the second latch, the two ends of the bistable circuit are also coupled to the third output end and the fourth output end, respectively; a first signal node connected to the first input terminal and the fourth output terminal; a second signal node connected to the second input terminal and the third output terminal; a third signal node connected to the first output terminal and the third input terminal; A fourth signal node is connected to the second output terminal and the fourth input terminal.

2. The orthogonal frequency division circuit according to claim 1, characterized in that: In the circuit of the first latch, the drain terminal of the first CMOS transistor is coupled to the first clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the second clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the first input terminal, the output terminal of the first CMOS transistor is coupled to the first output terminal, the drain terminal of the second CMOS transistor is coupled to the first clock terminal through the second PMOS transistor, the source terminal of the second CMOS transistor is coupled to the second clock terminal through the second NMOS transistor, the input terminal of the second CMOS transistor is coupled to the second input terminal, and the output terminal of the second CMOS transistor is coupled to the second output terminal.

3. The orthogonal frequency division circuit according to claim 1, characterized in that: In the circuit of the second latch, the drain terminal of the first CMOS transistor is coupled to the third clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the fourth clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the third input terminal, the output terminal of the first CMOS transistor is coupled to the third output terminal, the drain terminal of the second CMOS transistor is coupled to the third clock terminal through the second PMOS transistor, the source terminal of the second CMOS transistor is coupled to the fourth clock terminal through the second NMOS transistor, the input terminal of the second CMOS transistor is coupled to the fourth input terminal, and the output terminal of the second CMOS transistor is coupled to the fourth output terminal.

4. The orthogonal frequency division circuit according to claim 1, characterized in that: In the circuit of the first latch, the drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the first clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the first clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the second clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the second clock terminal.

5. The orthogonal frequency division circuit according to claim 1, characterized in that: In the circuit of the second latch, the drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the third clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the third clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the fourth clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the fourth clock terminal.

6. The orthogonal frequency division circuit according to claim 1, characterized in that: The first CMOS transistor includes: a third PMOS transistor, a gate of the third PMOS transistor is connected to the input end of the first CMOS transistor, a source end of the third PMOS transistor is connected to the output end of the first CMOS transistor, and a drain end of the third PMOS transistor is connected to the drain end of the first CMOS transistor; a third NMOS transistor, a gate of the third NMOS transistor is connected to the input end of the first CMOS transistor, a source end of the third NMOS transistor is connected to the output end of the first CMOS transistor, and a drain end of the third NMOS transistor is connected to the source end of the first CMOS transistor.

7. The orthogonal frequency division circuit according to claim 1, characterized in that: The second CMOS transistor includes: a fourth PMOS transistor, a gate of the fourth PMOS transistor is connected to the input end of the second CMOS transistor, a source end of the fourth PMOS transistor is connected to the output end of the second CMOS transistor, and a drain end of the fourth PMOS transistor is connected to the drain end of the second CMOS transistor; and a fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to the input end of the second CMOS transistor, a source end of the fourth NMOS transistor is connected to the output end of the second CMOS transistor, and a drain end of the fourth NMOS transistor is connected to the source end of the second CMOS transistor.

8. The orthogonal frequency division circuit according to claim 1, characterized in that: The bistable circuit includes: a first inverter and a second inverter; in the circuit of the first latch, the input end of the first inverter is coupled to the first output end, the output end of the first inverter is coupled to the second output end, the output end of the second inverter is coupled to the first output end, and the input end of the second inverter is coupled to the second output end; in the circuit of the second latch, the input end of the first inverter is coupled to the third output end, the output end of the first inverter is coupled to the fourth output end, the output end of the second inverter is coupled to the third output end, and the input end of the second inverter is coupled to the fourth output end.

9. A latch of CMOS structure, characterized in that: The latch of the CMOS structure has a first input terminal, a second input terminal, a first output terminal, a second output terminal, and a first clock terminal and a second clock terminal, wherein the first clock terminal and the second clock terminal are used to input an inverted clock signal, and the latch of the CMOS structure includes: a first pseudo inverting latch, wherein the first pseudo inverting latch includes a first PMOS transistor, a first CMOS transistor and a first NMOS transistor, wherein the drain terminal of the first CMOS transistor is coupled to the first clock terminal through the first PMOS transistor, the source terminal of the first CMOS transistor is coupled to the second clock terminal through the first NMOS transistor, the input terminal of the first CMOS transistor is coupled to the first input terminal, and the output terminal of the first CMOS transistor is coupled to the first The output terminal of the second CMOS transistor is coupled; a second pseudo-inverting latch, wherein the second pseudo-inverting latch includes a second PMOS transistor, a second CMOS transistor, and a second NMOS transistor, wherein the drain terminal of the second CMOS transistor is coupled to the first clock terminal through the second PMOS transistor, the source terminal of the second CMOS transistor is coupled to the second clock terminal through the second NMOS transistor, the input terminal of the second CMOS transistor is coupled to the second input terminal, and the output terminal of the second CMOS transistor is coupled to the second output terminal; a bistable circuit, wherein two ends of the bistable circuit are respectively connected to the output terminal of the first CMOS transistor and the output terminal of the second CMOS transistor, and the two ends of the bistable circuit are also respectively coupled to the first output terminal and the second output terminal.

10. The latch of CMOS structure as claimed in claim 9, characterized in that: The drain terminal of the first PMOS transistor is connected to the power supply voltage, the source terminal of the first PMOS transistor is connected to the drain terminal of the first CMOS transistor, the gate of the first PMOS transistor is coupled to the first clock terminal, the drain terminal of the second PMOS transistor is connected to the power supply voltage, the source terminal of the second PMOS transistor is connected to the drain terminal of the second CMOS transistor, the gate of the second PMOS transistor is coupled to the first clock terminal, the drain terminal of the first NMOS transistor is grounded, the source terminal of the first NMOS transistor is connected to the source terminal of the first CMOS transistor, the gate of the first NMOS transistor is coupled to the second clock terminal, the drain terminal of the second NMOS transistor is grounded, the source terminal of the second NMOS transistor is connected to the source terminal of the second CMOS transistor, and the gate of the second NMOS transistor is coupled to the second clock terminal.

11. The latch of CMOS structure as claimed in claim 9, characterized in that: The first CMOS transistor includes: a third PMOS transistor, a gate of the third PMOS transistor is connected to the input end of the first CMOS transistor, a source end of the third PMOS transistor is connected to the output end of the first CMOS transistor, and a drain end of the third PMOS transistor is connected to the drain end of the first CMOS transistor; a third NMOS transistor, a gate of the third NMOS transistor is connected to the input end of the first CMOS transistor, a source end of the third NMOS transistor is connected to the output end of the first CMOS transistor, and a drain end of the third NMOS transistor is connected to the source end of the first CMOS transistor.

12. The latch of CMOS structure as claimed in claim 9, characterized in that: The second CMOS transistor includes: a fourth PMOS transistor, a gate of the fourth PMOS transistor is connected to the input end of the second CMOS transistor, a source end of the fourth PMOS transistor is connected to the output end of the second CMOS transistor, and a drain end of the fourth PMOS transistor is connected to the drain end of the second CMOS transistor; and a fourth NMOS transistor, a gate of the fourth NMOS transistor is connected to the input end of the second CMOS transistor, a source end of the fourth NMOS transistor is connected to the output end of the second CMOS transistor, and a drain end of the fourth NMOS transistor is connected to the source end of the second CMOS transistor.

13. The latch of CMOS structure as claimed in claim 9, characterized in that: The bistable circuit includes: a first inverter, an input end of the first inverter is coupled to a first output end, and an output end of the first inverter is coupled to a second output end; a second inverter, an output end of the second inverter is coupled to the first output end, and an input end of the second inverter is coupled to the second output end.

14. A working method based on the orthogonal frequency division circuit according to any one of claims 1 to 8, characterized in that: include: A first clock signal is input into the first clock terminal and the fourth clock terminal, and a second clock signal is input into the second clock terminal and the third clock terminal, wherein the first clock signal and the second clock signal are in opposite phases, and the first clock signal and the second clock signal have a period T; A first input signal is input into the first input terminal, a second input signal is input into the second input terminal, and the first input signal and the second input signal are inverted; The first signal node outputs a first signal; The second signal node outputs a second signal, the first signal and the second signal are inverted, and the first signal and the second signal have a period of 2T; The third signal node outputs a third signal; The fourth signal node outputs a fourth signal, the third signal and the fourth signal are inverted, the third signal and the fourth signal have a period of 2T, and there is a phase difference of T / 2 between the first signal and the third signal.

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