Chip disconnection detection circuit and method and chip

Abstract

The present invention discloses a chip disconnection detection circuit and method and a chip, wherein the chip disconnection detection circuit comprises a first MOS tube group, a second MOS tube group, a first diode, a second diode, a first charge pump and a second charge pump; the first MOS tube group comprises at least one first MOS tube, and the second MOS tube group comprises at least one second MOS tube; the first end of the chip body is respectively connected to the first end of the second MOS tube group and the negative electrode of the second diode, the second end of the second MOS tube group is respectively connected to the positive electrode of the second diode, the first end of the first MOS tube group and the negative electrode of the first diode; the second end of the chip body is respectively connected to the second end of the first MOS tube group and the positive electrode of the first diode; the third end of the second MOS tube group is connected to the second charge pump, and the third end of the first MOS tube group is connected to the first charge pump. The chip disconnection detection circuit and method and the chip proposed by the present invention can timely detect when a chip power line or ground line is disconnected.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to a chip, and in particular to a chip disconnection detection circuit and a detection method. Background Art

[0002] Integrated circuit (IC) chips have become the core of modern industry, especially in the automotive industry. Various functional modules such as direction control, speed sensing, and assisted driving are inseparable from IC chips. Due to the special safety requirements of automobiles, automotive integrated circuit chips must meet certain functional safety standards, such as the ISO-26262 road vehicle functional safety standard, that is, when a single point failure occurs in the chip, the chip must provide early warning information to the ECU (automotive electronic control unit) in a timely manner, thereby reducing the probability of automobile safety accidents.

[0003] A wire break is one of the most common single-point failure modes, that is, the power line or ground line of the IC chip is accidentally disconnected. At this time, the output of the chip often gives an error message. Figure 1 As shown in the figure, the dotted box represents a simple chip, which includes power supply VDD, ground VSS and an output OUT, where OUT is connected to the external power supply VBAT through a pull-up resistor RL, and the chip ground VSS is connected to the external ground VGND. The chip is simplified into the core circuit CORE (equivalent to a resistor), the diode D1 between OUT and VSS, and the diode D2 between OUT and VDD. D1 and D2 can come from the parasitic diode of the OUT driving transistor or from the electrostatic protection device of OUT, which is a common structure in integrated circuits. When the chip power supply VDD is accidentally disconnected from VBAT, the chip is in a power-free state. At this time, the voltage of OUT will be determined by the resistor voltage divider of the current path of VBAT, RL, D2, CORE, and VGND. This value is obviously not the expected voltage of OUT, and it is also likely to fall between VBAT and VGND.

[0004] For a common automotive control unit ECU, it will regard the voltage close to VBAT or VGND output by the chip as an error warning information, activate a certain safety mechanism to avoid safety accidents, and regard the voltage between VBAT and VGND as a normal signal for collection. Therefore, the voltage of OUT at this time will likely be mistaken for a normal signal, resulting in possible functional safety risks.

[0005] Similarly, if Figure 2As shown in the figure, when the chip ground line VSS is accidentally disconnected from the external ground VGND, and the chip has a pull-down resistor RL connected to VGND, the chip's OUT voltage will be determined by the resistor voltage divider of the path VBAT, CORE, D1, RL, VGND. The OUT voltage is likely to fall in the middle area between VBAT and VGND and be mistaken by the ECU as a normal signal, resulting in functional safety risks.

[0006] In view of this, there is an urgent need to design a new chip power-off detection method to overcome at least part of the above-mentioned defects of the existing chip power-off detection method. Summary of the invention

[0007] The present invention provides a chip disconnection detection circuit and method as well as a chip, which can timely detect when a chip power line or ground line is disconnected.

[0008] To solve the above technical problem, according to one aspect of the present invention, the following technical solution is adopted:

[0009] A chip disconnection detection circuit, the chip disconnection detection circuit is connected to the chip body and is used to detect whether the power line and / or ground line of the chip body are disconnected;

[0010] The chip disconnection detection circuit comprises: a first MOS tube group, a second MOS tube group, a first diode, a second diode, a first charge pump, and a second charge pump;

[0011] The first MOS tube group includes at least one first MOS tube, and the second MOS tube group includes at least one second MOS tube;

[0012] The first end of the chip body is respectively connected to the first end of the second MOS tube group and the cathode of the second diode, the second end of the second MOS tube group is respectively connected to the anode of the second diode, the first end of the first MOS tube group, and the cathode of the first diode; the second end of the chip body is respectively connected to the second end of the first MOS tube group and the anode of the first diode;

[0013] The third end of the second MOS tube group is connected to the second charge pump, and the third end of the first MOS tube group is connected to the first charge pump.

[0014] As an embodiment of the present invention, the first charge pump is a negative voltage charge pump, which uses the chip ground pin as a reference voltage and is used to output different types of voltages when the chip is working normally or abnormally;

[0015] The second charge pump is a positive voltage charge pump, which uses the power supply voltage as a reference voltage and is used to output different types of voltages when the chip is working normally or abnormally.

[0016] As an embodiment of the present invention, the first charge pump is used to generate a negative voltage when the chip is working normally, and the output voltage is 0 when the power line and / or the ground line is disconnected;

[0017] The second charge pump is used to generate a positive voltage when the chip is operating normally, and the output voltage is 0 when the power line and / or the ground line is disconnected.

[0018] As an implementation manner of the present invention, the first MOS tube group includes a first MOS tube, and the second MOS tube group includes a second MOS tube.

[0019] As an implementation manner of the present invention, the first MOS tube group includes a plurality of first MOS tubes, each of which is sequentially connected in series; the second MOS tube group includes a plurality of second MOS tubes, each of which is sequentially connected in series.

[0020] As an implementation manner of the present invention, the first MOS tube included in the first MOS tube group is an N-type MOS tube, the source of the first MOS tube is the second end of the first MOS tube, the drain of the first MOS tube is the first end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube; or, the first MOS tube included in the first MOS tube group is a P-type MOS tube, the source of the first MOS tube is the first end of the first MOS tube, the drain of the first MOS tube is the second end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube;

[0021] The second MOS tube included in the second MOS tube group is a P-type MOS tube, the source of the second MOS tube is the first end of the second MOS tube, the drain of the second MOS tube is the second end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube; or, the second MOS tube included in the second MOS tube group is an N-type MOS tube, the source of the second MOS tube is the second end of the second MOS tube, the drain of the second MOS tube is the first end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube.

[0022] According to another aspect of the present invention, the following technical solution is adopted: a chip, the chip comprises a chip body and the above-mentioned chip disconnection detection circuit, the chip disconnection detection circuit is connected to the chip body.

[0023] As an embodiment of the present invention, the chip is provided with a power pin, a ground pin and an output pin; the second end of the first MOS tube group is connected to the ground pin, the first end of the first MOS tube group and the second end of the second MOS tube group are respectively connected to the output pin, and the first end of the second MOS tube group is connected to the power pin.

[0024] According to another aspect of the present invention, the following technical solution is adopted: a chip disconnection detection method of the above chip, the chip disconnection detection method comprising:

[0025] If the voltage output by the chip's output pin is close to the external ground voltage or close to the external power supply voltage, the chip is judged to be disconnected;

[0026] If the voltage output by the output pin of the chip is between the external ground voltage and the external power supply voltage, it is determined that the chip is not broken.

[0027] The beneficial effects of the present invention are as follows: the chip disconnection detection circuit and method and the chip proposed in the present invention can timely detect when a chip power line or ground line is disconnected, and when a disconnection occurs, the chip output voltage is set to be close to the external power supply VBAT or the external ground VGND, thereby providing timely error warning information for the automobile control system.

[0028] In one use scenario of the present invention, the present invention adds a depletion-type transistor between the chip output terminal OUT and the chip power supply VDD and the chip ground VSS, and uses a charge pump to bias the gate of the depletion-type transistor, so that when the power line or ground line of the chip is accidentally disconnected, the output OUT voltage can be close to the external power supply VBAT or the external ground VGND, as an abnormal alarm signal of disconnection, so that the upper-level control unit can handle the abnormality in time and reduce the probability of functional safety accidents. If the structure of the present invention is not adopted, when the chip is powered off, the output voltage V(OUT) may stop in the middle area between the external power supply VBAT and the external ground VGND, and this abnormal output signal will be regarded as a normal signal by the upper-level control unit, which may cause functional safety accidents.

[0029] In addition, the depletion-mode transistor used in the present invention is a component of the standard integrated circuit process, and the charge pump is a module well known to integrated circuit designers, so the solution is highly feasible in implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The figure is a circuit diagram of an existing chip disconnection detection circuit (power line disconnection).

[0031] Figure 2 The figure is a circuit diagram of an existing chip disconnection detection circuit (ground wire disconnection).

[0032] Figure 3 The figure is a circuit diagram of the chip disconnection detection circuit of the present invention.

[0033] Figure 4 FIG. 1 is a circuit diagram of a chip disconnection detection circuit of the present invention (power line disconnection).

[0034] Figure 5 Schematic diagram of a chip disconnection detection circuit of the present invention (ground wire disconnection).

[0035] Figure 6 The figure is a circuit diagram of the chip disconnection detection circuit of the present invention.

[0036] Figure 7 The figure is a circuit diagram of the chip disconnection detection circuit of the present invention.

[0037] Figure 8 The figure is a circuit diagram of the chip disconnection detection circuit of the present invention. DETAILED DESCRIPTION

[0038] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0040] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0041] The description of the steps in each embodiment in the specification is only for the convenience of explanation, and the implementation method of the present application is not limited by the order of implementation of the steps.

[0042] The term "connection" as used in the specification includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices known to those skilled in the art on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits.

[0043] The present invention discloses a chip disconnection detection circuit. Figure 3 This is a circuit diagram of the chip disconnection detection circuit of the present invention; please refer to Figure 3 The chip disconnection detection circuit is connected to the chip body CORE to detect whether the power line and / or ground line of the chip body are disconnected; the chip disconnection detection circuit includes: a first MOS tube group, a second MOS tube group, a first diode D1, a second diode D2, a first charge pump CP1, and a second charge pump CP2. The first MOS tube group includes at least one first MOS tube, and the second MOS tube group includes at least one second MOS tube.

[0044] The first end of the chip body is respectively connected to the first end of the second MOS tube group and the cathode of the second diode, the second end of the second MOS tube group is respectively connected to the anode of the second diode, the first end of the first MOS tube group, and the cathode of the first diode; the second end of the chip body is respectively connected to the second end of the first MOS tube group and the anode of the first diode. The third end of the second MOS tube group is connected to the second charge pump, and the third end of the first MOS tube group is connected to the first charge pump.

[0045] In one embodiment of the present invention, the first charge pump CP1 is a negative voltage charge pump, which uses the chip ground pin as a reference voltage, and is used to output different types of voltages when the chip is working normally and abnormally; the second charge pump CP2 is a positive voltage charge pump, which uses the power supply voltage as a reference voltage, and is used to output different types of voltages when the chip is working normally and abnormally.

[0046] In one embodiment, the first charge pump CP1 is used to generate a negative voltage when the chip is working normally, and the output voltage is 0 when the power line and / or the ground line is broken; the second charge pump CP2 is used to generate a positive voltage when the chip is working normally, and the output voltage is 0 when the power line and / or the ground line is broken.

[0047] In one embodiment of the present invention, the first MOS transistor group includes a first MOS transistor, and the second MOS transistor group includes a second MOS transistor (such as Figure 3 , Figure 6 , Figure 7 In one embodiment, the first MOS tube group includes a plurality of first MOS tubes, each of which is connected in series in sequence; the second MOS tube group includes a plurality of second MOS tubes, each of which is connected in series in sequence (as shown in FIG. Figure 8 shown).

[0048] See also Figure 3 In one embodiment of the present invention, the first MOS tube included in the first MOS tube group is an N-type MOS tube N1, the source of the first MOS tube is the second end of the first MOS tube, the drain of the first MOS tube is the first end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube. The second MOS tube included in the second MOS tube group is a P-type MOS tube P1, the source of the second MOS tube is the first end of the second MOS tube, the drain of the second MOS tube is the second end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube.

[0049] See also Figure 6In one embodiment of the present invention, the first MOS tube included in the first MOS tube group is an N-type MOS tube N1, the source of the first MOS tube is the second end of the first MOS tube, the drain of the first MOS tube is the first end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube. The second MOS tube included in the second MOS tube group is an N-type MOS tube N2 (the charge pump connected thereto may be a third charge pump CP3), the source of the second MOS tube is the second end of the second MOS tube, the drain of the second MOS tube is the first end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube.

[0050] See also Figure 7 In one embodiment of the present invention, the first MOS transistor included in the first MOS transistor group is a P-type MOS transistor P2 (the charge pump connected thereto may be a fourth charge pump CP4), the source of the first MOS transistor is the first end of the first MOS transistor, the drain of the first MOS transistor is the second end of the first MOS transistor, and the gate of the first MOS transistor is the third end of the first MOS transistor. The second MOS transistor included in the second MOS transistor group is a P-type MOS transistor P1, the source of the second MOS transistor is the first end of the second MOS transistor, the drain of the second MOS transistor is the second end of the second MOS transistor, and the gate of the second MOS transistor is the third end of the second MOS transistor.

[0051] The present invention further discloses a chip, which includes a chip body and the above-mentioned chip disconnection detection circuit, wherein the chip disconnection detection circuit is connected to the chip body.

[0052] In one embodiment of the present invention, the chip is provided with a power pin, a ground pin and an output pin; the second end of the first MOS tube group is connected to the ground pin, the first end of the first MOS tube group and the second end of the second MOS tube group are respectively connected to the output pin, and the first end of the second MOS tube group is connected to the power pin.

[0053] The present invention also discloses a chip disconnection detection method for the above-mentioned chip, the chip disconnection detection method comprising: if the voltage output by the output pin of the chip is close to the external ground voltage or close to the external power supply voltage, the chip is judged to be disconnected (such as the ratio of the voltage output by the output pin of the chip to the external ground voltage is within a set first threshold range, the chip is judged to be disconnected; or, the ratio of the voltage output by the output pin to the external power supply voltage is within a set second threshold range, the chip is judged to be disconnected); if the voltage output by the output pin of the chip is between the external ground voltage and the external power supply voltage, the chip is judged to be not disconnected. The first threshold range can be less than or equal to the first threshold (such as 5%), and the second threshold range can be greater than or equal to 95%.

[0054] In one embodiment of the present invention, when the output voltage is between 0V and 5% VBAT, it is called that the output voltage is close to VGND, and when the output voltage is between 95% and 100% VBAT, it is called that the output voltage is close to VBAT. The above situations can be judged as disconnection; and the range of 5% to 95% VBAT is between the two, that is, the chip is judged to be normal. Of course, the 5% and 95% here are commonly used values, and can also be larger or smaller.

[0055] The present invention proposes a method for detecting a disconnection of a chip power line or ground line, and sets the chip output voltage to be close to an external power supply VBAT or an external ground VGND when a disconnection occurs, thereby providing timely error warning information for an automobile control system.

[0056] The application of the present invention is not limited to automotive electronic systems. Any system that needs to warn of chip power and ground line disconnection accidents and can monitor chip output by a controller can use the method disclosed by the present invention.

[0057] The present invention proposes a method for detecting a disconnection of a chip power line or ground line, and can set the chip output OUT voltage to be close to an external power supply VBAT or an external ground VGND when a disconnection occurs, thereby providing a controller with disconnection protection warning information.

[0058] Specific implementation methods such as Figure 3 shown. Figure 3 VBAT and VGND are the external power supply and ground signal of the chip respectively. The dotted box indicates the chip range, including power supply VDD, ground VSS and output OUT, a total of 3 ports. When there is no disconnection, VBAT is connected to VDD, VGND is connected to VSS, RPU and RPD represent the pull-up resistor and pull-down resistor of the chip output to VBAT and VGND respectively. CORE inside the chip represents the core circuit, D1 and D2 are diodes, this diode can be a parasitic diode from the OUT drive transistor, or an electrostatic protection device from OUT, which is a common structure in integrated circuits. CP1 is a negative voltage charge pump, and CP2 is a positive voltage charge pump, and its output voltages are vgn and vgp respectively. N1 and P1 are depletion-type NMOS and depletion-type PMOS devices respectively. The gate terminal of N1 is connected to vgn, the source terminal is connected to VSS, and the drain terminal is connected to OUT; the gate terminal of P1 is connected to vgp, the source terminal is connected to VDD, and the drain terminal is connected to OUT, which is also the drain of N1.

[0059] It should be noted that N1 and P1 can be depletion-mode MOS devices, which are different from the commonly used enhancement-mode MOS. The threshold voltage VTHN of the depletion-mode NMOS is negative, so it can conduct when its gate-source voltage (VGS) is zero and turn off when VGS < VTH; the threshold voltage VTHP of the depletion-mode PMOS is positive, so it can conduct when its gate-source voltage (VGS) is zero and turn off when VGS > VTHP. However, the threshold voltage of the commonly used enhancement-mode NMOS is positive, and the threshold voltage of the enhancement-mode PMOS is negative, so it cannot conduct when VGS is zero.

[0060] In addition, CP1 and CP2 are charge pumps, which are modules well-known to integrated circuit designers and can generate voltages higher than the chip power supply VDD or lower than the chip ground VSS. Among them, CP1 is a negative voltage charge pump, with VSS as the reference voltage, and generates a negative voltage vgn < VSS + VTHN when the chip is working normally; CP2 is a positive voltage charge pump, with VDD as the reference voltage, and generates a positive voltage vgp > VDD + VTHP when the chip is working normally.

[0061] The working principle is as follows: As Figure 3 shown, when there is no wire break, the chip is normally powered, so CP1 generates a negative voltage vgn, and vgn < VSS + VTHN, (VTHN is the threshold voltage of N1), thus turning off N1; at the same time, CP2 generates a positive voltage vgp, and vgp > VDD + VTHP, that is, the gate-source voltage VGS of P1 = vgp - VDD > VTHP, so P1 is also turned off. That is to say, during normal operation, N1 and P1 used for wire break protection are both in the off state and will not affect the normal operation of the chip.

[0062] When an accidental wire break occurs in the power supply or ground wire of the chip, it is necessary to combine Figure 4 and Figure 5 for explanation. Among them Figure 4 is the case where the chip power supply VDD is accidentally disconnected, Figure 5 is the case where the chip ground VSS is accidentally disconnected.

[0063] As Figure 4 shown, the chip VDD has been disconnected from the external power supply VBAT, and here it is divided into two situations:

[0064] (1) The output OUT is connected to a pull-down resistor (only RPU = ∞) or the output OUT is floating (RPU = RPD = ∞)

[0065] At this time, since the chip ground VSS is still connected to VGND, but there is no path between the chip and VBAT, so the voltage of all nodes in the chip will eventually tend to VGND, that is, 0V, so OUT is finally 0V, which already meets the requirements of wire break protection warning.

[0066] (2) Output OUT connected to a pull-up resistor (only when RPD = ∞)

[0067] Although the chip VDD has lost power supply at this time, the current path of VBAT, RPU, D2, CORE, VSS still exists, and a VDD voltage can be determined. Since there is a voltage drop between RPU and D2 on the path, the voltage of VDD must be much smaller than VBAT at this time, causing the charge pumps CP1 and CP2 to fail to work properly. When the charge pump fails to work, its output will be equal to the reference voltage, that is, vgn=VSS, vgp=VDD, that is, the VGS of N1 and P1 are both zero, and P1 and N1 become conductive, which is equivalent to a very small resistance. At this time, since the resistance R(N1) of N1 decreases sharply, according to the resistance voltage division law, the voltage V(OUT) of OUT becomes:

[0068]

[0069] That is, the OUT voltage tends to 0V, meeting the requirements of line break protection warning.

[0070] Similarly, the chip VSS and external power supply VGND have been disconnected. Figure 5 As shown, there are also two situations:

[0071] (1) Output OUT is connected to a pull-up resistor (only RPD = ∞) or output OUT is left floating (RPU = RPD = ∞)

[0072] At this time, since the chip power supply VDD is still connected to VBAT, but there is no path between the chip and VGND, all node voltages in the chip will eventually tend to VBAT, so OUT is eventually equal to VBAT, which has met the requirements of line break protection warning.

[0073] (2) Output OUT connected to a pull-down resistor (only RPU=∞)

[0074] At this time, although the chip VSS has lost the ground signal, the current path of VDD, CORE, D1, RPD, VGND still exists, and a VSS voltage can be determined. Since there is a voltage drop between RPD and D1 on the path, the chip's power supply voltage VDD-VSS must be much smaller than VBAT, causing the charge pumps CP1 and CP2 to fail to work properly. When the charge pump fails to work, its output will be equal to the reference voltage, that is, vgn=VSS, vgp=VDD, that is, the VGS of N1 and P1 are both zero, and P1 and N1 become conductive, equivalent to a very small resistor. At this time, since the resistance R(P1) of P1 decreases sharply, according to the resistance voltage division law, the voltage V(OUT) of OUT becomes:

[0075]

[0076] That is, the OUT voltage tends to VBAT, meeting the requirements of open-circuit protection warning.

[0077] Adopt Figure 3 The chip structure shown with depletion devices N1, P1 and charge pumps CP1, CP2. Whether it is an accidental disconnection of the power supply line or the ground line, and regardless of the load form connected to the chip output, OUT can give a voltage close to VBAT or close to VGND after the disconnection occurs, thereby prompting the automotive control unit ECU to handle the power supply disconnection event and reducing the probability of safety accidents.

[0078] The other two embodiments of the present invention are respectively as Figure 6 and Figure 7 shown.

[0079] As Figure 6 , the difference between this embodiment and the embodiment shown in Figure 3 is that the depletion PMOS transistor P1 is replaced by a depletion NMOS transistor N2, and at the same time its gate voltage is driven by another charge pump CP3. CP3 uses the OUT voltage V(OUT) as the reference voltage. When working normally, it generates vgn2 < V(OUT) + VTHN, which is sufficient to turn off N2 and does not affect the normal operation of the chip; when there is a disconnection, vgn2 = V(OUT) is generated, so the VGS of N2 = 0, which is sufficient to turn on N2. When the chip is working normally or a disconnection occurs, its working principle is similar to that of Figure 4 , Figure 5 and will not be elaborated.

[0080] As Figure 7 , the difference between this embodiment and the embodiment shown in Figure 3 is that the depletion NMOS transistor N1 is replaced by a depletion PMOS transistor P2, and at the same time its gate voltage is driven by another charge pump CP4. CP4 uses the OUT voltage V(OUT) as the reference voltage. When working normally, it generates vgp2 > V(OUT) + VTHP, which is sufficient to turn off P2 and does not affect the normal operation of the chip; when there is a disconnection, vgp2 = V(OUT) is generated, so the VGS of P2 = 0, which is sufficient to turn on P2. When the chip is working normally or a disconnection occurs, its working principle is similar to that of Figure 4 , Figure 5 and will not be elaborated.

[0081] It should be noted that the depletion MOS transistors used in the present invention are not necessarily single devices as shown in Figure 3 , Figure 6 , Figure 7 but can also be a series connection of multiple devices, such as Figure 8 shown. Figure 8The devices MU1, MU2, ... MUm and MD1, MD2, ... MDn in the circuit can be either depletion-type NMOS or depletion-type PMOS, where the subscripts m and n are positive integers greater than 1. The series connection of multiple devices can be used to achieve additional functions such as high voltage resistance or reverse connection protection. When realizing the disconnection protection function, the principle of the series connection of multiple devices is the same as that of using a single device.

[0082] In summary, the chip disconnection detection circuit and method and chip proposed in the present invention can timely detect when the chip power line or ground line is disconnected, and set the chip output voltage to be close to the external power supply VBAT or the external ground VGND when the disconnection occurs, thereby providing timely error warning information for the automobile control system.

[0083] In one use scenario of the present invention, the present invention adds a depletion-type transistor between the chip output terminal OUT and the chip power supply VDD and the chip ground VSS, and uses a charge pump to bias the gate of the depletion-type transistor, so that when the power line or ground line of the chip is accidentally disconnected, the output OUT voltage can be close to the external power supply VBAT or the external ground VGND, as an abnormal alarm signal of disconnection, so that the upper-level control unit can handle the abnormality in time and reduce the probability of functional safety accidents. If the structure of the present invention is not adopted, when the chip is powered off, the output voltage V(OUT) may stop in the middle area between the external power supply VBAT and the external ground VGND, and this abnormal output signal will be regarded as a normal signal by the upper-level control unit, which may cause functional safety accidents.

[0084] In addition, the depletion-mode transistor used in the present invention is a component of the standard integrated circuit process, and the charge pump is a module well known to integrated circuit designers, so the solution is highly feasible in implementation.

[0085] It should be noted that the present application can be implemented in software and / or a combination of software and hardware; for example, it can be implemented using an application-specific integrated circuit (ASIC), a general-purpose computer, or any other similar hardware device. In some embodiments, the software program of the present application can be executed by a processor to implement the above steps or functions. Similarly, the software program of the present application (including related data structures) can be stored in a computer-readable recording medium; for example, a RAM memory, a magnetic or optical drive or a floppy disk and the like. In addition, some steps or functions of the present application can be implemented in hardware; for example, as a circuit that cooperates with a processor to perform various steps or functions.

[0086] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0087] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A chip disconnection detection circuit, characterized in that: The chip disconnection detection circuit is connected to the chip body to detect whether the power line and / or the ground line of the chip body are disconnected; The chip disconnection detection circuit comprises: a first MOS tube group, a second MOS tube group, a first diode, a second diode, a first charge pump, and a second charge pump; The first MOS tube group includes at least one first MOS tube, and the second MOS tube group includes at least one second MOS tube; The first end of the chip body is respectively connected to the first end of the second MOS tube group, the cathode of the second diode, and the first end of the second resistor; the second end of the second MOS tube group is respectively connected to the anode of the second diode, the first end of the first MOS tube group, the cathode of the first diode, the second end of the second resistor, and the first end of the first resistor; the second end of the chip body is respectively connected to the second end of the first MOS tube group and the anode of the first diode; the second end of the first resistor is grounded; The third end of the second MOS tube group is connected to the second charge pump, and the third end of the first MOS tube group is connected to the first charge pump; The first charge pump is a negative voltage charge pump, which uses the chip ground pin as a reference voltage and is used to output different types of voltages when the chip is working normally or abnormally; The second charge pump is a positive voltage charge pump, which uses the power supply voltage as a reference voltage and is used to output different types of voltages when the chip is working normally or abnormally; The first charge pump is used to generate a negative voltage when the chip is operating normally, and the output voltage is 0 when the power line and / or the ground line is disconnected; The second charge pump is used to generate a positive voltage when the chip is operating normally, and the output voltage is 0 when the power line and / or the ground line is disconnected.

2. The chip disconnection detection circuit according to claim 1, characterized in that: The first MOS tube group includes a first MOS tube, and the second MOS tube group includes a second MOS tube.

3. The chip disconnection detection circuit according to claim 1, characterized in that: The first MOS tube group includes a plurality of first MOS tubes, and the first MOS tubes are sequentially connected in series; the second MOS tube group includes a plurality of second MOS tubes, and the second MOS tubes are sequentially connected in series.

4. The chip disconnection detection circuit according to claim 1, characterized in that: The first MOS tube included in the first MOS tube group is an N-type MOS tube, the source of the first MOS tube is the second end of the first MOS tube, the drain of the first MOS tube is the first end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube; or, the first MOS tube included in the first MOS tube group is a P-type MOS tube, the source of the first MOS tube is the first end of the first MOS tube, the drain of the first MOS tube is the second end of the first MOS tube, and the gate of the first MOS tube is the third end of the first MOS tube; The second MOS tube included in the second MOS tube group is a P-type MOS tube, the source of the second MOS tube is the first end of the second MOS tube, the drain of the second MOS tube is the second end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube; or, the second MOS tube included in the second MOS tube group is an N-type MOS tube, the source of the second MOS tube is the second end of the second MOS tube, the drain of the second MOS tube is the first end of the second MOS tube, and the gate of the second MOS tube is the third end of the second MOS tube.

5. A chip, characterized in that: The chip comprises a chip body and a chip disconnection detection circuit as described in any one of claims 1 to 4, wherein the chip disconnection detection circuit is connected to the chip body.

6. The chip according to claim 5, characterized in that: The chip is provided with a power pin, a ground pin and an output pin; the second end of the first MOS tube group is connected to the ground pin, the first end of the first MOS tube group and the second end of the second MOS tube group are respectively connected to the output pin, and the first end of the second MOS tube group is connected to the power pin.

7. A chip disconnection detection method for the chip according to claim 6, characterized in that: The chip disconnection detection method comprises: If the voltage output by the chip's output pin is close to the external ground voltage or close to the external power supply voltage, the chip is judged to be disconnected; If the voltage output by the output pin of the chip is between the external ground voltage and the external power supply voltage, it is determined that the chip is not broken.

Images