Enhanced-mode gallium nitride high electron mobility transistor with stepped field plate structure and manufacturing method thereof

Abstract

The present invention discloses an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure and a method for manufacturing the same. In the enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure, both the gate-source connection region and the drain connection region are provided with a locally distributed second gate metal layer, the upper surface of each second gate metal layer is provided with a corresponding second interconnect metal layer, and one side of the second gate metal layer extends beyond the side of the second interconnect metal layer corresponding to its upper surface to form a stepped field plate structure. The present invention forms a stepped field plate structure by providing a second gate metal layer and a second interconnect metal layer in both the gate-source and gate-drain connection regions of the transistor. The stepped field plate structure is used to effectively improve the internal electric field distribution of the transistor under forward and reverse bias voltages, thereby increasing the breakdown voltage of the transistor and reducing leakage current. The metal layer constituting the stepped field plate structure and the metal layer of the transistor electrode region are formed simultaneously, and the preparation method is simple.

Description

Technical Field

[0001] The present invention relates to an enhanced gallium nitride high electron mobility transistor with a stepped field plate structure and a manufacturing method thereof, belonging to the technical field of semiconductors. Background Art

[0002] Gallium nitride (GaN) materials, due to their outstanding advantages such as wide bandgap, high breakdown field strength, fast electron saturation drift velocity, and high thermal conductivity, are suitable for the fabrication of power electronic devices with high power density, high switching speed, and high energy efficiency. Enhancement-mode high-electron-mobility transistors (EMHMTs) fabricated using GaN and its heterojunction materials are widely used in power electronic systems such as converters and inverters. These power electronic systems commonly utilize inductive components for energy storage and transfer. During transistor switching, the power supply transfers energy to these inductive components. When the energy stored in the inductive components is discharged into the transistor, it experiences a transient energy surge, generating a strong electric field within the transistor. When the transistor is in the forward blocking state, a strong electric field appears at the drain and gate-drain junction; when the transistor is in the reverse blocking state, a strong electric field appears at the source and gate-source junction. If this strong electric field exceeds the transistor's critical breakdown field, a breakdown failure point will occur within the transistor, causing device failure and potentially compromising the entire power electronic system.

[0003] Enhanced-mode gallium nitride high electron mobility transistors in the prior art are Figure 1 As shown in the figure, to reduce the strong electric field inside the transistor, the source and drain of the transistor are protected mainly by the edge field plate structure formed by the interconnected metal layers on both sides. However, existing technical solutions have difficulty in suppressing the strong electric field in the gate-source and gate-drain connection areas, especially the strong electric field in the gate-source area, and there is currently a lack of corresponding solutions. Summary of the Invention

[0004] In response to the deficiencies of the above-mentioned prior art, the present invention provides an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure and a method for manufacturing the same. By arranging a second gate metal layer and a second interconnect metal layer in the gate-source and gate-drain connection regions of the transistor to form a stepped field plate structure, the stepped field plate structure is utilized to effectively improve the internal electric field distribution of the transistor under forward and reverse bias voltages, thereby increasing the breakdown voltage of the transistor and reducing leakage current. The metal layer constituting the stepped field plate structure and the metal layer in the transistor electrode region are formed simultaneously, and the preparation method is simple, providing a solution for improving the forward and reverse blocking capabilities of the enhancement-mode gallium nitride high electron mobility transistor.

[0005] In order to solve the above technical problems, the technical solutions adopted by the present invention are as follows:

[0006] An enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure comprises, from bottom to top, a substrate layer, a gallium nitride layer, and an aluminum gallium nitride layer; a p-type gallium nitride layer is provided on the upper surface of the aluminum gallium nitride layer, and ohmic metal layers are distributed on both sides of the gallium nitride layer at unequal intervals, wherein the ohmic metal layer closer to the p-type gallium nitride layer forms the source of the transistor, and the ohmic metal layer farther from the p-type gallium nitride layer forms the drain of the transistor; a first gate metal layer is provided on the upper surface of the p-type gallium nitride layer to form the gate of the transistor, a gate-source connection region is provided between the gate and the source, and a gate-drain connection region is provided between the gate and the drain, and a first interconnect metal layer is provided on the upper surface of the ohmic metal layer;

[0007] Both the gate-source connection area and the drain connection area are provided with a locally distributed second gate metal layer, and the upper surface of each second gate metal layer is provided with a corresponding second interconnection metal layer. One side of the second gate metal layer extends beyond the side of the second interconnection metal layer corresponding to its upper surface to form a stepped field plate structure.

[0008] A second interconnect metal layer is correspondingly provided on the upper surface of each of the above-mentioned second gate metal layers, and one side of the second gate metal layer extends beyond the side of the second interconnect metal layer corresponding to its (second gate metal layer) upper surface, that is, there is a position deviation in the vertical direction between the second gate metal layer and the second interconnect metal layer on its upper surface.

[0009] The aforementioned stepped field plate structure can improve the distribution of strong electric fields within the transistor under forward and reverse bias voltages, thereby increasing the transistor's breakdown voltage and reducing leakage current. When the transistor is in the off state, the stepped field plate structure in the gate-source connection region improves the electric field distribution between the gate and source during reverse withstand voltage, thereby increasing its reverse breakdown voltage. Reverse withstand voltage refers to the situation where a high voltage is applied to the transistor's source and the gate and drain are short-circuited. The stepped field plate structure in the gate-drain connection region improves the electric field distribution between the gate and drain during forward withstand voltage, thereby increasing its forward breakdown voltage. Forward withstand voltage refers to the situation where a high voltage is applied to the transistor's drain and the gate and source are short-circuited.

[0010] The metal layer constituting the above-mentioned stepped field plate junction and the metal layer in the transistor electrode region can be formed simultaneously. The preparation method is simple, and provides a solution for simultaneously improving the forward and reverse blocking capabilities of the enhancement-mode gallium nitride high electron mobility transistor.

[0011] The device of the present application can be used in power electronic systems.

[0012] The directional words such as up and down, left and right, horizontal, and vertical in this application are all based on the relative directions or positional relationships shown in the drawings and should not be understood as absolute limitations on this application.

[0013] The horizontal lengths of the second gate metal layer and the second interconnect metal layer corresponding thereto are both greater than the horizontal length of the overlapping region between the two. That is, if one side of the second gate metal layer extends beyond the side of the second interconnect metal layer corresponding to its top surface, the other side of the second gate metal layer is retracted inwardly of the other side of the second interconnect metal layer.

[0014] To further improve device performance, in the gate-source connection region, the leftmost end of each second interconnect metal layer is closer to the source electrode than the leftmost end of its corresponding second gate metal layer, forming a lower stepped field plate structure. The horizontal length of the overlapping area between each second interconnect metal layer and its corresponding second gate metal layer is 100-500nm. In the gate-drain connection region, the rightmost end of each second interconnect metal layer is closer to the drain electrode than the rightmost end of its corresponding second gate metal layer, forming an upper stepped field plate structure. The horizontal length of the overlapping area between each second interconnect metal layer and its corresponding second gate metal layer is 100-800nm. To conserve metal layer area, the horizontal length of the overlapping area between the interconnect metal layer and the gate metal layer should be as small as possible.

[0015] When the transistor is in the off state, the lower stepped field plate structure in the gate-source connection area can improve the electric field distribution between the gate and the source of the transistor during reverse withstand voltage, thereby increasing its reverse breakdown voltage. The reverse withstand voltage refers to the application of a high voltage to the source of the transistor and the short circuit of the gate and the drain; the upper stepped field plate structure in the gate-drain connection area can improve the electric field distribution between the gate and the drain of the transistor during forward withstand voltage, thereby increasing its forward breakdown voltage. The forward withstand voltage refers to the application of a high voltage to the drain of the transistor and the short circuit of the gate and the source.

[0016] The top of the p-type gallium nitride layer is flush with the bottoms of the first gate metal layer and the second gate metal layer.

[0017] In order to take into account both device performance and miniaturization requirements, in the gate-source connection area, the horizontal length occupied by each second gate metal layer and its corresponding second interconnect metal layer is 200-1200nm; in the gate-drain connection area, the horizontal length occupied by each second gate metal layer and its corresponding second interconnect metal layer is 200-8000nm.

[0018] For ease of fabrication, the first gate metal layer and the second gate metal layer are formed simultaneously; the first interconnect metal layer and the second interconnect metal layer are formed simultaneously.

[0019] The second gate metal layer and the second interconnect metal layer are both deposited in the groove of the etched dielectric layer by using a plasma enhanced chemical vapor deposition method.

[0020] The method for manufacturing the enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure comprises the following steps:

[0021] (1) The epitaxial wafer includes a substrate layer, a gallium nitride layer, an aluminum gallium nitride layer, and a p-type gallium nitride layer from bottom to top. The p-type gallium nitride layer in the non-patterned area is removed by inductively coupled plasma dry etching, so that only the gate area retains the p-type gallium nitride layer;

[0022] (2) using a photolithography lift-off method, depositing an ohmic metal layer simultaneously in the source and drain regions, and then performing a high-temperature annealing treatment at 800-900°C in a nitrogen atmosphere for 20-40 seconds to form an ohmic contact;

[0023] (3) using plasma enhanced chemical vapor deposition to cover the entire epitaxial wafer with a gate dielectric layer, and then using inductively coupled plasma dry etching to remove the gate dielectric layer above the p-type gallium nitride layer and in the local areas of the gate source and gate drain, thereby forming a locally distributed groove area;

[0024] (4) depositing a gate metal layer (including the first and second gate metal layers) in the locally distributed groove region obtained in step (3) by using a photolithography lift-off method;

[0025] (5) using a plasma enhanced chemical vapor deposition method to cover the entire epitaxial wafer with a passivation dielectric layer, and then using an inductively coupled plasma dry etching method to remove the passivation dielectric layer above the ohmic electrode and the local areas of the gate source and gate drain, thereby forming a locally distributed groove area;

[0026] (6) using a photolithography lift-off method, depositing interconnect metal layers (including first and second interconnect metal layers) in the locally distributed groove regions obtained in step (5), and then depositing PAD thickened metal layers on the gate, source, and drain electrode metals of the transistors, respectively, scribing the epitaxial wafer along the scribing lanes, and packaging individual transistors to complete transistor fabrication;

[0027] In the above step (3), the gate dielectric layer is a single-layer dielectric layer formed by one material selected from silicon dioxide, silicon nitride or aluminum oxide, or a multi-layer dielectric layer formed by multiple materials, and the thickness of the gate dielectric layer is 100-1000nm; in step (4), the gate metal layer contains titanium nitride alloy, and the thickness of the gate metal layer is 100-1000nm; in step (5), the passivation dielectric layer is a single-layer dielectric layer formed by one material selected from silicon dioxide, silicon nitride or polyimide, or a multi-layer dielectric layer formed by multiple materials, and the thickness of the dielectric layer is 1000-4000nm; in step (6), the interconnect metal layer contains titanium metal and aluminum metal, and the thickness of the interconnect metal layer is 1000-5000nm; the photolithography stripping method in steps (2), (4) and (6) is as follows: first, a photoresist is covered on the non-patterned area, and then a metal layer is deposited on the epitaxial wafer by a plasma enhanced chemical vapor deposition method, and the metal layer in the non-patterned area is removed by a stripping method, and finally a metal layer is left in the patterned area.

[0028] The technologies not mentioned in this invention are all referred to the prior art.

[0029] The enhanced gallium nitride high electron mobility transistor with a stepped field plate structure of the present invention has the following beneficial effects:

[0030] (1) The gate-source and gate-drain connection regions of the transistor of the present invention are formed of a stepped field plate structure composed of a gate metal layer and an interconnect metal layer, which can suppress the gate leakage current when the transistor is in the off state; when the device is in the off state, the stepped field plate structure of the gate-source connection region can effectively modulate the electric field distribution between the gate and the source of the transistor during reverse withstand voltage, reduce the electric field on the side of the gate close to the source, effectively reduce the gate leakage current, and significantly enhance the reliability of the device in the reverse off state; the stepped field plate structure of the gate-drain connection region can effectively modulate the electric field distribution between the gate and the drain of the transistor during forward withstand voltage, reduce the electric field on the side of the gate close to the drain, effectively reduce the gate leakage current, and significantly enhance the reliability of the device in the forward off state. Therefore, the stepped field plate structure of the present invention can simultaneously improve the reliability of the transistor in both the forward and reverse off states;

[0031] (2) The metal layer constituting the stepped field plate structure and the metal layer in the transistor electrode region of the present invention are formed simultaneously, which is compatible with the method steps of the prior art. Therefore, the preparation method is simple and has commercial promotion value;

[0032] (3) Since the gate metal layer and the interconnect metal layer in the stepped field plate structure have a position deviation in the vertical direction, rather than the interconnect metal layer completely covering the gate metal layer, it can save metal area and reduce transistor R&D costs;

[0033] (4) The present invention provides a gate metal layer and an interconnect metal layer in both the gate-source and gate-drain connection regions of the transistor, and the gate metal layer and the interconnect metal layer have a position deviation in the vertical direction. As a further preferred embodiment, on the one hand, the leftmost end of the interconnect metal layer in the gate-source connection region is closer to the source electrode than the leftmost end of the gate metal layer, forming a lower stepped field plate structure, thereby suppressing the strong electric field in the gate-source connection region and improving the reverse breakdown voltage; on the other hand, the rightmost end of the interconnect metal layer in the gate-drain connection region is closer to the drain electrode than the rightmost end of the gate metal layer, forming an upper stepped field plate structure, thereby suppressing the strong electric field in the gate-drain connection region and improving the forward breakdown voltage. Therefore, the stepped field plate structure in the present invention can simultaneously improve the forward and reverse blocking capabilities of the transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 This is a schematic diagram of the structure of a gallium nitride high electron mobility transistor in the prior art;

[0035] Figure 2 This is a schematic diagram of the structure of an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure according to the present invention;

[0036] Figure 3 A schematic flow chart of a method for manufacturing an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure according to the technical solution of the present invention;

[0037] Figure 4a-4b The electric field distribution diagram in the barrier layer obtained by simulating the conventional device and the device of the present invention ( Figure 4a For the case where high voltage is applied to the drain and the gate and source are grounded, Figure 4b (This is the case where a high voltage is applied to the source and the gate and drain are grounded). DETAILED DESCRIPTION

[0038] In order to better understand the present invention, the content of the present invention is further illustrated below in conjunction with the examples, but the content of the present invention is not limited to the following examples.

[0039] Example 1

[0040] like Figure 2As shown, an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure comprises a p-type gallium nitride layer 4, and ohmic metal layers 5 of varying intervals are distributed on both sides of the gallium nitride layer 4, wherein the ohmic metal layer 5 closer to the p-type gallium nitride layer 4 forms the source of the transistor, and the ohmic metal layer 5 farther from the p-type gallium nitride layer 4 forms the drain of the transistor; a first gate metal layer 61 is provided on the upper surface of the p-type gallium nitride layer 4 to form the gate of the transistor, a gate-source connection region exists between the gate and the source, a gate-drain connection region exists between the gate and the drain, and a first interconnection region is provided on the upper surface of the ohmic metal layer 5. The gate-source connection area and the drain connection area are both provided with a locally distributed second gate metal layer 62. Each second gate metal layer 62 has a corresponding second interconnect metal layer 72 on its upper surface. One side of the second gate metal layer 62 extends beyond the side of the corresponding second interconnect metal layer 72 on its upper surface, forming a stepped field plate structure. This means that the second gate metal layer 62 and its corresponding second interconnect metal layer 72 are vertically offset, and the horizontal lengths of the second gate metal layer 62 and its corresponding second interconnect metal layer 72 are both greater than the horizontal length of their overlapping region. The top of the p-type gallium nitride layer 4 is flush with the bottoms of the first gate metal layer 61 and the second gate metal layer 62.

[0041] In the gate-source connection area, the leftmost end of each second interconnect metal layer 72 is closer to the source than the leftmost end of its corresponding second gate metal layer 62, forming a lower stepped field plate structure, and the horizontal length of the overlapping area between each second interconnect metal layer 72 and its corresponding second gate metal layer 62 is 100-500nm; in the gate-drain connection area, the rightmost end of each second interconnect metal layer 72 is closer to the drain than the rightmost end of its corresponding second gate metal layer 62, forming an upper stepped field plate structure, and the horizontal length of the overlapping area between each second interconnect metal layer 72 and its corresponding second gate metal layer 62 is 100-800nm. When the transistor is in the off state, the stepped field plate structure in the gate-source connection region can improve the electric field distribution between the gate and source of the transistor during reverse withstand voltage, thereby increasing its reverse breakdown voltage. Reverse withstand voltage refers to the situation where a high voltage is applied to the source of the transistor and the gate and drain are short-circuited. The stepped field plate structure in the gate-drain connection region can improve the electric field distribution between the gate and drain of the transistor during forward withstand voltage, thereby increasing its forward breakdown voltage. Forward withstand voltage refers to the situation where a high voltage is applied to the drain of the transistor and the gate and source are short-circuited. At the same time, when the transistor is in the off state, the lower stepped field plate structure in the gate-source connection region can effectively modulate the electric field distribution between the gate and source of the transistor during reverse withstand voltage, reducing the electric field on the source side of the gate, effectively reducing gate leakage current, and significantly enhancing the reliability of the device in the reverse off state. The upper stepped field plate structure in the gate-drain connection region can effectively modulate the electric field distribution between the gate and drain of the transistor during forward withstand voltage, reducing the electric field on the drain side of the gate, effectively reducing gate leakage current, and significantly enhancing the reliability of the device in the forward off state. The first gate metal layer 61 and the second gate metal layer 62 are formed simultaneously; the first interconnect metal layer 71 and the second interconnect metal layer 72 are formed simultaneously.

[0042] The method for manufacturing the enhanced gallium nitride high electron mobility transistor with a stepped field plate structure is as follows: Figure 3 As shown, the following steps are included:

[0043] Step 1: If Figure 3 As shown in a, the p-type gallium nitride layer 4 is etched:

[0044] The epitaxial wafer includes, from bottom to top, a substrate layer 1, a gallium nitride layer 2, an aluminum gallium nitride layer 3, and a p-type gallium nitride layer 4. Using an inductively coupled plasma dry etching process, the p-type gallium nitride layer 4 in the non-patterned area is removed, leaving only the gate area with the p-type gallium nitride layer 4.

[0045] Step 2: If Figure 3 As shown in b, an ohmic metal layer 5 is deposited:

[0046] Using a photolithography lift-off process, Ti / Al ohmic metal layers 5 with a thickness of 200nm / 1000nm are deposited in the source and drain regions simultaneously, and then subjected to a high-temperature annealing treatment at 850°C in a nitrogen atmosphere for 30 seconds to form ohmic contacts;

[0047] Step 3: Etching the silicon nitride gate dielectric layer:

[0048] Using a plasma-enhanced chemical vapor deposition process, a 200nm thick silicon nitride gate dielectric layer is deposited on the entire epitaxial wafer. Subsequently, an inductively coupled plasma dry etching process is used to remove the gate dielectric layer above the p-type gallium nitride layer 4 and in the gate-source and gate-drain regions, forming locally distributed groove regions. The horizontal lengths of individual grooves in the gate-source connection region and the gate-drain connection region are 500nm and 4000nm, respectively. Note: The accompanying drawings are schematic diagrams and do not depict the grooves to scale.

[0049] Step 4: If Figure 3 As shown in c, a gate metal layer 6 is deposited:

[0050] Using a photolithography lift-off process, TiN / Al gate metal layers 6 with a thickness of 100 nm / 500 nm are sequentially deposited in the locally distributed groove areas in step 3;

[0051] Step 5: Etching the silicon dioxide passivation dielectric layer:

[0052] Using a plasma-enhanced chemical vapor deposition process, a 3000nm thick silicon dioxide dielectric layer is deposited on the entire epitaxial wafer. Subsequently, an inductively coupled plasma dry etching process is used to remove the passivation dielectric layer above the ohmic electrode 5 and in the local areas of the gate-source and gate-drain regions, forming locally distributed groove regions. The horizontal lengths of the grooves in the gate-source and gate-drain connection regions are 500nm and 4000nm, respectively.

[0053] Step 6: Figure 3 As shown in d, an interconnect metal layer 7 is deposited:

[0054] Using the photolithography stripping process, a Ti / Al interconnect metal layer 7 with a thickness of 500nm / 4000nm is deposited in the locally distributed groove area in step 5. The horizontal lengths of the overlapping areas of the gate metal layer 6 and the interconnect metal layer 7 in the gate-source connection area and the gate-drain connection area are 100nm and 300nm respectively. Subsequently, a PAD thickened metal layer is deposited on the gate, source and drain electrode metals of the transistor respectively, the epitaxial wafer is diced along the dicing lanes, and a single transistor is packaged to finally complete the transistor preparation.

[0055] Figure 4a-4bThe electric field simulation diagrams in the barrier layer of the conventional device and the stepped field plate structure device adopted by the present invention are given respectively. Figure 4a For the case where high voltage is applied to the drain and the gate and source are grounded, Figure 4b This figure shows the case where a high voltage is applied to the source and the gate and drain are grounded. As can be seen from this figure, compared to conventional devices, the electric field at the peak electric field of the stepped field plate structure device employed in the present invention is significantly smaller than that of conventional devices under the same operating conditions. Since the device's breakdown voltage is the voltage at which the barrier layer reaches the critical electric field, this indicates that both the forward and reverse breakdown voltages of the device of the present invention are significantly greater than those of conventional devices.

Claims

1. A method for manufacturing an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure, characterized in that: An enhanced gallium nitride high electron mobility transistor with a stepped field plate structure comprises, from bottom to top, a substrate layer (1), a gallium nitride layer (2), and an aluminum gallium nitride layer (3); a p-type gallium nitride layer (4) is provided on the upper surface of the aluminum gallium nitride layer (3); ohmic metal layers (5) with unequal intervals are distributed on both sides of the gallium nitride layer (4), wherein the ohmic metal layer (5) closer to the p-type gallium nitride layer (4) forms the source of the transistor, and the ohmic metal layer (5) farther from the p-type gallium nitride layer (4) forms the drain of the transistor; a first gate metal layer (61) is provided on the upper surface of the p-type gallium nitride layer (4) to form the gate of the transistor, a gate-source connection region is provided between the gate and the source, and a gate-drain connection region is provided between the gate and the drain, and a first interconnect metal layer (71) is provided on the upper surface of the ohmic metal layer (5); The gate-source connection region and the gate-drain connection region are both provided with a second gate metal layer (62) that is locally distributed, and the upper surface of each second gate metal layer (62) is provided with a corresponding second interconnection metal layer (72), and one side of the second gate metal layer (62) extends beyond the side of the second interconnection metal layer (72) corresponding to its upper surface, forming a stepped field plate structure; A method for manufacturing an enhancement-mode gallium nitride high electron mobility transistor with a stepped field plate structure comprises the following steps: 1) The epitaxial wafer includes, from bottom to top, a substrate layer (1), a gallium nitride layer (2), an aluminum gallium nitride layer (3), and a p-type gallium nitride layer (4); the p-type gallium nitride layer (4) in the non-patterned area is removed by an inductively coupled plasma dry etching method, so that only the gate area retains the p-type gallium nitride layer (4); 2) using a photolithography lift-off method, depositing an ohmic metal layer (5) simultaneously on the source and drain regions, and then performing a high-temperature annealing treatment on the layer in a nitrogen atmosphere at 800-900° C. for 20-40 seconds to form an ohmic contact; 3) using a plasma enhanced chemical vapor deposition method to cover the entire epitaxial wafer with a gate dielectric layer, and then using an inductively coupled plasma dry etching method to remove the gate dielectric layer above the p-type gallium nitride layer (4) and in the local areas of the gate source and gate drain, thereby forming a locally distributed groove area; 4) using a photolithography lift-off method, depositing a gate metal layer (6) in the locally distributed groove region obtained in step 3), the gate metal layer (6) comprising a first gate metal layer (61) and a second gate metal layer (62); 5) using a plasma enhanced chemical vapor deposition method to cover the entire epitaxial wafer with a passivation dielectric layer, and then using an inductively coupled plasma dry etching method to remove the passivation dielectric layer above the ohmic metal layer (5) and the local areas of the gate source and gate drain, thereby forming a locally distributed groove area; 6) Using a photolithographic stripping method, an interconnect metal layer (7) is deposited in the locally distributed groove area obtained in step 5), wherein the deposited interconnect metal layer (7) includes a first interconnect metal layer (71) and a second interconnect metal layer (72), and then a PAD thickened metal layer is deposited on the gate, source, and drain electrode metals of the transistor respectively, and the epitaxial wafer is diced along the dicing path, and a single transistor is packaged, thereby completing the transistor preparation.

2. The production method according to claim 1, characterized in that In step 3), the gate dielectric layer is a single dielectric layer formed of one material selected from silicon dioxide, silicon nitride or aluminum oxide, or a multi-layer dielectric layer formed of multiple materials, and the thickness of the gate dielectric layer is 100-1000 nm; In step 4), the gate metal layer (6) comprises a titanium nitride alloy, and the thickness of the gate metal layer (6) is 100-1000 nm; In step 5), the passivation dielectric layer is a single dielectric layer formed of one material selected from silicon dioxide, silicon nitride, or polyimide, or a multi-layer dielectric layer formed of multiple materials, and the thickness of the dielectric layer is 1000-4000 nm; In step 6), the interconnection metal layer (7) contains titanium metal and aluminum metal, and the thickness of the interconnection metal layer (7) is 1000-5000 nm; The photolithography stripping method in steps 2), 4), and 6) is as follows: first, a photoresist is applied to cover the non-patterned area, a metal layer is deposited on the epitaxial wafer using plasma-enhanced chemical vapor deposition, and the metal layer in the non-patterned area is removed using a stripping method, leaving the metal layer in the patterned area.

3. The production method according to claim 1 or 2, characterized in that: The horizontal lengths of the second gate metal layer (62) and the corresponding second interconnect metal layer (72) are both greater than the horizontal length of the overlapping region thereof.

4. The production method according to claim 3, characterized in that: In the gate-source connection region, the leftmost end of each second interconnect metal layer (72) is closer to the source electrode than the leftmost end of its corresponding second gate metal layer (62), forming a lower stepped field plate structure, and the horizontal length of the overlapping region of each second interconnect metal layer (72) and its corresponding second gate metal layer (62) is 100-500 nm; In the gate-drain connection area, the rightmost end of each second interconnect metal layer (72) is closer to the drain than the rightmost end of its corresponding second gate metal layer (62), forming an upper stepped field plate structure, and the horizontal dimension length of the overlapping area of ​​each second interconnect metal layer (72) and its corresponding second gate metal layer (62) is 100-800 nm.

5. The production method according to claim 1 or 2, characterized in that: The top of the p-type gallium nitride layer (4) is flush with the bottoms of the first gate metal layer (61) and the second gate metal layer (62).

6. The production method according to claim 1 or 2, characterized in that: In the gate-source connection region, the horizontal length occupied by each second gate metal layer (62) and the corresponding second interconnect metal layer (72) is 200-1200 nm; In the gate-drain connection region, the horizontal length occupied by each second gate metal layer (62) and the corresponding second interconnect metal layer (72) is 200-8000 nm.

7. The production method according to claim 1 or 2, characterized in that: When the transistor is in the off state, the stepped field plate structure in the gate-source connection area can improve the electric field distribution between the gate and the source of the transistor during reverse withstand voltage, thereby increasing its reverse breakdown voltage. Reverse withstand voltage refers to the situation where a high voltage is applied to the source of the transistor and the gate and drain are short-circuited. The stepped field plate structure in the gate-drain connection area can improve the electric field distribution between the gate and the drain of the transistor during forward withstand voltage, thereby increasing its forward breakdown voltage. Forward withstand voltage refers to the situation where a high voltage is applied to the drain of the transistor and the gate and source are short-circuited.

8. The production method according to claim 1 or 2, characterized in that: The first gate metal layer (61) and the second gate metal layer (62) are formed simultaneously; the first interconnect metal layer (71) and the second interconnect metal layer (72) are formed simultaneously.

9. The production method according to claim 1 or 2, characterized in that: The second gate metal layer (62) and the second interconnect metal layer (72) are both deposited in the etched dielectric layer groove using a plasma enhanced chemical vapor deposition method.

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