Semiconductor process method, chip and manufacturing method thereof

Abstract

A semiconductor process method is provided. The method includes bonding a device wafer to a carrier wafer. The device wafer is to be thinned from an initial thickness to a target thickness. The method also includes determining the radial dimension of an unbonded area formed between the device wafer and the carrier wafer. The unbonded area extends radially from the edge of the bonding interface between the device wafer and the carrier wafer along the radial direction of the device wafer to the edge of the device wafer. The method also includes thinning the device wafer from an initial thickness to an intermediate thickness. The intermediate thickness is greater than or equal to a predetermined proportion of the radial dimension. The method also includes filling the unbonded area so that the radial dimension of the unfilled area in the unbonded area is reduced to below a critical dimension. The critical dimension is a function of the target thickness. The method also includes thinning the device wafer from the intermediate thickness to the target thickness.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, in particular to the field of semiconductor manufacturing technology, and specifically to a semiconductor process method, a chip manufacturing method, and a chip. Background Art

[0002] In wafer manufacturing technologies for fields such as integrated circuits, optoelectronic components, and micro-electromechanical sensors, it is necessary to reduce the thickness of device wafers from the millimeter level to the micrometer level. Thinning of device wafers can be achieved by bonding the device wafer to a carrier wafer and grinding the device wafer.

[0003] During the thinning process, when the device wafer is thinned to a relatively thin thickness, it often breaks and falls off at the edge of the wafer, which is called chipping. This phenomenon may make it impossible to perform subsequent processing on the device wafer, and may also cause an increase in particle contaminants in the grinding machine, and may even damage the grinding machine in severe cases. In addition, this phenomenon may also lead to a decrease in product yield. Therefore, it is necessary to avoid chipping during the thinning process. Summary of the invention

[0004] The present disclosure provides a semiconductor process method, a chip manufacturing method and a chip.

[0005] According to one aspect of the present disclosure, a semiconductor process method is provided. The method includes bonding a device wafer to a carrier wafer. The device wafer is to be thinned from an initial thickness to a target thickness. The method also includes determining the radial dimension of an unbonded area formed between the device wafer and the carrier wafer. The unbonded area extends radially from the edge of the bonding interface between the device wafer and the carrier wafer along the radial direction of the device wafer to the edge of the device wafer. The method also includes thinning the device wafer from an initial thickness to an intermediate thickness. The intermediate thickness is greater than or equal to a predetermined proportion of the radial dimension. The method also includes filling the unbonded area so that the radial dimension of the unfilled unfilled area in the unbonded area is reduced to below a critical dimension. The critical dimension is a function of the target thickness. The method also includes thinning the device wafer from the intermediate thickness to a target thickness.

[0006] According to another aspect of the present disclosure, a method for manufacturing a chip is provided, which includes providing a wafer for manufacturing a chip, wherein the wafer is thinned according to the method described above.

[0007] According to another aspect of the present disclosure, a chip is provided. The chip is manufactured according to the method described above.

[0008] According to one or more embodiments of the present disclosure, the edge chipping problem occurring during wafer thinning may be solved.

[0009] These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Further details, features and advantages of the present disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0011] Figure 1 A flowchart of a semiconductor process method according to an embodiment of the present disclosure is shown.

[0012] Figures 2A to 2H A schematic diagram showing a semiconductor processing method according to an embodiment of the present disclosure is shown.

[0013] Figures 3A to 3H A schematic diagram showing a semiconductor processing method according to another embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0014] It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

[0015] Spatially relative terms such as "below," "beneath," "lower," "below," "above," "upper," and the like may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as "below other elements or features" or "below other elements or features" or "below other elements or features" will be oriented to "above other elements or features." Therefore, the exemplary terms "below" and "below" can cover both orientations above and below. Terms such as "before" or "before" and "after" or "followed by" can be similarly used, for example, to indicate the order in which light passes through the elements. The device can be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used in this article are interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between two layers,” it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0016] The terms used herein are only for the purpose of describing a specific embodiment and are not intended to limit the present disclosure. As used herein, the singular forms "one", "one" and "the" are intended to also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "include" and / or "comprise" specify the existence of the features, integral bodies, steps, operations, elements and / or parts when used in this specification, but do not exclude the existence of one or more other features, integral bodies, steps, operations, elements, parts and / or their groups or add one or more other features, integral bodies, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of A and B" refers to only A, only B, or both A and B.

[0017] It will be understood that when an element or layer is referred to as being "on another element or layer," "connected to another element or layer," "coupled to another element or layer," or "adjacent to another element or layer," it may be directly on another element or layer, directly connected to another element or layer, directly coupled to another element or layer, or directly adjacent to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "directly on another element or layer," "directly connected to another element or layer," "directly coupled to another element or layer," or "directly adjacent to another element or layer," there are no intermediate elements or layers. However, in no case should "on..." or "directly on..." be interpreted as requiring that one layer completely cover the layer below.

[0018] Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations in the illustrated shapes, for example as a result of manufacturing techniques and / or tolerances, should be expected. Therefore, embodiments of the present disclosure should not be interpreted as being limited to the specific shapes of the zones illustrated herein, but should include shape deviations, for example, due to manufacturing. Therefore, the zones illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the zones of the device and are not intended to limit the scope of the present disclosure.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the relevant art and / or the context of this specification, and will not be interpreted in an idealized or overly formal sense, unless explicitly defined as such herein.

[0020] As used herein, the term "substrate" may refer to the substrate of a cut wafer, or may indicate the substrate of an uncut wafer. Similarly, the terms chip and die may be used interchangeably unless such interchange would cause a conflict. It should be understood that the term "layer" includes thin films and should not be interpreted as indicating vertical or horizontal thickness unless otherwise specified.

[0021] In the related art, some methods for solving the edge collapse problem have been proposed. One method is to trim the device wafer before performing the thinning process to remove the rounded and / or sharp structures on the device wafer that are not conducive to bonding. Another method is to perform injection molding to seal the bonded device wafer and carrier wafer, and fill the gap between the device wafer and the carrier wafer with an organic polymer.

[0022] However, the above two traditional methods still cannot completely solve the edge collapse problem caused by the thinning process. For the first method, when the bonding quality between the device wafer and the carrier wafer is not high, there is a narrow gap between the device wafer and the carrier wafer. The narrow gap may cause structural instability during the thinning process, thereby causing edge collapse. For the second method, due to the limitation of the injection molding edge sealing process filled with organic polymers, not only the filling degree of the gap cannot be guaranteed, but also the cleanliness of the wafer and the implementation of subsequent high-temperature processes will be affected. At the same time, it is also difficult to extend to non-circular wafers or die-to-wafer bonding methods.

[0023] In view of at least one of the above problems, according to one aspect of an embodiment of the present disclosure, a semiconductor process method is proposed.

[0024] Figure 1 FIG. 1 is a flow chart of a semiconductor process method 100 according to an embodiment of the present disclosure. Figure 1 As shown, the method 100 includes steps S110 to S150.

[0025] In step S110 , the device wafer is bonded to the carrier wafer. The device wafer is thinned from an initial thickness to a target thickness.

[0026] In the example, it is generally necessary to thin the device wafer from the millimeter level to the micron level, for example, from hundreds of microns to tens of microns. The device wafer may refer to a wafer or a die, and the shape may not be limited to a circle (such as a rectangle or a polygon). One device wafer may be thinned, or multiple device wafers may be thinned simultaneously.

[0027] In an example, the carrier wafer can play a role of mechanically supporting the device wafer during the thinning process. The carrier wafer can contain semiconductor device structures on its surface or inside, or may not contain semiconductor device structures.

[0028] In an example, the device wafer may be bonded to the carrier wafer using a direct bonding process or a hybrid bonding process.

[0029] In step S120, the radial dimension of the unbonded area formed between the device wafer and the carrier wafer is determined. The unbonded area extends from the edge of the bonding interface between the device wafer and the carrier wafer along the radial direction of the device wafer to the edge of the device wafer.

[0030] In an example, the unbonded area may be in the shape of a gap. For example, the gap may have a vertical height of about 10 nm to 10 μm and a length (ie, radial dimension) of the order of millimeters. In an example, the radial dimension may be measured by an ultrasonic scanning device or an infrared imaging device.

[0031] The inventors have found through research that the probability of edge collapse in the thinning process is correlated with the radial size of the unbonded area. When the radial size of the unbonded area is less than or equal to a certain predetermined size, the probability of edge collapse can be significantly reduced, and the predetermined size is associated with the remaining wafer thickness after thinning. In other words, the thinning process is performed while considering the relationship between the radial size of the unbonded area and the remaining wafer thickness after thinning, so that the edge collapse phenomenon can be avoided or at least minimized.

[0032] Therefore, according to an embodiment of the present disclosure, before executing the first thinning process such as step S130, the radial dimension of the unbonded area formed between the device wafer and the carrier wafer is first determined, and the radial dimension is used as a reference to control the thinning degree in the first thinning process, that is, the remaining wafer thickness after thinning, thereby avoiding edge collapse in the first thinning process.

[0033] In step S130 , the device wafer is thinned from an initial thickness to an intermediate thickness, wherein the intermediate thickness is greater than or equal to a predetermined ratio of the radial dimension.

[0034] In an example, a device wafer may be thinned from an initial thickness to an intermediate thickness by a rough thinning process. The device wafer may be thinned to a certain extent quickly by the rough thinning process. The rough thinning process may be performed by a mechanical grinding device.

[0035] In the example, when the bonding quality between the device wafer and the carrier wafer is poor, there may be a large unbonded area between the device wafer and the carrier wafer, such as a large gap. Therefore, such gaps can be preliminarily removed by means of a first thinning process from the initial thickness to the intermediate thickness, while only smaller gaps with a vertical height of less than about 10 μm are retained, so that such smaller gaps can be directly filled in the filling process such as step S140.

[0036] In the first thinning process such as step S130, by controlling the thinning degree so that the remaining wafer thickness after thinning (i.e., the middle thickness) is greater than or equal to a predetermined proportion of the radial dimension, that is, by making the radial dimension of the unbonded area less than or equal to a certain predetermined dimension, it can be ensured that edge collapse will not occur in the first thinning process.

[0037] In step S140 , the unbonded region is filled so that the radial dimension of the unfilled region in the unbonded region is reduced to below a critical dimension, which is a function of the target thickness.

[0038] In the example, the unbonded area can be filled by a vapor deposition process. In the example where the unbonded area is in the shape of a gap, the gap can be completely filled, or partially filled to a certain extent so that the radial dimension of the unfilled unfilled gap in the gap is reduced to below the critical dimension. For the case where the unbonded area is completely filled, the complete closure of the unbonded area is achieved through the filling process, so there is no unfilled unfilled area that is not filled, that is, the radial dimension of the unfilled unfilled area is reduced to 0. This situation can provide optimal structural stability during the thinning process to avoid edge collapse. For the case where the unbonded area is partially filled, as long as the radial dimension of the unfilled unfilled area (i.e., the remaining unbonded area) is reduced to below the critical dimension, the conditions for not causing edge collapse or at least minimizing edge collapse as described above can be met.

[0039] Therefore, according to an embodiment of the present disclosure, before performing the second thinning process as step S150, the unbonded area is first filled to control the radial size of the remaining unbonded area. Thus, the second thinning process is performed while ensuring that the remaining wafer thickness (i.e., target thickness) after thinning and the radial size of the remaining unbonded area meet the conditions of not causing edge collapse or at least minimizing the edge collapse, so that the edge collapse does not occur or at least minimizes the edge collapse during the second thinning process.

[0040] In step S150 , the device wafer is thinned from an intermediate thickness to a target thickness.

[0041] In an example, a device wafer can be thinned from an intermediate thickness to a target thickness by a fine thinning process. The thinning degree of the wafer can be precisely controlled by the fine thinning process. The fine thinning process can be performed by a mechanical grinding device.

[0042] Since the radial dimension of the remaining unbonded area is controlled below the critical dimension before the second thinning process, the edge collapse phenomenon is avoided during the second thinning process.

[0043] According to the embodiments of the present disclosure, the thinning process is performed while considering the relationship between the radial size of the unbonded area (or the unbonded area remaining after the filling process) and the thinning degree (i.e., the remaining wafer thickness after thinning), thereby satisfying the condition that the edge collapse phenomenon does not occur or at least minimizes the edge collapse phenomenon. Therefore, it does not cause contamination problems and equipment damage problems caused by the edge collapse phenomenon, and it can also ensure that the thinned device wafer can be processed normally in the subsequent processing process, thereby improving the product yield.

[0044] In addition, according to the embodiments of the present disclosure, by performing two thinning processes respectively while ensuring that edge collapse does not occur or at least minimizes the edge collapse, the thinning of the device wafer can be achieved quickly and accurately, thereby improving the efficiency and effect of the overall process flow.

[0045] Figures 2A to 2H A schematic diagram showing a semiconductor processing method according to an embodiment of the present disclosure is shown.

[0046] like Figures 2A to 2H As shown, the process flow of thinning the device wafer 210 from the initial thickness T0 = 725 μm to the target thickness T1 = 20 μm according to an embodiment of the present disclosure is described. Considering the symmetry of the structure, for the convenience of description, Figures 2A to 2H Take one side of the structure as an example.

[0047] According to some embodiments, Figure 2A As shown, the device wafer 210 may be bonded to a carrier wafer (eg, Figure 2B Before bonding the device wafer 210 to the carrier wafer 220, the surface 2101 of the device wafer 210 to be bonded is trimmed.

[0048] The edge trimming process can remove the rounded and / or sharp structures on the device wafer that are not conducive to bonding, thereby improving the bonding quality between the device wafer and the carrier wafer. Better bonding quality can help reduce the radial size of the unbonded area, thereby helping to avoid edge collapse during the thinning process.

[0049] In addition, the subsequent first thinning process and filling process can be assisted by a specific trimming process, which will be combined with Figures 2A to 2H The present embodiment shown and the following will be combined with Figures 3A to 3H Another embodiment shown is described in detail.

[0050] According to some embodiments, the trimming process may include removing a predetermined peripheral portion of the surface 2101 to be bonded so that the edge 2102 of the device wafer 210 has a stepped profile.

[0051] In the example, Figure 2A As shown, a grinding device such as a grinding wheel 202 may be used to grind the peripheral portion of the surface 2101 to be bonded to a predetermined trimming depth T trim , so that the edge 2102 has a stepped profile. That is, the step height of the stepped profile is equal to the trimming depth T trim For example, the trimming depth T trim The thickness may be 1 / 2 to 1 / 3 of the initial thickness T0 of the device wafer 210 , that is, approximately 362 μm to 242 μm.

[0052] The specific trimming process that forms the stepped profile can help to form a flat profile in the subsequent first thinning process, which in turn can help to perform the subsequent filling process.

[0053] like Figure 2B As shown, the device wafer 210 can be bonded to the carrier wafer 220. This step can correspond to bonding Figure 1 The step S110.

[0054] In an example, the device wafer 210 may be bonded to the carrier wafer 220 by a hybrid bonding process. Figure 2B The bonding method shown may be a wafer-to-wafer bonding method.

[0055] Figure 2B The figure also schematically shows an unbonded area 230 formed between the device wafer 210 and the carrier wafer 220. The unbonded area 230 extends from an edge 2150 of the bonding interface 215 between the device wafer 210 and the carrier wafer 220 along the radial direction of the device wafer 210 to an edge 2102 of the device wafer 210. Figure 2B As illustrated, the unbonded area 230 may be in the shape of a gap.

[0056] like Figure 2C As shown, the radial dimension L of the unbonded area 230 can be determined. This step can correspond to the bonding Figure 1 The step S120.

[0057] According to some embodiments, the radial dimension L may be measured by detecting a reflected wave at an interface between the device wafer 210 and the carrier wafer 220 using an ultrasonic scanning apparatus.

[0058] Figure 2C The ultrasonic probe 204 of the ultrasonic scanning device is schematically shown. The ultrasonic probe 204 is arranged along Figure 2C During the process, the ultrasonic probe 204 continuously emits a transmission wave 2040 to detect a reflection wave 2042 at the interface between the device wafer 210 and the carrier wafer 220 .

[0059] In an example, detection can be started from the edge 2102 of the device wafer 210 along the scanning direction. The ultrasonic probe 204 can receive a reflected wave 2042 when scanning through the unbonded area 230, and no reflected wave 2042 is received when exceeding the unbonded area 230. In this way, the radial dimension L of the unbonded area 230 can be measured by detection of the ultrasonic probe 204.

[0060] By using an ultrasonic scanning device, information about the radial dimension L can be quickly and easily obtained, thereby facilitating the implementation of the overall process flow.

[0061] like Figure 2D As shown, the device wafer 210 can be formed from an initial thickness T0 (eg Figure 2A as shown) is thinned to an intermediate thickness T inter . Middle thickness T inter The radial dimension L is greater than or equal to a predetermined ratio. This step may correspond to combining Figure 1 The step S130.

[0062] As mentioned above, when the radial dimension of the unbonded area is less than or equal to a certain predetermined dimension, the probability of edge collapse can be significantly reduced. The predetermined dimension is related to the remaining wafer thickness after thinning. Figure 2D In the first thinning process shown in FIG. 1 , the radial dimension L of the unbonded area 230 is used as a reference to control the remaining wafer thickness after thinning, that is, the intermediate thickness T inter , to meet the conditions of no edge collapse or at least minimize edge collapse.

[0063] According to some embodiments, the predetermined ratio may be greater than or equal to 1 / 20 and less than or equal to 1 / 5. inter It can be greater than or equal to 1 / 20 to 1 / 5 of the radial dimension L.

[0064] In other words, the radial dimension L of the unbonded region 230 may be smaller than the intermediate thickness T inter This ratio can facilitate the process implementation while most advantageously reducing the probability of edge collapse during the first thinning process.

[0065] According to some embodiments, a grinding process may be performed on the device wafer 210 to thin the device wafer 210 so that the stepped profile is thinned to have an intermediate thickness T inter Smooth contour.

[0066] In the example, in order to quickly thin the device wafer 210 from the initial thickness T0 to the intermediate thickness T inter To obtain a flat profile, a rough thinning process may be performed by, for example, a mechanical grinding device. In the rough thinning process, the grinding rate, pressure and / or feed speed of the mechanical grinding device may be appropriately selected to achieve rapid grinding.

[0067] By trimming the outer contour of the device wafer 210 to a flat contour, it is convenient to perform the processes of depositing and etching the dielectric film in the subsequent filling process.

[0068] like Figure 2E and 2FAs shown, the unbonded area 230 may be filled. This step may correspond to bonding Figure 1 The step S140.

[0069] According to some embodiments, filling the unbonded area 230 may include: forming a dielectric film 240 covering the device wafer 210 and the carrier wafer 220 using a vapor deposition process; and dry etching the dielectric film 240 to expose the device wafer 210 using the device wafer 210 as an etching mask.

[0070] According to some embodiments, the vapor deposition process may include a chemical vapor deposition process, a physical vapor deposition process, or a spray film forming process.

[0071] According to some embodiments, the vapor deposition process may be performed at an operating temperature equal to or less than 450° C. and an operating pressure of 0.1 to 10 Torr.

[0072] The vapor deposition process may help increase the diffusion characteristics of gas phase molecules or plasma, thereby facilitating the formation of a dielectric film with a thickness in the sub-micron to micron range, thereby facilitating the filling of the unbonded region 230 .

[0073] In the example, Figure 2E As shown, a silicon dioxide (SiO2) thin film 240 can be deposited using a chemical vapor deposition process to cover the device wafer 210 and the carrier wafer 220. In particular, the upper surface and side surfaces of the device wafer 210 can be covered, and the upper surface of the carrier wafer 220 can be covered, thereby increasing the possibility that the unbonded area 230 is fully filled.

[0074] The process of depositing the SiO 2 film 240 may be performed at a working temperature of 350° C. to 450° C. and a working pressure of 0.1 to 1.0 Torr.

[0075] In the example, Figure 2F As shown, the device wafer 210 may be used as a hard mask and a fluorine-based gas may be used to dry-etch the SiO 2 film 240 to expose the device wafer 210 .

[0076] Understandably, for ease of presentation, Figure 2E and 2FThe case where the unbonded area 230 is completely filled is shown, that is, the radial dimension of the unfilled unfilled area is reduced to 0. In the case where the unbonded area 230 is partially filled, the unbonded area 230 is not completely closed, so that there may still be unfilled unfilled areas near the edge of the bonding interface 215, that is, residual unbonded areas. However, according to the embodiments of the present disclosure, as long as the radial dimension of the residual unbonded area is below the critical dimension, it can be ensured that the edge collapse phenomenon does not occur or at least minimizes the edge collapse phenomenon in the subsequent second thinning process.

[0077] According to some embodiments, the critical dimension may be greater than or equal to the target thickness T1 (eg Figure 2H 5 times of the target thickness T1) and less than or equal to 20 times of the target thickness T1.

[0078] In other words, the critical dimension may be in the range of 5 to 20 times (100 to 400 μm) of the target thickness T1 (20 μm). This ratio can facilitate process implementation while most advantageously reducing the probability of edge collapse during the second thinning process.

[0079] like Figure 2G As shown, you can execute again as Figure 2C The step of determining the radial dimension is shown to check whether the radial dimension of the unfilled area after filling is less than or equal to the critical dimension.

[0080] According to some embodiments, after filling the unbonded area 230, it may be checked whether there is an unfilled unfilled area in the unbonded area 230. In response to checking the existence of the unfilled area, it may be determined whether the radial dimension of the unfilled area is less than or equal to the critical dimension. In response to determining that the radial dimension of the unfilled area is greater than the critical dimension, the thinning of the device wafer 210 may be abandoned.

[0081] Giving up thinning the device wafer 210 means that the radial size of the current unfilled area cannot meet the condition of not causing edge collapse or at least minimizing edge collapse. In an example, the device wafer 210 can be treated as a defective product.

[0082] By setting up additional inspection processes, device wafers that have been determined to be likely to experience edge collapse can be eliminated, thereby optimizing the overall process flow.

[0083] like Figure 2H As shown, for the device wafer 210 that has passed the above inspection, the device wafer 210 can be cut from the middle thickness T inter (like Figure 2D As shown) is thinned to the target thickness T1.

[0084] According to some embodiments, the thickness T inter(like Figure 2D The values ​​of the grinding parameters used in the thinning from the initial thickness T0 (as shown) to the target thickness T1 can be lower than those used in the thinning from the initial thickness T0 (as shown) to the target thickness T1. Figure 2A As shown) to the middle thickness T inter The grinding parameters may include at least one of a grinding rate, a pressure, and a feed rate.

[0085] In the example, from the initial thickness T0 to the intermediate thickness T inter During the first thinning process, a rough thinning process can be used, and in the process of reducing the thickness from the middle T inter During the second thinning process to the target thickness T1, a fine thinning process may be used. In an example, the grinding rate, pressure and feed speed used in the fine thinning process may be much smaller than those used in the rough thinning process.

[0086] In this way, the degree of thinning can be precisely controlled in the second thinning process.

[0087] Through Figures 2A to 2H According to the embodiment, the device wafer 210 can be thinned from an initial thickness T0 = 725 μm to a target thickness T1 = 20 μm, and edge collapse does not occur or at least is minimized during the thinning process.

[0088] Figures 3A to 3H A schematic diagram showing a semiconductor processing method according to another embodiment of the present disclosure is shown.

[0089] like Figures 3A to 3H As shown, a process flow of simultaneously thinning two device wafers 310 from an initial thickness T0 = 500 μm to a target thickness T1 = 50 μm according to an embodiment of the present disclosure is described. In this embodiment, the device wafer 310 may be a single bare die.

[0090] According to some embodiments, Figure 3A As shown, the device wafer 310 may be bonded to a carrier wafer (eg, Figure 3B Before bonding the device wafer 310 to the carrier wafer 320 as shown, the surface 3101 of the device wafer 310 to be bonded is trimmed.

[0091] The edge trimming process can remove rounded and / or sharp structures on the device wafer that are not conducive to bonding, thereby improving the bonding quality between the device wafer and the carrier wafer. Better bonding quality can help reduce the radial size of the unbonded area, thereby helping to avoid edge collapse during the thinning process.

[0092] In addition, the specific trimming process can also assist the subsequent first thinning process and filling process, which will be described in detail below.

[0093] According to some embodiments, the trimming process may include cutting the trench 3103 at a predetermined peripheral position on the surface 3101 of the device wafer 310 to be bonded so that the inner sidewall of the trench 3103 serves as the edge 3102 of the device wafer 310 .

[0094] In the example, Figure 3A As shown, a groove 3103 with a depth of, for example, about 200 μm can be cut at a peripheral position on the surface 3101 by, for example, laser cutting. The peripheral position can be close to the outer contour edge of the device wafer 310 .

[0095] The trimming process of forming the groove 3103 can help to perform the subsequent first thinning process. With the help of the groove 3103, a part of the device wafer 310 can be easily removed (such as falling off or falling off) in a thinning process such as using grinding, thereby quickly thinning the device wafer 310 to a certain extent. At the same time, a flat profile can also be formed with the help of the groove 3103, which in turn can help to perform the subsequent filling process.

[0096] like Figure 3B As shown, two device wafers 310 can be bonded to a carrier wafer 320. This step can correspond to bonding Figure 1 The step S110.

[0097] In an example, the two device wafers 310 may be bonded to the carrier wafer 320 by a direct bonding process or a hybrid bonding process. In the case where the device wafer 310 is a bare die, such as Figure 3B The bonding method shown may involve a die-to-wafer bonding method.

[0098] Figure 3B Schematically shows an unbonded region 330 formed between the device wafer 310 and the carrier wafer 320. The unbonded region 330 extends from an edge 3150 of the bonding interface 215 between the device wafer 310 and the carrier wafer 320 along the radial direction of the device wafer 310 to an edge 3102 of the device wafer 310. Figure 3B As illustrated, the unbonded area 330 may be in the shape of a gap.

[0099] It is understandable that due to structural symmetry, Figure 3B The bonding structure of the device wafer 310 and the carrier wafer 320 shown may include four unbonded areas 330 .

[0100] like Figure 3C As shown, the radial dimension L of the unbonded area 330 can be determined. This step can correspond to the bonding Figure 1 The step S120.

[0101] According to some embodiments, the radial dimension L of the unbonded area 330 may be measured by photographing infrared light waves transmitted through the unbonded area 330 using the infrared imaging device 302 .

[0102] Figure 3C The infrared imaging device 302 and the infrared light source 304 are schematically shown. The infrared light source 304 can be disposed on one side of the carrier wafer 320 to emit infrared light waves (e.g., short-wave infrared light waves) toward the carrier wafer 320 and the device wafer 310. The infrared imaging device 202 can be disposed on one side of the device wafer 310 to receive the infrared light waves from the infrared light source 304. The infrared light waves can be transmitted through the unbonded area 330 to be photographed by the infrared imaging device 302. In this way, the radial dimension L of the unbonded area 330 can be measured.

[0103] By using an infrared imaging device, information about the radial dimension L can be quickly and easily obtained, thereby facilitating the implementation of the overall process.

[0104] like Figure 3D As shown, the device wafer 310 can be formed from an initial thickness T0 (eg Figure 3A as shown) is thinned to an intermediate thickness T inter . Middle thickness T inter The radial dimension L is greater than or equal to a predetermined ratio. This step may correspond to combining Figure 1 The step S130.

[0105] As mentioned above, when the radial dimension of the unbonded area is less than or equal to a certain predetermined dimension, the probability of edge collapse can be significantly reduced. The predetermined dimension is related to the remaining wafer thickness after thinning. Figure 3D In the first thinning process shown in FIG. 1 , the radial dimension L of the unbonded area 330 is used as a reference to control the remaining wafer thickness after thinning, that is, the intermediate thickness T inter , to meet the conditions of no edge collapse or at least minimize edge collapse.

[0106] According to some embodiments, the predetermined ratio may be greater than or equal to 1 / 20 and less than or equal to 1 / 5. inter It can be greater than or equal to 1 / 20 to 1 / 5 of the radial dimension L.

[0107] In other words, the radial dimension L of the unbonded region 330 may be smaller than the intermediate thickness T inter This ratio can facilitate the process implementation while most advantageously reducing the probability of edge collapse during the first thinning process.

[0108] According to some embodiments, a grinding process may be performed on the device wafer 310 to thin the device wafer 310 so that an edge 3102 of the device wafer 310 is exposed and has an intermediate thickness T inter .

[0109] By means of groove 3103 (such as Figure 3A and 3B As shown in FIG. 3 , the groove 3103 can be used as a reference to quickly remove a portion of the device wafer 310 during the grinding process. For example, the groove 3103 can be ground below the groove depth so that the upper portion and the side portion of the device wafer 310 can be easily removed. At the same time, since the inner wall of the groove 3103 serves as the edge 3102 of the device wafer 310, a flat profile can also be formed. The flat profile can facilitate the process of depositing and etching the dielectric film in the subsequent filling process.

[0110] In an example, the rough thinning process may be performed by, for example, a mechanical grinding device. In the rough thinning process, the grinding rate, pressure, and / or feed speed of the mechanical grinding device may be appropriately selected to achieve rapid grinding.

[0111] like Figure 3E and 3F As shown, the unbonded area 330 may be filled. This step may correspond to bonding Figure 1 The step S140.

[0112] According to some embodiments, filling the unbonded region 230 may include: forming a dielectric film 340 covering the device wafer 310 and the carrier wafer 320 using a vapor deposition process; and dry etching the dielectric film 340 using the device wafer 310 as an etching mask to expose the device wafer 310 .

[0113] According to some embodiments, the vapor deposition process may include a chemical vapor deposition process, a physical vapor deposition process, or a spray film forming process.

[0114] According to some embodiments, the vapor deposition process may be performed at an operating temperature equal to or less than 450° C. and an operating pressure of 0.1 to 10 Torr.

[0115] The above-mentioned vapor deposition process can help to increase the diffusion characteristics of gas-phase molecules or plasma, thereby promoting the formation of a dielectric film with a thickness in the sub-micron to micron range, thereby facilitating the filling of the unbonded region 330 .

[0116] In the example, Figure 3EAs shown, a plasma enhanced chemical vapor deposition (PECVD) process can be used to deposit a TEOS silicon oxide film 340 to cover the device wafer 310 and the carrier wafer 320. In particular, the upper surface and side surfaces of the device wafer 310 can be covered, and the upper surface of the carrier wafer 320 can be covered, thereby increasing the possibility that the unbonded area 330 is fully filled.

[0117] The process of depositing the TEOS silicon oxide film 340 may be performed at a working temperature of 150° C. to 450° C. and a working pressure of 0.1 to 10 Torr.

[0118] In the example, Figure 3F As shown, the device wafer 310 may be used as a hard mask and a fluorine-based gas may be used to dry-etch the TEOS silicon oxide film 340 to expose the device wafer 310 .

[0119] Understandably, for ease of presentation, Figure 3E and 3F The case where the unbonded area 330 is completely filled is shown, that is, the radial dimension of the unfilled unfilled area is reduced to 0. In the case where the unbonded area 330 is partially filled, the unbonded area 330 is not completely closed, so that there may still be unfilled unfilled areas near the edge of the bonding interface 315, that is, residual unbonded areas. However, according to the embodiments of the present disclosure, as long as the radial dimension of the residual unbonded area is below the critical dimension, it can be ensured that the edge collapse phenomenon does not occur or at least minimizes the edge collapse phenomenon in the subsequent second thinning process.

[0120] According to some embodiments, the critical dimension may be greater than or equal to the target thickness T1 (eg Figure 3H 5 times of the target thickness T1) and less than or equal to 20 times of the target thickness T1.

[0121] In other words, the critical dimension may be in the range of 5 to 20 times (250 to 1000 μm) the target thickness T1 (50 μm). This ratio can facilitate process implementation while most advantageously reducing the probability of edge collapse during the second thinning process.

[0122] like Figure 3G As shown, you can execute again as Figure 3C The step of determining the radial dimension is shown to check whether the radial dimension of the unfilled area after filling is less than or equal to the critical dimension.

[0123] According to some embodiments, after filling the unbonded area 330, it may be checked whether there is an unfilled unfilled area in the unbonded area 330. In response to checking the existence of the unfilled area, it may be determined whether the radial dimension of the unfilled area is less than or equal to the critical dimension. In response to determining that the radial dimension of the unfilled area is greater than the critical dimension, the thinning of the device wafer 310 may be abandoned.

[0124] Giving up thinning the device wafer 310 means that the radial size of the current unfilled area cannot meet the condition of not causing edge collapse or at least minimizing edge collapse. In an example, the device wafer 310 can be treated as a defective product.

[0125] By setting up additional inspection processes, device wafers that have been determined to be likely to experience edge collapse can be eliminated, thereby optimizing the overall process flow.

[0126] like Figure 3H As shown, for the device wafer 310 that has passed the above inspection, the device wafer 310 can be cut from the middle thickness T inter (like Figure 3D As shown) is thinned to the target thickness T1.

[0127] According to some embodiments, the thickness T inter (like Figure 3D The values ​​of the grinding parameters used in the thinning from the initial thickness T0 (as shown) to the target thickness T1 can be lower than those used in the thinning from the initial thickness T0 (as shown) to the target thickness T1. Figure 3A As shown) to the middle thickness T inter The grinding parameters may include at least one of a grinding rate, a pressure, and a feed rate.

[0128] In the example, from the initial thickness T0 to the intermediate thickness T inter During the first thinning process, a rough thinning process can be used, and in the process of reducing the thickness from the middle T inter During the second thinning process to the target thickness T1, a fine thinning process may be used. In an example, the grinding rate, pressure and feed speed used in the fine thinning process may be much smaller than those used in the rough thinning process.

[0129] In this way, the degree of thinning can be precisely controlled in the second thinning process.

[0130] Through Figures 3A to 3H According to the embodiment, two device wafers 310 can be thinned from an initial thickness T0 = 500 μm to a target thickness T1 = 50 μm at the same time, and edge collapse does not occur or at least is minimized during the thinning process.

[0131] According to another aspect of the embodiments of the present disclosure, a method for manufacturing a chip is also provided, wherein the method includes providing a wafer for manufacturing a chip, wherein the wafer is thinned according to the method described above.

[0132] According to the embodiments of the present disclosure, the wafer can be thinned from the millimeter level to the micrometer level, and the edge collapse phenomenon does not occur or at least is minimized during the thinning process. As a result, the chip manufacturing method can also be improved accordingly.

[0133] According to another aspect of an embodiment of the present disclosure, a chip is further provided. The chip is manufactured according to the method described above.

[0134] The above description is only an illustration of the illustrative embodiments and application technical principles of the present disclosure. Those skilled in the art should understand that the scope of the present disclosure to which the embodiments of the present disclosure relate is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, and should also cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the above-mentioned inventive concept. For example, the technical solutions formed by replacing the above-mentioned features with technical features (but not limited to) having similar functions to the technical features disclosed in the embodiments of the present disclosure also fall within the scope of protection of the present disclosure.

[0135] Although the present disclosure has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description should be considered illustrative and schematic, not restrictive; the present disclosure is not limited to the disclosed embodiments. By studying the drawings, the disclosure and the appended claims, those skilled in the art will be able to understand and implement variations to the disclosed embodiments when practicing the claimed subject matter. In the claims, the word "comprising" does not exclude other elements or steps that are not listed, the indefinite article "a" or "an" does not exclude a plurality, the term "plurality" means two or more, and the term "based on" should be interpreted as "based at least in part on". The mere fact that certain measures are recorded in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A semiconductor process method, comprising: Bonding a device wafer to a carrier wafer, wherein the device wafer is thinned from an initial thickness to a target thickness; Determine a radial dimension of an unbonded area formed between the device wafer and the carrier wafer, wherein the unbonded area extends from an edge of a bonding interface between the device wafer and the carrier wafer along a radial direction of the device wafer by the radial dimension to an edge of the device wafer; Thinning the device wafer from the initial thickness to an intermediate thickness, wherein the thinning is performed in consideration of the following relationship between the radial dimension of the unbonded area and the intermediate thickness of the device wafer: the intermediate thickness is greater than or equal to a predetermined ratio of the radial dimension, the predetermined ratio being greater than or equal to 1 / 20 and less than or equal to 1 / 5; Filling the unbonded area so that a radial dimension of an unfilled area in the unbonded area has the following relationship with the target thickness of the device wafer: the radial dimension is reduced to below a critical dimension, the critical dimension being greater than or equal to 5 times the target thickness and less than or equal to 20 times the target thickness; and The device wafer is thinned from the intermediate thickness to the target thickness, such that the thinning is performed in consideration of the relationship between a radial dimension of an unfilled region that is not filled in the unbonded region and the target thickness of the device wafer.

2. The method according to claim 1, further comprising: Before bonding the device wafer to the carrier wafer, the surface of the device wafer to be bonded is trimmed.

3. The method according to claim 2, wherein: The trimming process includes removing a predetermined peripheral portion of the surface so that the edge has a stepped profile.

4. The method according to claim 3, wherein: Thinning the device wafer from the initial thickness to an intermediate thickness comprises: A grinding process is performed on the device wafer to thin the device wafer so that the stepped profile is thinned to a flat profile having the intermediate thickness.

5. The method according to claim 2, wherein: The trimming process includes cutting a groove at a predetermined peripheral position on the surface so that the inner sidewall of the groove serves as the edge of the wafer.

6. The method according to claim 5, wherein: Thinning the device wafer from the initial thickness to an intermediate thickness comprises: A grinding process is performed on the device wafer to thin the device wafer so that the edge is exposed and has the intermediate thickness.

7. The method according to any one of claims 1 to 6, wherein: Determining the radial dimension of the unbonded area formed between the device wafer and the carrier wafer includes: The radial dimension is measured by detecting a reflected wave at an interface between the device wafer and the carrier wafer using an ultrasonic scanning device.

8. The method according to any one of claims 1 to 6, wherein: Determining the radial dimension of the unbonded area formed between the device wafer and the carrier wafer includes: The radial dimension is measured by photographing infrared light waves transmitted through the unbonded area using an infrared imaging device.

9. The method according to any one of claims 1 to 6, wherein: Filling the unbonded area includes: Using a vapor deposition process to form a dielectric film covering the device wafer and the carrier wafer; and The device wafer is used as an etching mask to dry-etch the dielectric film to expose the device wafer.

10. The method according to claim 9, wherein: The vapor deposition process includes a chemical vapor deposition process, a physical vapor deposition process or a spray film forming process.

11. The method according to claim 9, wherein: The vapor deposition process is performed at a working temperature equal to or less than 450° C. and a working pressure of 0.1 to 10 Torr.

12. The method according to any one of claims 1 to 6, further comprising: After filling the unbonded area, checking whether there is an unfilled area in the unbonded area that has not been filled; In response to detecting the presence of the unfilled region, determining whether a radial dimension of the unfilled region is less than or equal to the critical dimension; and In response to determining that the radial dimension of the unfilled region is greater than the critical dimension, thinning of the device wafer is foregone.

13. The method according to any one of claims 1 to 6, wherein: The values ​​of grinding parameters used in thinning from the intermediate thickness to the target thickness are lower than the values ​​of grinding parameters used in thinning from the initial thickness to the intermediate thickness, and the grinding parameters include at least one of grinding rate, pressure and feed speed.

14. A method for manufacturing a chip, comprising providing a wafer for manufacturing the chip, wherein: The wafer is thinned according to the method of any one of claims 1-13.

15. A chip, wherein: The chip is manufactured according to the method of claim 14.

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