Chip packaging process and chip

Abstract

An embodiment of the present application provides a chip packaging process and a chip, in which a first metal layer is set on the second surface of a bare core, and the drain electrode of the first surface of the bare core is led to the second surface of the bare core through the metal in the first hole and the second hole, so that the conductive protective layer on the second surface of the bare core can be welded to the PCB board, so that the distance between the source electrode of the chip and the PCB board is relatively close, resulting in good heat dissipation of the chip, and the first surface of the bare core is protected by the second metal layer being plastic-sealed by the third plastic sealing layer.

Description

Technical Field

[0001] The embodiments of the present application belong to the field of semiconductors, and specifically relate to a chip packaging process and a chip. Background Art

[0002] The existing chip preparation process is to connect the chip drain to the heat sink, which has poor heat dissipation performance, poor internal resistance, and small PCB space, resulting in the inability to improve power density and product performance.

[0003] Therefore, a new method is needed to solve the above problems. Summary of the Invention

[0004] The embodiments of the present application aim to overcome the above-mentioned problems or at least partially solve or alleviate the above-mentioned problems. The chip prepared by the chip packaging process provided in the present application has good heat dissipation performance.

[0005] In a first aspect, an embodiment of the present application provides a chip packaging process, comprising the following steps:

[0006] Step 1: fix the first surface of the bare core to the first support member through a first connector, and the second surface of the bare core is provided with an electrode lead layer;

[0007] Step 2: performing a first plastic sealing on the second surface of the bare die to form a first plastic sealing layer, wherein the first plastic sealing layer covers the electrode lead-out layer on the second surface of the bare die;

[0008] Step 3: thinning the first plastic sealing layer until the electrode lead layer leaks out;

[0009] Step 4: drilling a first hole in the first plastic packaging layer from the second surface toward the first surface, and filling the first hole with metal;

[0010] Step 5: Disposing first metal layers at intervals at positions corresponding to the first holes of the first plastic packaging layer and positions corresponding to the electrode lead-out layer;

[0011] Step 6: performing a second plastic sealing on the second surface of the bare die to form a second plastic sealing layer, wherein the second plastic sealing layer covers the first metal layer;

[0012] Step seven, thinning the second plastic sealing layer until the first metal layer leaks out;

[0013] Step eight, placing the surface of the first metal layer away from the electrode lead layer on the second support member through the second connector, and removing the first connector and the first support member on the first surface of the bare core;

[0014] Step nine, drilling a second hole in the first plastic packaging layer from the first surface toward the second surface at a position corresponding to the first hole until the second hole is connected to the first hole, and filling the second hole with metal;

[0015] Step 10, disposing a second metal layer at a position corresponding to the second hole and on the first surface of the bare core respectively;

[0016] Step 11: performing a third plastic sealing on the first surface of the bare die to form a third plastic sealing layer, wherein the third plastic sealing layer covers the second metal layer;

[0017] Step 12: remove the second support member and provide a conductive protective layer on the upper surface of the first metal layer.

[0018] Compared with the prior art, the embodiment of the present application provides a chip packaging process, in which the second surface conductive protective layer of the bare core is welded to the PCB board, so that the distance between the source of the chip and the PCB board is relatively close, and the chip has better heat dissipation.

[0019] In a second aspect, an embodiment of the present application provides a chip packaging process, comprising the following steps:

[0020] Step 1: fix the first surface of the bare core to the first support member through a first connector, and the second surface of the bare core is provided with an electrode lead layer;

[0021] Step 2: performing a first plastic sealing on the second surface of the bare die to form a first plastic sealing layer, wherein the first plastic sealing layer covers the electrode lead-out layer on the second surface of the bare die;

[0022] Step 3: thinning the first plastic sealing layer until the electrode lead layer leaks out;

[0023] Step 4: drilling a first hole in the first plastic packaging layer from the second surface toward the first surface, and filling the first hole with metal;

[0024] Step 5: Disposing first metal layers at intervals at positions corresponding to the first holes of the first plastic packaging layer and positions corresponding to the electrode lead-out layer;

[0025] Step 6: performing a second plastic sealing on the second surface of the bare die to form a second plastic sealing layer, wherein the second plastic sealing layer covers the first metal layer;

[0026] Step seven, removing the first connector and the first support member on the first surface of the bare core, and placing the surface of the first metal layer away from the electrode lead layer on the second support member through the second connector;

[0027] Step eight, drilling a second hole in the first plastic packaging layer from the first surface toward the second surface at a position corresponding to the first hole until the second hole is connected to the first hole, and filling the second hole with metal;

[0028] Step nine, providing a second metal layer at a position corresponding to the second hole on the first surface of the bare die and on the first surface of the bare die respectively;

[0029] Step 10, performing a third plastic sealing on the first surface of the bare die to form a third plastic sealing layer, wherein the third plastic sealing layer covers the second metal layer;

[0030] Step 11: remove the second support member on the surface of the first metal layer away from the electrode lead-out layer, and place the surface of the second metal layer away from the first surface of the bare core on the third support member through a third connecting member;

[0031] Step 12: thinning the second plastic sealing layer until the first metal layer leaks out;

[0032] Step thirteen: providing a protective layer on the upper surface of the first metal layer, and then removing the third support member.

[0033] In a third aspect, an embodiment of the present application provides a chip prepared by the chip packaging process described in the first and second aspects.

[0034] Compared with the prior art, the beneficial effects of the embodiments provided in the second, third and fourth aspects of the present application are the same as the beneficial effects of any of the above technical solutions, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application. Hereinafter, some specific embodiments of the present application will be described in detail in an illustrative and non-restrictive manner with reference to the drawings. The same reference numerals in the drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the drawings:

[0036] Figure 1 A packaging process flow chart provided for a specific embodiment of the present application;

[0037] Figure 2-13 A schematic diagram of each step in the process flow provided in the embodiment of the present application;

[0038] Figure 14 A packaging process flow chart provided for another specific embodiment of the present application;

[0039] Figures 15-21 A structural schematic diagram of some steps in the process flow provided in another embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0041] Example 1

[0042] like Figure 1 As shown, the embodiment of the present application provides a chip packaging process, which specifically includes the following steps:

[0043] Step 1 S01: fix the first surface of the bare die 203 on a substrate 201 via a connector 202, and provide a plurality of electrode lead-out layers 204 spaced apart on the second surface of the bare die 203;

[0044] refer to Figure 1 and Figure 2 , the cut bare core 203 is fixed on the first support member 201, and the first support member 201 plays a supporting role. In order to achieve the fixation of the bare core 203 and the first support member 201, a connector 202 is provided between the bare core 203 and the first support member 201. The connector 202 can be a fixing glue or other materials. As long as the bare core 203 can be fixed to the substrate 201, it falls within the scope of protection of the embodiment of the present application. However, the connector 202 needs to have high temperature resistance. The electrode lead layer 204 is realized by a ball planting process or a wire bonding process, and the gold electrode lead layer 204 is connected to the PAD on the second surface of the bare core 203.

[0045] Step 2 S02, performing a first plastic sealing on the second surface of the bare core 203 to form a first plastic sealing layer 205, wherein the first plastic sealing layer 105 covers the electrode lead-out layer 204 on the second surface of the bare core 203;

[0046] refer to Figure 1 and Figure 3 In order to protect the second surface of the bare core 203 , the second surface of the bare core 203 is plastic-sealed, and the formed first plastic-sealing layer 205 needs to cover the electrode lead-out layer 204 .

[0047] Step three S03, thinning the first plastic packaging layer 205 until the electrode lead layer 204 leaks out;

[0048] refer to Figure 1 and Figure 4 The first plastic packaging layer 205 is thinned until the multi-electrode lead layer 204 leaks out.

[0049] Step 4 S04: drilling a first hole 206 in the first plastic packaging layer 205 from the second surface toward the first surface, and filling the first hole 206 with metal;

[0050] refer to Figure 1 and Figure 5 The first hole 206 is formed by laser drilling or mechanical drilling at a specific position of the first plastic layer 205. The drilling can be performed in multiple times. The metal in the first hole 203 is copper, and the metal in the first hole 206 is filled by electroplating.

[0051] Step five S05 , disposing a first metal layer 207 at positions corresponding to the first holes 206 on the second surface of the bare core 203 and at positions corresponding to the plurality of electrode lead-out layers 204 ;

[0052] refer to Figure 1 and Figure 6 , by setting a first metal layer 207 at a position corresponding to the first hole 206 and the electrode lead layer 204 on the second surface of the bare core 203, so as to form an electrical connection with the electrode lead layer 204 and the metal in the first hole 206.

[0053] Step six S06, performing a second plastic sealing on the second surface of the bare die 203 to form a second plastic sealing layer 208, wherein the second plastic sealing layer 208 covers the first metal layer 207;

[0054] refer to Figure 1 and Figure 7 The first metal layer 207 can be protected by the second plastic packaging layer 208 .

[0055] Step seven, thinning the second plastic layer 208 until the first metal layer 207 leaks out;

[0056] refer to Figure 1 and Figure 8 The second plastic layer 208 is thinned so that the first metal layer 207 can solder the second surface of the bare core 203 to the PCB board.

[0057] Step eight, pass the surface of the first metal layer 207 away from the electrode lead layer through the second connector 210 and the second support 209, and remove the first connector 202 and the first support 202 on the first surface of the bare core 203;

[0058] refer to Figure 1 and Figure 9 By providing the second support member 209 on the second surface of the bare core 203 , it can play a supporting role for all the bare cores 203 after the first support member 202 is removed.

[0059] Step nine: drilling a second hole 211 in the first plastic layer 205 from the first surface toward the second surface at a position corresponding to the first hole 206 until the second hole 211 is connected to the first hole 206 , and filling the second hole 211 with metal;

[0060] refer to Figure 1 and Figure 10 A second hole 211 is formed by laser drilling or mechanical drilling at a specific position of the first plastic layer 205 on the first surface of the bare core 203. The drilling can be performed in multiple times. The metal in the second hole 211 is copper. The metal in the second hole 211 is filled by electroplating, and the second hole 211 is connected to the first hole 206.

[0061] Step ten, disposing a second metal layer 212 at a position corresponding to the second hole 211 and on the first surface of the bare core 203;

[0062] refer to Figure 1 and Figure 11 By providing the second metal layer 212 , the electrode on the first surface of the bare core 203 can be led out to the first surface of the bare core 203 through the metal in the first hole 206 and the second hole 211 .

[0063] Step 11: performing a third plastic sealing on the first surface of the bare die 203 to form a third plastic sealing layer 213 , wherein the third plastic sealing layer 213 covers the second metal layer 212 ;

[0064] refer to Figure 1 and Figure 12 The third plastic packaging layer 213 covers the second metal layer 212 to protect the metal from being oxidized. In the embodiment of the present application, the second metal layer 212 is copper.

[0065] Step 12: remove the second support member 209 and provide a protection layer 214 on the upper surface of the first metal layer 207 .

[0066] refer to Figure 1 and Figure 13 The protective layer 214 can protect the first metal layer 207 from being oxidized so that the second surface of the bare core 203 can be soldered to the PCB through the first metal layer 207. The protective layer 214 is made of metal tin.

[0067] In an embodiment of the present application, after completing the first plastic sealing layer 205, the second plastic sealing layer 208 and the third plastic sealing layer 213, the first plastic sealing layer 205, the second plastic sealing layer 208 and the third plastic sealing layer 213 are subjected to a high-temperature curing treatment so as to cure the plastic sealing layer into shape.

[0068] An embodiment of the present application provides a chip packaging process, in which a first metal layer is set on the second surface of the bare core, and the drain of the first surface of the bare core is led to the second surface of the bare core through the metal in the first hole and the second hole, so that the conductive protective layer on the second surface of the bare core can be welded to the PCB board, resulting in a relatively close distance between the source of the chip and the PCB board, resulting in good heat dissipation of the chip, and the first surface of the bare core is protected by the second metal layer being plastic-sealed by the third plastic layer.

[0069] Example 2

[0070] like Figure 15 As shown, the differences from Example 1 are steps 7 to 12, and the same parts are not repeated here.

[0071] The specific steps after step 7 of Example 1 are as follows:

[0072] Step 7: Remove the first connector 202 and the first support 201 on the first surface of the bare core 203; and place the surface of the second plastic encapsulation layer 208 away from the electrode lead layer 207 on the second support 209 through the second connector 210;

[0073] refer to Figure 15 and Figure 16 Through step seven, after removing the first connecting member 202 and the first supporting member 201, the first surface of the bare core 203 can be easily processed.

[0074] Step eight: drill a second hole 211 in the first plastic layer 205 from the first surface to the second surface at a position corresponding to the first hole 206 until the second hole 211 is connected to the first hole 206 , and fill the second hole 211 with metal.

[0075] refer to Figure 15 and Figure 16 A second hole 211 is formed by laser drilling or mechanical drilling at a specific position of the first plastic layer 205 on the first surface of the bare core 203. The drilling can be performed in multiple times. The metal in the second hole 211 is copper. The metal in the second hole 211 is filled by electroplating, and the second hole 211 is connected to the first hole 206.

[0076] Step nine, disposing a second metal layer 212 at a position corresponding to the second hole 211 on the first surface of the bare core 203 and on the first surface of the bare core 203;

[0077] refer to Figure 15 and Figure 17 By providing the second metal layer 212 , the electrode on the first surface of the bare core 203 can be led out to the first surface of the bare core 203 through the metal in the first hole 206 and the second hole 211 .

[0078] Step ten, performing a third plastic sealing on the first surface of the bare die 203 to form a third plastic sealing layer 213 , wherein the third plastic sealing layer 213 covers the second metal layer 212 ;

[0079] refer to Figure 15 and Figure 18 The second metal layer 212 is covered by the second plastic packaging layer 213 to protect the metal from being oxidized. In the embodiment of the present application, the second metal layer 212 is copper.

[0080] Step 11: remove the second support member 209 on the surface of the second plastic encapsulation layer 208 away from the electrode lead layer 207, and place the surface of the second metal layer 212 away from the first surface of the bare core on the third support member 215 through the third connector 214;

[0081] refer to Figure 15 and Figure 19 By setting a second support member 209 on the first surface of the bare core 203, after the second support member 209 is removed, it can support all the bare cores 203, so that the second plastic packaging layer 208 on the second surface of the bare core 203 can be thinned.

[0082] Step 12: thinning the second plastic layer 208 until the first metal layer 207 leaks out;

[0083] refer to Figure 15 and Figure 20 , the second plastic layer 208 is thinned so that the first metal layer 207 can be welded to the second surface of the bare core 203 on the PCB board

[0084] In step thirteen, a protective layer 216 is provided on the upper surface of the first metal layer 207 , and then the third support member 215 is removed.

[0085] refer to Figure 15 and Figure 21 The protective layer 214 can protect the first metal layer 207 from being oxidized so that the second surface of the bare core 203 can be soldered to the PCB through the first metal layer 207. The protective layer 214 is made of metal tin.

[0086] Compared with the prior art, the embodiment of the present application provides a chip packaging process, in which a first metal layer is set on the second surface of the bare core, and the drain of the first surface of the bare core is led to the second surface of the bare core through the metal in the first hole and the second hole, so that the conductive protective layer on the second surface of the bare core can be welded to the PCB board, resulting in a relatively close distance between the source of the chip and the PCB board, resulting in good heat dissipation of the chip, and the first surface of the bare core is protected by the second metal layer being plastic-sealed by the third plastic sealing layer.

[0087] In a second aspect, an embodiment of the present application provides a chip structure, which is prepared by the chip packaging process described in the first aspect.

[0088] In a third aspect, an embodiment of the present application provides a device comprising a PCB board and the chip described in the second aspect, wherein the device is obtained by welding the first metal layer of the chip structure described in the second aspect to the PCB board.

[0089] Compared with the prior art, the beneficial effects of the embodiments provided in the second and third aspects of the present application are the same as the beneficial effects of any of the above technical solutions, and will not be repeated here.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A chip packaging process, characterized in that: The following steps are involved: Step 1: fix the first surface of the bare core to the first support member through a first connector, and the second surface of the bare core is provided with an electrode lead layer; Step 2: performing a first plastic sealing on the second surface of the bare die to form a first plastic sealing layer, wherein the first plastic sealing layer covers the electrode lead-out layer on the second surface of the bare die; Step 3: thinning the first plastic sealing layer until the electrode lead layer leaks out; Step 4: drilling a first hole in the first plastic packaging layer from the second surface toward the first surface, and filling the first hole with metal; Step 5: Disposing first metal layers at intervals at positions corresponding to the first holes of the first plastic packaging layer and positions corresponding to the electrode lead-out layer; Step 6: performing a second plastic sealing on the second surface of the bare die to form a second plastic sealing layer, wherein the second plastic sealing layer covers the first metal layer; Step seven, thinning the second plastic sealing layer until the first metal layer leaks out; Step eight, placing the surface of the first metal layer away from the electrode lead layer on the second support member through the second connector, and removing the first connector and the first support member on the first surface of the bare core; Step nine, drilling a second hole in the first plastic packaging layer from the first surface toward the second surface at a position corresponding to the first hole until the second hole is connected to the first hole, and filling the second hole with metal; Step 10, disposing a second metal layer at a position corresponding to the second hole and on the first surface of the bare core respectively; Step 11: performing a third plastic sealing on the first surface of the bare die to form a third plastic sealing layer, wherein the third plastic sealing layer covers the second metal layer; Step 12: remove the second support member and provide a protective layer on the upper surface of the first metal layer; After the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer are completed, the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer are subjected to high temperature curing.

2. A chip packaging process according to claim 1, characterized in that: In step 1, the electrode lead layer is formed by ball planting or wire bonding.

3. The chip packaging manufacturing process according to claim 1, wherein: The first hole and the second hole are formed by laser or mechanical drilling, respectively.

4. A chip packaging process, characterized in that: The following steps are involved: Step 1: fix the first surface of the bare core to the first support member through a first connector, and the second surface of the bare core is provided with an electrode lead layer; Step 2: performing a first plastic sealing on the second surface of the bare die to form a first plastic sealing layer, wherein the first plastic sealing layer covers the electrode lead-out layer on the second surface of the bare die; Step 3: thinning the first plastic sealing layer until the electrode lead layer leaks out; Step 4: drilling a first hole in the first plastic packaging layer from the second surface toward the first surface, and filling the first hole with metal; Step 5: Disposing first metal layers at intervals at positions corresponding to the first holes of the first plastic packaging layer and positions corresponding to the electrode lead-out layer; Step 6: performing a second plastic sealing on the second surface of the bare die to form a second plastic sealing layer, wherein the second plastic sealing layer covers the first metal layer; Step seven, removing the first connector and the first support member on the first surface of the bare core, and placing the surface of the second plastic encapsulation layer away from the electrode lead layer on the second support member through the second connector; Step eight, drilling a second hole in the first plastic packaging layer from the first surface toward the second surface at a position corresponding to the first hole until the second hole is connected to the first hole, and filling the second hole with metal; Step nine, providing a second metal layer at a position corresponding to the second hole on the first surface of the bare die and on the first surface of the bare die respectively; Step 10, performing a third plastic sealing on the first surface of the bare die to form a third plastic sealing layer, wherein the third plastic sealing layer covers the second metal layer; Step 11: remove the second support member on the surface of the first metal layer away from the electrode lead-out layer, and place the surface of the second metal layer away from the first surface of the bare core on the third support member through a third connecting member; Step 12: thinning the second plastic sealing layer until the first metal layer leaks out; Step 13: providing a protective layer on the upper surface of the first metal layer, and then removing the third support member; After the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer are completed, the first plastic sealing layer, the second plastic sealing layer and the third plastic sealing layer are subjected to high temperature curing.

5. A chip packaging process according to claim 4, characterized in that: In step 1, the electrode lead layer is formed by ball planting or wire bonding.

6. The chip packaging manufacturing process according to claim 4, characterized in that: The first hole and the second hole are formed by laser or mechanical drilling respectively.

7. A chip, characterized in that: Prepared by the chip packaging process according to any one of claims 1 to 6.

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