Clock signal generator, on-chip clock system and chip

Abstract

A clock signal generator (100), an on-chip clock system, and a chip. Among them, the clock signal generator (100) includes: a first transistor (T1), a second transistor (T2), a flip-flop, and a power supply terminal; a first pole of the first transistor (T1) and the second transistor (T2) is coupled to the power supply terminal, and a second pole of the first transistor (T1) and the second transistor (T2) is coupled to the common ground (Gnd); a first input terminal of the flip-flop is coupled to the first pole of the first transistor (T1), and a second input terminal of the flip-flop is coupled to the first pole of the second transistor (T2). This clock signal generator (100) can make the frequency of the output clock signal more stable.

Description

Technical Field

[0001] The embodiments of the present application relate to electronic circuit technologies, and in particular, to a clock signal generator, an on-chip clock system, and a chip. Background Art

[0002] With the development of electronic technologies such as artificial intelligence technology, communication technology, and semiconductor technology, the functions of on-chip systems are becoming increasingly complex. To ensure the high reliability and high operating speed of on-chip systems, a clock signal generator is usually required to be provided inside the on-chip system to provide accurate and stable clock signals for the on-chip system.

[0003] In related technologies, a clock signal generator usually includes a trigger and a comparator. By providing the signal output from the output terminal of the comparator to the input terminal of the trigger, the trigger can generate a clock pulse at the output terminal based on the signal received at the input terminal. Generally, there is a time delay between the input terminal and the output terminal of the comparator, and this time delay usually varies based on the circuit's static operating point, temperature drift, etc. This results in a change in the clock frequency output by the clock output circuit, reducing the stability of the clock signal frequency output by the clock signal generator. Thus, how to make the clock signal generator output a clock signal with a stable frequency becomes a problem. Summary of the Invention

[0004] For the clock signal generator, on-chip clock system, and chip provided in the present application, by coupling the input terminals of the trigger to the first poles of the first transistor and the second transistor respectively, the output frequency of the clock signal generator can be made to be only related to the on-off times of the first transistor and the second transistor, so that the clock signal generator can generate a clock signal with a stable frequency.

[0005] The present application adopts the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a clock signal generator, which includes a first transistor, a second transistor, a trigger, and a power supply terminal; the first poles of the first transistor and the second transistor are coupled to the power supply terminal, and the second poles of the first transistor and the second transistor are coupled to the common ground; the first input terminal of the trigger is coupled to the first pole of the first transistor, and the second input terminal of the trigger is coupled to the first pole of the second transistor.

[0007] By coupling the first input terminal and the second input terminal of the flip-flop to the first pole of the first transistor and the first pole of the second transistor respectively, the high-level signal or low-level signal received by the first input terminal and the second input terminal of the flip-flop is only related to the on-time or off-time of the first transistor and the second transistor, and further, the period or frequency of the clock pulse signal at the output terminal of the flip-flop is only related to the on-time and off-time of the first transistor and the second transistor. In this way, it is possible to avoid the change in the clock frequency caused by the delay of the signal received by the flip-flop changing with temperature, so that the frequency of the clock signal output by the clock signal generator can be more stable.

[0008] In a possible implementation manner, the clock signal generator further includes a control signal generation circuit; the output terminal of the control signal generation circuit is respectively coupled to the control pole of the first transistor and the control pole of the second transistor; the control signal generation circuit periodically provides a control signal to the control pole of the first transistor and the control pole of the second transistor, so that the first transistor and the second transistor are alternately turned on and off based on the control signal.

[0009] In a possible implementation manner, the control signal output by the output terminal of the control signal generation circuit is a voltage signal. At this time, the control signal generation circuit may include two output terminals, one of which is coupled to the control pole of the first transistor, and the other is coupled to the control pole of the second transistor. The control signal generation circuit may apply the generated voltage signal between the control pole and the first pole of the first transistor and between the control pole and the second pole of the second transistor to alternately control the on and off of the first transistor and the second transistor.

[0010] In a possible implementation manner, the clock signal generator further includes a first capacitor and a second capacitor; the first pole of the first capacitor is coupled to the control pole of the first transistor, the second pole of the first capacitor is coupled to the common ground, and the first transistor is periodically turned on or off based on the charge and discharge of the first capacitor; the first pole of the second capacitor is coupled to the control pole of the second transistor, the second pole of the second capacitor is coupled to the common ground, and the second transistor is periodically turned on or off based on the charge and discharge of the second capacitor.

[0011] By using the charge and discharge of the first capacitor and the second capacitor to control the first transistor and the second transistor, and then triggering the level inversion of the first output terminal and the second output terminal of the flip-flop to generate a clock signal. The charge and discharge time of the capacitor is related to the material, capacitance and charge and discharge constant of the capacitor itself. Therefore, by controlling the charge and discharge time of the first capacitor and the second capacitor, the clock frequency output by the clock signal generator can be controlled, avoiding the change of the clock signal frequency output caused by the temperature drift of other devices such as operational amplifiers and the change of the static operating point in the clock signal generator, and making the frequency of the clock signal output by the clock signal generator more stable. In addition, in some application scenarios, when a higher clock frequency is required, a capacitor with a small capacitance and a fast charge and discharge time can be used; when a lower clock frequency is required, a capacitor with a large capacitance and a slow charge and discharge time can be used, so that the maximum frequency of the clock signal to be output by the clock signal generator can be effectively increased, and then the performance of the clock signal generator is improved. The control signal output by the output terminal of the control signal generation circuit is a current signal, and the control signal generation circuit periodically and alternately provides the current signal to the first pole of the first capacitor and the first pole of the second capacitor to charge the first capacitor and the second capacitor.

[0012] In a possible implementation manner, the clock signal generator further includes a third transistor; the control electrode and the first electrode of the third transistor are coupled to the power supply terminal, and the second electrode is coupled to the common ground; the control signal generation circuit generates a current signal based on the voltage signal between the first electrode and the second electrode of the third transistor.

[0013] In a possible implementation manner, the clock signal generator further includes a current mirror circuit; the control signal generation circuit converts the voltage between the first electrode and the second electrode of the third transistor into a current and provides it to the current mirror circuit; the current mirror circuit performs mirror processing on the received current based on a preset ratio and provides the processed current to the first pole of the first capacitor and the first pole of the second capacitor.

[0014] By setting up a current mirror circuit, the requirements for the control signal generation circuit can be reduced. When the clock signal generator needs to input a large current, it can be achieved through the current mirror circuit, thereby improving the stability of the control signal generation circuit and further improving the stability of the clock signal generated by the clock signal generator.

[0015] In a possible implementation, the clock signal generator further includes a first selector and a second selector; a control terminal of the first selector is coupled to a first output terminal of the flip-flop, a first input terminal of the first selector is coupled to an output terminal of the control signal generation circuit, a second input terminal of the first selector is coupled to the common ground, and an output terminal of the first selector is coupled to a control electrode of the first transistor; a control terminal of the second selector is coupled to a second output terminal of the flip-flop, a first input terminal of the second selector is coupled to the output terminal of the control signal generation circuit, a second input terminal of the second selector is coupled to the common ground, and an output terminal of the second selector is coupled to a control electrode of the second transistor; under the control of the clock signal output by the first output terminal of the flip-flop, the first selector periodically gates the first input terminal and the second input terminal of the first selector, so that the first capacitor is periodically charged and discharged; under the control of the clock signal output by the first output terminal of the flip-flop, the second selector periodically gates the first input terminal and the second input terminal of the second selector, so that the second capacitor is periodically charged and discharged.

[0016] In a possible implementation, a first input terminal of the flip-flop is coupled to a first pole of the second transistor through an even number of inverters.

[0017] In a possible implementation, a second input terminal of the flip-flop is coupled to a first pole of the third transistor through an even number of inverters.

[0018] By setting the inverters, the circuit driving ability can be improved, thereby improving the inversion speed of the level signals at the first input terminal and the second input terminal of the flip-flop.

[0019] In a possible implementation, the numbers of the first transistor, the second transistor, and the third transistor are proportional. For example, the numbers of the first transistor, the second transistor, and the third transistor are 1:1:1. The parameters of the first transistor, the second transistor, and the third transistor are the same. Specifically, the first transistor, the second transistor, and the third transistor can have the same physical parameters and operating parameters, that is, parameters such as conduction voltage drop, internal resistance, and power are the same. Thereby reducing the temperature drift of the static operating point of the clock signal generator and making the static operating point of the clock signal generator more stable.

[0020] In a second aspect, an embodiment of the present application provides an on-chip clock system, and the on-chip clock system includes the clock signal generator as described in the first aspect.

[0021] In a third aspect, an embodiment of the present application provides a chip, and the chip includes the on-chip clock system as described in the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] To more clearly illustrate the technical solutions of the embodiments of the present application, the accompanying drawings required for the description of the embodiments of the present application will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0023] Figure 1 is a schematic structural diagram of a clock circuit in the prior art;

[0024] Figure 2 is a schematic structural diagram of a clock signal generator provided by an embodiment of the present application;

[0025] Figure 3 is another schematic structural diagram of a clock signal generator provided by an embodiment of the present application;

[0026] Figure 4 is another schematic structural diagram of a clock signal generator provided by an embodiment of the present application;

[0027] Figure 5 is a schematic structural diagram of a voltage-current conversion circuit provided by an embodiment of the present application;

[0028] Figure 6 is another schematic structural diagram of a clock signal generator provided by an embodiment of the present application;

[0029] Figure 7 is a specific schematic structural diagram of a clock signal generator provided by an embodiment of the present application. Specific Embodiments

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are some, but not all, of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.

[0031] As used herein, the terms "first", "second", and similar terms do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not denote a quantity limitation, but rather indicate the presence of at least one. Terms such as "coupled", "connected", or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0032] As used herein, a "unit" generally refers to a functional structure divided logically. Such a "unit" may be implemented by pure hardware or by a combination of software and hardware.

[0033] In the implementation of this application, "and / or" describes the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three cases: A exists alone, both A and B exist simultaneously, and B exists alone.

[0034] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or having more advantages than other embodiments or design solutions. Rather, the use of words such as "exemplary" or "for example" is intended to present relevant concepts in a specific manner.

[0035] In the description of the embodiments of this application, unless otherwise specified, "a plurality of" means two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0036] Please refer to Figure 1 , Figure 1 which shows a typical clock circuit in the prior art. As Figure 1 shown, the clock circuit includes a voltage-current conversion unit 01 for converting a voltage signal into a current signal and a clock signal unit 02 for generating a clock signal. The voltage-current conversion unit 01 is the previous-stage circuit of the clock circuit. The integrated operational amplifier B1 in it converts the voltage into a current and provides it to the gate of the transistor A1, so as to input a signal to the clock signal unit 02 through the transistor A1. The clock signal unit 02 is the subsequent-stage circuit of the clock circuit. Two comparators C1 and C2 are provided in the clock signal unit 02 for generating a trigger signal for the SR flip-flop. From Figure 1It can be seen that one signal input terminal of comparator C1 and comparator C2 is respectively connected to the drains of transistor A3 and transistor A4, and the gates of transistors A3 and A4 are controlled by the drain current of transistor A1, so that the signal for triggering the SR flip-flop depends on the voltage-current conversion circuit 01 and the signals output by comparators C1 and C2. Furthermore, the clock signal CLK generated by the SR flip-flop has the characteristic of following the current generated by the integrated operational amplifier B1 and the signals output by comparators C1 and C2. When the signal VREF input to the input terminal of the integrated operational amplifier B1 or the devices in the voltage-current conversion unit 01 change with temperature or power supply, the clock signal CLK will also change accordingly. In this way, the stability of the clock signal output by the clock circuit is greatly reduced. Secondly, compared with the input signal, there is usually a time delay in the output signals of comparators C1 and C2. This time delay usually limits the highest frequency of the clock signal output by the clock circuit. In view of this, the clock signal generator provided in the embodiments of the present application can generate a clock signal by controlling the on or off of the first transistor and the second transistor without setting a comparator. The frequency of the clock signal is only related to the on and off times of the first transistor and the second transistor. By stably controlling the on and off times of the first transistor and the second transistor, a clock signal with a stable frequency can be output. Secondly, in some implementation manners provided in the embodiments of the present application, by controlling the on and off of the first transistor and the second transistor using the charge and discharge of a capacitor, the on and off times of the first transistor and the second transistor will not be affected by the time delay, temperature drift, etc. of the integrated operational amplifier in the voltage-current conversion unit, thereby further increasing the highest frequency of the clock signal that can be output by the clock circuit.

[0037] Please refer to Figure 2 , which shows a schematic structural diagram of the clock signal generator provided in the embodiments of the present application.

[0038] In Figure 2 , the clock signal generator 100 includes a power supply terminal Vdd and a clock signal generation circuit 10. The clock signal generation circuit 10 includes a transistor T1, a transistor T2, and an SR flip-flop.

[0039] In this embodiment, the transistors T1 and T2 each include a control electrode, a first electrode, and a second electrode. The first electrodes of the transistors T1 and T2 are respectively coupled to the power supply terminal Vdd. The power supply terminal Vdd is used to receive the electric energy provided externally. The second electrodes of the transistors T1 and T2 are respectively coupled to the common ground Gnd. The transistors T1 and T2 here may be insulated gate field effect transistors, such as PMOS transistors, NMOS transistors, etc., which are not limited herein. When the transistors T1 and T2 are NMOS transistors, the control electrode may be a gate, the first electrode may be a drain, and the second electrode may be a source; when the transistors T1 and T2 are PMOS transistors, the control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain. The figure schematically shows the case where the transistors T1 and T2 are NMOS transistors.

[0040] The SR flip-flop includes an input terminal S, an input terminal R, an output terminal QN, and an output terminal Q. Among them, the input terminal S of the SR flip-flop is connected to the first electrode of the transistor T1, the input terminal R of the SR flip-flop is connected to the first electrode of the transistor T2, and the output terminal QN or the output terminal Q of the SR flip-flop is used to output a clock signal. Figure 2 The figure schematically shows the case where the output terminal Q of the SR flip-flop outputs a clock signal. That is to say, the clock signal generator 100 outputs a clock signal through the external interface Clk_out. During the operation of the SR flip-flop, when the level signals or logic signals currently received by the input terminal S and the input terminal R of the SR flip-flop are different from the level signals or logic signals received last time, the level signal transitions of the output terminal QN and the output terminal Q of the SR flip-flop are triggered. In order to make the signal output by the clock signal generator 100 more stable, generally, the input terminal S and the input terminal R of the SR flip-flop receive different levels or different logic signals at the same time. That is, when the input terminal S receives "logic 0", the input terminal R receives "logic 1"; when the input terminal S receives "logic 1", the input terminal R receives "logic 0".

[0041] As Figure 2 shown, the clock signal generator 100 may further include a control signal generation circuit 20 for controlling the conduction and cutoff of the transistors T1 and T2. The control signal generation circuit 20 may include, but is not limited to, a programmable logic controller (PLC), a digital signal processor (DSP), a signal generator, etc. Among them, the output terminals of the control signal generation circuit 20 are respectively coupled to the control electrodes of the transistors T1 and T2.

[0042] Specifically, as Figure 2As shown, the control signal generation circuit 20 may include two output terminals, one of which is coupled to the control electrode of the transistor T1, and the other is coupled to the control electrode of the transistor T2. Here, the signal output by the control signal generation circuit 20 may be a voltage signal. Taking the transistor T1 as an example, the control signal generation circuit 20 may be coupled to the second pole of the transistor T1 to the same common ground, so that the control signal generation circuit 20 may apply a voltage signal between the control electrode and the second pole of the transistor T1. When the voltage signal is greater than the turn-on voltage of the transistor T1, the transistor T1 is turned on; when the voltage signal is no longer applied, the transistor T1 is turned off. In this embodiment, the control signal generation circuit 20 may control the transistors T1 and T2 to alternately turn on and off. That is to say, when the transistor T1 is turned on, the transistor T2 is turned off; when the transistor T2 is turned on, the transistor T2 is turned off. Thus, the input terminal S and the output terminal R of the SR flip-flop can alternately receive signals of different levels.

[0043] Combined with Figure 2 the circuit structure shown, the working principle of the clock signal generator 100 shown in the embodiments of the present application will be described.

[0044] Taking the working state of the transistor T1 as an example, the signal received by the input terminal S of the SR flip-flop will be described first. When the transistor T1 is turned on, the potential at the node a is the internal resistance voltage drop of the transistor T1. Generally, the internal resistance voltage drop of the transistor T1 is very small and can be almost ignored. Here, the potential of the node a can be regarded as 0V. At this time, the input terminal S of the SR flip-flop receives a low-level signal or "logic 0". When the transistor T1 is turned off, the potential at the node a is the potential of the power supply terminal Vdd. At this time, the input terminal S of the SR flip-flop receives a high-level signal or "logic 1". For the working state of the transistor T2 and the signal received by the input terminal R of the SR flip-flop, refer to the description of the signal received by the transistor T1 and the input terminal S of the SR flip-flop, which will not be repeated here.

[0045] In the first time period, the transistor T1 is controlled to be turned on, and the transistor T2 is controlled to be turned off. At this time, the input terminal S of the SR flip-flop receives a low-level signal or "logic 0", and the input terminal R of the SR flip-flop receives a high-level signal or "logic 1". At this time, the Q terminal outputs a low-level signal or "logic 0"; in the second time period, the transistor T1 is controlled to be turned off, and the transistor T2 is controlled to be turned on. At this time, the input terminal S of the SR flip-flop receives a high-level signal or "logic 1", and the input terminal R of the SR flip-flop receives a low-level signal or "logic 0". At this time, the Q terminal outputs a high-level signal or "logic 1". Thus, based on the clock period to be generated, the transistors T1 and T2 are periodically controlled to be turned on or off, and high and low level signals can be alternately output at the output terminal Q of the SR flip-flop, that is, the clock pulse signal.

[0046] As can be seen from Figure 2 in the embodiments of the present application, by connecting the input terminal S and the input terminal R of the SR flip-flop to the first pole of the transistor T1 and the first pole of the transistor T2 respectively, the signals input to the input terminal S and the input terminal R of the SR flip-flop can be separated from the control signals for controlling the conduction or cutoff of the transistors T1 and T2. Compared with Figure 1 the clock circuit shown in which the output terminal of the comparator is connected to the input terminal of the SR flip-flop, in the embodiments of the present application, the period or frequency of the clock pulse signal at the output terminal of the SR flip-flop is only related to the conduction time and cutoff time of the transistors T1 and T2. As long as the conduction time and cutoff time of the transistors T1 and T2 are stably controlled, a stable clock signal can be output by the SR flip-flop, avoiding the change of the clock frequency caused by the delay of the output signal of the comparator changing with temperature, making the frequency of the clock signal output by the clock signal generator 100 more stable. The signals applied to the control electrodes of the first transistor T1 and the second transistor T2 can also be realized by the charge and discharge of capacitors. Specifically, referring to Figure 3 which shows a schematic structural diagram of another clock signal generator provided by the embodiments of the present application.

[0047] As Figure 3 shown, a capacitor C1 is connected between the control electrode of the transistor T1 and the common ground Gnd, and a capacitor C2 is connected between the control electrode of the transistor T2 and the common ground Gnd. At this time, a switching switch can be provided inside the control signal generating circuit 20 to charge and discharge the capacitors C1 and C2. When the control signal generating circuit 20 charges the capacitors C1 and C2, the control signal output by the control signal generating circuit 20 is a current signal. Taking the capacitor C1 as an example, the control signal generating circuit 20 inputs a current signal to the capacitor C1, and the capacitor C1 is charged, and the potential of the n1 point gradually rises. When the potential of the n1 point rises to a certain value such that the voltage between the control electrode and the second electrode of the transistor T1 is greater than the turn-on voltage, the transistor T1 conducts; when the current signal generating end inside the control signal generating circuit 20 switches to the low potential end (such as the common ground end), the capacitor C1 discharges. Under the action of the capacitor C1, the potential of the n1 point does not change suddenly. When the capacitor C1 discharges to a certain value such that the transistor T1 is less than the turn-on voltage, the transistor T1 turns off. When the capacitor C1 is charged, the capacitor C2 discharges; when the capacitor C2 is charged, the capacitor C1 discharges. Thus, by controlling the alternating charge and discharge of the capacitors C1 and C2, the alternating conduction and cutoff of the transistors T1 and T2 are realized. In a possible implementation manner, the clock signal generator 100 further includes a third transistor T3, as Figure 4 shown. In Figure 4Among them, the transistor T3 can be an NMOS transistor, a PMOS transistor, etc., which is not limited here. Among them, the control electrode and the first electrode of the transistor T3 are coupled to the power supply terminal Vdd. The power supply terminal Vdd is used to receive the electric energy provided externally. The second electrode of the transistor T3 is coupled to the common ground Gnd. When the external electric energy of the clock signal generator 100 is provided to the control electrode and the first electrode of the transistor T3 through the power supply terminal Vdd, the voltage between the control electrode and the second electrode of the transistor T3 is greater than the turn-on voltage, and the transistor T3 is turned on. At this time, Figure 4 the potential of the node b in is equal to the voltage drop between the first electrode and the second electrode of the transistor T3. In Figure 4 Among them, as long as the voltage difference between the electric energy provided by the power supply terminal Vdd and the common ground Gnd is greater than the turn-on voltage of the transistor T3, the transistor can work in the on state, and even if the power signal changes, it will not have a great impact on the potential of the node b. Therefore, by setting the transistor T3, a stable voltage signal can be provided for the control signal generation circuit 20, and further the control signal generation circuit 20 provides a stable current signal to the clock signal generation circuit 10.

[0048] In Figure 4 Among them, the control signal generation circuit 20 can convert the voltage signal between the first electrode and the second electrode of the transistor T3 into a current signal and alternately provide it to Figure 3 the capacitors C1 and C2 shown.

[0049] In this implementation manner, the control signal generation circuit 20 can be a circuit in which the output current is proportional to the input voltage. Any circuit in the prior art that can implement the proportional relationship between the output current and the input voltage can be the control signal generation circuit 20 shown in this application, which is not specifically limited here. In a specific implementation, the control signal generation circuit 20 can be Figure 5 the structure shown. In Figure 5 the control signal generation circuit shown, the current output by the output terminal of the integrated operational amplifier B1 is: the sum of the bias voltage of the integrated operational amplifier and the potential of the node b divided by the resistance value of the resistor R. By setting the bias voltage of the integrated operational amplifier B1 and the resistance value of the resistor R, the output current of the integrated operational amplifier B1 can have a certain proportional relationship with the potential of the node b.

[0050] In some optional implementation manners, the clock signal generator 100 may further include a current mirror circuit 30, as Figure 6 shown, Figure 6The schematic diagram of the connection relationship between the current mirror circuit 30 and other circuit elements is shown. The output terminal of the control signal generation circuit 20 is coupled to the input terminal of the current mirror circuit 30, and the output terminal of the current mirror circuit 30 is coupled to the gate of transistor T1 and the control electrode of transistor T2 in the clock signal generation circuit 10. After mirroring the received current signal, the current mirror circuit 30 provides the current signal to capacitors C1 and C2 in the clock signal generation circuit 10 through the output terminal. Among them, the control signal generation circuit 20 can be a circuit that realizes the proportional relationship between the output current and the input voltage, such as Figure 5 the circuit structure of the control signal generation circuit 20 shown. The current mirror circuit 30 can be a current mirror circuit that mirrors the current at a preset ratio, or a circuit that amplifies the current at a preset ratio. For example, the current ratio between the input terminal and the output terminal of the current mirror circuit is 1:N. Here, N is an integer greater than or equal to 1. That is to say, in this optional implementation, the current mirror circuit 30 mirrors the current input by the control signal generation circuit 20 at a preset ratio and provides the processed current to the clock signal generation circuit 10.

[0051] In this optional implementation, by setting the current mirror circuit 30, the requirements for the control signal generation circuit 20 can be reduced. When the clock signal generation circuit 10 needs to input a large current, it can be realized through the current mirror circuit 30, thereby improving the stability of the control signal generation circuit 20 and further improving the stability of the clock signal generated by the clock signal generator 100.

[0052] Next, in conjunction with Figure 7 , the specific structure of the clock signal generator 100 provided by the embodiments of the present application will be described.

[0053] In Figure 7 , the clock signal generator 100 includes a clock signal generation circuit 10, a control signal generation circuit 20, a current mirror circuit 30, a transistor T3, a power supply terminal Vdd, and a clock signal output terminal Clk_out. Among them, the clock signal generation circuit 10 includes a transistor T1, a transistor T2, an SR flip-flop, a capacitor C1, and a capacitor C2. Among them, the connection relationship between the components in the clock signal generation circuit 10 can refer to Figure 2 , Figure 3 for the relevant description. The structural units and connection relationships in the control signal generation circuit 20 and the current mirror circuit 30 can refer to Figures 4 - 6 for the relevant description, which will not be elaborated here.

[0054] As Figure 7In the clock signal generator 100 shown, the clock signal generation circuit 10 further includes a selector M1 and a selector M2. Among them, the control terminal k1 of the selector M1 is coupled to the output terminal QN of the SR flip-flop, the input terminal d1 of the selector M1 is coupled to the output terminal of the current mirror circuit 30, the input terminal d2 of the selector M1 is coupled to the common ground Gnd, and the output terminal o1 of the selector M1 is coupled to the control electrode of the transistor T1. The control terminal k2 of the selector M2 is coupled to the output terminal Q of the SR flip-flop, the input terminal d3 of the selector M2 is coupled to the output terminal of the current mirror circuit 30, the input terminal d4 of the selector M2 is coupled to the common ground Gnd, and the output terminal o2 of the selector M2 is coupled to the control electrode of the transistor T2. The capacitor C1 is coupled between the control electrode of the transistor T1 and the common ground Gnd, and the capacitor C2 is coupled between the control electrode of the transistor T2 and the common ground Gnd.

[0055] Taking the selector M1 as an example, the working principles of the selector M1 and the selector M2 are described. When the control terminal k1 of the selector M1 receives a "logic 0" or a low-level signal, the selector M1 gates the input terminal d1. At this time, the output terminal of the current mirror unit 22 is connected to the control electrode of the transistor T1, and the capacitor C1 is charged, and the potential of the n1 point gradually rises. When the potential of the n1 point rises to a certain value such that the voltage between the control electrode and the second electrode of the transistor T1 is greater than the turn-on voltage, the transistor T1 conducts. When the control terminal k1 of the selector M1 receives a "logic 1" or a high-level signal, the selector M1 gates the input terminal d2. At this time, the control electrode of the transistor T1 is connected to the common ground Gnd, and the capacitor C1 discharges. Under the action of the capacitor C1, the potential of the n1 point does not change suddenly. When the capacitor C1 discharges to a certain value such that the transistor T1 is less than the turn-on voltage, the transistor T1 turns off. The working principle of the selector M2 is the same as that of the selector M1 and will not be elaborated.

[0056] In Figure 7 , the conduction or turn-off of the transistor T1 and the transistor T2 is realized by the charging and discharging of the capacitor C1 and the capacitor C2. The capacitor C1, the capacitor C2, the selector M1, the selector M2, the transistor T1, the transistor T2, and the flip-flop SR act together to generate a clock signal periodically.

[0057] Specifically, the level signal of the output terminal QN of the SR flip-flop is the same as that of the input terminal S of the SR flip-flop, and the level signal of the output terminal Q of the SR flip-flop is the same as that of the input terminal R of the SR flip-flop.

[0058] Assume that at the current moment, the output terminal QN of the SR flip-flop outputs a "logic 1" or a high-level signal, and the output terminal Q of the SR flip-flop outputs a "logic 0" or a low-level signal. In the first time period, the capacitor C1 is charged, and the potential of the node n1 gradually increases. When the potential of the node n1 increases to a certain value, the transistor T1 conducts, making the potential of the point a1 a low potential. The input terminal S of the SR flip-flop receives a low-level signal or "logic 0". At this time, the output terminal QN of the SR flip-flop flips, that is, the output terminal QN of the SR flip-flop outputs a "logic 0" or a low-level signal; the capacitor C2 discharges, and the potential of the node n2 gradually decreases. When the potential of the node n2 drops to a certain value, the transistor T2 turns off, making the potential of the node a2 a high potential. The input terminal R of the SR flip-flop receives a high-level signal. At this time, the output terminal Q of the SR flip-flop flips, that is, the output terminal Q of the SR flip-flop outputs a "logic 1" or a high-level signal. Then, it enters the second time period.

[0059] In the second time period, the capacitor C1 discharges, and the potential of the node n1 gradually decreases. When the potential of the node n1 drops to a certain value, the transistor T1 turns off, making the potential of the point a1 a high potential. The input terminal S of the SR flip-flop receives a high-level signal or "logic 1". At this time, the output terminal QN of the SR flip-flop flips, that is, the output terminal QN of the SR flip-flop outputs a "logic 1" or a high-level signal; the capacitor C2 is charged, and the potential of the node n2 gradually increases. When the potential of the node n2 rises to a certain value, the transistor T2 conducts, making the potential of the node a2 a low potential. The input terminal R of the SR flip-flop receives a low-level signal. At this time, the output terminal Q of the SR flip-flop flips, that is, the output terminal Q of the SR flip-flop outputs a "logic 0" or a low-level signal.

[0060] Thus, through the charging and discharging of the capacitor C1 and the capacitor C2, the output terminal Q and the output terminal QN of the SR flip-flop periodically output high-level signals and low-level signals, that is, clock signals are formed at the output terminal Q and the output terminal QN respectively. Among them, the clock frequency of the clock signal is the flip frequency of the level signal at the output terminal Q or the flip frequency of the level signal at the output terminal QN.

[0061] From Figure 7 it can be seen that in this embodiment, by using the charging and discharging of the capacitor C1 and the capacitor C2 to control the transistors T1 and T2, and then triggering the level flip of the output terminal QN and the output terminal Q of the RS flip-flop to generate a clock signal.

[0062] Compared with Figure 1Different from the prior art shown, in this embodiment, the on and off times of transistors T1 and T2 are only related to the charging and discharging times of capacitors C1 and C2. By controlling the charging and discharging times of capacitors C1 and C2, the clock frequency output by the clock signal generator 100 can be controlled. The charging and discharging times of capacitors C1 and C2 are related to the materials, capacitances, and charging and discharging constants of capacitors C1 and C2 themselves. Thus, the on and off times of transistors T1 and T2 are decoupled from the output current of the control signal generation circuit 20, and the clock signal output by the SR flip-flop is decoupled from the control signal generation circuit, avoiding the change of the on and off times of the transistors caused by the temperature drift of the integrated operational amplifier and the change of the static operating point in the control signal generation circuit, and improving the stability of the output clock signal. In addition, in some application scenarios, when a higher clock frequency is required, capacitors with small capacitance and fast charging and discharging times can be used; when a lower clock frequency is required, capacitors with large capacitance and slow charging and discharging times can be used. Therefore, the maximum frequency of the clock signal to be output by the clock signal generator 100 can be effectively increased, and the performance of the clock signal generator is improved.

[0063] In some implementation manners, the input terminal S of the SR flip-flop is coupled to the first pole of the transistor T1 through an even number of inverters; the input terminal R of the SR flip-flop is coupled to the first pole of the transistor T2 through an even number of inverters. As Figure 7 shown, Figure 7 schematically shows the case where the input terminal S of the SR flip-flop is coupled to the first pole of the transistor T1 through two inverters F1 and F2, and the input terminal R of the SR flip-flop is coupled to the first pole of the transistor T2 through two inverters F3 and F4. By setting the inverters F1, F2, F3, and F4, the clock signal generator 100 can improve the circuit driving ability, thereby increasing the inversion speed of the level signals at the input terminal S and the input terminal R of the SR flip-flop.

[0064] In some implementation manners, the parameters of transistors T1, T2, and T3 are correlated. Specifically, in order to provide a stable static operating point for the clock signal generator 100, transistors T1 and T2 can have the same physical and operating parameters, that is, parameters such as on-voltage drop, internal resistance, and power are the same, and the physical and operating parameters of transistors T1 and T3 can also have a certain proportional relationship. Thus, the currents flowing through node a1 and node a2 can be made to have the same magnitude, and the magnitude of the current flowing through node b and the current flowing through node a1 can have a certain proportional relationship, reducing the temperature drift of the static operating point of the clock signal generator 100.

[0065] Figures 2 - 7In the illustrated embodiment, the numbers of transistors T1, T2, and T3 are schematically shown to have a 1:1:1 relationship. In some scenarios, the numbers of transistors T1, T2, and T3 can also have other proportional relationships. For example, the number of transistors T1 can be two, and these two transistors T1 are connected in series between the power supply terminal Vdd and the common ground Gnd, and the numbers of transistors T2 and T3 can be one.

[0066] The embodiment of the present application also provides an on-chip clock system, which can include any of the above-mentioned clock signal generators and other structures such as voltage sources. Structures such as voltage sources are all existing well-known technologies and will not be elaborated here.

[0067] The embodiment of the present application also provides a chip, which includes the above on-chip clock system. The on-chip clock system including any of the above-mentioned clock signal generators can provide stable clock signals for each module inside the chip, so that each module inside the chip can work stably based on the clock signals.

[0068] Specifically, the chip can be an integrated circuit chip, including but not limited to artificial intelligence chips, digital signal processing chips, image processing chips, etc. When the chip is used to provide image processing functions, data analysis and calculation functions for applications installed in terminal devices (such as mobile phones, computers, wearable intelligent devices), etc., the above electronic device can be a server device, and the chip can be arranged in the server device. When the chip is applied to the field of autonomous driving to provide necessary vehicle-mounted computing, the above electronic device can be a vehicle-mounted control device, and the AI chip can also be arranged in the vehicle-mounted control device. The above chip can also be a 5G chip. At this time, the above electronic device can be a base station hardware device for communicating with the terminal, and the AI chip can be arranged in the base station hardware device.

[0069] The embodiments of the present application have been described above in conjunction with the accompanying drawings. However, the present application is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present application, those of ordinary skill in the art can also make many forms without departing from the purpose of the present application and the scope protected by the claims, and all belong to the protection scope of the present application.

Claims

1. A clock signal generator, characterized in that, It includes a first transistor, a second transistor, a flip-flop, and a power supply terminal; The first poles of the first transistor and the second transistor are coupled to the power supply terminal, and the second poles of the first transistor and the second transistor are coupled to the common ground; The first input terminal of the flip-flop is coupled to the first pole of the first transistor, and the second input terminal of the flip-flop is coupled to the first pole of the second transistor; Wherein, the clock signal generator further includes a control signal generation circuit; The signal output terminals of the control signal generation circuit are respectively coupled to the control poles of the first transistor and the second transistor; The control signal generation circuit periodically provides control signals to the control poles of the first transistor and the second transistor, so that the first transistor and the second transistor are alternately turned on and off based on the control signals.

2. The clock signal generator according to claim 1, wherein, The control signal is a voltage signal.

3. The clock signal generator according to claim 1, characterized in that, The clock signal generator further includes a first capacitor and a second capacitor; The first pole of the first capacitor is coupled to the control pole of the first transistor, and the second pole of the first capacitor is coupled to the common ground. The first transistor is periodically turned on or off based on the charge and discharge of the first capacitor; The first pole of the second capacitor is coupled to the control pole of the second transistor, and the second pole of the second capacitor is coupled to the common ground. The second transistor is periodically turned on or off based on the charge and discharge of the second capacitor.

4. The clock signal generator according to claim 3, wherein The control signal is a current signal, and the control signal generation circuit periodically and alternately provides the current signal to the first pole of the first capacitor and the first pole of the second capacitor to charge the first capacitor and the second capacitor.

5. The clock signal generator according to claim 4, wherein The clock signal generator further includes a third transistor; The control pole and the first pole of the third transistor are coupled to the power supply terminal, and the second pole of the third transistor is coupled to the common ground; The control signal generation circuit generates the current signal based on the voltage signal between the first pole and the second pole of the third transistor.

6. The clock signal generator according to claim 5, characterized in that, The clock signal generator further includes a current mirror circuit; The control signal generation circuit provides the current signal to the current mirror circuit; The current mirror circuit mirrors the received current based on a preset ratio and provides the processed current to the first pole of the first capacitor and the first pole of the second capacitor.

7. The clock signal generator according to any one of claims 4-6, characterized in that, The clock signal generator further includes a first selector and a second selector; The control terminal of the first selector is coupled to the first output terminal of the flip-flop, the first input terminal of the first selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the first selector is coupled to the common ground, and the output terminal of the first selector is coupled to the control pole of the first transistor; The control terminal of the second selector is coupled to the second output terminal of the flip-flop, the first input terminal of the second selector is coupled to the output terminal of the control signal generation circuit, the second input terminal of the second selector is coupled to the common ground, and the output terminal of the second selector is coupled to the control pole of the second transistor; Under the control of the clock signal output at the first output terminal of the trigger, the first selector periodically gates the first input terminal and the second input terminal of the first selector, so that the first capacitor is periodically charged and discharged; Under the control of the clock signal output at the first output terminal of the trigger, the second selector periodically gates the first input terminal and the second input terminal of the second selector, so that the second capacitor is periodically charged and discharged.

8. The clock signal generator according to any one of claims 1-6, characterized in that, The first input terminal of the trigger is coupled to the first pole of the second transistor through an even number of inverters.

9. The clock signal generator according to claim 5, wherein The second input terminal of the trigger is coupled to the first pole of the third transistor through an even number of inverters.

10. The clock signal generator according to claim 5, wherein The numbers of the first transistor, the second transistor, and the third transistor are in a preset ratio; The parameters of the first transistor, the second transistor, and the third transistor are the same.

11. An on-chip clock system, characterized in that, The on-chip clock system includes the clock signal generator as described in any one of claims 1-10.

12. A chip, characterized in that, The chip includes the on-chip clock system as described in claim 11.

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