Display panel and method for manufacturing the same

Abstract

The present application discloses a display panel and a method for preparing the same, wherein the display panel comprises: a substrate; a source-drain electrode layer disposed on one side of the substrate; a light shielding layer covering the source-drain electrode layer and disposed on one side of the substrate; an insulating layer disposed on a side of the light shielding layer away from the substrate; and an active layer disposed on a side of the insulating layer away from the light shielding layer and electrically connected to the light shielding layer through the insulating layer. The technical effect of the present application is to avoid the phenomenon of potential coupling between the light shielding layer and the source-drain electrode layer, and to reduce the parasitic capacitance between the source-drain electrode layer and the gate layer. At the same time, the light shielding layer can also be electrically connected to the gate layer through the conductive layer above the gate layer, so as to achieve a higher mobility and obtain a top-gate low-temperature polysilicon display panel with a bottom-gate structure.

Description

Technical Field

[0001] The present application relates to the display field, and in particular to a display panel and a method for preparing the same. Background Art

[0002] Low Temperature Poly Silicon (LTPS) thin film transistor structure has the advantages of high mobility and good stability, and is currently mainly used in small-size displays.

[0003] The beam width of traditional excimer laser annealing (ELA) technology is limited (less than 1.3m), which cannot meet the requirements of large-size glass substrates above G6 or G8, cannot meet the requirements of active luminescence for high mobility and uniformity, and has high operating and maintenance costs.

[0004] BLA technology is suitable for large substrates such as G10.5, has a deeper laser penetration depth, and can obtain poly-Si films with high crystallinity, large grain size, and no grain boundary protrusions, thereby achieving high mobility and excellent anti-folding performance, and has advantages in application in large-size, flexible displays.

[0005] The active layer has a narrow bandwidth and is sensitive to visible light. During the use of LCD or outdoor direct display, strong light from the bottom can easily cause device characteristics to drift.

[0006] In direct display, if the bottom light shielding layer is at a floating potential, it is very easy to have potential coupling with the source and drain, causing Vth shift under different Vd and affecting the driving characteristics. Summary of the invention

[0007] The purpose of the present application is to provide a display panel and a method for preparing the same, which can solve the technical problems in existing low-temperature polysilicon display devices, such as the narrow bandwidth of the active layer, sensitivity to visible light, easy drift of device characteristics due to strong light from the bottom during use, and easy potential coupling between the light shielding layer and the source and drain layer.

[0008] To achieve the above-mentioned objectives, the present application provides a display panel, comprising: a substrate; a source-drain layer, disposed on the substrate; a light-shielding layer, disposed on the substrate and covering the source-drain layer; an insulating layer, disposed on a side of the light-shielding layer away from the substrate; and an active layer, disposed on a side of the insulating layer away from the light-shielding layer and electrically connected to the light-shielding layer through the insulating layer.

[0009] Furthermore, the display panel also includes: a gate insulating layer, which is arranged on a side of the insulating layer away from the substrate and covers the active layer; a gate layer, which is arranged on a side of the gate insulating layer away from the insulating layer; and a passivation layer, which is arranged on a side of the gate insulating layer away from the insulating layer and covers the gate layer.

[0010] Furthermore, the display panel also includes: a first through hole penetrating the passivation layer, the gate insulating layer and the gate layer, exposing the light shielding layer covering the source and drain layer; and a second through hole recessed in the passivation layer, exposing part of the gate layer.

[0011] Furthermore, the display panel further includes: a conductive layer disposed in the first through hole and the second through hole.

[0012] Furthermore, the light-shielding layer includes a first light-shielding layer and a second light-shielding layer; the first light-shielding layer covers the source and drain layer and extends to the substrate, the second light-shielding layer is arranged on the substrate, and the first light-shielding layer and the second light-shielding layer are isolated and insulated from each other, and the second metal layer is arranged opposite to the gate layer; part of the conductive layer in the second through hole passes through the passivation layer, the gate insulating layer and the insulating layer, and is electrically connected to the second light-shielding layer.

[0013] Furthermore, the active layer penetrates the insulating layer and is electrically connected to the first light shielding layer.

[0014] Furthermore, the light shielding layer is made of a metal material, and the metal material includes: molybdenum or a stacked material of molybdenum and silicon.

[0015] To achieve the above-mentioned objectives, the present application also provides a method for preparing a display panel, comprising the following steps: providing a substrate; preparing a source-drain electrode layer on the substrate; preparing a light-shielding layer on the source-drain electrode layer and on the substrate; preparing an insulating layer on the light-shielding layer and the substrate, and opening an insulating layer through hole on the insulating layer; and preparing an active layer on the insulating layer and in the insulating layer through hole, so that the active layer is electrically connected to the light-shielding layer through the insulating layer through hole.

[0016] Furthermore, in the step of preparing a light-shielding layer on the source and drain layer and on the substrate, a layer of metal material is sputtered on the substrate and the source and drain layer, and patterned to form a first light-shielding layer and a second light-shielding layer that are isolated and insulated from each other, wherein the first light-shielding layer covers the source and drain layer and extends to the substrate, and the second light-shielding layer is arranged on the substrate.

[0017] Furthermore, the method for preparing the display panel also includes the following steps: preparing a gate insulating layer on the active layer; preparing a gate layer on the gate insulating layer; preparing a passivation layer on the gate layer; performing an opening process, penetrating the passivation layer, the gate insulating layer and the insulating layer until the light shielding layer provided on the source and drain layer is exposed to form a first through hole, penetrating the passivation layer until a portion of the gate layer is exposed to form a second through hole; preparing a conductive layer in the first through hole and the second through hole, and a portion of the conductive layer in the second through hole is electrically connected to the light shielding layer through the passivation layer, the gate insulating layer and the insulating layer.

[0018] The technical effect of the present application is that the light shielding layer in the top-gate low-temperature polysilicon display panel is covered above the source and drain and the active layer is electrically connected to the light shielding layer, thereby avoiding the phenomenon of potential coupling between the light shielding layer and the source and drain layer, and further reducing the parasitic capacitance between the gate layer and the source and drain layer. At the same time, the light shielding layer can also be electrically connected to the gate layer through the conductive layer above the gate layer, which can achieve higher mobility and obtain a top-gate low-temperature polysilicon display panel with a bottom-gate structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application;

[0021] Figure 2 is a flow chart of a method for preparing a display panel provided in an embodiment of the present application;

[0022] Figure 3 is a schematic diagram of the structure after the source and drain layers are prepared according to an embodiment of the present application;

[0023] Figure 4 is a schematic diagram of the structure after preparing the light shielding layer provided in an embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the structure after the insulating layer is opened according to the embodiment of the present application;

[0025] Figure 6 is a schematic diagram of the structure after the active layer is prepared according to an embodiment of the present application;

[0026] Figure 7 is a schematic diagram of the structure after preparing the gate layer provided in an embodiment of the present application;

[0027] Figure 8 It is a schematic diagram of the structure after the passivation layer is opened according to the embodiment of the present application;

[0028] Fig. 9 It is a schematic diagram of the structure after preparing the conductive layer provided in an embodiment of the present application.

[0029] Description of reference numerals:

[0030] 100, substrate; 200, source and drain electrode layer; 300, light shielding layer; 400, insulating layer; 500, active layer; 600, gate insulating layer; 700, gate layer; 800, passivation layer; 900, conductive layer;

[0031] 310, first light shielding layer; 320, second light shielding layer; 410, insulating layer through hole; 810, first through hole; 820, second through hole. DETAILED DESCRIPTION

[0032] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words such as "upper" and "lower" used generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the accompanying drawings; while "inside" and "outside" refer to the outline of the device.

[0033] like Figures 1 to 9 As shown, this embodiment provides a display panel and a method for manufacturing the same, referring to Figure 1 The display panel includes a substrate 100, a source-drain electrode layer 200, a light shielding layer 300, an insulating layer 400, an active layer 500, a gate insulating layer 600, a gate layer 700, a passivation layer 800, and a conductive layer 900. The display panel in this embodiment is a top-gate low-temperature polysilicon thin film transistor structure with a bottom gate. The light shielding layer 300 covers the source-drain electrode layer 200 and is connected to the active layer 500 in potential, so as to avoid the problem of potential coupling between the light shielding layer and the source-drain electrode layer, thereby causing characteristic drift of the display panel. The following will describe in detail each film layer in the display panel.

[0034] The substrate 100 is a glass substrate, which has good substrate and supporting functions.

[0035] like Figure 3As shown, the source-drain electrode layer 200 is disposed on the upper surface of the substrate 100, and the source-drain electrode layer 200 includes a source electrode and a drain electrode, which are respectively used to connect the light-emitting structure and the data line. The source-drain electrode layer 200 is made of a metal material with low resistivity, and the metal material includes a laminated structure of metals such as aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti), for example: Al / Mo or Mo / Al / Mo or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb.

[0036] like Figure 4 As shown, the light-shielding layer 300 includes a first light-shielding layer 310 and a second light-shielding layer 320. The first light-shielding layer 310 covers the source-drain electrode layer 200 and extends to the upper surface of the substrate 100. The second light-shielding layer 320 is arranged on the upper surface of the substrate 100 and is located between the two first light-shielding layers 310. The second light-shielding layer 320 and the first light-shielding layer 310 are isolated and insulated from each other.

[0037] The light shielding layer 300 is made of a metal material, including molybdenum (Mo) or a laminated material of molybdenum and silicon (Si) or other metal materials with high temperature resistance and good light shielding performance. Using a material with high temperature resistance and good light shielding performance to make the light shielding layer can prevent the light shielding layer from melting during the laser annealing process, thereby protecting the light shielding layer 300.

[0038] like Figure 5 As shown, the insulating layer 400 is disposed on the upper surface of the light shielding layer 300 and the substrate 100, and is made of an inorganic insulating material, including silicon oxide (SiOx) or silicon nitride (SiNx) or a stack thereof (SiNx / SiOx) or silicon oxynitride (SiNOx), etc., to isolate the electrical connection between the metal layers on both sides to prevent short circuit problems. The insulating layer 400 is provided with an insulating layer through hole 410, and the insulating layer through hole 410 is used as a connection channel between the active layer 500 and the light shielding layer 300.

[0039] like Figure 6As shown, the active layer 500 is arranged on the upper surface of the insulating layer 400. The material of the active layer 500 is semiconductor material. After laser baking, the two sides change from a semiconductor state to a conductor state and have conductivity. The conductor parts at both ends respectively penetrate the insulating layer 400 downward, and are electrically connected to the first light-shielding layer 310 from the insulating layer through hole 410. The light-shielding layer 300 can be connected to the active layer 500 in potential while playing a light-shielding role, thereby avoiding the problem of potential coupling between the light-shielding layer 300 and the source-drain layer 200 causing characteristic drift of the display panel.

[0040] The gate insulating layer 600 is disposed on the upper surface of the insulating layer 400 and covers the active layer 500. The gate insulating layer 600 is made of an inorganic insulating material, including silicon oxide (SiOx) or silicon nitride (SiNx) or a stacked structure (Al2O3 / SiNx / SiOx, SiOx / SiNx / SiOx), which serves to isolate the metal layers on both sides.

[0041] like Figure 7 As shown, the gate layer 700 is disposed on the upper surface of the gate insulating layer 600, and the material of the gate layer 700 is a metal material, and the metal material includes metals such as aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti) or metal laminated structures, such as: Mo or Mo / Al or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb. The gate layer 700 is disposed opposite to the active layer 500 and the second light shielding layer 320, and the active layer portion directly below the gate layer 700 is a channel portion with semiconductor properties, and the outer side thereof is a conductor.

[0042] like Figure 8 As shown, the passivation layer 800 is arranged on the upper surface of the gate insulating layer 600 and covers the gate layer 700. The material of the passivation layer 800 is also an inorganic insulating material, including silicon oxide (SiOx) or silicon nitride (SiNx) or silicon oxynitride (SiNOx). The passivation layer 800 is provided with a first through hole 810 and a second through hole 820. The first through hole 810 starts from the passivation layer 800 and penetrates the passivation layer 800, the gate insulating layer 600 and the insulating layer 400 in sequence downward until the first light shielding layer 310 covering the source and drain electrode layer 200 is exposed. The second through hole 820 is recessed in the passivation layer 800 to expose part of the gate layer 700. The first through hole 810 and the second through hole 820 are used as connection channels between the conductive layer 900 and other film layers.

[0043] like Figure 1 , Fig. 9 As shown, the conductive layer 900 is disposed in the first through hole 810 and the second through hole 820, and is electrically connected to the gate layer 700 and the first light shielding layer 310, respectively. In the first through hole 810, the conductive layer 900 serves as a pixel electrode, and in the second through hole 820, part of the conductive layer 900 passes through the passivation layer 800, the gate insulating layer 600, and the insulating layer 400 until the second light shielding layer 320 is exposed, and is electrically connected to the second light shielding layer 320, as shown in the attached Fig. 9 As shown, the figure is depicted by dotted lines, because it is blocked and cannot be seen at this cross section, and is represented by dotted lines for illustration. At this time, the second light shielding layer 320 can be electrically connected to the gate layer 700 through the conductive layer 900, that is, the top-gate low-temperature polysilicon thin film transistor structure with a bottom-gate structure described above can be realized, and a DG design with higher mobility can be realized.

[0044] The technical effect of the display panel described in this embodiment is that the light shielding layer in the top-gate low-temperature polysilicon display panel covers the source and drain electrodes and the active layer is electrically connected to the light shielding layer, thereby avoiding the phenomenon of potential coupling between the light shielding layer and the source and drain electrode layers, and further reducing the parasitic capacitance between the gate layer and the source and drain electrode layers. At the same time, the light shielding layer can also be electrically connected to the gate layer through the conductive layer above the gate layer, which can achieve higher mobility and obtain a top-gate low-temperature polysilicon display panel with a bottom-gate structure.

[0045] like Figure 2 As shown, this embodiment also provides a method for preparing a display panel, including steps S1 to S9.

[0046] S1 provides a substrate 100, wherein the substrate 100 is a glass substrate having good substrate and supporting functions.

[0047] S2 prepares the source-drain electrode layer 200 on the substrate 100. Specifically, a layer of low-resistivity metal material is sputtered on the substrate 100. The metal material includes a laminated structure of metals such as aluminum (Al), molybdenum (Mo), copper (Cu), and titanium (Ti), for example: Al / Mo or Mo / Al / Mo or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb, and then performs patterning to form the source-drain electrode layer 200 (see Figure 3 ).

[0048] S3 prepares a light shielding layer 300 on the source and drain electrode layer 200 and the substrate 100. Specifically, a layer of metal material is sputtered on the source and drain electrode layer 200 and the substrate 100. The metal material includes molybdenum (Mo) or a stacked material of molybdenum and silicon (Si) or other metal materials that are resistant to high temperatures and have good light shielding properties. The use of high-temperature resistant and light-shielding materials to make the light shielding layer can prevent the light shielding layer from melting during the laser annealing process, thereby protecting the light shielding layer 300. Patterning is then performed to form a first light shielding layer 310 and a second light shielding layer 320 that are complementary and connected. The first light shielding layer 310 covers the source and drain electrode layer 200 and extends to the upper surface of the substrate 100. The second light shielding layer 320 is provided on the upper surface of the substrate 100 and is located between the two first light shielding layers 310 (see Figure 4 ).

[0049] S4: preparing an insulating layer 400 on the light shielding layer 300 and the substrate 100, and opening an insulating layer through hole 410 on the insulating layer 400. Specifically, a layer of inorganic insulating material, including silicon oxide (SiOx) or silicon nitride (SiNx) or a stack (SiNx / SiOx) thereof or silicon oxynitride (SiNOx), is sputtered on the upper surface of the light shielding layer 300 and the substrate 100 to isolate the electrical connection between the metal layers on both sides and prevent short circuit problems, thereby forming an insulating layer 400. Opening an insulating layer through hole 410 on the insulating layer 400 (see Figure 5 ), the insulating layer through hole 410 is used as a connection channel between the subsequent film layer and the light shielding layer 300.

[0050] S5: preparing an active layer 500 on the insulating layer 400 and in the insulating layer through hole 410, so that the active layer 500 is electrically connected to the light shielding layer 300 through the insulating layer through hole 410 (see Figure 6 ). Specifically, a layer of semiconductor material is sputtered on the upper surface of the insulating layer 400. After laser baking, the conductive properties on both sides of the insulating layer 400 change from a semiconductor state to a conductor state, and the conductive parts at both ends respectively penetrate the insulating layer 400 downward, and are electrically connected to the first light shielding layer 310 from the insulating layer through hole 410. The light shielding layer 300 can be connected to the active layer 500 at a potential while playing a light shielding role, thereby avoiding the problem of characteristic drift of the display panel caused by potential coupling between the light shielding layer 300 and the source and drain layer 200.

[0051] S6: preparing a gate insulating layer 600 on the active layer 500, and depositing a layer of inorganic insulating material on the upper surface of the insulating layer 400 and the active layer 500, including silicon oxide (SiOx) or silicon nitride (SiNx) or a stacked structure (Al2O3 / SiNx / SiOx, SiOx / SiNx / SiOx), to isolate the metal layers on both sides.

[0052] S7: a gate layer 700 is formed on the gate insulating layer 600 (see Figure 7 ), a layer of metal material is sputtered on the upper surface of the gate insulating layer 600, and the metal material includes metals such as aluminum (Al), molybdenum (Mo), copper (Cu), titanium (Ti) or metal stacked structures, such as: Mo or Mo / Al or Mo / Cu or Mo / Cu / IZO or IZO / Cu / IZO or Mo / Cu / ITO or Ni / Cu / Ni or MoTiNi / Cu / MoTiNi or NiCr / Cu / NiCr or CuNb, etc., and patterned, and ion implantation is performed using a self-aligned process.

[0053] S8: A passivation layer 800 is prepared on the gate layer 700, and a hole is formed by drilling through the passivation layer 800, the gate insulating layer 600, and the insulating layer 400 until the first light shielding layer 310 disposed on the source and drain electrode layer 200 is exposed, thereby forming a first through hole 810; and a second through hole 820 is formed by drilling through the passivation layer 800 until a portion of the gate layer 700 is exposed (see FIG. Figure 8 ), the first through hole 810 and the second through hole 820 are used as connection channels between the conductive layer 900 and other film layers.

[0054] S9: preparing a conductive layer 900 in the first through hole 810 and the second through hole 820; in the first through hole 810, the conductive layer 900 serves as a pixel electrode; a portion of the conductive layer 900 in the second through hole 820 passes through the passivation layer 800, the gate insulating layer 600, and the insulating layer 400 and is electrically connected to the second light shielding layer 320; see the attached Fig. 9 As shown, the figure is depicted by dotted lines, because it is blocked and cannot be seen at this cross section, and is represented by dotted lines for illustration. At this time, the second light shielding layer 320 can be electrically connected to the gate layer 700 through the conductive layer 900, that is, the top-gate low-temperature polysilicon thin film transistor structure with a bottom-gate structure described above can be realized, and a DG design with higher mobility can be realized.

[0055] The technical effect of the method for preparing the display panel described in this embodiment is that the light shielding layer in the top-gate low-temperature polysilicon display panel is covered above the source and drain electrodes and the active layer is electrically connected to the light shielding layer, thereby avoiding the phenomenon of potential coupling between the light shielding layer and the source and drain electrode layers, and further reducing the parasitic capacitance between the gate layer and the source and drain electrode layers. At the same time, the light shielding layer can also be electrically connected to the gate layer through the conductive layer above the gate layer, which can achieve higher mobility and obtain a top-gate low-temperature polysilicon display panel with a bottom-gate structure.

[0056] The above is a detailed introduction to a display panel and a preparation method thereof provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: include: substrate; A source-drain electrode layer is disposed on the substrate; A light shielding layer, disposed on the substrate and covering the source and drain electrode layer; an insulating layer, disposed on a side of the light shielding layer away from the substrate; and An active layer, disposed on a side of the insulating layer away from the light shielding layer, and electrically connected to the light shielding layer through the insulating layer; The light-shielding layer includes a first light-shielding layer and a second light-shielding layer; The first light-shielding layer covers the source and drain layer and extends onto the substrate, the second light-shielding layer is disposed on the substrate, and the first light-shielding layer and the second light-shielding layer are isolated and insulated from each other, the active layer passes through the insulating layer and is electrically connected to the first light-shielding layer, and the portion of the first light-shielding layer extending onto the substrate is connected to the active layer.

2. The display panel according to claim 1, wherein: Also includes: A gate insulating layer, disposed on a side of the insulating layer away from the substrate and covering the active layer; A gate layer, disposed on a side of the gate insulating layer away from the insulating layer; The passivation layer is disposed on a side of the gate insulating layer away from the insulating layer and covers the gate layer.

3. The display panel according to claim 2, wherein: The display panel further includes: A first through hole penetrates the passivation layer, the gate insulating layer and the gate layer to expose the light shielding layer covering the source and drain electrode layer; A second through hole is recessed in the passivation layer to expose a portion of the gate layer.

4. The display panel according to claim 3, wherein: Also includes: The conductive layer is disposed in the first through hole and the second through hole.

5. The display panel according to claim 4, wherein: The second light shielding layer is arranged opposite to the gate layer; A portion of the conductive layer in the second through hole passes through the passivation layer, the gate insulating layer, and the insulating layer, and is electrically connected to the second light shielding layer.

6. The display panel according to claim 5, characterized in that: The active layer penetrates the insulating layer and is electrically connected to the first light shielding layer.

7. The display panel according to claim 1, wherein: The light shielding layer is made of metal material, and the metal material includes molybdenum or a stacked material of molybdenum and silicon.

8. A method for preparing a display panel, characterized in that: The following steps are involved: providing a substrate; preparing a source-drain electrode layer on the substrate; A light shielding layer is prepared on the source-drain electrode layer and the substrate, a layer of metal material is sputtered on the substrate and the source-drain electrode layer, and patterned to form a first light shielding layer and a second light shielding layer which are isolated and insulated from each other, wherein the first light shielding layer covers the source-drain electrode layer and extends to the substrate, and the second light shielding layer is arranged on the substrate; Preparing an insulating layer on the light-shielding layer and the substrate, and opening an insulating layer through hole on the insulating layer; as well as An active layer is prepared on the insulating layer and in the insulating layer through hole, so that the active layer is electrically connected to the light shielding layer through the insulating layer through hole, and a portion of the first light shielding layer extending onto the substrate is connected to the active layer.

9. The method for preparing a display panel according to claim 8, wherein: The following steps are also included: preparing a gate insulating layer on the active layer; preparing a gate layer on the gate insulating layer; preparing a passivation layer on the gate layer; Performing a hole opening process, penetrating the passivation layer, the gate insulating layer and the insulating layer until the light shielding layer provided on the source and drain electrode layer is exposed, thereby forming a first through hole, and penetrating the passivation layer until a portion of the gate layer is exposed, thereby forming a second through hole; A conductive layer is prepared in the first through hole and the second through hole, and a portion of the conductive layer in the second through hole is electrically connected to the light shielding layer through the passivation layer, the gate insulating layer and the insulating layer.

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