Array substrate and preparation method thereof, and display panel

Abstract

The embodiment of the present application discloses an array substrate and a preparation method thereof, and a display panel, wherein the array substrate comprises: a substrate; a conductive film layer, which is arranged on the substrate; a first light shielding layer, a second light shielding layer, and a third light shielding layer, wherein the first light shielding layer, the second light shielding layer, and the third light shielding layer are all arranged on the side of the conductive film layer away from the substrate, wherein the first light shielding layer and the second light shielding layer are located in the orthographic projection area of ​​the substrate within the orthographic projection area of ​​the conductive film layer, and wherein the first light shielding layer and the second light shielding layer are both made of conductor materials; and an array device layer, wherein a pixel unit in the array device layer comprises a first thin film transistor, a second thin film transistor, and a third thin film transistor, wherein the first light shielding layer is located between the substrate and the first thin film transistor, the second light shielding layer is located between the substrate and the second thin film transistor, and the third light shielding layer is located between the substrate and the third thin film transistor. The present application avoids the metal traces connecting the first light shielding layer and the second light shielding layer from being short-circuited with other metal traces.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular, relates to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] Light can affect the stability of the oxide semiconductor thin film transistors in the display panel. To solve this problem, traditional technical solutions usually add a light-shielding layer at the bottom of the oxide semiconductor thin film transistor to shield the oxide semiconductor thin film transistor from light, thereby improving the stability of the oxide semiconductor thin film transistor.

[0003] A pixel unit in a display panel with a 3T1C driving architecture includes three thin-film transistors. Traditional technical solutions usually add a shading layer under the three thin-film transistors for shading. Among the three thin-film transistors, the shading layers corresponding to the other two thin-film transistors except the driving thin-film transistor are directly connected through metal routing, and are led out through the metal routing on the same layer as the shading layer and connected to a given potential. Although this method avoids the threshold voltage offset between the two thin-film transistors, the metal routing between the two is prone to short circuit with other signal lines. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a method for manufacturing the same, and a display panel, which prevent a metal wiring connecting a first light shielding layer and a second light shielding layer from being short-circuited with other metal wirings.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, comprising:

[0006] substrate;

[0007] A conductive film layer is disposed on the substrate;

[0008] a first light-shielding layer, a second light-shielding layer and a third light-shielding layer, wherein the first light-shielding layer, the second light-shielding layer and the third light-shielding layer are all arranged on a side of the conductive film layer away from the substrate, the first light-shielding layer and the second light-shielding layer are located within the orthographic projection region of the conductive film layer on the substrate in the orthographic projection region of the substrate, and the first light-shielding layer and the second light-shielding layer are both made of conductor materials;

[0009] An array device layer, wherein a pixel unit in the array device layer comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, the first light shielding layer is located between the substrate and the first thin film transistor, the second light shielding layer is located between the substrate and the second thin film transistor, and the third light shielding layer is located between the substrate and the third thin film transistor.

[0010] Optionally, in some embodiments, the array substrate further includes a first planar layer, the first planar layer is disposed between the conductive film layer and the third shading layer, and the third shading layer is located within the orthographic projection area of ​​the first planar layer on the substrate in the orthographic projection area of ​​the substrate.

[0011] Optionally, in some embodiments, the first planarizing layer is disposed on the same layer as the first light-shielding layer and the second light-shielding layer on the conductive film layer, respectively, and the sum of the orthographic projection areas of the first light-shielding layer, the second light-shielding layer and the first planarizing layer on the substrate is less than or equal to the orthographic projection area of ​​the conductive film layer on the substrate.

[0012] Optionally, in some embodiments, the conductive film layer is provided with a groove on a side away from the substrate, and the third light shielding layer is located within the groove in the orthographic projection area of ​​the substrate.

[0013] Optionally, in some embodiments, the depth of the groove is less than the thickness of the conductive film layer.

[0014] Optionally, in some embodiments, the conductive film layer is connected to a common voltage input terminal located in a peripheral area of ​​the array substrate.

[0015] Optionally, in some embodiments, the material of the conductive film layer is indium tin oxide.

[0016] Optionally, in some embodiments, the base substrate further includes a gate insulating layer and a second planarizing layer, the gate insulating layer is disposed on the conductive film layer, the gate insulating layer covers the first light-shielding layer, the second light-shielding layer, the third light-shielding layer and the first planarizing layer, and the second planarizing layer is disposed on the gate insulating layer.

[0017] In a second aspect, an embodiment of the present application further provides a method for preparing an array substrate, comprising:

[0018] providing a substrate;

[0019] forming a conductive thin film layer on the substrate;

[0020] A first light shielding layer, a second light shielding layer and a third light shielding layer are formed on the side of the conductive film layer away from the substrate, wherein the first light shielding layer and the second light shielding layer are located within the orthographic projection area of ​​the conductive film layer on the substrate in the orthographic projection area of ​​the substrate, and the first light shielding layer and the second light shielding layer are both made of conductor materials;

[0021] An array device layer is formed on the first light-shielding layer, the second light-shielding layer and the third light-shielding layer, wherein a pixel unit in the array device layer comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, the first light-shielding layer is located between the substrate and the first thin film transistor, the second light-shielding layer is located between the substrate and the second thin film transistor, and the third light-shielding layer is located between the substrate and the third thin film transistor.

[0022] Optionally, in some embodiments, the method further comprises:

[0023] A first planar layer is formed on the conductive film layer, wherein the first planar layer is disposed between the conductive film layer and the third light shielding layer, and the third light shielding layer is located within the orthographic projection region of the first planar layer on the substrate.

[0024] Optionally, in some embodiments, after forming a first light shielding layer, a second light shielding layer and a third light shielding layer on a side of the conductive film layer away from the substrate, the method further comprises:

[0025] forming a gate insulating layer on the conductive film layer, wherein the gate insulating layer covers the first light shielding layer, the second light shielding layer, the third light shielding layer and the first planarization layer;

[0026] A second planarization layer is formed on the gate insulating layer.

[0027] In a third aspect, an embodiment of the present application further provides a display panel, comprising an array substrate as described in any one of the above items.

[0028] The array substrate provided by the embodiment of the present application includes: a substrate; a conductive film layer, which is arranged on the substrate; a first light shielding layer, a second light shielding layer and a third light shielding layer, wherein the first light shielding layer, the second light shielding layer and the third light shielding layer are all arranged on the side of the conductive film layer away from the substrate, the first light shielding layer and the second light shielding layer are located in the orthographic projection area of ​​the substrate in the orthographic projection area of ​​the conductive film layer in the substrate, and the first light shielding layer and the second light shielding layer are both conductor materials; an array device layer, wherein a pixel unit in the array device layer includes a first thin film transistor, a second thin film transistor and a third thin film transistor, the first light shielding layer is located between the substrate and the first thin film transistor, the second light shielding layer is located between the substrate and the second thin film transistor, and the third light shielding layer is located between the substrate and the third thin film transistor. In the present application, the first light shielding layer and the second light shielding layer are conductive materials, so that electrical connection can be achieved through the conductive film layer, thereby avoiding the metal traces connecting the first light shielding layer and the second light shielding layer from short-circuiting with other metal traces. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1This is a schematic diagram of the first structure of an array substrate in the related technology provided by an embodiment of the present application.

[0030] Figure 2 This is a second structural schematic diagram of an array substrate in the related technology provided in an embodiment of the present application.

[0031] Figure 3 This is a schematic diagram of the first structure of the array substrate provided in an embodiment of the present application.

[0032] Figure 4 This is a schematic diagram of the second structure of the array substrate provided in an embodiment of the present application.

[0033] Figure 5 This is a third structural schematic diagram of the array substrate provided in an embodiment of the present application.

[0034] Figure 6 This is a fourth structural schematic diagram of the array substrate provided in an embodiment of the present application.

[0035] Figure 7 It is a schematic diagram of the process of the method for preparing the array substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0037] Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the present invention belongs. The "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] A pixel unit in a display panel with a 3T1C driving architecture includes three thin film transistors. Traditional technical solutions usually add a light shielding layer under the driving thin film transistor for light shielding, while the other two thin film transistors do not provide light shielding. If a light shielding layer is added under the other two thin film transistors for light shielding, the potential of the added light shielding layer needs to be considered.

[0039] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of the first structure of an array substrate in the related art provided by an embodiment of the present application, Figure 2 The array substrate 100 may include a substrate 110 , a gate insulating layer 120 , a first light shielding layer 130 , a second light shielding layer 140 , a third light shielding layer 150 and a planar layer 160 .

[0040] Among them, the bottom of each of the three thin film transistors included in a pixel unit in the 3T1C display panel corresponds to the first light-shielding layer 130, the second light-shielding layer 140 and the third light-shielding layer 150, that is, the first light-shielding layer 130, the second light-shielding layer 140 and the third light-shielding layer 150 respectively play a light-shielding role for the three thin film transistors in a pixel unit in the array substrate 100.

[0041] In order to avoid the first light shielding layer 130 and the second light shielding layer 140, such as the third light shielding layer 150, being connected to the source of the corresponding thin film transistor, so that the first light shielding layer 130 and the second light shielding layer 140 are subjected to long-term gate pressure, resulting in a threshold voltage shift between the corresponding two thin film transistors, resulting in leakage during the light-emitting stage. In the related art, the first light shielding layer 130 and the second light shielding layer 140 are electrically connected together through a metal wiring, and the metal wiring is arranged in the same layer as the first light shielding layer 130 and the second light shielding layer 140, and the metal wiring is led out through the first light shielding layer 130 and the second light shielding layer 140, and a given potential is applied to it, and the signal externally connected to the first light shielding layer 130 and the second light shielding layer 140 can be controlled by the given potential.

[0042] However, since metal wiring for controlling other signals is arranged on the same layer as the first shading layer 130 and the second shading layer 140, there will be many cross-wires between the metal wiring connecting the first shading layer 130 and the second shading layer 140 and the metal wiring of other signals, which may easily cause a short circuit.

[0043] In order to solve the problems existing in the related art, the embodiments of the present application provide an array substrate, a method for preparing the array substrate and a display panel. Figure 3 and Figure 4 , Figure 3is a schematic diagram of a first structure of an array substrate provided in an embodiment of the present application, Figure 4 2 is a schematic diagram of a second structure of an array substrate provided in an embodiment of the present application. The array substrate 200 may include a substrate 210 , a conductive film layer 220 , a first light shielding layer 230 , a second light shielding layer 240 and a third light shielding layer 250 .

[0044] The substrate 210 may be a glass substrate or the like. The conductive film layer 220 may be disposed on the substrate 210. Specifically, the conductive film layer 220 may be formed on the substrate 210 in its entirety, that is, the area of ​​the conductive film layer 220 is the same as the area of ​​the substrate 210. The conductive film layer 220 may be made of a conductive material, such as indium tin oxide, etc. Therefore, the conductive film layer 220 may be used as a common electrode, and the conductive film layer 220 may form a common electrode in its entirety on the substrate 210. The conductive film layer 220 may be connected to a common voltage input terminal located in the peripheral area of ​​the array substrate 200, so that the conductive film layer 220 obtains a common voltage.

[0045] The first light shielding layer 230, the second light shielding layer 240 and the third light shielding layer 250 are all arranged on the side of the conductive film layer 220 away from the substrate 210. The first light shielding layer 230 and the second light shielding layer 240 are both made of conductive materials. The first light shielding layer 230 and the second light shielding layer 240 are both arranged in contact with the conductive film layer 220, and the orthographic projection area of ​​the first light shielding layer 230 and the second light shielding layer 240 on the substrate 210 is located within the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. In addition, since the first light-shielding layer 230 and the second light-shielding layer 240 are both made of conductive materials, the first light-shielding layer 230 and the second light-shielding layer 240 are both electrically connected to the conductive film layer 220. Since the first light-shielding layer 230 and the second light-shielding layer 240 are in direct contact with the conductive film layer 220, there is no need to set a metal wiring between the first light-shielding layer 230 and the second light-shielding layer 240 and the conductive film layer 220 to achieve the electrical connection between the first light-shielding layer 230 and the second light-shielding layer 240 and the conductive film layer 220, thereby achieving the electrical connection between the first light-shielding layer 230 and the second light-shielding layer 240 through the conductive film layer 220.

[0046] As can be seen from the above, the difference between the array substrate 200 provided in this embodiment and the array substrate 100 in the related art is that: in this embodiment, the electrical connection between the first light-shielding layer 230 and the second light-shielding layer 240 is not achieved by metal wiring, but the electrical connection between the two is achieved by direct contact between the first light-shielding layer 230 and the second light-shielding layer 240 and the conductive film layer 220. Since the conductive film layer 220 and the first light-shielding layer 230 and the second light-shielding layer 240 are not in the same layer, the short circuit problem caused by the first light-shielding layer 230 and the second light-shielding layer 240 being connected by metal wiring in the same layer and the metal wiring controlling other signals in the same layer is avoided, thereby improving product quality.

[0047] It should be noted that the array substrate 200 includes an array device layer, and the array device layer includes a plurality of pixel units, and each pixel unit may include three thin film transistors, namely a first thin film transistor, a second thin film transistor, and a third thin film transistor. In order to shield each thin film transistor from light, a light shielding layer is correspondingly arranged under each thin film transistor. Specifically, the first thin film transistor is arranged correspondingly to the first light shielding layer 230, and the first light shielding layer 230 is located between the substrate 210 and the first thin film transistor, and the first light shielding layer 230 shields the first thin film transistor; the second thin film transistor is arranged correspondingly to the second light shielding layer 240, and the second light shielding layer 240 is located between the substrate 210 and the second thin film transistor, and the second light shielding layer 240 shields the second thin film transistor; the third thin film transistor is arranged correspondingly to the third light shielding layer 250, and the third light shielding layer 250 is located between the substrate 210 and the third thin film transistor, and the third light shielding layer 250 shields the third thin film transistor.

[0048] It should be noted that, since the array device layer of the array substrate 200 includes multiple pixel units, each pixel unit includes a first thin film transistor, a second thin film transistor and a third thin film transistor. In order to achieve light shielding for the thin film transistors, the three thin film transistors of each pixel unit need to be respectively provided with a first light shielding layer 230, a second light shielding layer 240 and a third light shielding layer 250, that is, multiple pixel units are correspondingly provided with multiple first light shielding layers 230, multiple second light shielding layers 240 and multiple third light shielding layers 250, and a first light shielding layer 230 and a second light shielding layer 240 corresponding to a pixel unit are electrically connected through a conductive film layer 220.

[0049] In the array substrate 100 provided by the prior art, a first light shielding layer 130 and a second light shielding layer 140 corresponding to a pixel unit are connected to an external chip through a metal wiring connected thereto, so that there are multiple metal wirings connected thereto during the connection between the two and multiple chips, thereby increasing the output signal of the array substrate 100. In this embodiment, the conductive film layer 220 is disposed on the substrate 210 in its entirety, so that it can be electrically connected to multiple external chips, and the multiple first light shielding layers 230 and the multiple second light shielding layers 240 in the array substrate 200 are directly electrically connected to the conductive film layer 220, so that there is no need to respectively connect the multiple first light shielding layers 230 and the multiple second light shielding layers 240 with multiple chips, and the multiple thin film transistors in the array substrate 200 can control the signals of multiple chips by connecting to the conductive film layer 220, thereby reducing the metal wirings connected thereto, reducing the output signal, and improving the quality of the product.

[0050] Among them, the first shading layer 230 and the second shading layer 240 can be prepared by the same process. Specifically, a first shading layer 230 and a second shading layer 240 corresponding to each pixel unit in the array substrate 200 can also be prepared by the same process, thereby reducing the preparation process.

[0051] In addition, the array substrate 200 may further include a first flat layer 260, which may be disposed on the conductive film layer 220. Specifically, the first flat layer 260 may be disposed between the conductive film layer 220 and the third light shielding layer 250, and the first flat layer 260 is an insulating material. It should be noted that the third light shielding layer 250 corresponds to the third thin film transistor, that is, the third light shielding layer 250 shields the third thin film transistor, and the third thin film transistor may be a driving thin film transistor, which is used to connect to the light emitting device in the pixel unit to emit light. Therefore, the third light shielding layer 250 needs to be connected to the source of the third thin film transistor to obtain a given voltage of the light emitting device. Since the conductive film layer 220 is conductive, if the third light shielding layer 250 is in direct contact with the conductive film layer 220, if the given voltage obtained by the third light shielding layer 250 is the same as the common voltage obtained by the conductive film layer 220, a short circuit phenomenon is easily caused.

[0052] Therefore, in order to avoid the short circuit between the third light-shielding layer 250 and the conductive film layer 220, the orthographic projection area of ​​the third light-shielding layer 250 on the substrate 210 can be set within the orthographic projection area of ​​the first flat layer 260 on the substrate 210, so that the first flat layer 260 with insulating properties can block the electrical connection between the third light-shielding layer 250 and the film layer 220.

[0053] See also Figure 3 and Figure 5 , Figure 5 : is a third structural schematic diagram of the array substrate provided in an embodiment of the present application. Among them, the first flat layer 260 can be arranged on the same layer as the first light shielding layer 230 and the second light shielding layer 240 on the conductive film layer 220, and the sum of the orthographic projection areas of the first light shielding layer 230, the second light shielding layer 240 and the first flat layer 260 on the substrate 210 can be less than or equal to the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. It can be understood that the first flat layer 260 is arranged corresponding to the third light shielding layer 250, which can block the electrical connection between the third light shielding layer 250 and the conductive film layer 220 to avoid the occurrence of a short circuit. Therefore, the first flat layer 260 is arranged at a position corresponding to the third light shielding layer 250, so that the sum of the orthographic projection areas of the first light shielding layer 230, the second light shielding layer 240 and the first flat layer 260 on the substrate 210 is less than the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. In addition, since other metal traces are arranged on the same layer as the first light-shielding layer 230, the second light-shielding layer 240 and the third light-shielding layer 250, in order to avoid short circuit caused by direct contact between the conductive film layer 220 and other metal traces, the first flat layer 260 can be set in other remaining areas on the same layer as the first light-shielding layer 230 and the second light-shielding layer 240. Then, the sum of the orthographic projection areas of the first light-shielding layer 230, the second light-shielding layer 240 and the first flat layer 260 on the substrate 210 is equal to the orthographic projection area of ​​the conductive film layer 220 on the substrate 210, so that the first flat layer 260 plays a good insulating role and further improves the quality of the product.

[0054] Also, please continue to read Figure 3 and Figure 5 The base substrate 200 may further include a gate insulating layer 270 and a second planarizing layer 280. The gate insulating layer 270 may be disposed on the conductive film layer 220, and the gate insulating layer 270 covers the first light shielding layer 230, the second light shielding layer 240, the third light shielding layer 250 and the first planarizing layer 260. The second planarizing layer 280 may be disposed on the gate insulating layer 270.

[0055] See also Figure 6 , Figure 6This is a fourth structural schematic diagram of the array substrate provided by the embodiment of the present application. In order to avoid a short circuit caused by direct contact between the third light shielding layer 250 and the conductive film layer 220, a groove 50 may be provided on the side of the conductive film layer 220 away from the substrate 210, and the orthographic projection area of ​​the third light shielding layer 250 on the substrate 210 is located within the orthographic projection area of ​​the groove 50 on the substrate 210, so that the third light shielding layer 250 and the conductive film layer 220 are spaced apart by the groove 50 to avoid a short circuit. It is understandable that the groove 50 may be filled with an insulating material to support the third light shielding layer 250 through the insulating material, thereby ensuring that the third light shielding layer 250 can be provided in the area corresponding to the groove 50.

[0056] It should be noted that the first light shielding layer 230 and the second light shielding layer 240 can be respectively arranged on both sides of the third light shielding layer 250, that is, the third light shielding layer 250 is arranged between the first light shielding layer 230 and the second light shielding layer 240, then the groove 50 arranged on the conductive film layer 220 is also arranged between the first light shielding layer 230 and the second light shielding layer 240. However, in order to realize the electrical connection between the first light shielding layer 230 and the second light shielding layer 240 through the conductive film layer 220, the depth of the groove 50 needs to be less than the thickness of the conductive film layer 220, so as to ensure that the position corresponding to the groove 50 has at least a part of the conductive film layer 220 for realizing the electrical connection between the first light shielding layer 230 and the second light shielding layer 240.

[0057] As can be seen from the above, in this embodiment, the electrical connection between the first light-shielding layer 230 and the second light-shielding layer 240 is not achieved by metal wiring. Instead, the electrical connection between the two is achieved by direct contact between the first light-shielding layer 230 and the second light-shielding layer 240 and the conductive film layer 220. Since the conductive film layer 220 and the first light-shielding layer 230 and the second light-shielding layer 240 are not in the same layer, the short-circuit problem caused by the first light-shielding layer 230 and the second light-shielding layer 240 being connected by metal wiring in the same layer and the metal wiring controlling other signals in the same layer is avoided, thereby improving product quality.

[0058] In addition, by directly electrically connecting the plurality of first light shielding layers 230 and the plurality of second light shielding layers 240 corresponding to the plurality of pixel units in the array substrate 200 to the conductive film layer 220, the metal wirings drawn out for connecting the plurality of external chips are reduced, thereby reducing the output signal. Furthermore, by arranging the first flat layer 260 between the third light shielding layer 250 and the conductive film layer 220 or arranging the groove 50 on the conductive film layer 220 to block the electrical connection between the two, a short circuit between the third light shielding layer 250 and the conductive film layer 220 is avoided, thereby further improving the product quality.

[0059] Accordingly, the present application also provides a method for preparing an array substrate. Figure 7 , Figure 7 : is a schematic flow chart of a method for preparing an array substrate provided in an embodiment of the present application. The method for preparing an array substrate may include the following steps:

[0060] 301, providing a substrate.

[0061] In this embodiment, the substrate 210 may be a glass substrate or the like.

[0062] 302, forming a conductive film layer on a substrate.

[0063] The conductive film layer 220 can be formed on the substrate 210 by deposition. Specifically, the conductive film layer 220 can be formed on the substrate 210 on the entire surface, that is, the area of ​​the conductive film layer 220 is the same as the area of ​​the substrate 210. The conductive film layer 220 can be made of a conductive material, such as indium tin oxide, etc. Therefore, the conductive film layer 220 can be used as a common electrode, and the conductive film layer 220 can form a common electrode on the entire surface of the substrate 210. The conductive film layer 220 can be connected to the common voltage input terminal located in the peripheral area of ​​the array substrate 200, so that the conductive film layer 220 obtains a common voltage.

[0064] 303 , forming a first light shielding layer, a second light shielding layer and a third light shielding layer on a side of the conductive film layer away from the substrate.

[0065] Among them, the first light-shielding layer and the second light-shielding layer are located in the orthographic projection area of ​​the conductive film layer in the orthographic projection area of ​​the substrate, and the first light-shielding layer and the second light-shielding layer are both made of conductive materials; the first light-shielding layer 230, the second light-shielding layer 240 and the third light-shielding layer 250 can all be formed on the side of the conductive film layer 220 away from the substrate 210 by deposition, and the first light-shielding layer 230 and the second light-shielding layer 240 can be prepared by the same process. Specifically, a first light-shielding layer 230 and a second light-shielding layer 240 corresponding to each pixel unit in the array substrate 200 can also be prepared by the same process, thereby reducing the preparation process.

[0066] Among them, the first light shielding layer 230 and the second light shielding layer 240 are both made of conductive materials. The first light shielding layer 230 and the second light shielding layer 240 are both arranged in contact with the conductive film layer 220, and the orthographic projection area of ​​the first light shielding layer 230 and the second light shielding layer 240 on the substrate 210 is located within the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. In addition, since the first light shielding layer 230 and the second light shielding layer 240 are both made of conductive materials, the first light shielding layer 230 and the second light shielding layer 240 are both electrically connected to the conductive film layer 220. Since the first light shielding layer 230 and the second light shielding layer 240 are in direct contact with the conductive film layer 220, it is not necessary to set a metal wiring between the first light shielding layer 230 and the second light shielding layer 240 and the conductive film layer 220 to realize the electrical connection between the first light shielding layer 230 and the second light shielding layer 240 and the conductive film layer 220, thereby realizing the electrical connection between the first light shielding layer 230 and the second light shielding layer 240 through the conductive film layer 220.

[0067] It should be noted that the array substrate 200 includes an array device layer, and the array device layer includes a plurality of pixel units, and each pixel unit may include three thin film transistors, namely a first thin film transistor, a second thin film transistor, and a third thin film transistor. In order to shield each thin film transistor from light, a light shielding layer is correspondingly arranged under each thin film transistor. Specifically, the first thin film transistor is arranged correspondingly to the first light shielding layer 230, and the first light shielding layer 230 is located between the substrate 210 and the first thin film transistor, and the first light shielding layer 230 shields the first thin film transistor; the second thin film transistor is arranged correspondingly to the second light shielding layer 240, and the second light shielding layer 240 is located between the substrate 210 and the second thin film transistor, and the second light shielding layer 240 shields the second thin film transistor; the third thin film transistor is arranged correspondingly to the third light shielding layer 250, and the third light shielding layer 250 is located between the substrate 210 and the third thin film transistor, and the third light shielding layer 250 shields the third thin film transistor.

[0068] It should be noted that, since the array device layer of the array substrate 200 includes multiple pixel units, each pixel unit includes a first thin film transistor, a second thin film transistor and a third thin film transistor. In order to achieve light shielding for the thin film transistors, the three thin film transistors of each pixel unit need to be respectively provided with a first light shielding layer 230, a second light shielding layer 240 and a third light shielding layer 250, that is, multiple pixel units are correspondingly provided with multiple first light shielding layers 230, multiple second light shielding layers 240 and multiple third light shielding layers 250, and a first light shielding layer 230 and a second light shielding layer 240 corresponding to a pixel unit are electrically connected through a conductive film layer 220.

[0069] In the array substrate 100 provided by the prior art, a first light shielding layer 130 and a second light shielding layer 140 corresponding to a pixel unit are connected to an external chip through a metal wiring connected thereto, so that there are multiple metal wirings connected thereto during the connection between the two and multiple chips, thereby increasing the output signal of the array substrate 100. In this embodiment, the conductive film layer 220 is disposed on the substrate 210 in its entirety, so that it can be electrically connected to multiple external chips, and the multiple first light shielding layers 230 and the multiple second light shielding layers 240 in the array substrate 200 are directly electrically connected to the conductive film layer 220, so that there is no need to respectively connect the multiple first light shielding layers 230 and the multiple second light shielding layers 240 with multiple chips, and the multiple thin film transistors in the array substrate 200 can control the signals of multiple chips by connecting to the conductive film layer 220, thereby reducing the metal wirings connected thereto, reducing the output signal, and improving the quality of the product.

[0070] In addition, a first planar layer 260 may be formed on the conductive film layer 220. Specifically, the first planar layer 260 may be disposed between the conductive film layer 220 and the third light shielding layer 250, that is, the third light shielding layer 250 may be formed on the first planar layer 260 by deposition, and the first planar layer 260 is an insulating material. It should be noted that the third light shielding layer 250 corresponds to the third thin film transistor, that is, the third light shielding layer 250 shields the third thin film transistor, and the third thin film transistor may be a driving thin film transistor, which is used to connect to the light emitting device in the pixel unit to emit light. Therefore, the third light shielding layer 250 needs to be connected to the source of the third thin film transistor to obtain a given voltage of the light emitting device. Since the conductive film layer 220 is conductive, if the third light shielding layer 250 is in direct contact with the conductive film layer 220, if the given voltage obtained by the third light shielding layer 250 is the same as the common voltage obtained by the conductive film layer 220, it is easy to cause a short circuit.

[0071] Therefore, in order to avoid the short circuit between the third light-shielding layer 250 and the conductive film layer 220, the orthographic projection area of ​​the third light-shielding layer 250 on the substrate 210 can be set within the orthographic projection area of ​​the first flat layer 260 on the substrate 210, so that the first flat layer 260 with insulating properties can block the electrical connection between the third light-shielding layer 250 and the film layer 220.

[0072] See also Figure 3 and Figure 5, wherein the first planar layer 260 may be disposed on the same layer as the first light shielding layer 230 and the second light shielding layer 240 on the conductive film layer 220, and the sum of the orthographic projection areas of the first light shielding layer 230, the second light shielding layer 240 and the first planar layer 260 on the substrate 210 may be less than or equal to the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. It can be understood that the first planar layer 260 is disposed corresponding to the third light shielding layer 250, which can block the electrical connection between the third light shielding layer 250 and the conductive film layer 220 to avoid the occurrence of a short circuit, and therefore the first planar layer 260 is disposed at a position corresponding to the third light shielding layer 250, so that the sum of the orthographic projection areas of the first light shielding layer 230, the second light shielding layer 240 and the first planar layer 260 on the substrate 210 is less than the orthographic projection area of ​​the conductive film layer 220 on the substrate 210. In addition, since other metal traces are arranged on the same layer as the first light-shielding layer 230, the second light-shielding layer 240 and the third light-shielding layer 250, in order to avoid short circuit caused by direct contact between the conductive film layer 220 and other metal traces, the first flat layer 260 can be set in other remaining areas on the same layer as the first light-shielding layer 230 and the second light-shielding layer 240. Then, the sum of the orthographic projection areas of the first light-shielding layer 230, the second light-shielding layer 240 and the first flat layer 260 on the substrate 210 is equal to the orthographic projection area of ​​the conductive film layer 220 on the substrate 210, so that the first flat layer 260 plays a good insulating role and further improves the quality of the product.

[0073] In addition, a gate insulating layer 270 is formed on the conductive film layer 220 by deposition, wherein the gate insulating layer 270 covers the first light shielding layer 230, the second light shielding layer 240, the third light shielding layer 250 and the first planarization layer 260. A second planarization layer 280 is formed on the gate insulating layer 270 by deposition.

[0074] Please continue reading Figure 6 In order to avoid a short circuit caused by direct contact between the third light shielding layer 250 and the conductive film layer 220, a groove 50 may be provided on the side of the conductive film layer 220 away from the substrate 210, and the orthographic projection area of ​​the third light shielding layer 250 on the substrate 210 is located within the orthographic projection area of ​​the groove 50 on the substrate 210, so that the third light shielding layer 250 and the conductive film layer 220 are spaced apart by the groove 50 to avoid a short circuit. It is understandable that the groove 50 may be filled with an insulating material, so that the insulating material supports the third light shielding layer 250, thereby ensuring that the third light shielding layer 250 can be provided in the area corresponding to the groove 50.

[0075] It should be noted that the first light shielding layer 230 and the second light shielding layer 240 can be respectively arranged on both sides of the third light shielding layer 250, that is, the third light shielding layer 250 is arranged between the first light shielding layer 230 and the second light shielding layer 240, then the groove 50 arranged on the conductive film layer 220 is also arranged between the first light shielding layer 230 and the second light shielding layer 240. However, in order to realize the electrical connection between the first light shielding layer 230 and the second light shielding layer 240 through the conductive film layer 220, the depth of the groove 50 needs to be less than the thickness of the conductive film layer 220, so as to ensure that the position corresponding to the groove 50 has at least a part of the conductive film layer 220 for realizing the electrical connection between the first light shielding layer 230 and the second light shielding layer 240.

[0076] 304 , forming an array device layer on the first light shielding layer, the second light shielding layer, and the third light shielding layer.

[0077] A pixel unit in the array device layer of the array substrate 200 includes a first thin film transistor, a second thin film transistor and a third thin film transistor, wherein the first light shading layer 230 is located between the substrate 210 and the first thin film transistor, the second light shading layer 240 is located between the substrate 210 and the second thin film transistor, and the third light shading layer 250 is located between the substrate 210 and the third thin film transistor.

[0078] As can be seen from the above, the embodiment of the present application provides a substrate, forms a conductive film layer on the substrate, forms a first light shielding layer, a second light shielding layer and a third light shielding layer on the side of the conductive film layer away from the substrate, and forms an array device layer on the first light shielding layer, the second light shielding layer and the third light shielding layer. In this embodiment, the electrical connection between the first light shielding layer 230 and the second light shielding layer 240 is not achieved by metal wiring, but the first light shielding layer 230 and the second light shielding layer 240 are directly in contact with the conductive film layer 220 to achieve electrical connection between the two. Since the conductive layer and the first light shielding layer 230 and the second light shielding layer 240 are not in the same layer, the short circuit problem caused by the first light shielding layer 230 and the second light shielding layer 240 being connected by metal wiring in the same layer and the metal wiring controlling other signals in the same layer is avoided, thereby improving product quality.

[0079] In addition, by directly electrically connecting the plurality of first light shielding layers 230 and the plurality of second light shielding layers 240 corresponding to the plurality of pixel units in the array substrate 200 to the conductive film layer 220, the metal wirings drawn out for connecting the plurality of external chips are reduced, thereby reducing the output signal. Furthermore, by arranging the first flat layer 260 between the third light shielding layer 250 and the conductive film layer 220 or arranging the groove 50 on the conductive film layer 220 to block the electrical connection between the two, a short circuit between the third light shielding layer 250 and the conductive film layer 220 is avoided, thereby further improving the product quality.

[0080] The embodiment of the present application further provides a display panel, which includes the array substrate provided in the above embodiment. The display panel may be a full-screen display panel, for example, the display panel may be a wearable device such as a watch or a bracelet, or the display panel may be an electronic device such as a mobile phone or a tablet computer, or the display panel may be a product or component with a display function such as a television, a monitor, a laptop computer, a digital photo frame or a navigator.

[0081] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0082] The array substrate and its preparation method, and the display panel provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A conductive film layer is disposed on the substrate; a first light-shielding layer, a second light-shielding layer and a third light-shielding layer, wherein the first light-shielding layer, the second light-shielding layer and the third light-shielding layer are all arranged on a side of the conductive film layer away from the substrate, the first light-shielding layer and the second light-shielding layer are located within the orthographic projection region of the conductive film layer on the substrate in the orthographic projection region of the substrate, and the first light-shielding layer and the second light-shielding layer are both made of conductor materials; An array device layer, wherein a pixel unit in the array device layer comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, the first light-shielding layer is located between the substrate and the first thin film transistor, the second light-shielding layer is located between the substrate and the second thin film transistor, the third light-shielding layer is located between the substrate and the third thin film transistor, the third light-shielding layer is arranged corresponding to the third thin film transistor, the first light-shielding layer and the second light-shielding layer are both in direct contact with the conductive film layer to realize electrical interconnection, and the third light-shielding layer is insulated from the conductive film layer.

2. The array substrate according to claim 1, characterized in that: The array substrate further includes a first flat layer, which is disposed between the conductive film layer and the third light shielding layer. The third light shielding layer is located in the orthographic projection area of ​​the substrate within the orthographic projection area of ​​the first flat layer.

3. The array substrate according to claim 2, characterized in that: The first planarizing layer is arranged on the same layer as the first light-shielding layer and the second light-shielding layer on the conductive film layer, respectively, and the sum of the orthographic projection areas of the first light-shielding layer, the second light-shielding layer and the first planarizing layer on the substrate is less than or equal to the orthographic projection area of ​​the conductive film layer on the substrate.

4. The array substrate according to claim 1, characterized in that: The conductive film layer is provided with a groove on a side away from the substrate, and the third light shielding layer is located in the orthographic projection area of ​​the substrate where the groove is located.

5. The array substrate according to claim 4, characterized in that: The depth of the groove is less than the thickness of the conductive film layer.

6. The array substrate according to claim 1, characterized in that: The conductive film layer is connected to a common voltage input terminal located in a peripheral area of ​​the array substrate.

7. The array substrate according to any one of claims 1 to 6, characterized in that: The material of the conductive film layer is indium tin oxide.

8. The array substrate according to any one of claims 2 to 3, characterized in that: The array substrate also includes a gate insulating layer and a second flat layer, the gate insulating layer is arranged on the conductive film layer, the gate insulating layer covers the first light shielding layer, the second light shielding layer, the third light shielding layer and the first flat layer, and the second flat layer is arranged on the gate insulating layer.

9. A method for preparing an array substrate, characterized in that: include: providing a substrate; forming a conductive thin film layer on the substrate; A first light shielding layer, a second light shielding layer and a third light shielding layer are formed on the side of the conductive film layer away from the substrate, wherein the first light shielding layer and the second light shielding layer are located within the orthographic projection area of ​​the conductive film layer on the substrate in the orthographic projection area of ​​the substrate, and the first light shielding layer and the second light shielding layer are both made of conductor materials; An array device layer is formed on the first light-shielding layer, the second light-shielding layer and the third light-shielding layer, wherein a pixel unit in the array device layer comprises a first thin film transistor, a second thin film transistor and a third thin film transistor, the first light-shielding layer is located between the substrate and the first thin film transistor, the second light-shielding layer is located between the substrate and the second thin film transistor, the third light-shielding layer is located between the substrate and the third thin film transistor, the third light-shielding layer is arranged corresponding to the third thin film transistor, the first light-shielding layer and the second light-shielding layer are both in direct contact with the conductive thin film layer to realize electrical interconnection, and the third light-shielding layer is insulated from the conductive thin film layer.

10. The method for preparing an array substrate according to claim 9, characterized in that: The method further comprises: A first planar layer is formed on the conductive film layer, wherein the first planar layer is disposed between the conductive film layer and the third light shielding layer, and the third light shielding layer is located within the orthographic projection region of the first planar layer on the substrate.

11. The method for preparing an array substrate according to claim 10, characterized in that: After forming a first light shielding layer, a second light shielding layer and a third light shielding layer on a side of the conductive film layer away from the substrate, the method further comprises: forming a gate insulating layer on the conductive film layer, wherein the gate insulating layer covers the first light shielding layer, the second light shielding layer, the third light shielding layer and the first planarization layer; A second planarization layer is formed on the gate insulating layer.

12. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 8.

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