A driving circuit for reducing switching glitch voltage

Abstract

The present invention provides a driving circuit for reducing switching glitch voltage, comprising: a main driving circuit, connected to a PWM signal, an active switching tube, and a gate of a freewheeling tube, and configured to generate a first clock signal and a second clock signal that do not overlap; a first switchable auxiliary driving module, connected to the gate of the freewheeling tube, a switch node of a switching power supply, and the main driving circuit; a second switchable auxiliary driving module, connected to both the switch node and the main driving circuit; a first auxiliary driving tube, whose gate is connected to the first auxiliary driving circuit and whose drain is connected to the gate of the active switching tube; and a second auxiliary driving tube, whose gate is connected to the second auxiliary driving circuit and whose drain is connected to the gate of the active switching tube. The driving circuit for reducing switching glitch voltage of the present invention changes the number of power tubes used for driving in the circuit by using the switchable auxiliary driving module to turn on and off the auxiliary driving tubes, thereby effectively enhancing or weakening the gate driving capability, controlling the transition of the current change rate, and effectively reducing the overshoot voltage.

Description

Technical Field

[0001] The present invention belongs to the technical field of power management, and in particular relates to a power stage segmented drive control circuit suitable for reducing switch glitch voltage. Background Art

[0002] As more and more switching power supply chips operate at high frequencies, the switching speed is constantly increased to improve work efficiency and reduce dead time. Since chips have many parasitic inductors and capacitors in actual applications, the voltage and current in the circuit will change rapidly during the fast switching of the power tube, which means that the current flowing through the parasitic inductance of the PCB traces is also changing rapidly, which will bring serious reliability issues, especially in high-current applications.

[0003] Take the traditional BOOST circuit as an example, Figure 1 As shown, the switching power supply includes a voltage input terminal VIN that provides an input voltage source, a switching node SW connected to the input source via an energy storage inductor L, and an active switch transistor NSW and a freewheeling transistor PSW, whose drains are connected to the switching node SW. PG is a first clock signal (i.e., the gate voltage of the freewheeling transistor PSW), NG is a second clock signal (i.e., the gate voltage of the active switch transistor NSW), the freewheeling transistor PSW has a body diode D1 connected in parallel therewith, the source of the active switch transistor NSW is grounded via a ground wire, L1 is a first parasitic inductance of a conductor on the ground wire, and the source of the freewheeling transistor PSW is a voltage output terminal VO of the switching power supply. Between the voltage output terminal VO of the switching power supply and ground, there is a second parasitic inductance L2 on a PCB trace connected in series, an output capacitor CO, and an equivalent series resistance Resr. The equivalent series resistance Resr refers to the loss of the output capacitor CO due to its own material and other factors, which is replaced by a resistor. In addition to the above components, the switching power supply also includes a drive circuit and a load. The drive circuit is used to generate the first clock signal PG and the second clock signal NG.

[0004] Common power tube drive circuits such as Figure 2As shown, PWM is a pulse-width modulated signal. The input end of the pulse-width modulated signal PWM is sequentially connected to the first NOR gate H1, the first level shifter circuit LS1, the first inverter F1, the first driver circuit Driver1, and the output end of the first clock signal PG. The first NOR gate H1 is connected to the input end of the pulse-width modulated signal PWM via one of its input ends, the first NOR gate H1 is connected to the first level shifter circuit LS1 via its output end, and the first driver circuit Driver1 is connected to the output end of the first clock signal PG via its output end. Furthermore, the input end of the pulse-width modulated signal PWM is also connected in series with the second inverter F2, the second NOR gate H2, the third inverter F3, the fourth inverter F4, the second driver circuit Driver2, and the output end of the second clock signal NG. The second NOR gate H2 is connected to the second inverter F2 via one of its input ends, the second NOR gate H2 is connected to the third inverter F3 via its output end, and the second driver circuit Driver2 is connected to the output end of the second clock signal NG via its output end. Furthermore, a fifth inverter F5, a sixth inverter F6, and a second delay circuit Delay2 are connected in series between the output of the second clock signal NG and the other input of the first NOR gate H1. Three inverters (i.e., the seventh, eighth, and ninth inverters F7, F8, and F9), a second level shifter circuit LS2, and a first delay circuit Delay1 are connected in series between the output of the first clock signal PG and the other input of the second NOR gate H2. Thus, two non-overlapping clock signals (the first clock signal PG and the second clock signal NG) are generated through the inverters, NOR gates, level shifters (LS1 and LS2, used to switch power supply voltages between modules, a common BOOST circuit with identical input and output logic), delay circuits (Delay1 and Delay2), and driver circuits (Driver1 and Driver2). Non-overlapping clock signals refer to signals that use delays as feedback signals to control switching signals, ensuring that the first clock signal PG and the second clock signal NG do not simultaneously turn on the freewheeling transistor PSW and the active switch transistor NSW (i.e., NG being high and PG being low do not occur simultaneously). Among them, the driving capacity of the driver modules (Driver1 and Driver2) that control the switching speed of the power tube is often controlled by changing the number of parallel inverter tubes. In order to improve efficiency, it is often chosen to increase the switching speed and enhance the driving capacity of the driver tube. Figure 2 and Figure 4 For gate circuits not specially marked, their power supply voltage is the internal power supply voltage VDD. In addition, some marked gate circuits use the gate circuit power supply voltage REG as the power supply voltage to improve the driving capability. This is a common practice in BOOST circuits. The gate circuit power supply voltage REG is generally selected from the higher of the output voltage of the voltage input terminal VIN and the voltage output terminal VO.

[0005] The following combination Figure 1 Detailed analysis Figure 3 Before the active switch NSW is turned off, the energy storage inductor L does not provide current to the load. The current is provided by the output capacitor CO. Therefore, the current flows from the output capacitor CO to the load. The current on the energy storage inductor L flows in the same direction, which is Figure 1 To the right, so the direction of the current on the second parasitic inductor L2 is Figure 1 When the driving capability of the power tube drive circuit is strong, that is, the active switch tube NSW is turned off (when the second clock signal NG changes from high to low) and the freewheeling tube PSW is turned on, the current flow direction of the energy storage inductor L cannot change suddenly due to its own characteristics. The current flows through the body diode D1 of the freewheeling tube PSW, causing the current flowing through the second parasitic inductor L2 to change rapidly from top to bottom, which will continue to produce a rapid voltage increase at the voltage output terminal VO. Since the switch node SW is always higher than the voltage output terminal VO by a tube body diode voltage, this spike voltage will also be superimposed on the switch node SW. Similarly, when the freewheeling transistor PSW is turned off (when the first clock signal PG changes from low to high) and the active switch NSW has not yet turned on, the current flow direction of the energy storage inductor L cannot change suddenly due to its own characteristics. However, at this time, the current path where the freewheeling transistor PSW is located is forced to close and there is no discharge path. Therefore, the current quickly increases the voltage of the switch node SW, charging the output capacitor CO and the load, and the original top-to-bottom current on the second parasitic inductor L2 quickly disappears. Due to the rapid current change of the second parasitic inductor L2, a voltage spike will be generated; the peak value of the voltage spike V spike =V O +V D1 +ΔV spike (V D1 is the body diode voltage of the freewheeling tube PSW, ΔV spike If the overshoot is too large, it will damage the power transistor, and efficiency will not be effectively improved. However, if the driving capability of the driver circuit is reduced to reduce the speed of current change and thus reduce the peak voltage, this method will inevitably reduce the switching speed of the switch, increase the overlap time of the switch, and reduce chip power consumption. Summary of the Invention

[0006] In view of the shortcomings of the traditional driving structure of the switching power supply, the present invention proposes a segmented driving structure that reduces the switching glitch voltage, thereby solving the problem that EMI, power tube withstand voltage and switching efficiency loss cannot be achieved at the same time.

[0007] In order to solve the problems in conventional technology, the present invention provides a driving circuit for reducing switching glitch voltage, which is applicable to a switching power supply having an active switching tube, a freewheeling tube and a switch node, and includes: a main driving circuit, which is connected to the PWM signal, the gates of the active switching tube and the freewheeling tube, and is configured to generate non-overlapping first clock signals and second clock signals with dead zones; a first switchable auxiliary driving module, which is connected to the gate of the freewheeling tube, the switch node of the switching power supply and the main driving circuit; a second switchable auxiliary driving module, which is connected to both the switch node and the main driving circuit; a first auxiliary driving tube, whose gate is connected to the first auxiliary driving circuit and whose drain is connected to the gate of the active switching tube; and a second auxiliary driving tube, whose gate is connected to the second auxiliary driving circuit and whose drain is connected to the gate of the active switching tube.

[0008] The first switchable auxiliary driving module increases or decreases the turn-off speed of the active switching tube of the switching power supply by turning on or off the first auxiliary driving tube, and the second switchable auxiliary driving module increases or decreases the turn-on speed of the active switching tube of the switching power supply by turning on or off the second auxiliary driving tube.

[0009] The first switchable auxiliary drive module is configured to: generate a level for turning off the first auxiliary drive tube when the PWM signal is at a high level; generate a level for turning on the first auxiliary drive tube when the PWM signal is at a low level and the voltage signal of the switch node is lower than the turn-off threshold voltage of the first auxiliary drive tube; generate a level for turning off the first auxiliary drive tube when the PWM signal is at a low level, the voltage signal of the switch node is higher than the turn-off threshold voltage of the first auxiliary drive tube, and the voltage of the first clock signal is higher than the turn-on threshold voltage of the first auxiliary drive tube; generate a level for turning on the first auxiliary drive tube when the PWM signal is at a low level, the voltage signal of the switch node is higher than the turn-off threshold voltage of the first auxiliary drive tube, and the voltage of the first clock signal is lower than the turn-on threshold voltage of the first auxiliary drive tube.

[0010] The turn-on threshold voltage of the first auxiliary driving transistor is the same as the turn-off threshold voltage of the first auxiliary driving transistor.

[0011] The first switchable auxiliary drive module includes: a first detection circuit, which is connected to the gate of the freewheeling tube and the main drive circuit; a third detection circuit, which is connected to the switch node of the switching power supply; and a first auxiliary drive circuit, wherein the first auxiliary drive circuit is connected to the output end of the first detection circuit, the output end of the third detection circuit and the main drive circuit.

[0012] The first detection circuit includes a first latch, one input end of the first latch is connected to the main driving circuit, and the other input end is connected to the gate of the freewheeling tube through a tenth inverter, an eleventh inverter and a twelfth inverter connected in series in sequence; the threshold voltage V GS_N2is the threshold voltage for turning on the first auxiliary driving tube; the third detection circuit includes a sixteenth inverter and a seventeenth inverter connected in series; the threshold voltage V GS_N3 The first auxiliary drive tube is turned off at a threshold voltage; and the first auxiliary drive circuit includes: a second latch, two input ends of the second latch are respectively connected to the output end of the third detection circuit and the output end of the second NOR gate; a third NOR gate, two input ends of the third NOR gate are respectively connected to the output end of the second latch and the output end of the second NOR gate; a fourth NOR gate, two input ends of the fourth NOR gate are respectively connected to the output end of the first detection circuit and the output end of the third NOR gate; and an eighteenth inverter, a nineteenth inverter, a twentieth inverter connected in series with the fourth NOR gate.

[0013] The second switchable auxiliary drive module is configured to: generate a level for turning off the second auxiliary drive tube when the PWM signal is at a low level; generate a level for turning off the second auxiliary drive tube when the PWM signal is at a high level and the voltage of the switch node is higher than the working threshold voltage of the second auxiliary drive tube; generate a level for turning on the second auxiliary drive tube when the PWM signal is at a high level and the voltage of the switch node is lower than the working threshold voltage of the second auxiliary drive tube.

[0014] The second switchable auxiliary driving module includes: a second detection circuit connected to the switch node of the switching power supply; and a second auxiliary driving circuit connected to both the output end of the second detection circuit and the main driving circuit.

[0015] The second detection circuit includes a thirteenth inverter, a fourteenth inverter, a fifteenth inverter and a third level conversion circuit connected in series in sequence; the threshold voltage V REG -V GS_P1 is the working threshold voltage of the second auxiliary driving tube; the second auxiliary driving circuit includes a twenty-first inverter connected to the output end of the second NOR gate, a third latch whose two input ends are respectively connected to the twenty-first inverter and the output end of the first detection circuit, a first NAND gate whose two input ends are respectively connected to the output end of the second NOR gate and the output end of the third latch, a twenty-second inverter and a twenty-third inverter connected in series with the output end of the first NAND gate.

[0016] The main drive circuit includes: a first NOR gate, a first level shifting circuit, a first inverter, a first drive circuit, and an output terminal of a first clock signal, connected in series from an input terminal of a PWM signal, wherein the first NOR gate is connected to the input terminal of the PWM signal via one of its input terminals and is connected to the first level shifting circuit via its output terminal; a second inverter, a second NOR gate, a third inverter, a fourth inverter, the second drive circuit, and an output terminal of a second clock signal, connected in series from the input terminal of the PWM signal, wherein the second NOR gate is connected to the second inverter via one of its input terminals and is connected to the third inverter via its output terminal; a fifth inverter, a sixth inverter, and a second delay circuit connected in series in sequence, which are arranged between the output terminal of the second clock signal and the other input terminal of the first NOR gate; and a seventh inverter, an eighth inverter, a ninth inverter, a second level shifting circuit, and a first delay circuit connected in series in sequence, which are arranged between the output terminal of the first clock signal and the other input terminal of the second NOR gate. The main drive circuit is connected to the first switchable auxiliary drive module and the second switchable auxiliary drive module via the output terminal of its second NOR gate.

[0017] The driving circuit for reducing switching glitch voltage of the present invention changes the number of power tubes used for driving in the circuit by using a first switchable auxiliary driving module and a second switchable auxiliary driving module to turn on and off the auxiliary driving tubes, thereby effectively enhancing or weakening the gate driving capability, controlling the transition of the current change rate, and effectively reducing the overshoot voltage.

[0018] In addition, the switchable auxiliary drive module of the drive circuit for reducing the switching glitch voltage of the present invention controls the active switch tube by detecting the gate voltage of the freewheeling tube and the voltage of the switch node, thereby reducing the switching glitch voltage; reducing the switching loss generated during the switching process, improving the working efficiency of the switching power supply, and at the same time enhancing the safe operating area (SOA) of the chip during operation; and reducing EMI on the switching power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural diagram of a traditional DC-DC boost switching power supply.

[0020] Figure 2 This is a circuit diagram of a common power tube drive circuit in a switching power supply.

[0021] Figure 3 It is a voltage waveform diagram of each node during the working cycle of the switching power supply in the existing traditional technology.

[0022] Figure 4 The present invention is a schematic diagram of the circuit structure of a driving circuit for reducing switch glitch voltage.

[0023] Figure 5 Yes Figure 1The switching power supply shown is a voltage waveform diagram of each node when the switching power supply is operated by adopting the driving circuit for reducing the switching glitch voltage of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, scheme and advantages of the present invention more clear, the detailed working principle and state of the preferred embodiment of the present invention are described in more detail below with reference to the accompanying drawings. The embodiments mentioned are only used to explain the present invention and are not limited to the present embodiments, nor are they used to limit the scope of application of the present invention.

[0025] The following content is intended to enable the public to have a clearer understanding of the present invention. For those working in the relevant field, the present invention can be clearly understood even without the following detailed description.

[0026] The driving circuit for reducing the switch glitch voltage of the present invention is suitable for Figure 1 The switching power supply shown in FIG. Figure 1 As shown, the switching power supply includes a voltage input terminal VIN for providing an input voltage source, a switching node SW connected to the input source via an energy storage inductor L, and an active switch transistor NSW and a freewheeling transistor PSW, whose drains are connected to the switching node SW. The active switch transistor NSW is an NMOS power transistor, and the freewheeling transistor PSW is a PMOS power transistor. PG is a first clock signal (i.e., the gate voltage of the freewheeling transistor PSW), and NG is a second clock signal (i.e., the gate voltage of the active switch transistor NSW). The freewheeling transistor PSW has a body diode D1. The source of the active switch transistor NSW is grounded via a ground wire. L1 is the parasitic inductance of the conductor on the ground wire. The source of the freewheeling transistor PSW is the voltage output terminal VO of the switching power supply. Between the voltage output terminal VO of the switching power supply and ground are connected in series: an energy storage inductor L2 on a PCB trace, an output capacitor CO, and an equivalent series resistance Resr of the output capacitor CO. The equivalent series resistance Resr refers to the loss of the output capacitor CO due to its own material and other factors, which is replaced by a resistor. In addition, the switching power supply also includes a drive circuit and a load in addition to the above parts. The drive circuit for reducing the switching glitch voltage of the present invention is used to generate Figure 1 The switching power supply shown has a first clock signal PG and a second clock signal NG.

[0027] like Figure 4As shown, the driving circuit for reducing switching glitch voltage of the present invention improves upon the conventional driving circuit by designing a segmented driving structure. The driving circuit for reducing switching glitch voltage includes: a main driving circuit 100 connected to a PWM signal and the gates of an active switching transistor NSW and a freewheeling transistor PSW of a switching power supply; a first detection circuit 10 connected to the gate of the freewheeling transistor PSW and the main driving circuit 100; a second detection circuit 20 and a third detection circuit 30 connected to a switch node SW of the switching power supply; a first auxiliary driving circuit MDN1 connected to the output of the first detection circuit 10, the output of the third detection circuit 30, and the main driving circuit 100; a second auxiliary driving circuit MDN2 connected to the output of the second detection circuit 20 and the main driving circuit 100; a first auxiliary driving transistor NDN1 having a gate connected to the first auxiliary driving circuit MDN1 and a drain connected to the gate of the active switching transistor NSW; and a second auxiliary driving transistor PDN2 having a gate connected to the second auxiliary driving circuit MDN2 and a drain connected to the gate of the active switching transistor NSW.

[0028] like Figure 4 As shown in the dotted box, the main driving circuit 100 is based on the existing power tube driving circuit. Figure 2 The power transistor driver circuit shown in the figure shares the same architecture, configured to convert a PWM signal into two non-overlapping clock signals with dead zones: a first clock signal PG and a second clock signal NG. The pulse-width modulated signal PWM drives the active switching transistor NSW and the freewheeling transistor PSW via a NOR gate, an inverter, a level shifter module LS2, and a driver. The first clock signal PG and the second clock signal NG are then fed back to the input of the NOR gate via an inverter, a level shifter circuit, and delay modules Delay1 / Delay2, respectively, to create the dead zone.

[0029] As described above, the main driver circuit 100 includes a first NOR gate H1, a first level shifter circuit LS1, a first inverter F1, a first driver circuit Driver1, and an output terminal of a first clock signal PG, which are connected in series from the input terminal of the pulse-width modulation signal PWM. The first NOR gate H1 is connected to the input terminal of the pulse-width modulation signal PWM via one of its input terminals, and is connected to the first level shifter circuit LS1 via its output terminal. The first driver circuit Driver1 is connected to the output terminal of the first clock signal PG via its output terminal. Furthermore, the main driver circuit 100 also includes a second inverter F2, a second NOR gate H2, a third inverter F3, a fourth inverter F4, a second driver circuit Driver2, and an output terminal of a second clock signal NG, which are connected in series from the input terminal of the pulse-width modulation signal PWM. The second NOR gate H2 is connected to the second inverter F2 via one of its input terminals, and is connected to the third inverter F3 via its output terminal. The second driver circuit Driver2 is connected to the output terminal of the second clock signal NG via its output terminal. In addition, a fifth inverter F5, a sixth inverter F6, and a second delay circuit Delay2 are connected in series between the output terminal of the second clock signal NG and the other input terminal of the first NOR gate H1; a seventh, eighth, and ninth inverter F7, F8, and F9, a second level shifter circuit LS2, and a first delay circuit Delay1 are connected in series between the output terminal of the first clock signal PG and the other input terminal of the second NOR gate H2. The fifth inverter F5 is composed of two PMOS transistors and one NMOS transistor with a common gate, and its threshold voltage is V GS_N5 The seventh inverter F7 consists of a PMOS transistor and two NMOS transistors with a common gate, and its threshold voltage is V REG -V GS_P4 , V REG is the gate circuit power supply voltage REG.

[0030] Therefore, the main driving circuit 100 has a signal output end for a first clock signal PG and a signal output end for a second clock signal NG. The signal output end for the first clock signal PG is connected to the freewheeling tube PSW, and the signal output end for the second clock signal NG is connected to the active switch tube NSW.

[0031] The input end of the first detection circuit 10 is respectively connected to the gate of the freewheeling tube PSW and the output end of the second NOR gate H2 of the main drive circuit 100. It is used to detect the gate voltage of the freewheeling tube PSW (that is, the first clock signal PG). It is configured to generate a first detection signal Net1 based on the first clock signal PG and the output of the second NOR gate H2.

[0032] Specifically, the first detection circuit 10 includes a first latch J1, one input end of which is connected to the output end of the second NOR gate H2, and the other input end of which is connected to the gate of the freewheeling transistor PSW through three inverters connected in series (i.e., the tenth inverter F10, the eleventh inverter F11, and the twelfth inverter F12 connected in series). The tenth inverter F10 is composed of two PMOS transistors and one NMOS transistor with a common gate, and its threshold voltage is V GS_N2 .

[0033] The second detection circuit 20 is configured to generate a second detection signal Net2 based on the voltage of the switch node SW. The second detection circuit 20 includes a thirteenth inverter F13, a fourteenth inverter F14, a fifteenth inverter F15, and a third level shifter circuit LS3 connected in series. The thirteenth inverter F13 is composed of a PMOS transistor and two NMOS transistors with a common gate, and its threshold voltage is V REG -V GS_P1 .

[0034] The third detection circuit 30 is configured to generate a third detection signal Net5 according to the voltage of the switch node SW. The third detection circuit 30 includes a sixteenth inverter F16 and a seventeenth inverter F17 connected in series. The sixteenth inverter F16 is composed of two PMOS transistors and one NMOS transistor, and its threshold voltage is V GS_N3 .

[0035] The first auxiliary drive circuit MDN1 has three input terminals, each of which is connected to the output terminal of the first detection circuit 10, the output terminal of the third detection circuit 30, and the output terminal of the second NOR gate H2 of the main drive circuit 100. The first auxiliary drive circuit MDN1 is configured to generate a first auxiliary drive signal DN1 based on the first detection signal Net1, the third detection signal Net5, and the output of the second NOR gate H2. The first auxiliary drive circuit MDN1, the first detection circuit 10, and the third detection circuit 30 constitute a first switchable auxiliary drive module. This first switchable auxiliary drive module is connected to the gate of the freewheeling transistor PSW, the switch node SW of the switching power supply, and the main drive circuit 100. The first auxiliary drive circuit MDN1 switches the first auxiliary drive transistor NDN1 on and off to increase or decrease the turn-off speed of the active switch transistor NSW of the switching power supply.

[0036] Among them, the first sub-drive circuit MDN1 includes a second latch J2 whose two input ends are respectively connected to the output end of the third detection circuit 30 and the output end of the second NOR gate H2, a third NOR gate H3 whose two input ends are respectively connected to the output end of the second latch J2 and the output end of the second NOR gate H2, a fourth NOR gate H3 whose two input ends are respectively connected to the output end of the first detection circuit 10 and the output end of the third NOR gate H3, and an eighteenth inverter F18, a nineteenth inverter F19 and a twentieth inverter F20 which are connected in series with the fourth NOR gate H3.

[0037] The second auxiliary drive circuit MDN2 has three input terminals, each of which is connected to the output of the second detection circuit 20 and the output of the second NOR gate H2 of the main drive circuit 100. The second auxiliary drive circuit MDN2 is configured to generate a second auxiliary drive signal DN2 based on the second detection signal Net2 and the output of the second NOR gate H2. The second auxiliary drive circuit MDN2 and the second detection circuit 20 form a second switchable auxiliary drive module, which is connected to both the switching node SW of the switching power supply and the main drive circuit 100. This module increases or decreases the turn-on speed of the active switch NSW of the switching power supply by turning on and off the second auxiliary drive transistor PDN2 through its second auxiliary drive circuit MDN2.

[0038] Among them, the second sub-drive circuit MDN2 includes a twenty-first inverter F21 connected to the output end of the second NOR gate H2, a third latch J3 whose two input ends are respectively connected to the twenty-first inverter F21 and the output end of the first detection circuit 10, a first NAND gate Y1 whose two input ends are respectively connected to the output end of the second NOR gate H2 and the output end of the third latch J3, a twenty-second inverter F22 and a twenty-third inverter F23 connected in series with the output end of the first NAND gate Y1.

[0039] The three latches (first, second and third latches J1, J2 and J3) inserted in the above circuit are latches composed of NOR gates, which are used to lock the current state to prevent repeated switching during logic control and cause oscillation.

[0040] It should be noted that Figure 4 The main purpose is to describe the driving circuit of the switching power supply. Other peripheral components are not drawn. In the periphery, the switch node SW is connected to an energy storage inductor, and the other end of the inductor is connected to the voltage input terminal VIN, which is the same as the structure of the traditional switching power supply. The present invention also requires the voltage input terminal VIN. Figure 4 Not drawn in detail.

[0041] The following combination Figure 4 The working principle of the driving circuit for reducing the switching glitch voltage of the present invention is described in detail.

[0042] The driving circuit for reducing switching glitch voltage of the present invention changes the number of power tubes used for driving in the circuit by using the first auxiliary driving signal DN1 and the second auxiliary driving signal DN2 to turn on and off the auxiliary driving tubes, thereby effectively enhancing or weakening the gate driving capability, controlling the transition of the current change rate, and effectively reducing the overshoot voltage.

[0043] While reducing the overshoot voltage, the segmented drive controls the auxiliary drive circuit and the auxiliary drive tube by sampling the voltage change of the switch node SW and the gate voltage change of the freewheeling tube PSW, effectively reducing power loss.

[0044] During the conduction phase of the active switch NSW: the main drive circuit 100 operates normally, the first clock signal NG is high, the second auxiliary drive transistor PDN2 does not operate first, and the active switch NSW operates in a weak drive state, which does not cause a large overshoot; when the second detection circuit 20 of the second switchable auxiliary drive module samples that the voltage of the switch node SW has dropped to a second auxiliary drive transistor operating threshold voltage, the second auxiliary drive transistor PDN2 operates in a strong drive state to reduce power consumption. The operating threshold voltage of the second auxiliary drive transistor is the threshold voltage V of the thirteenth inverter F13. REG -V GS_P1 , V GS_P1 Indicates the gate-source voltage of the PMOS tube.

[0045] Active switch NSW is turned off: the main drive circuit 100 operates normally, the first clock signal NG is low, the first auxiliary drive tube NDN1 operates first, and the active switch NSW operates in a strong drive state; when the third detection circuit 30 of the first switchable auxiliary drive module detects that the voltage of the switch node SW rises to a first auxiliary drive tube turn-off threshold voltage (i.e., the threshold voltage V GS_N3 ), the first auxiliary drive transistor NDN1 is turned off and does not work, and the driving capability is weakened to avoid overshoot voltage. When the first detection circuit 10 of the first switchable auxiliary drive module detects that the voltage of the first clock signal PG is reduced to a first auxiliary drive transistor turn-on threshold voltage (i.e., the threshold voltage V GS_N2 ), it is about to be fully opened. At this time, the first auxiliary driving tube NDN1 starts to work again to enhance the driving capability to prevent the voltage of the first clock signal PG from being coupled high by the voltage of the switch node SW.

[0046] The first auxiliary driving tube turn-off threshold voltage of the switch node SW when the first auxiliary driving tube NDN1 starts working is equal to the first auxiliary driving tube turn-on threshold voltage of the first clock signal PG when the first auxiliary driving tube NDN1 switches to non-working, that is, V GS_N2 =V GS_N3 , represents the gate-source voltage of the NMOS tube.

[0047] The circuit for sampling the SW and PG voltages described above is mainly composed of inverters with different thresholds, so as to detect different voltage flip points. As mentioned above, the threshold voltage of the thirteenth inverter F13 of the second detection circuit 20 is V REG -V GS_P1 , the threshold voltage of the seventh inverter F7 of the main driving circuit 100 is V REG -V GS_P4 , the threshold voltage of the tenth inverter F10 of the first detection circuit 10 is V GS_N2 , the threshold voltage of the sixteenth inverter F16 of the third detection circuit 30 is V GS_N3 , the threshold voltage of the fifth inverter F5 of the main driving circuit 100 is V GS_N5 .

[0048] The structure of the driving circuit for reducing switching glitch voltage of the present invention has the following advantages compared with the traditional structure: improved reliability. The traditional structure increases the switching speed to reduce power consumption, which leads to a large overshoot voltage. If the overshoot is to be reduced, the switching speed must be reduced and the power loss is increased. It is difficult to have both. The present invention adds a structure for switching between strong and weak driving capabilities on the basis of the traditional structure. The segmented driving structure neither generates a large overshoot peak voltage due to excessively fast switching speed nor generates a large power loss due to excessively long switching time, thereby significantly improving chip reliability and power.

[0049] In this embodiment, when the active switch NSW is turned on, the PWM signal is at a high level. After passing through the logic gate circuit, the gate voltage of the freewheeling tube PSW is first high. At this time, the feedback voltage sampling PG voltage is fed back to the input end of the second NOR gate H2. When the first clock signal PG voltage rises to the threshold voltage V REG -V GS_P4 When (V GS_P4 represents a threshold voltage of the PMOS tube), the threshold voltage of the seventh inverter is a relatively high threshold voltage, and the input voltage transmitted to the second NOR gate H2 is a low level. At this time, the output of the second NOR gate H2 is high, and the main driving circuit 100 outputs a high level to control the active switch tube NSW to turn on. This process is to prevent the active switch tube NSW and the freewheeling tube PSW from being turned on at the same time.

[0050] Since the previous state of the output of the second NOR gate H2 is low, the second auxiliary drive signal DN2 is high, and the pull-up auxiliary drive tube (i.e., the second auxiliary drive tube PDN2) does not work. At this time, when the output of the second NOR gate H2 becomes high, due to the existence of the third latch J3, the second auxiliary drive signal DN2 maintains the previous state (i.e., the second auxiliary drive signal DN2 is high). When the voltage of the switch node SW drops to the working threshold voltage of the second auxiliary drive tube (i.e., the threshold voltage VREG -V GS_P1 ), the second detection signal Net2 is high, so the second auxiliary driving signal DN2 becomes low, the second auxiliary driving tube PDN2 is activated, and the conduction speed of the active switch tube NSW is increased.

[0051] Therefore, the conduction process of the active switch tube NSW is driven in segments. In the front section of NSW conduction, a weak drive is used to drive the power tube, which reduces the conduction speed of the switch and reduces the overshoot peak voltage. In the latter section, the voltage value of the switch node SW is judged to convert the weak drive into a strong drive, thereby reducing the conduction loss.

[0052] Similarly, when the active switch NSW is turned off, the PWM signal is low, the output of the second NOR gate H2 is low, and the second clock signal NG output by the main drive circuit 100 is converted to a low level to turn off the gate voltage. When the level of the second clock signal NG drops below the threshold voltage V GS_N5 When (V GS_N5 Represents a threshold voltage of NMOS). This threshold voltage is a relatively low threshold voltage. After a delay, the voltage transmitted to the input end of the first NOR gate H1 is low. Since the PWM signal is low, the output of the first NOR gate H1 is low, and the voltage of the first clock signal PG becomes low. This process is also used as the dead time.

[0053] Before this, when the second clock signal NG starts to go low, the output of the second NOR gate H2 is high due to the change of the previous state. The first detection signal Net1 is activated by the first latch J1 when the voltage of the first clock signal PG drops to the threshold voltage V of the tenth inverter F10. GS_N2 When the voltage is below 1, it is always low, and the signal Net3 is also low; the signal Net4 is low, and the first auxiliary drive signal DN1 is low. That is, when the second clock signal NG is high, the first auxiliary drive transistor NDN1 must not work.

[0054] When PWM becomes low, the output of the second NOR gate H2 becomes low, the signal Net4 remains unchanged under the action of the second latch J2, the signal Net3 becomes high, the first auxiliary drive signal DN1 is high, the pull-down drive (i.e., the first auxiliary drive tube NDN1) is strongly driven, and as the active switch tube NSW is turned off, the voltage of the switch node SW gradually rises. When the voltage rises to the first auxiliary drive tube turn-off threshold voltage (i.e., the threshold voltage V GS_N3 ) voltage, the third detection signal Net5 becomes high, Net4 is high, and Net3 is low, so the first auxiliary drive signal DN1 becomes low. At this time, the driving capability is weakened, the speed of change of the power tube current slows down, and the overshoot peak voltage at the SW end is also reduced.

[0055] When the voltage of the first clock signal PG drops to the first auxiliary driving transistor opening threshold voltage (i.e., the threshold voltage V GS_N2 ), it indicates that the freewheeling tube PSW is about to be fully turned on, the first detection signal Net1 becomes high, DN1 becomes high, the driving capability returns to strong driving, and the gate voltage of the NSW end is pulled up and shut down.

[0056] refer to Figure 5 As shown in FIG, the voltage waveform of each node when the switching power supply is working after adopting the segmented driving structure proposed by the present invention is shown. Figure 3 , it can be clearly seen that the improved present invention has advantages in reliability.

[0057] Combine Figure 5 Analysis shows that at time t1, the PWM signal switches from low level to high level. At this time, the first clock signal PG starts to become high level, DN1 becomes low level, and DN2 is high level.

[0058] At time t2, due to the dead zone, the second clock signal NG has to go through a delay of Delay1 at one end and starts to rise at time t2;

[0059] At time t3, it is detected that the voltage signal of the switch node SW drops to the working threshold voltage of the second auxiliary drive tube (that is, the threshold voltage V REG -V GS_P1 ) below, the DN2 signal becomes low, enhancing the driving capability of the active switch NSW. Previously, it worked in a weak driving state and did not generate a large overshoot voltage.

[0060] At time t4, the PWM signal becomes low, and the second clock signal NG begins to decrease. DN2 is high, the pull-up tube (i.e., the second auxiliary drive tube PDN2) is turned off, and DN1 becomes high. The first auxiliary drive tube NDN1 is turned on to enter the strong drive stage, reducing power consumption.

[0061] At time t5, it is detected that the voltage signal of the switch node SW rises to a threshold voltage (V GS_N3 ), DN1 changes to low level and enters weak drive state, which reduces the current change speed and overshoot voltage;

[0062] At time t6, the first clock signal PG starts to become low after a dead time Delay2;

[0063] At time t7, it is detected that the first clock signal PG drops to the threshold voltage (V GS_N2 ) below, DN1 becomes high again and enters the strong drive state.

[0064] That is to say,

[0065] The first switchable auxiliary drive module is configured as:

[0066] When the PWM signal is at a high level, a level is generated to turn off the first auxiliary driving tube NDN1;

[0067] When the PWM signal is at a low level and the voltage signal of the switch node SW is lower than the turn-off threshold voltage of the first auxiliary driving tube, a level for turning on the first auxiliary driving tube NDN1 is generated;

[0068] When the PWM signal is at a low level, the voltage signal of the switch node SW is higher than the turn-off threshold voltage of the first auxiliary driver transistor, and the voltage of the first clock signal PG is higher than the turn-on threshold voltage of the first auxiliary driver transistor, a level is generated to turn off the first auxiliary driver transistor NDN1;

[0069] When the PWM signal is low, the voltage signal of the switch node SW is higher than the first auxiliary driving tube turn-off threshold voltage, and the voltage of the first clock signal PG is lower than the first auxiliary driving tube turn-on threshold voltage, a level is generated to turn on the first auxiliary driving tube NDN1.

[0070] The second switchable auxiliary drive module is configured as:

[0071] When the PWM signal is at a low level, a level is generated to turn off the second auxiliary driving tube PDN2;

[0072] When the PWM signal is at a high level and the voltage of the switch node SW is higher than the working threshold voltage of the second auxiliary driving tube, a level is generated to turn off the second auxiliary driving tube PDN2;

[0073] When the PWM signal is at a high level and the voltage of the switch node SW is lower than the operating threshold voltage of the second auxiliary driving tube, a level for turning on the second auxiliary driving tube PDN2 is generated.

[0074] The above is a schematic diagram of waveforms of various nodes of the segmented driving circuit proposed in the present invention within a switching cycle at various time stages.

[0075] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Various modifications are possible. In other words, any simple, equivalent changes and modifications made in accordance with the claims and description of the present invention are within the scope of protection of the patent claims. Anything not fully described in this invention constitutes conventional technology.

Claims

1. A driving circuit for reducing switching glitch voltage, which is applicable to a switching power supply having an active switch tube (NSW), a freewheeling tube (PSW) and a switch node (SW), characterized in that: include: A main driving circuit (100) is connected to the PWM signal, the gate of the active switch tube (NSW) and the freewheeling tube (PSW), and is configured to generate a non-overlapping first clock signal (PG) and a second clock signal (NG) with a dead zone; A first switchable auxiliary driving module, which is connected to the gate of the freewheeling tube (PSW), the switch node (SW) of the switching power supply and the main driving circuit (100); a second switchable auxiliary driving module connected to both the switch node (SW) and the main driving circuit (100); a first auxiliary driving transistor (NDN1), whose gate is connected to the first auxiliary driving circuit (MDN1) and whose drain is connected to the gate of the active switching transistor (NSW); and a second auxiliary driving transistor (PDN2), whose gate is connected to the second auxiliary driving circuit (MDN2) and whose drain is connected to the gate of the active switching transistor (NSW); The first switchable auxiliary drive module is configured as: When the PWM signal is high, it generates a level that turns off the first auxiliary driver tube (NDN1); When the PWM signal is at a low level and the voltage signal of the switch node (SW) is lower than the turn-off threshold voltage of the first auxiliary drive tube, a level for turning on the first auxiliary drive tube (NDN1) is generated; When the PWM signal is at a low level, the voltage signal of the switch node (SW) is higher than the turn-off threshold voltage of the first auxiliary drive tube, and the voltage of the first clock signal (PG) is higher than the turn-on threshold voltage of the first auxiliary drive tube, a level is generated to turn off the first auxiliary drive tube (NDN1); When the PWM signal is at a low level, the voltage signal of the switch node (SW) is higher than the turn-off threshold voltage of the first auxiliary drive tube, and the voltage of the first clock signal (PG) is lower than the turn-on threshold voltage of the first auxiliary drive tube, a level for turning on the first auxiliary drive tube (NDN1) is generated; The first switchable auxiliary drive module includes: A first detection circuit (10) connected to the gate of the freewheeling transistor (PSW) and the main drive circuit (100); a third detection circuit (30) connected to a switch node (SW) of the switching power supply; and a first auxiliary driving circuit (MDN1), the first auxiliary driving circuit (MDN1) being connected to the output end of the first detection circuit (10), the output end of the third detection circuit (30) and the main driving circuit (100); The second switchable auxiliary drive module is configured as: When the PWM signal is at a low level, a level is generated to turn off the second auxiliary driver tube (PDN2); When the PWM signal is high and the voltage of the switch node (SW) is higher than the working threshold voltage of the second auxiliary drive tube, a level is generated to turn off the second auxiliary drive tube (PDN2); When the PWM signal is high and the voltage of the switch node (SW) is lower than the working threshold voltage of the second auxiliary driver tube, a level is generated to turn on the second auxiliary driver tube (PDN2); The second switchable auxiliary drive module includes: a second detection circuit (20) connected to a switch node (SW) of the switching power supply; and The second auxiliary driving circuit (MDN2) is connected to the output end of the first detection circuit (10), the output end of the second detection circuit (20) and the main driving circuit (100).

2. The driving circuit for reducing switching glitch voltage according to claim 1, wherein: The first switchable auxiliary driver module increases or decreases the turn-off speed of the active switch tube (NSW) of the switching power supply by turning on or off the first auxiliary driver tube (NDN1), and the second switchable auxiliary driver module increases or decreases the turn-on speed of the active switch tube (NSW) of the switching power supply by turning on or off the second auxiliary driver tube (PDN2).

3. The driving circuit for reducing switching glitch voltage according to claim 1, wherein: The turn-on threshold voltage of the first auxiliary driving transistor is the same as the turn-off threshold voltage of the first auxiliary driving transistor.

4. The driving circuit for reducing switching glitch voltage according to claim 1, wherein: The first detection circuit (10) comprises a first latch (J1), one input end of the first latch (J1) is connected to the main drive circuit (100), and the other input end is connected to the gate of the freewheeling tube (PSW) via a tenth inverter (F10), an eleventh inverter (F11), and a twelfth inverter (F12) connected in series in sequence; the threshold voltage V GS_N2 A threshold voltage for turning on the first auxiliary driving transistor; The third detection circuit (30) comprises a sixteenth inverter (F16) and a seventeenth inverter (F17) connected in series; a threshold voltage V GS_N3 The first auxiliary driving transistor is turned off at a threshold voltage; The first secondary driving circuit (MDN1) includes: a second latch (J2), wherein two input terminals of the second latch (J2) are respectively connected to the output terminal of the third detection circuit (30) and the output terminal of the second NOR gate (H2); a third NOR gate (H3), wherein two input terminals of the third NOR gate (H3) are respectively connected to the output terminal of the second latch (J2) and the output terminal of the second NOR gate (H2); a fourth NOR gate (H3), wherein two input terminals of the fourth NOR gate (H3) are respectively connected to the output terminal of the first detection circuit (10) and the output terminal of the third NOR gate (H3); and An eighteenth inverter (F18), a nineteenth inverter (F19), and a twentieth inverter (F20) are sequentially connected in series with the fourth NOR gate (H3).

5. The driving circuit for reducing switching glitch voltage according to claim 1, wherein: The second detection circuit (20) comprises a thirteenth inverter (F13), a fourteenth inverter (F14), a fifteenth inverter (F15) and a third level conversion circuit (LS3) connected in series in sequence; the threshold voltage V REG -V GS_P1 is the working threshold voltage of the second auxiliary driving tube; The second auxiliary driving circuit (MDN2) includes a twenty-first inverter (F21) connected to the output end of the second NOR gate (H2), a third latch (J3) whose two input ends are respectively connected to the twenty-first inverter (F21) and the output end of the first detection circuit (10), a first NAND gate (Y1) whose two input ends are respectively connected to the output end of the second NOR gate (H2) and the output end of the third latch (J3), a twenty-second inverter (F22) and a twenty-third inverter (F23) connected in series with the output end of the first NAND gate (Y1).

6. The driving circuit for reducing switching glitch voltage according to claim 1, wherein: The main driving circuit (100) comprises: A first NOR gate (H1), a first level conversion circuit (LS1), a first inverter (F1), a first drive circuit (Driver1), and an output end of a first clock signal (PG) are sequentially connected in series from an input end of a PWM signal, wherein the first NOR gate (H1) is connected to an input end of the PWM signal via one of its input ends and is connected to the first level conversion circuit (LS1) via its output end; a second inverter (F2), a second NOR gate (H2), a third inverter (F3), a fourth inverter (F4), a second drive circuit (Driver2), and an output end of a second clock signal (NG) connected in series from an input end of the PWM signal, wherein the second NOR gate (H2) is connected to the second inverter (F2) via one of its input ends and is connected to the third inverter (F3) via its output end; a fifth inverter (F5), a sixth inverter (F6), and a second delay circuit (Delay2) connected in series, which are arranged between the output terminal of the second clock signal (NG) and the other input terminal of the first NOR gate (H1); and A seventh inverter (F7), an eighth inverter (F8), a ninth inverter (F9), a second level conversion circuit (LS2), and a first delay circuit (Delay1) are sequentially connected in series and are provided between an output end of the first clock signal (PG) and another input end of the second NOR gate (H2); The main driving circuit (100) is connected to the first switchable auxiliary driving module and the second switchable auxiliary driving module via the output end of its second NOR gate (H2).

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