A single-ended input differential output low noise amplifier based on adjustable active inductor

Abstract

The present invention discloses a single-ended input differential output low noise amplifier based on adjustable active inductance, comprising a first resistor, a second resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a coupling capacitor, a first adjustable active inductance and a second adjustable active inductance, wherein the first resistor is connected between a power supply terminal and a drain of the third NMOS tube, the second resistor is connected between a power supply terminal VDD and a drain of the fourth NMOS tube, the drain of the third NMOS tube serves as a first differential voltage output terminal, and the drain of the fourth NMOS tube serves as a second differential voltage output terminal; the first adjustable active inductance is connected between a source of the first NMOS tube and a ground terminal, the second adjustable active inductance is connected between a source of the second NMOS tube and a ground terminal, and the first adjustable active inductance and the second adjustable active inductance can adjust the inductance value according to the frequency of the input voltage. The present invention reduces the internal inductance of the chip through the use of the adjustable active inductance, greatly reduces the area, and reduces the cost.

Description

Technical Field

[0001] The invention belongs to the technical field of radio frequency integrated circuits, and in particular relates to a single-ended input differential output low noise amplifier based on adjustable active inductance. Background Art

[0002] The low noise amplifier is usually the first stage of the receiving system. It needs to provide sufficient gain to reduce the noise contribution of the subsequent modules to the receiver input. In addition, it must also have a very low noise factor, because its noise factor will be reflected 1:1 in the overall noise factor of the receiver. With the rapid development of wireless communication technology, the vision of the Internet of Everything is gradually becoming a reality, which requires more wireless devices to access the Internet, and the demand for low power consumption and high performance is becoming more and more obvious. With the development of technology, the energy consumption of a single transistor is decreasing, the cut-off frequency is getting higher and higher, and the design of high-density integrated CMOS transceiver chips is becoming more mature.

[0003] In the design of traditional low noise amplifiers, on-chip inductors are widely used by designers. On-chip inductors are often used for impedance matching and negative feedback of the source. The increase in CMOS integration makes the design of on-chip inductors more and more difficult. This is because on-chip inductors require wider high-layer metal and more metal turns, which faces great challenges under small processes. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a single-ended input differential output low noise amplifier based on adjustable active inductor. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The present invention provides a single-ended input differential output low noise amplifier based on adjustable active inductance, comprising a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a coupling capacitor C c , the first adjustable active inductor L AI1 And the second adjustable active inductor L AI2 ,in,

[0006] The first resistor R1 is connected between the power supply terminal VDD and the drain of the third NMOS transistor M3, the second resistor R2 is connected between the power supply terminal VDD and the drain of the fourth NMOS transistor M4, the drain of the third NMOS transistor M3 serves as a first differential voltage output terminal, and the drain of the fourth NMOS transistor M4 serves as a second differential voltage output terminal;

[0007] The gate of the third NMOS tube M3 is connected to the gate of the fourth NMOS tube M4 and to the first bias voltage input terminal, the source of the third NMOS tube M3 is connected to the drain of the first NMOS tube M1, and the source of the fourth NMOS tube M4 is connected to the drain of the second NMOS tube M2;

[0008] The coupling capacitor C c The first adjustable active inductor L is connected between the source of the third NMOS tube M3 and the gate of the second NMOS tube M2. AI1 The second adjustable active inductor L is connected between the source of the first NMOS tube M1 and the ground terminal. AI2 connected between the source of the second NMOS tube M2 and the ground terminal, the gate of the first NMOS tube M1 is connected to the voltage input terminal and the second bias voltage input terminal, and the gate of the second NMOS tube M2 is connected to the third bias voltage input terminal;

[0009] The first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 The inductance value can be adjusted according to the frequency of the input voltage.

[0010] In one embodiment of the present invention, the single-ended input differential output low noise amplifier based on adjustable active inductance also includes a third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is connected between the second bias voltage input terminal and the gate of the first NMOS tube M1, and the fourth resistor R4 is connected between the third bias voltage input terminal and the gate of the second NMOS tube M2.

[0011] In one embodiment of the present invention, the first adjustable active inductor L AI1 It includes a fifth resistor R5, a first capacitor C1 and a first adjustable parallel transistor unit, wherein:

[0012] The fifth resistor R5 and the first capacitor C1 are connected in series between the source of the first NMOS transistor M1 and the ground terminal;

[0013] The first adjustable parallel transistor unit includes two parallel n NMOS tube M5, the 2 n The gates of the two NMOS transistors M5 are connected between the fifth resistor R5 and the first capacitor C1. n The sources of the two NMOS tubes M5 are connected to the ground terminal. n The drains of the NMOS transistors M5 are all connected to the source of the first NMOS transistor M1, and n is an integer greater than or equal to 1.

[0014] In one embodiment of the present invention, the drain of each NMOS tube M5 is connected to a first switch K C1 The source of each NMOS tube M5 is connected to a second switch K C2 , the first switch K C1 and the second switch K C2 Used to control the on and off of the current NMOS tube M5.

[0015] In one embodiment of the present invention, the second adjustable active inductor L AI2 It includes a sixth resistor R6, a second capacitor C2 and a second adjustable parallel transistor unit, wherein:

[0016] The sixth resistor R6 and the second capacitor C2 are connected in series between the source of the second NMOS transistor M2 and the ground terminal;

[0017] The second adjustable parallel transistor unit includes two parallel n NMOS tube M6, the 2 n The gates of the NMOS transistors M6 are connected between the sixth resistor R6 and the second capacitor C2. n The sources of the two NMOS tubes M6 are connected to the ground terminal. n The drains of the NMOS transistors M6 are all connected to the source of the second NMOS transistor M2, and n is an integer greater than or equal to 1.

[0018] In one embodiment of the present invention, the drain of each NMOS tube M6 is connected to a third switch K C3 The source of each NMOS tube M6 is connected to a fourth switch K C4 , the third switch K C3 and the fourth switch K C4 Used to control the on and off of the current NMOS tube M6.

[0019] In one embodiment of the present invention, the single-ended input differential output low noise amplifier based on adjustable active inductance further includes a control module, wherein a lookup table is provided in the control module, wherein the lookup table pre-sets the relationship between the output signal frequency and the first switch K C1 The second switch K C2 , the third switch K C3 And the fourth switch K C4 The control module is used to control the first switch K according to the input signal and the lookup table. C1 The second switch K C2 , the third switch K C3 And the fourth switch K C4The on-off of the first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 The inductance value.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. The present invention utilizes the inductance characteristics of transistors under specific structures to replace the use of traditional inductors. The on-chip active inductor can be realized only by connecting the transistors in the special way described in the present invention, without the need for a thick top metal (which usually occupies a large chip area, and a general on-chip inductor will occupy half or more of the chip area of ​​a low-noise amplifier) ​​during manufacturing, thus significantly saving chip area. At the same time, the adjustable active inductor of the present invention has a simple structure, can easily realize the function of the on-chip adjustable inductor, can flexibly adjust the input impedance matching, and reduces the difficulty of inductor design. At the same time, the adjustable active inductor structure can be used as a second-stage load inductor, and the low-noise amplifier (LNA) can be configurably adjusted through a digital control circuit. The use of the adjustable active inductor increases the configurability and flexibility of the circuit, allowing the circuit to adapt to more frequency ranges and matching requirements.

[0022] 2. Due to the existence of parasitic capacitance, the ordinary balun LNA causes a phase difference between the first stage and the second stage. However, the low noise amplifier proposed in the present invention can compensate for the phase error caused by the parasitic capacitance by adjusting the active inductor load of the second stage to achieve a configurable effect.

[0023] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit structure diagram of a single-ended input differential output low noise amplifier based on adjustable active inductance provided in an embodiment of the present invention;

[0025] Figure 2 is a schematic diagram of the working principle of an active inductor provided by an embodiment of the present invention;

[0026] Figure 3 is a schematic diagram of a circuit structure of a first adjustable active inductor provided in an embodiment of the present invention;

[0027] Figure 4 It is a schematic diagram of the circuit structure of a second adjustable active inductor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a single-ended input differential output low noise amplifier based on adjustable active inductor proposed by the present invention is described in detail below in combination with the accompanying drawings and specific implementation methods.

[0029] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0030] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0031] See also Figure 1 , Figure 1 The circuit structure diagram of a single-ended input differential output low noise amplifier based on adjustable active inductance provided by an embodiment of the present invention. The single-ended input differential output low noise amplifier includes a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a coupling capacitor C c , the first adjustable active inductor L AI1 And the second adjustable active inductor L AI2 , wherein the first resistor R1 is connected between the power supply terminal VDD and the drain of the third NMOS tube M3, the second resistor R2 is connected between the power supply terminal VDD and the drain of the fourth NMOS tube M4, and the drain of the third NMOS tube M3 serves as the first differential voltage output terminal V OUT+ The drain of the fourth NMOS tube M4 serves as the second differential voltage output terminal V OUT- The gate of the third NMOS tube M3 is connected to the gate of the fourth NMOS tube M4 and is connected to the first bias voltage input terminal, and the first bias voltage input terminal is used to input the bias voltage V Bias, the source of the third NMOS tube M3 is connected to the drain of the first NMOS tube M1, and the source of the fourth NMOS tube M4 is connected to the drain of the second NMOS tube M2; the coupling capacitor C c Connected between the source of the third NMOS tube M3 and the gate of the second NMOS tube M2, the first adjustable active inductor L AI1 connected between the source of the first NMOS tube M1 and the ground terminal, the second adjustable active inductor L AI2 The gate of the first NMOS tube M1 is connected between the voltage input terminal and the second bias voltage input terminal, and the second bias voltage input terminal is used to input the bias voltage V B1 The gate of the second NMOS tube M2 is connected to the third bias voltage input terminal, and the third bias voltage input terminal is used to input the bias voltage V B2 ; The first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 The inductance value can be adjusted according to the frequency of the input voltage.

[0032] The low noise amplifier of this embodiment adopts a two-stage amplification structure, a first resistor R1, a third NMOS transistor M3, a first NMOS transistor M1 and a first adjustable active inductor L AI1 The first stage amplifier structure is formed, the second resistor R2, the fourth NMOS tube M4, the second NMOS tube M2, the second adjustable active inductor L AI2 The structure of the second-stage amplifier. Specifically, the first resistor R1 and the second resistor R2 are output load resistors, which provide load resistors for the first-stage amplifier circuit and the second-stage amplifier circuit respectively, and convert the amplified current signal into a voltage signal for output. The third NMOS tube M3 and the fourth NMOS tube M4 are two cascode-level transistors with a common gate connection. This connection can effectively improve the isolation of input and output in the circuit of this embodiment. At the same time, the bias voltage V Bias Therefore, these two NMOS tubes can effectively isolate the noise coupled to the output from other parts of the circuit.

[0033] The first NMOS tube M1 and the second NMOS tube M2 are two amplifying transistors with a common source connection, and their function is to provide an amplification function for the input signal. Furthermore, the low noise amplifier also includes a third resistor R3 and a fourth resistor R4, the third resistor R3 is connected between the second bias voltage input terminal and the gate of the first NMOS tube M1, and the fourth resistor R4 is connected between the third bias voltage input terminal and the gate of the second NMOS tube M2. The third resistor R3 and the fourth resistor R4 are both large resistors with a resistance value of more than 10kΩ. The bias voltage V of the first NMOS tube M1 and the second NMOS tube M2 is B1 and V B2The AC signals are input to the corresponding gates through the third resistor R3 and the fourth resistor R4 respectively, and the third resistor R3 and the fourth resistor R4 play the role of isolating the AC signals.

[0034] See also Figure 2 , Figure 2 Schematic diagram of the working principle of an active inductor provided by an embodiment of the present invention. Under the circuit structure of the active inductor, the transistor has the characteristics of an inductor. Specifically, the voltage at point X can be expressed as V x , the current at the input point is i1 and i x The following formula can be derived from the relationship between loop voltage and node current:

[0035]

[0036] Among them, V in Indicates the input voltage at the input point, g m1 represents the transconductance of transistor M0, C gs1 represents the parasitic capacitance of the gate source of transistor M0. When calculating the impedance of the capacitor, ω represents the angular frequency of the signal, f represents the signal frequency, s represents the Fourier transform operator, s=jω, j represents the imaginary unit, and R equ Represents the equivalent resistance of the active inductor structure, L equ = represents the equivalent inductance of the active inductor structure. Formula (1) represents the voltage at point X, formula (2) represents the current I1 flowing into the drain of transistor M0, and formula (3) represents the impedance of the two-port active inductor structure. It can be seen from formula (3) that the impedance of the active inductor includes a real part and an imaginary part. Formula (4) represents these two parts of impedance respectively, and the real part is represented by R equ Indicates that it exhibits resistance characteristics, and the imaginary part can be represented by L equ It shows obvious inductive characteristics. It can be clearly seen that the change Figure 2 The width-to-length ratio of transistor M0 or the number of transistors connected in parallel can change the transistor transconductance g m1 value, thereby changing the equivalent inductance L equ The effect is achieved by achieving a low noise amplifier suitable for different matching frequencies.

[0037] Furthermore, the first adjustable active inductor L of this embodiment AI1 The first adjustable parallel transistor unit includes a fifth resistor R5, a first capacitor C1 and a first adjustable parallel transistor unit, wherein the fifth resistor R5 and the first capacitor C1 are connected in series between the source of the first NMOS tube M1 and the ground terminal; the first adjustable parallel transistor unit includes 2 parallel n NMOS tube M5, 2 n The gates of the NMOS transistors M5 are connected between the fifth resistor R5 and the first capacitor C1. nThe source of each NMOS tube M5 is connected to the ground terminal. n The drains of the NMOS transistors M5 are connected to the source of the first NMOS transistor M1, where n is an integer greater than or equal to 1. The drain of each NMOS transistor M5 is connected to a first switch K C1 The source of each NMOS tube M5 is connected to a second switch K C2 , the first switch K C1 and the second switch K C2 Used to control the on and off of the current NMOS tube M5.

[0038] The second adjustable active inductor L of this embodiment AI2 The sixth resistor R6, the second capacitor C2 and the second adjustable parallel transistor unit are included, wherein the sixth resistor R6 and the second capacitor C2 are connected in series between the source of the second NMOS tube M2 and the ground terminal; the second adjustable parallel transistor unit includes 2 parallel n NMOS tube M6, 2 n The gates of the NMOS transistors M6 are connected between the sixth resistor R6 and the second capacitor C2. n The source of each NMOS tube M6 is connected to the ground terminal. n The drains of the NMOS transistors M6 are connected to the source of the second NMOS transistor M2, where n is an integer greater than or equal to 1. The drain of each NMOS transistor M6 is connected to a third switch K C3 The source of each NMOS tube M6 is connected to a fourth switch K C4 , the third switch K C3 and the fourth switch K C4 Used to control the on and off of the current NMOS tube M6.

[0039] Specifically, the first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 They are active inductors with adjustable number of internal transistors. Figure 2 The proposed active inductor structure is extended by switching K C1 and K C2 Control the transistor M5 in the first adjustable parallel transistor unit, through the switch K C3 and K C4 Control the transistor M6 in the first adjustable parallel transistor unit. The first adjustable parallel transistor unit and the second adjustable parallel transistor unit are both composed of binary (2, 4, 8...) parallel transistors. The switch K C1 and K C2 Control the number of transistors M5 that are turned on to control the transconductance g of M5 m5 The equivalent inductance of transistor M5 can be controlled by switch KC3 and K C4 Control the number of transistors M6 that are turned on to achieve the control of the transconductance g of transistor M6 m6 , thereby achieving the effect of controlling the equivalent inductance of M6.

[0040] Furthermore, the single-ended input differential output low noise amplifier of this embodiment further comprises a control module, wherein a lookup table is provided in the control module, and the lookup table pre-sets the output signal frequency and the first switch K C1 , the second switch K C2 , the third switch K C3 And the fourth switch K C4 The control module is used to control the first switch K according to the input signal and the lookup table. C1 , the second switch K C2 , the third switch K C3 And the fourth switch K C4 The on-off of the first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 The inductance value.

[0041] Specifically, when the low noise amplifier circuit is working, the radio frequency signal received from the antenna enters the gate of the first NMOS transistor M1 through the input for the first stage of amplification. At this time, the input impedance of the low noise amplifier is mainly composed of the g of the input transistor M1. m1 , the gate-source parasitic capacitance C of transistor M1 gs And the first adjustable active inductor L AI1 In actual use, the first adjustable active inductor L can be adjusted according to different input frequencies or different matching requirements. AI1 The switch is used to adjust the load inductance L AI1 By changing L AI1 The inductance value is adjusted to change the input impedance of the amplifier, thereby adjusting the input matching. The signal amplified by the first NMOS tube M1 is coupled to the input of the amplifier through the coupling capacitor C C The input is sent to the gate of the second stage amplifier for the second amplification, where C C It is the coupling capacitor of the two amplifier stages, which plays the role of coupling the signal amplified by the first stage to the second stage. It also acts as the Miller compensation capacitor of the two-stage amplifier to adjust the amplifier pole. Since the first-stage amplifier and the second-stage amplifier are essentially common-source amplifiers, the input signal will undergo a phase inversion after passing through the first NMOS tube M1. C After being amplified by the second NMOS tube M2, a phase reversal will also occur.

[0042] From the output signal V outFrom the perspective of the input signal, the amplified signal presents an opposite phase, so the low noise amplifier also completes the single-ended input to differential conversion, so the LNA proposed in this embodiment is a balun LNA. Compared with the general two-stage balun LNA, the second-stage load of this structure also uses an adjustable active inductor structure, which can adjust the second adjustable active inductor L by adjusting the number of transistors M6. AI2 The phase of the second stage can be adjusted by adjusting the inductance value. The adjustable structure can effectively eliminate the influence of the parasitic capacitance between the two-stage amplifier to ensure that the phase difference between the first stage and the second stage is close to 180°.

[0043] In summary, the embodiments of the present invention utilize the inductance characteristics of transistors under specific structures to replace the use of traditional inductors. The on-chip active inductor can be realized by only connecting the transistors in the special way described in the present invention, without the need for a thick top metal (which usually occupies a large chip area, and a general on-chip inductor will occupy half of the LNA chip area or more) during manufacturing, thus significantly saving chip area. At the same time, the adjustable active inductor of the present invention has a simple structure, can easily realize the function of the on-chip adjustable inductor, can flexibly adjust the input impedance matching, and reduces the difficulty of inductor design. At the same time, the adjustable active inductor structure can be used as a second-stage load inductor, and the low noise amplifier (LNA) can be configurably adjusted through a digital control circuit. The use of the adjustable active inductor increases the configurability and flexibility of the circuit, allowing the circuit to adapt to more frequency ranges and matching requirements.

[0044] In addition, due to the existence of parasitic capacitance, the ordinary balun LNA has a phase difference between the first stage and the second stage, while the low noise amplifier proposed in the present invention can compensate for the phase error caused by the parasitic capacitance by adjusting the active inductor load of the second stage to achieve a configurable effect.

[0045] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A single-ended input differential output low noise amplifier based on adjustable active inductor, characterized in that: The first resistor R1, the second resistor R2, the first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, the fourth NMOS transistor M4, the coupling capacitor C c , the first adjustable active inductor L AI1 And the second adjustable active inductor L AI2 ,in, The first resistor R1 is connected between the power supply terminal VDD and the drain of the third NMOS transistor M3, the second resistor R2 is connected between the power supply terminal VDD and the drain of the fourth NMOS transistor M4, the drain of the third NMOS transistor M3 serves as a first differential voltage output terminal, and the drain of the fourth NMOS transistor M4 serves as a second differential voltage output terminal; The gate of the third NMOS tube M3 is connected to the gate of the fourth NMOS tube M4 and to the first bias voltage input terminal, the source of the third NMOS tube M3 is connected to the drain of the first NMOS tube M1, and the source of the fourth NMOS tube M4 is connected to the drain of the second NMOS tube M2; The coupling capacitor C c The first adjustable active inductor L is connected between the source of the third NMOS tube M3 and the gate of the second NMOS tube M2. AI1 The second adjustable active inductor L is connected between the source of the first NMOS tube M1 and the ground terminal. AI2 connected between the source of the second NMOS tube M2 and the ground terminal, the gate of the first NMOS tube M1 is connected to the voltage input terminal and the second bias voltage input terminal, and the gate of the second NMOS tube M2 is connected to the third bias voltage input terminal; The first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 Ability to adjust the inductance value according to the frequency of the input voltage, The first adjustable active inductor L AI1 It includes a fifth resistor R5, a first capacitor C1 and a first adjustable parallel transistor unit, wherein: The fifth resistor R5 and the first capacitor C1 are connected in series between the source of the first NMOS transistor M1 and the ground terminal; The first adjustable parallel transistor unit includes two parallel n NMOS tube M5, the 2 n The gates of the two NMOS transistors M5 are connected between the fifth resistor R5 and the first capacitor C1. n The sources of the two NMOS tubes M5 are connected to the ground terminal. n The drains of the NMOS transistors M5 are all connected to the source of the first NMOS transistor M1, and n is an integer greater than or equal to 1; The drain of each NMOS tube M5 is connected to a first switch K C1 The source of each NMOS tube M5 is connected to a second switch K C2 , the first switch K C1 and the second switch K C2 Used to control the on / off of the current NMOS tube M5; The second adjustable active inductor L AI2 It includes a sixth resistor R6, a second capacitor C2 and a second adjustable parallel transistor unit, wherein: The sixth resistor R6 and the second capacitor C2 are connected in series between the source of the second NMOS transistor M2 and the ground terminal; The second adjustable parallel transistor unit includes two parallel n NMOS tube M6, the 2 n The gates of the NMOS transistors M6 are connected between the sixth resistor R6 and the second capacitor C2. n The sources of the two NMOS tubes M6 are connected to the ground terminal. n The drains of the NMOS transistors M6 are all connected to the source of the second NMOS transistor M2, where n is an integer greater than or equal to 1; The drain of each NMOS tube M6 is connected to a third switch K C3 The source of each NMOS tube M6 is connected to a fourth switch K C4 , the third switch K C3 and the fourth switch K C4 Used to control the on and off of the current NMOS tube M6.

2. The single-ended input differential output low noise amplifier based on adjustable active inductance according to claim 1, characterized in that: It also includes a third resistor R3 and a fourth resistor R4, wherein the third resistor R3 is connected between the second bias voltage input terminal and the gate of the first NMOS tube M1, and the fourth resistor R4 is connected between the third bias voltage input terminal and the gate of the second NMOS tube M2.

3. The single-ended input differential output low noise amplifier based on adjustable active inductance according to claim 2, characterized in that: The invention also includes a control module, wherein a lookup table is provided in the control module, and the lookup table pre-sets the frequency of the output signal and the first switch K C1 The second switch K C2 , the third switch K C3 And the fourth switch K C4 The control module is used to control the first switch K according to the input signal and the lookup table. C1 The second switch K C2 , the third switch K C3 And the fourth switch K C4 The on-off of the first adjustable active inductor L AI1 and the second adjustable active inductor L AI2 The inductance value.

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