Image sensor readout circuit

Abstract

The present invention provides an image sensor readout circuit, comprising: a first analog-to-digital conversion unit, used to perform successive approximation high-bit analog-to-digital conversion on collected pixel data to obtain high-bit conversion data and residual pixel data; a second analog-to-digital conversion unit, electrically connected to the first analog-to-digital conversion unit, used to perform single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data; wherein the sum of the first conversion accuracy of the first analog-to-digital conversion unit and the second conversion accuracy of the second analog-to-digital conversion unit is equal to the preset conversion accuracy of the pixel data. The present invention can achieve a higher image conversion frame rate of pixel data with lower power consumption and circuit area, and effectively shorten the pixel data conversion cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an image sensor readout circuit. Background Art

[0002] CMOS image sensor (CIS) is an image sensor made of complementary metal oxide semiconductor. It has been widely used in imaging fields such as video, surveillance, industrial manufacturing, automobiles, and home appliances. With the continuous upgrading of CIS application requirements in recent years, the requirements for CIS resolution, frame rate, and image quality have been continuously improved. How to complete high-quality image data conversion and transmission in a shorter time has become a hot research topic. The mainstream readout circuit structure of CIS is a readout circuit based on a column-level single-slope analog-to-digital converter (SS-ADC) to ensure that CIS has sufficient conversion accuracy and speed under reasonable area and power consumption. However, a 12-bit SS-ADC requires at least 4095 conversion cycles. In high-frame-rate and high-resolution applications, the ADC counter needs to have a very high clock frequency to meet the requirements of short conversion time. When the frequency increases, the power consumption will also increase accordingly, which is not allowed for some low-power applications. Some applications use successive approximation register analog to digital converter (SAR-ADC) instead of SS-ADC. Although it solves the problem of high conversion frame rate, since each column of SAR-ADC requires a DAC composed of a switched capacitor array, the capacitor array will occupy a large area when the CIS resolution is high.

[0003] Therefore, it is necessary to provide a new image sensor readout circuit to solve the above problems existing in the prior art. Summary of the invention

[0004] The object of the present invention is to provide an image sensor readout circuit, which can achieve a higher image conversion frame rate of pixel data with lower power consumption and circuit area, and effectively shorten the pixel data conversion period.

[0005] To achieve the above object, the image sensor readout circuit of the present invention includes:

[0006] A first analog-to-digital conversion unit, configured to perform successive approximation high-bit analog-to-digital conversion on the collected pixel data to obtain high-bit conversion data and residual pixel data;

[0007] A second analog-to-digital conversion unit is electrically connected to the first analog-to-digital conversion unit, and is used to perform a single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data;

[0008] The sum of the first conversion accuracy of the first analog-to-digital conversion unit and the second conversion accuracy of the second analog-to-digital conversion unit is equal to the preset conversion accuracy of the pixel data.

[0009] The beneficial effect of the image sensor readout circuit of the present invention is that: within a preset conversion accuracy, the collected pixel data is first subjected to successive approximation high-bit conversion by the first analog-to-digital conversion unit to obtain high-bit conversion data and residual pixel data, and then the residual pixel data is subjected to single-slope low-bit analog-to-digital conversion by the second analog-to-digital conversion unit to obtain low-bit conversion data, thereby completing the analog-to-digital conversion process of the pixel data. The combination of successive approximation conversion and single-slope conversion greatly shortens the data conversion cycle compared to traditional single-slope conversion, facilitates the realization of high output frame rate at high resolution, and effectively reduces circuit power consumption and circuit area.

[0010] Optionally, the first analog-to-digital conversion unit includes a switch capacitor array, a comparison module and a control logic module, the first input terminal of the comparison module is electrically connected to the switch capacitor array, the control logic module is electrically connected to the switch capacitor array to control the plate voltage of the switch capacitor array, the second input terminal of the comparison module inputs a comparison reference voltage to compare the comparison reference voltage with the voltage signal input by the first input terminal, and the output terminal of the comparison module is electrically connected to the control logic module to output the high-bit conversion data through the control logic module.

[0011] Optionally, the switch capacitor array includes a first capacitor, K second capacitors and K switching switches, K is a positive integer, one end of the first capacitor and the K second capacitors are connected to the first input end, the other end of the first capacitor inputs a ramp signal, the other end of each second capacitor is electrically connected to a fixed end of the switching switch, the switching switch has at least two switching ends, the two switching ends respectively input a first reference voltage and a second reference voltage, and the control logic module is electrically connected to the switching switch to switch the voltage signal input by the switching switch.

[0012] Optionally, the capacitance of the first capacitor is C, and the capacitance of the i-th second capacitor is 2 i-1 C, where 1≤i≤K, and i and K are both natural numbers.

[0013] Optionally, each of the second capacitors corresponds to the switch on a one-to-one basis, and the second reference voltage is greater than the first reference voltage.

[0014] Optionally, the comparison reference voltage is equal to the difference between the first reference voltage and the second reference voltage.

[0015] Optionally, the second analog-to-digital conversion unit includes a counting module, the output end of the comparison module is connected to the input end of the counting module, and the counting module outputs low-bit conversion data after stopping counting.

[0016] Optionally, the image sensor readout circuit also includes an output unit, which is electrically connected to the output end of the counting module and the output end of the control logic module respectively to obtain the high-bit conversion data and the low-bit conversion data and unify them into complete data corresponding to the potential of the pixel data.

[0017] Optionally, the image sensor readout circuit includes a control switch, and the control switch is electrically connected to the first input terminal of the comparison module.

[0018] Optionally, the image sensor readout circuit also includes a row selection decoding drive unit, a ramp generator and a timing control unit, the output end of the ramp generator is connected to the first capacitor to input the ramp signal, the output end of the timing control unit is connected to the input end of the ramp generator, and the timing control unit is connected to the input end of the row selection decoding drive unit, and the output end of the row selection decoding drive unit is connected to the pixel unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A circuit diagram of a readout circuit in the prior art;

[0020] Figure 2 It is a working timing diagram of the readout circuit in the prior art;

[0021] Figure 3 A circuit diagram of an image sensor readout circuit according to an embodiment of the present invention;

[0022] Figure 4 is a working timing diagram of the image sensor readout circuit according to an embodiment of the present invention;

[0023] Figure 5 is an overall circuit diagram of the image sensor readout circuit according to an embodiment of the present invention;

[0024] Figure 6 is a circuit diagram of a pixel circuit in a pixel unit according to an embodiment of the present invention;

[0025] Figure 7 For the embodiment of the present invention Figure 6 0047 is a timing diagram of the pixel circuit described in . DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0027] In the prior art, reference Figure 1 The existing readout circuit generally includes a pixel array 101, a comparator 102, a counter 103, a ramp generator 104, a timing control 105, a row selection decoding driver 106 and an output signal processing 107. The pixel array 101 is composed of a plurality of pixel circuits P arranged in an array. The comparator 102 and the counter 103 form an analog-to-digital converter ADC. The pixel array 101 is read out row by row, and the specific order is ROW(0), ROW(1), ..., ROW(k-1), ROW(k). Each column of the pixel array 101 has an output bus, which are PIX_OUT(0), PIX_OUT(1), ...PIX_OUT(n-1), PIX_OUT(n). The PIX_OUT output is connected to the ADC. The comparator 102 compares the pixel output with the ramp signal RAMP, and the comparison result determines the size of the count value of the counter 103. The ADC judges the above-mentioned VRST and VSIG potentials respectively, and converts the VRST-VSIG difference into a digital quantity and outputs it to the system.

[0028] Specifically, the timing diagram is used for explanation. Figure 2 , Figure 2 for Figure 1 The working timing of the readout circuit shown is Figure 2The Read phase of the timing. After entering the Read phase, the selection signal SEL is pulled "high", and the pixel unit is reset when the receiving signal RX is "high". After that, the receiving signal RX and the reset signal RST_CM change from "high" to "low", EN_CM is the comparator enable control signal, and EN_CM is also "high" to enable all comparators 102 in the ADC to enter the working state. The ADC working process consists of two processes: comparison and counting. First, when the ramp signal RAMP starts to decrease, the counter CNT starts counting until the comparator 103 signal flips from "low" to "high", then CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC needs to perform the above operation twice. The ramp signal RAMP will be generated twice as the ADC reference. The first ramp stage (that is, Figure 2 The ADC will determine and store the reset potential VRST, and the counter CNT will count and store the count value CN1 corresponding to the t1 period during the t1 period; the second ramp stage (i.e. Figure 2 The ADC will determine and store the reset potential VSIG, and the counter CNT will count and store the count value CN2 corresponding to the t2 period. Finally, the counter CNT will output the count difference ΔCN=CN2-CN1, which corresponds to the difference between VSIG and VRST.

[0029] In view of the problems existing in the prior art, an embodiment of the present invention provides an image sensor readout circuit, referring to Figure 3 ,include:

[0030] The first analog-to-digital conversion unit 32 is used to perform successive approximation high-bit analog-to-digital conversion on the collected pixel data to obtain high-bit conversion data and residual pixel data.

[0031] In some embodiments, the first analog-to-digital conversion unit 32 includes a switch capacitor array 321, a comparison module and a control logic module 323, the first input terminal of the comparison module is electrically connected to the switch capacitor array 321, the control logic module 323 is electrically connected to the switch capacitor array 321 to control the plate voltage of the switch capacitor array 321, the second input terminal of the comparison module inputs a comparison reference voltage to compare the comparison reference voltage with the voltage signal input by the first input terminal, and the output terminal of the comparison module is electrically connected to the control logic module 323 to output the high-bit conversion data through the control logic module 323.

[0032] The second analog-to-digital conversion unit 33 is electrically connected to the first analog-to-digital conversion unit 32, and is used for performing a single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data.

[0033] In some embodiments, the second analog-to-digital conversion unit 33 includes a counting module, the output end of the comparison module is connected to the input end of the counting module, and the counting module outputs low-bit conversion data after stopping counting.

[0034] The sum of the first conversion accuracy of the first analog-to-digital conversion unit 32 and the second conversion accuracy of the second analog-to-digital conversion unit 33 is equal to the preset conversion accuracy of the pixel data.

[0035] In this embodiment, after collecting pixel data, within the preset conversion accuracy, the first analog-to-digital conversion unit 32 first performs a successive approximation high-bit conversion on the collected pixel data to obtain high-bit conversion data and residual pixel data, and then the second analog-to-digital conversion unit 33 performs a monoslope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data, thereby completing the analog-to-digital conversion process of the pixel data. The combination of successive approximation conversion and monoslope conversion is adopted. Compared with the traditional monoslope conversion, the data conversion cycle is greatly shortened, which facilitates the realization of high output frame rate at high resolution and effectively reduces circuit power consumption and circuit area.

[0036] In some other embodiments, the switch capacitor array 321 includes a first capacitor 3211, K second capacitors 3212 and K switching switches 3213, K is a positive integer, one end of the first capacitor 3211 and the K second capacitors 3212 are connected to the first input end, the other end of the first capacitor 3211 inputs a ramp signal, the other end of each second capacitor 3212 is electrically connected to a fixed end of the switching switch, the switching switch 3213 has at least two switching ends, the two switching ends respectively input a first reference voltage and a second reference voltage, and the control logic module 323 is electrically connected to the switching switch 3213 to switch the voltage signal input by the switching switch 3213.

[0037] In some embodiments, the capacitance of the first capacitor 3211 is C, and the capacitance of the i-th second capacitor 3212 is 2 i-1 C, where 1≤i≤K, and i and K are both natural numbers.

[0038] In some embodiments, each of the second capacitors 3212 corresponds to the switch 3213 one by one, and the second reference voltage VREF2 is greater than the first reference voltage VREF1.

[0039] In some embodiments, the comparison reference voltage is equal to the difference between the first reference voltage VREF1 and the second reference voltage VREF2 .

[0040] In some embodiments, the image sensor readout circuit includes a control switch 31 , and the control switch 31 is electrically connected to the first input terminal of the comparison module.

[0041] Exemplarily, the comparison module is a comparator 322, the counting module is a counter 331, and the K control switches 3213 in the switch capacitor array 321 are respectively recorded as S(0), S(1), ... S(K-2), S(K-1), each control switch 3213 is connected to the lower plate of the corresponding second capacitor 3212, and the upper plates of the first capacitor 3211 and the K second capacitors 3212 are connected to the positive input terminal FB of the comparator. The sizes of the first capacitor 3211 and the K second capacitors 3212 are distributed in a weighted binary manner, that is, C, C, 2C, 4C, ..., 2 K-2 C. 2 K-1 C. Under the control of the control logic module 323, except for the lower plate of the first capacitor 3211 connected to the ramp signal RAMP, the lower plate of each other second capacitor 3212 will be connected to the first reference voltage VREF1 or the second reference voltage VREF2, and the negative input terminal of the comparator 322 is connected to the comparison reference voltage VREF3, and VREF3 = VREF2-VREF1. The switch capacitor array 321, the control logic module 323 and the comparator 322 form a high K-bit SAR-ADC circuit, while the comparator 322 and the counter 331 form a low J-bit SS-ADC circuit. As a result, the image sensor readout circuit in this scheme first performs a successive approximation A / D conversion on the collected pixel data PIX_OUT to achieve a K-bit conversion accuracy; then the PIX_OUT margin is subjected to a single slope A / D conversion with an accuracy of J bits. Not only can a higher conversion frame rate be achieved within a reasonable power consumption and area, but also compared with the traditional single slope AD conversion, the conversion cycle is greatly shortened, which is conducive to achieving a high output frame rate at a high resolution.

[0042] In order to further explain the image sensor readout circuit in this scheme, the timing diagram is specifically described in conjunction with reference to Figure 4 The signal readout process of the image readout single channel is also divided into two signal readout stages: reset VRST and output integral VSIG. The readout process principles of these two stages are basically the same. Figure 4The timing diagram illustrates the process of the image sensor readout circuit in this solution for reading the VRST or VSIG signal. Taking the VRST readout as an example, first, the high K-bit conversion of the SAR-ADC is performed (successive approximation quantization stage). When SHC is high, the control switch 312 is turned on, and PIX_OUT is sampled to the upper plate FB terminals of the first capacitor 3211 and the K-th second capacitor 3212, while the lower plates of all the second capacitors 3212 are connected to VREF1. At this time, the ramp signal RAMP potential is VREF1, and the potential at the FB point is the potential VRST of PIX_OUT at this moment. Under the control of the control logic module 323, the lower plate of the largest capacitor 2 K-1 C changes from being connected to VREF1 to being connected to VREF2 (VREF2 is a reference voltage higher than VREF1), causing the FB potential to increase by (VREF2 - VREF1) / 2 (since each second capacitor 3212 is distributed according to the weighted binary size, so when the smallest unit capacitor C changes by VREF3 voltage, the FB changes by VREF3 / 2 K ), becoming VRST + (VREF2 - VREF1) / 2 = VRST + VREF3 / 2. The enable signal of the comparator 322 is in the form of a periodic pulse. When the comparator 322 is enabled, this voltage is compared with VREF3 and the judgment result CMO is output. The SAR-ADC performs the conversion bit by bit from the high bit to the low bit. When the highest bit is converted, if VRST + VREF3 / 2 > VREF3, the control bit B(K - 1) of the highest bit of the control logic module 323 outputs 1, and the lower plate of the largest capacitor 2 K-1 C is connected to VREF1; if (VRST + VREF3) / 2 < VREF3, the control bit B(K - 1) of the highest bit of the control logic module 323 outputs 0, and the lower plate of the largest capacitor 2 K-1 C remains connected to VREF2. When the second highest bit is converted, the lower plate of the second largest capacitor 2 K-2 C is connected to VREF2, so that FB will first increase by VREF3 / 4 based on the potential after the highest bit judgment. If the FB potential is higher than VREF3 at this time, the control bit B(K - 2) of the second highest bit of the control logic module 323 outputs 1, and the lower plate of the second largest capacitor 2 K-2 C is changed to be connected to VREF1, otherwise it remains connected to VREF2, and the control bit B(K - 2) of the second highest bit of the control logic module 323 outputs 0. And so on, until the SAR-ADC has completed the conversion of all high K-bit data, and the smallest unit capacitor C is determined to be connected to VREF2 or VREF1, and the lowest bit B(0) will also output a final data. After the high K-bit conversion is completed, there will be a remaining margin voltage Vs (that is, the potential at the FB terminal after the high K-bit conversion, and its voltage range is VREF3 - VREF3 / 2 KTo VREF3). The control logic module 323 logic will output the high K bits of data.

[0043] Subsequently, the low J-bit SS-ADC conversion will be performed, which is the ramp quantization stage. The ramp signal RAMP first drops to VRB, and then gradually rises in steps, changing from VRB to the highest potential VREF3 (that is, the range of change is VREF3), and the quantization accuracy is (VREF3) / 2 J , each RAMP change step is (VREF3) / 2 J , a total of 2J step signals. Since RAMP is connected to the smallest unit capacitor C, that is, the first capacitor 3211, through capacitor voltage division, the FB terminal changes from Vs to Vs+(VREF3) / 2 K , where FB changes in step size of VREF3 / 2 during the low J bit conversion phase K+J . After the comparator enable signal EN_CM remains high and the counter enable signal EN_CNT is high, the counter 331 starts counting. When RAMP gradually changes to make FB higher than VREF3, the comparator 322 flips, CMO will change from low to high, and the counter 331 will stop counting and output the low J-bit data. After that, the high K-bit and low J-bit data are unified into the complete data corresponding to VRST and temporarily stored in the column register. Similarly, after the data conversion of VSIG is completed, the column readout circuit finally outputs the digital value corresponding to VRST-VSIG to the subsequent system, thereby completing the pixel data readout process.

[0044] In this embodiment, since the conversion of each bit of the SAR-ADC circuit only requires one clock cycle, the conversion of the high K bits only requires K clock cycles; the conversion of the low J bits requires 2 clock cycles. J-1 clock cycles, so a total of K+2 J-1 clock cycle. The column readout circuit of the traditional SS-ADC needs 2 K+J-1 clock cycle, when the ADC resolution is higher (for example, 12 bits), the image sensor readout circuit proposed in the present invention obviously has a shorter conversion cycle, which is conducive to achieving a higher frame rate. If K=6, J=6, a traditional SS-ADC A / D conversion requires 4095 cycles, and the SAR-SS-ADC proposed in the present invention requires 69 cycles, of which the SAR-ADC high-bit conversion is 6 cycles, a total of 6μs (if the SAR-ADC comparator enables the clock frequency of 1MHz), and the SS-ADC low-bit conversion is 63 cycles, a total of 0.3μs (if the SS-ADC conversion counter clock frequency is 200MHz). A total of 6.3μs is required, while a 12-bit traditional SS-ADC requires 20.48μs. On the other hand, the readout circuit structure combining SAR and SS-ADC proposed in the present invention takes into account both conversion speed and area, and is more conducive to realizing CIS applications with high resolution and high frame rate.

[0045] In some embodiments, reference Figure 5 The image sensor readout circuit also includes an output unit 34, which is electrically connected to the output end of the counting module and the output end of the control logic module 323 respectively to obtain the high-bit conversion data and the low-bit conversion data and unify them into complete data corresponding to the potential of the pixel data, so as to temporarily store the read complete data in the column memory, so as to output the final data to the subsequent system.

[0046] In some embodiments, reference Figure 6 The pixel unit 35 includes a plurality of pixel circuits 351 arranged in an array. The pixel circuit 351 includes a photosensitive diode 3511, a charge transfer tube 3512, a reset tube 3513, a row selection tube 3514 and an amplifier tube 3515. The anode of the photosensitive diode 3511 is grounded, the cathode of the photosensitive diode 3511 is connected to the source of the charge transfer tube 3512, the drain of the charge transfer tube 3512 and the source of the reset tube 3513 are both connected to the gate of the amplifier tube 3515, the drain of the reset tube 3513 and the drain of the amplifier tube 3515 are both connected to the working voltage, the gate of the charge transfer tube 3512 inputs a sending signal TX, the gate of the reset tube 3513 inputs a receiving signal RX, the gate of the row selection tube 3514 inputs a selection signal SEL, the source of the row selection tube 3514 is connected to a current source, and the source of the row selection tube 3514 is connected to the output end of the pixel data.

[0047] Among them, the photosensitive diode 3511 is used for light sensing and generates photoelectrons proportional to the light intensity. The function of the charge transfer tube 3512 is to transfer the photoelectrons in the photosensitive diode 3511. When TX is a high voltage, the charge transfer tube 3512 is turned on, and the photoelectrons in the photosensitive diode 3511 are transferred to the floating node FD. The function of the reset tube 3513 is to reset the floating node FD when RX is a high potential. When SEL is a high potential and the row selection tube 3514 is turned on, the amplifier tube 3515, the row selection tube 3514 and the current source to the ground form a path. At this time, the amplifier tube 3515 is essentially a source follower, following the change in the potential of the floating node FD and finally output by PIX_OUT.

[0048] For example, in order to specifically describe the working process of the pixel circuit 351, the operation timing is described in conjunction with reference to Figure 7 , the working process of the pixel circuit 351 is divided into reset (Rst), exposure (Exp), and signal reading (Read). In the Rst stage, TX and RX are "high", the charge transfer tube 3512 and the reset tube 3513 are both turned on, FD is reset and its potential is pulled up to VDD. After that, RX and TX are "low", entering the Exp stage, the photodiode 3511 senses light and accumulates electrons. Entering the Read stage, SEL is "high", RX is first "high" to reset FD, RX is then pulled "low", and TX remains "low". At this time, the amplifier tube 3515 is controlled by the FD potential and outputs the reset potential VRST through PIX_OUT. After that, TX pulls "high" to transfer the electrons on the photodiode 3511 to FD. At this time, the amplifier tube 3515 is controlled by the FD potential and outputs the integral potential VSIG through PIX_OUT. The VRST and VSIG potentials are read by the subsequent image reading circuit and converted into digital quantities, and then subtracted to obtain the digital quantity actually corresponding to the photoelectrons on the photodiode 3511. If the ADC conversion accuracy is 12 bits and the ADC reference voltage range is VREF, the final output is DOUT = (VRST-VSIG) × 2 12 / VREF.

[0049] It should be noted that in this embodiment, the CIS standard four-tube pixel unit circuit structure is used for explanation, but this solution can adopt either a four-tube pixel unit or a pixel unit of other structures. The working process of the pixel units of other structures is similar and will not be repeated here.

[0050] In some embodiments, the image sensor readout circuit also includes a row selection decoding drive unit 36, a ramp generator 37 and a timing control unit 38, the output end of the ramp generator 37 is connected to the first capacitor 3211 to input the ramp signal, the output end of the timing control unit 38 is connected to the input end of the ramp generator 37, and the timing control unit 38 is connected to the input end of the row selection decoding drive unit 36, and the output end of the row selection decoding drive unit 36 ​​is connected to the pixel unit 35.

[0051] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. An image sensor readout circuit, characterized in that: include: A first analog-to-digital conversion unit, configured to perform successive approximation high-bit analog-to-digital conversion on the collected pixel data to obtain high-bit conversion data and residual pixel data; A second analog-to-digital conversion unit is electrically connected to the first analog-to-digital conversion unit, and is used to perform a single-slope low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data; Wherein, the sum of the first conversion accuracy of the first analog-to-digital conversion unit and the second conversion accuracy of the second analog-to-digital conversion unit is equal to the preset conversion accuracy of the pixel data; After collecting pixel data, within a preset conversion accuracy, the first analog-to-digital conversion unit first performs a successive approximation high-bit conversion on the collected pixel data to obtain high-bit conversion data and residual pixel data, and then the second analog-to-digital conversion unit performs a monoslant low-bit analog-to-digital conversion on the residual pixel data to obtain low-bit conversion data, thereby completing the analog-to-digital conversion process of the pixel data; In the ramp quantization stage, the ramp signal RAMP first drops to VRB, and then gradually rises in steps, changing from VRB to the highest potential VREF3, and the quantization accuracy is (VREF3) / 2 J , each RAMP change step is (VREF3) / 2 J , a total of 2J step signals; the conversion of the high K bits only requires K clock cycles; the conversion of the low J bits requires 2 J-1 clock cycles.

2. The image sensor readout circuit according to claim 1, characterized in that: The first analog-to-digital conversion unit includes a switch capacitor array, a comparison module and a control logic module, the first input end of the comparison module is electrically connected to the switch capacitor array, the control logic module is electrically connected to the switch capacitor array to control the plate voltage of the switch capacitor array, the second input end of the comparison module inputs a comparison reference voltage to compare the comparison reference voltage with the voltage signal input by the first input end, and the output end of the comparison module is electrically connected to the control logic module to output the high-bit conversion data through the control logic module.

3. The image sensor readout circuit according to claim 2, characterized in that: The switch capacitor array includes a first capacitor, K second capacitors and K switching switches, K is a positive integer, one end of the first capacitor and the K second capacitors are connected to the first input end, the other end of the first capacitor inputs a ramp signal, the other end of each second capacitor is electrically connected to a fixed end of the switching switch, the switching switch has at least two switching ends, the two switching ends respectively input a first reference voltage and a second reference voltage, and the control logic module is electrically connected to the switching switch to switch the voltage signal input by the switching switch.

4. The image sensor readout circuit according to claim 3, characterized in that: The capacitance of the first capacitor is C, and the capacitance of the i-th second capacitor is 2 i-1 C, where 1≤i≤K, and i and K are both natural numbers.

5. The image sensor readout circuit according to claim 3, characterized in that: Each of the second capacitors corresponds to the switch one by one, and the second reference voltage is greater than the first reference voltage.

6. The image sensor readout circuit according to claim 3, characterized in that: The comparison reference voltage is equal to the difference between the first reference voltage and the second reference voltage.

7. The image sensor readout circuit according to claim 2, characterized in that: The second analog-to-digital conversion unit includes a counting module, the output end of the comparison module is connected to the input end of the counting module, and the counting module outputs low-bit conversion data after stopping counting.

8. The image sensor readout circuit according to claim 7, characterized in that: The image sensor readout circuit also includes an output unit, which is electrically connected to the output end of the counting module and the output end of the control logic module respectively to obtain the high-bit conversion data and the low-bit conversion data and unify them into complete data corresponding to the potential of the pixel data.

9. The image sensor readout circuit according to claim 3, characterized in that: The image sensor readout circuit includes a control switch, and the control switch is electrically connected to the first input terminal of the comparison module.

10. The image sensor readout circuit according to any one of claims 3 to 6, characterized in that: The image sensor readout circuit also includes a row selection decoding driving unit, a ramp generator and a timing control unit, the output end of the ramp generator is connected to the first capacitor to input the ramp signal, the output end of the timing control unit is connected to the input end of the ramp generator, and the timing control unit is connected to the input end of the row selection decoding driving unit, and the output end of the row selection decoding driving unit is connected to the pixel unit.

Images