Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure is provided. The method includes forming a gate structure over an active region of a substrate; forming an epitaxial layer comprising a first dopant of a first conductivity type over a portion of the active region on the opposite side of the gate structure; applying a cleaning solution comprising ozone and deionized water to the epitaxial layer to form an oxide layer on the epitaxial layer; forming a patterned photoresist layer over the oxide layer and the gate structure to expose a portion of the oxide layer; forming a contact region comprising a second dopant of a second conductivity type opposite to the first conductivity type in a portion of the epitaxial layer not covered by the patterned photoresist layer; and forming contacts covering the contact region. The method for forming the semiconductor structure can improve the photoresist pattern profile.

Description

Technical Field

[0001] This disclosure relates to a method for forming semiconductor structures. Background Technology

[0002] In high-performance integrated circuits, static random access memory (SRAM) devices have been used as on-chip memory due to their high access speed and compatibility with manufacturing processes and supply voltages. An SRAM device comprises an array of individual SRAM cells implemented using metal-oxide-semiconductor (MOS) field-effect transistors. Within an SRAM cell, pairs of contacts are used to connect one or more transistors to a first metal interconnect layer. These contacts are large contacts that allow one or more gates to be connected to one or more active regions (i.e., source / drain structures) without the need for a horizontal metal interconnect layer. The size of an SRAM cell can be reduced by using a single pair of contacts connected to the gate and active regions. Summary of the Invention

[0003] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes: forming a gate structure over an active region of a substrate; forming an epitaxial layer over multiple portions of the active region on multiple opposite sides of the gate structure, the epitaxial layer comprising a plurality of first dopants of a first conductivity type; applying a cleaning solution comprising ozone and deionized water to the epitaxial layer to form an oxide layer on the epitaxial layer; forming a patterned photoresist layer over the oxide layer and the gate structure, the patterned photoresist layer exposing a portion of the oxide layer; forming a contact region in a portion of the epitaxial layer not covered by the patterned photoresist layer, the contact region comprising a plurality of second dopants of a second conductivity type opposite to the first conductivity type; and forming contacts covering the contact region.

[0004] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes: forming a first transistor, the first transistor including a first gate structure and first source / drain structures on a plurality of opposite sides of the first gate structure; forming a second transistor, the second transistor including a second gate structure and second source / drain structures on a plurality of opposite sides of the second gate structure; cleaning a plurality of surfaces of the first source / drain structures and the second source / drain structures using a cleaning solution including ozone and deionized water, wherein a first oxide layer is formed on the surface of the first source / drain structure and on the surface of the second source / drain structure. A second oxide layer is formed; a patterned photoresist layer is formed to expose a portion of a first source / drain structure adjacent to the second gate structure and a portion of a second source / drain structure adjacent to the first gate structure; a plurality of dopants are implanted into the exposed portions of the first source / drain structure and the exposed portions of the second source / drain structure to form a first pair of contact point regions in the first source / drain structure and a second pair of contact point regions in the second source / drain structure; and a first pair of contact points is formed to contact the first pair of contact point regions and the second gate structure, and a second pair of contact points is formed to contact the second pair of contact point regions and the first gate structure.

[0005] According to some embodiments of this disclosure, a method of forming a semiconductor structure includes: forming a first active region and a second active region on a substrate; forming a first gate structure extending over the first active region and a second gate structure extending over the second active region, each of the first gate structure and the second gate structure including a sacrificial gate stack and a plurality of gate spacers on a plurality of sidewalls of the sacrificial gate stack; forming a first source / drain structure on a plurality of portions of the first active region not covered by the first gate structure, and forming a second source / drain structure on a plurality of portions of the second active region not covered by the second gate structure; applying a cleaning solution including ozone and deionized water to a plurality of surfaces of the first source / drain structure and the second source / drain structure, cleaning to form a first oxide layer on the surface of the first source / drain structure, and forming a second oxide layer on the surface of the second source / drain structure; forming a patterned photoresist layer to expose the first source / drain structure adjacent to the second gate structure. A portion of a gate structure and a portion of a second source / drain structure adjacent to a first gate structure; forming a first pair of contact regions in the exposed portion of the first source / drain structure and a second pair of contact regions in the exposed portion of the second source / drain structure, the first pair of contact regions and the second pair of contact regions comprising multiple dopants having a conductivity type opposite to that of multiple dopants in the first source / drain structure and the second source / drain structure; depositing a first dielectric layer over a substrate to surround the first gate structure and the second gate structure; forming a functional gate stack to replace the sacrificial gate stack in each of the first gate structure and the second gate structure; depositing a second dielectric layer over the first dielectric layer and the first gate structure and the second gate structure; and forming a first pair of contact points and a second pair of contact points within the first dielectric layer and the second dielectric layer, the first pair of contact points connecting the first pair of contact regions to the second gate structure, and the second pair of contact points connecting the second pair of contact regions to the first gate structure. Attached Figure Description

[0006] The features disclosed herein will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

[0007] Figure 1 It is a configuration of a semiconductor device using a contact-coupled transistor according to some embodiments;

[0008] Figure 2 This is a flowchart of a method for manufacturing a semiconductor structure according to some embodiments;

[0009] Figures 3A to 11B According to some embodiments Figure 2 Various views of the semiconductor structure in various stages of the method.

[0010] [Symbol Explanation]

[0011] 100: Semiconductor device configuration

[0012] 102: Active Zone

[0013] 102a: Source / Drain structure

[0014] 102b: For the contact area

[0015] 104: Gate structure

[0016] 110: For contact points

[0017] 200: Method

[0018] 202: Operation

[0019] 204: Operation

[0020] 206: Operation

[0021] 208: Operation

[0022] 210: Operation

[0023] 212: Operation

[0024] 214: Operation

[0025] 216: Operation

[0026] 218: Operation

[0027] 302: Substrate

[0028] 302B: Base

[0029] 308: Isolation Structure

[0030] 312: First Active Zone

[0031] 314: Second Active Zone

[0032] 316: Third Active Zone

[0033] 318: Fourth Active Zone

[0034] 322: Gate structure

[0035] 324: Gate structure

[0036] 326: Gate structure

[0037] 328: Gate structure

[0038] 332: Gate dielectric

[0039] 334: Gate electrode

[0040] 336: Gate cap

[0041] 338: Gate spacer

[0042] 342: Source / Drain Structure

[0043] 342C: Source / Drain Contact Region

[0044] 344: Source / Drain Structure

[0045] 344B: For the contact area

[0046] 344C: Source / Drain contact region

[0047] 346: Source / Drain Structure

[0048] 346B: For the contact area

[0049] 346C: Source / Drain Contact Region

[0050] 348: Source / Drain Structure

[0051] 348C: Source / Drain Contact Region

[0052] 352: Oxide layer

[0053] 354: Oxide layer

[0054] 356: Oxide layer

[0055] 358: Oxide layer

[0056] 360: Patterned photoresist layer

[0057] 364: ILD layer

[0058] 372: Gate dielectric

[0059] 374: Gate electrode

[0060] 380: Contact-level dielectric layer

[0061] 382: Source / drain contact opening

[0062] 384: Opening at the contact point

[0063] 386: Source / Drain Contacts

[0064] 388: For contact points

[0065] 392: Contact Lining

[0066] 394: Contact plug

[0067] 1100: Semiconductor Structure

[0068] B-Bʹ: line

[0069] PD-1: First pull-down transistor

[0070] PD-2: Second pull-down transistor

[0071] PG-1: First gate-on transistor

[0072] PG-2: Second gate transistor

[0073] PU-1: First pull-up transistor

[0074] PU-2: Second pull-up transistor

[0075] T1: First transistor

[0076] T2: Second transistor Detailed Implementation

[0077] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element(s) or feature(s), spatial relative terms such as "below," "under," "lower," "above," "upper," and the like are used herein. Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0079] In SRAM, contact points are widely used to connect the source / drain structure of a transistor to the gate structure of an adjacent transistor. Figure 1 A semiconductor device configuration 100 is illustrated according to some embodiments, using such a pair contact 110 to couple a first transistor T1 and a second transistor T2. Each of the first transistor T1 and the second transistor T2 includes an active region 102 and a gate structure 104 extending over the active region 102. The pair contact 110 is formed to contact both the gate structure 104 of the first transistor T1 and the source / drain structure 102a of the second transistor T2, and thus electrically couples the first transistor T1 to the second transistor T2.

[0080] To reduce the contact resistance, dopants are implanted into the contact ends of the source / drain structure 102a to form a contact region 102b, and a contact point 110 is formed above the contact region 102b. Because the dopants in the contact region 102b have a conductivity type opposite to that of the dopants in the source / drain structure 102a of transistor T2, a portion of the source / drain structure 102a adjacent to the gate structure 104 of the first transistor T1 needs to be masked with a patterned photoresist during the ion implantation process to form the contact region 102b. The patterned photoresist is formed by applying a photoresist layer to a substrate, exposing the photoresist layer to radiation via a photomask, and then etching away either the exposed or unexposed area using a developer. Before applying the photoresist layer, the surface of the source / drain structure is chemically cleaned to remove contaminants. A commonly used cleaning solution is SPM, which is a mixture of H2SO4 and H2O2. SPM has strong oxidation capabilities and can form a relatively thick oxide layer on top of the source / drain structure 102a. During photoresist patterning, the thick oxide layer tends to reflect a large amount of light, forming a notch (i.e., undercut) on the sidewalls of the patterned photoresist at the bottom portion. During subsequent ion implantation, dopants can be implanted into the shielded portion of the source / drain structure via the notch on the sidewalls of the patterned photoresist, leading to leakage to contact 110. As integrated circuits continue to shrink in size, leakage to contact points becomes a significant reliability issue. Therefore, obtaining a notch-free photoresist pattern profile is crucial for improving the reliability of integrated circuits.

[0081] Therefore, this disclosure relates to a cleaning method that helps improve the profile of a photoresist pattern. In some embodiments, after forming the source / drain structure of an SRAM cell, the source / drain structure is cleaned with an ozone solution instead of a conventional SPM cleaning solution. The ozone solution reduces the thickness of the native oxide layer formed on the source / drain structure, which helps reduce the degree of reflection of the native oxide layer during photoresist patterning. As a result, slots caused by reflections of the patterned photoresist are prevented. Eliminating slots caused by reflections of the patterned photoresist helps reduce leakage to the contact points formed in the SRAM cell. This improves the reliability of the device. Although the cleaning method disclosed herein is described as being used for the formation of contact points in SRAM cells, it should be noted that the cleaning method disclosed herein is applicable to any semiconductor manufacturing process when improved profile of the patterned photoresist is required.

[0082] Figure 2 This is a flowchart of a method 200 for manufacturing a semiconductor structure (e.g., an SRAM cell) 1100 according to some embodiments of this disclosure. Figures 3A to 11B These are various views of the semiconductor structure 1100 at various stages of method 200 according to some embodiments. Reference is made below. Figures 3A to 11B The semiconductor structure 1100 is used to discuss method 200 in detail. In some embodiments, additional operations are performed before, during, and / or after method 200, or some of the described operations are replaced and / or eliminated. In some embodiments, additional features are added to the semiconductor structure 1100. In some embodiments, some features described below are replaced or eliminated. Those skilled in the art will understand that although some embodiments are discussed with respect to operations performed in a particular order, these operations may be performed in another logical order.

[0083] refer to Figure 2 Method 200 includes operation 202, wherein, according to some embodiments, gate structures 322, 324, 326, 328 are formed on respective active regions 312, 314, 316, 318. Figure 3A This is a top view of the semiconductor structure after the gate structures 322, 324, 326, and 328 are formed on their respective active regions 312, 314, 316, and 318. Figure 3B It is intercepted along line B-Bʹ. Figure 3A A cross-sectional view of the semiconductor structure.

[0084] refer to Figure 3A and Figure 3BA substrate 302 is provided. In some embodiments, the substrate 302 is a host semiconductor substrate comprising a semiconductor material or a stack of semiconductor materials, such as, for example, silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon-doped carbon (Si:C), silicon-germanium-carbon (SiGeC); or III-V compound semiconductors, such as, for example, gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), gallium arsenide phosphide (GaAsP), indium aluminum arsenide (AlInAs), gallium aluminum arsenide (AlGaAs), gallium indium arsenide (GaInAs), indium gallium phosphide (GaInP), or gallium arsenide indium phosphide (GaInAsP). In some embodiments, the host semiconductor substrate comprises a single-crystal semiconductor material, such as, for example, single-crystal silicon. In some embodiments, the host semiconductor substrate is doped according to design requirements. In some embodiments, the host semiconductor substrate is doped with a p-type dopant or an n-type dopant. The term "p-type" refers to the addition of an impurity to an intrinsic semiconductor, thereby creating a valence electron defect. Exemplary p-type dopants, i.e., p-type impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "N-type" refers to the addition of impurities that contribute free electrons to the intrinsically semiconductor. Exemplary n-type dopants, i.e., n-type impurities, include, but are not limited to, antimony, arsenic, and phosphorus. If doped, in some embodiments, substrate 302 has a [1.0 x 10] [size / permeability]. 14 Atoms per cubic centimeter to 1.0 x 10⁻⁶ 17 Dopant concentration in the range of atoms per cubic centimeter, although the dopant concentration can be greater or smaller.

[0085] In some embodiments, substrate 302 is a semiconductor-on-insulator (SOI) substrate, including a top semiconductor layer formed on an insulating layer (not shown). The top semiconductor layer includes the aforementioned semiconductor materials, such as, for example, Si, Ge, SiGe, Si:C, SiGeC; or III-V compound semiconductors, including GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInASP. The insulating layer is, for example, a silicon oxide layer, or the like. The insulating layer is disposed above a base substrate, typically a silicon or glass substrate.

[0086] An isolation structure 308 is formed in the substrate 302 to define various active regions. The active regions include a first active region 312, a second active region 314, a third active region 316, and a fourth active region 318. In some embodiments, the first and fourth active regions 312 and 318 are used to form n-type transistors, while the second and third active regions 314 and 316 are used to form p-type transistors in SRAM cells. In some embodiments, the active regions 312, 314, 316, and 318 are intrinsically (i.e., undoped) semiconductor regions. In some embodiments, the first active region 312 and the fourth active region 318, which subsequently form n-type transistors, are doped with p-type dopant, and the second active region 314 and the third active region 316, which subsequently form p-type transistors, are doped with n-type dopant. In some embodiments, the active regions 312, 314, 316, and 318 are planar regions formed in the upper portion of the substrate 302 for forming planar FETs (not shown). In some other embodiments, and as... Figure 3B As shown, active regions 312, 314, 316, and 318 are semiconductor fins protruding from the base 302B of substrate 302 for forming a FinFET. In some embodiments, the semiconductor fins are formed by photolithography and etching. In some embodiments, a photoresist layer (not shown) is applied to substrate 302 and patterned to provide a patterned photoresist layer on top of substrate 302. The pattern in the patterned photoresist layer is then transferred to substrate 302 by anisotropic etching to provide the semiconductor fins. In some embodiments, the etching process for pattern transfer includes dry etching, for example, reactive ion etching (RIE), plasma etching, ion beam etching, or laser ablation. After the pattern is transferred to substrate 302, the patterned photoresist layer is removed using a deresist process such as ashing. In some embodiments, other methods such as sidewall image transfer (SIT) or directional self-assembly (DSA) are used to form the semiconductor fins. In yet other embodiments, active regions 312, 314, 316, and 318 are semiconductor nanosheets, such as nanowires (not shown) used to form nanowire FETs.

[0087] In some embodiments, the isolation structure 308 is a shallow trench isolation (STI) structure. Forming the isolation structure 308 includes etching trenches (not shown) in a substrate 302 and filling the trenches with one or more insulating materials (such as silicon dioxide, silicon nitride, or silicon oxynitride). In some embodiments, one or more isolation structures 308 have a multilayer structure, including a thermal oxide liner and silicon nitride filling the trenches. In some embodiments, the trenches are formed by applying a photoresist layer (not shown) to the substrate 302, patterning the photoresist layer using photolithography, and transferring the pattern in the photoresist layer to an upper portion of the substrate 302 using anisotropic etching (such as RIE or plasma etching). An insulating material is then deposited to fill the trenches using, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Next, a chemical mechanical planarization (CMP) process is performed to polish away excess insulating material and planarize the top surface of the isolation structure 308. In some embodiments, the isolation structure 308 is formed by oxidizing or nitriding portions of the substrate 302. In examples where active regions 312, 314, 316, and 318 are semiconductor fins, the insulating material is etched back to solidly expose the upper portion of the semiconductor fin. In some embodiments, wet etching can be used to etch the insulating material, employing etching chemicals such as dilute hydrofluoric acid. Thus, the isolation structure 308 surrounds the bottom portion of the semiconductor fin.

[0088] Gate structures 322, 324, 326, and 328 are formed above substrate 302. A first gate structure 322 is disposed extending across active regions 312 and 314. A second gate structure 324 is disposed extending across active regions 316 and 318. A third gate structure 326 is disposed on active region 312. A fourth gate structure 328 is disposed on active region 318. Each of the gate structures 322, 324, 326, and 328 includes a gate stack and gate spacers 338 on the sidewalls of the gate stack. In some embodiments, the gate stack includes, from bottom to top, a gate dielectric 332, a gate electrode 334, and a gate cap 336.

[0089] In some embodiments, a gate stack (332, 334, 336) is formed by providing a gate material stack (not shown) including a gate dielectric layer, a gate electrode layer, and a gate cap layer on a substrate 302, and by patterning the gate material stack using photolithography.

[0090] In some embodiments, the gate dielectric layer is on substrate 302 and includes a dielectric material, such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the gate dielectric layer includes a high-k dielectric material having a dielectric constant greater than that of silicon oxide. Exemplary high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanate (SrTiO3), lanthanum aluminate (LaAlO3), and yttrium oxide (Y2O3). In some embodiments, the gate dielectric layer is formed using a deposition process, such as, for example, CVD, plasma-enhanced chemical vapor deposition (PECVD), ALD, or PVD. In some embodiments, the gate dielectric layer is formed by transforming surface portions of active regions 312, 314, 316, and 318 using thermal oxidation or nitriding.

[0091] The gate electrode layer is located on the gate dielectric layer. In some embodiments, the gate electrode layer comprises a semiconductor material, such as polysilicon. In some embodiments, the gate electrode layer comprises a conductive metal, such as, for example, tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), or alloys thereof. In some embodiments, the gate electrode layer is formed by a suitable deposition process, such as, for example, CVD, PECVD, ALD, or PVD.

[0092] The gate cap layer is on the gate electrode layer. In some embodiments, the gate cap layer includes a dielectric material, such as, for example, silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the gate cap layer is formed using a deposition process, such as, for example, CVD, PECVD, ALD, or PVD.

[0093] In some embodiments, the gate material stack is patterned by lithography and etching. For example, a photoresist layer (not shown) is applied over the top surface of the gate material stack, and lithography patterning is performed by exposure and development. The pattern in the photoresist layer is sequentially transferred to the gate material stack by at least one anisotropic etching. The anisotropic etching is, for example, dry etching, wet etching, or a combination thereof of RIE. If not completely consumed, any remaining photoresist layer after the formation of the gate material stack is removed by, for example, ashing.

[0094] In some embodiments, gate structures 322, 324, 326, and 328 are sacrificial gate structures, wherein the gate stacks (332, 334, and 336) are sacrificial gate stacks. The sacrificial gate stacks are subsequently replaced by functional gate stacks. The term "sacrificial gate stack" is used throughout this disclosure to refer to a stack of material serving as a placeholder for a subsequently formed functional gate stack. The term "functional gate stack" as used herein refers to a permanent gate stack used to control the output current (i.e., the carrier flow in a channel) of a semiconductor device via an electric field.

[0095] After the gate stacks (332, 334, 336) are formed, gate spacers 338 are formed on the sidewalls of the gate stacks (332, 334, 336). In some embodiments, gate spacers 338 comprise a dielectric material, such as a dielectric oxide, a dielectric nitride, a dielectric oxynitride, or a combination thereof. In some embodiments, gate spacers 338 comprise silicon nitride. In some embodiments, gate spacers 338 are formed by depositing a gate spacer material layer (not shown) on the exposed surfaces of the gate stacks (332, 334, 336) and substrate 302 and etching the gate spacer material layer to remove horizontal portions of the gate spacer material layer. In some embodiments, the gate spacer material layer is provided by a suitable deposition process, including, for example, CVD, PECVD, or ALD. Etching of the gate spacer material layer is performed by dry etching, for example, RIE. The remaining vertical portions of the gate spacer material layer on the sidewalls of the gate stacks (332, 334, 336) constitute gate spacers 338.

[0096] refer to Figure 2 According to some embodiments, method 200 includes operation 204, wherein source / drain structures 342, 344, 346, 348 are formed on portions of their respective active regions 312, 314, 316, 318 that are not covered by gate structures 322, 324, 326, 328. Figure 4A This refers to the formation of source / drain structures 342, 344, 346, and 348 on the portions of their respective active regions 312, 314, 316, and 318 that are not occupied by gate structures 322, 324, 326, and 328. Figure 3A and Figure 3B A top view of the semiconductor structure. Figure 4B It is intercepted along line B-Bʹ. Figure 4A A cross-sectional view of the semiconductor structure.

[0097] refer to Figure 4A and Figure 4BThe source / drain structures 342, 344, 346, and 348 include: a first source / drain structure 342, formed on a portion of the first active region 312 not covered by the first gate structure 322 and the third gate structure 326; a second source / drain structure 344, formed on a portion of the second active region 314 not covered by the first gate structure 322; a third source / drain structure 346, formed on a portion of the third active region 316 not covered by the second gate structure 324; and a fourth source / drain structure 348, formed on a portion of the fourth active region 318 not covered by the second gate structure 324 and the fourth gate structure 328. Here, depending on the transistor wiring, the source / drain structure is used as either a source or a drain.

[0098] Source / drain structures 342, 344, 346, and 348 are doped semiconductor structures. In some embodiments, source / drain structures 342, 344, 346, and 348 independently comprise semiconductor materials, such as, for example, Si, SiGe, Si:C, Ge, or III-V materials, such as GaAs, InP, GaP, or GaN. Source / drain structures 342, 344, 346, and 348 contain dopants of a suitable conductivity type. For example, the first source / drain structure 342 and the fourth source / drain structure 348 may contain n-type dopants for forming n-type transistors, while the second source / drain structure 344 and the third source / drain structure 346 may contain p-type dopants for forming p-type transistors of SRAM cells. The doping concentration in source / drain structures 342, 344, 346, and 348 may be from about 1 × 10⁻⁶. 19 atoms / cubic centimeter to approximately 2 × 10 21 Atoms per cubic centimeter, although smaller or larger doping concentrations are also considered.

[0099] In some embodiments, the source / drain structures 342, 344, 346, and 348 are epitaxial layers formed by one or more selective epitaxial growth processes. During selective epitaxial growth, the deposited semiconductor material grows only on the exposed semiconductor surfaces (such as the surfaces of active regions 312, 314, 316, and 318), but not on the dielectric surfaces (such as the surfaces of the isolation structure 308, the gate cap 336, and the gate spacer 338). In some embodiments, when the active regions 312, 314, 316, and 318 are semiconductor fins, the deposited semiconductor material grows on the sidewalls and top surface of the semiconductor fins. In some embodiments, the source / drain structures 342, 344, 346, and 348 are formed by molecular beam epitaxy (MBE).

[0100] In some embodiments, source / drain structures 342, 344, 346, and 348 are in-situ doped with a dopant of appropriate conductivity type, n-type or p-type, during the epitaxial growth process. In some embodiments, source / drain structures 342, 344, 346, and 348 are doped (non-in-situ) after an epitaxial growth process, such as ion implantation. For example, to form n-type transistors in active regions 312 and 318, an n-type dopant, such as phosphorus or arsenic, is implanted into the deposited semiconductor material on active regions 312 and 318, while active regions 314 and 316 are covered by a mask. Similarly, to form p-type transistors in active regions 314 and 316, a p-type dopant, such as boron or BF2, is implanted into the deposited semiconductor material on active regions 314 and 316, while active regions 312 and 318 are covered by a mask.

[0101] Alternatively, in some embodiments, the source / drain structures 342, 344, 346, 348 are formed by implanting appropriate types of dopants into portions of the respective active regions 312, 314, 316, 318 that are not covered by the gate structures 322, 324, 326, 328.

[0102] In some embodiments, after the formation of source / drain structures 342, 344, 346, 348 and / or after subsequent doping processes, the source / drain structures 342, 344, 346, 348 are further exposed to an annealing process to activate the dopants in the source / drain structures 342, 344, 346, 348. In some embodiments, the dopants in the source / drain structures 342, 344, 346, 348 are activated by a thermal annealing process including a rapid thermal annealing process, a laser annealing process, or a furnace annealing process. In some embodiments, the dopants in the source / drain structures 342, 344, 346, 348 diffuse to the underlying corresponding active regions 312, 314, 316, 318 to dope the surface portions of the corresponding active regions 312, 314, 316, 318.

[0103] Therefore, various transistors for SRAM cells are formed. These transistors include a first pull-up transistor PU-1 and a first pull-down transistor PD-1 for constructing a first inverter of an SRAM cell, a second pull-up transistor PU-2 and a second pull-down transistor PD-2 for constructing a second inverter of an SRAM cell, and a first gate transistor PG-1 and a second gate transistor PG-2.

[0104] The first pull-up transistor PU-1 includes a first portion of the gate structure 322 above a portion of the active region 314 and a source / drain structure 344 on the opposite side of the first portion of the gate structure 322. The second pull-up transistor PU-2 includes a first portion of the gate structure 324 above a portion of the active region 316 and a source / drain structure 346 on the opposite side of the first portion of the gate structure 324.

[0105] The first pull-down transistor PD-1 includes a second portion of a gate structure 322 above a first portion of the active region 312 and a source / drain structure 342 on the opposite side of the second portion of the gate structure 322. The second pull-down transistor PD-2 includes a second portion of a gate structure 324 above a first portion of the active region 318 and a source / drain structure 348 on the opposite side of the second portion of the gate structure 324. Therefore, the first pull-down transistor PD-1 and the first pull-up transistor PU-1 share a common gate structure (i.e., gate structure 322), while the second pull-down transistor PD-2 and the second pull-up transistor PU-2 share a common gate structure (i.e., gate structure 324).

[0106] The first gate-on transistor PG-1 includes a gate structure 326 above the second portion of the active region 312 and a source / drain structure 342 on the opposite side of the gate structure 326. In some embodiments, the first gate-on transistor PG-1 and the first pull-down transistor PD-1 share the common source / drain structure 342 located between the gate structures 322 and 326. The second gate-on transistor PG-2 includes a gate structure 328 above the second portion of the active region 318 and a source / drain structure 348 on the opposite side of the gate structure 328. In some embodiments, the second gate-on transistor PG-2 and the second pull-down transistor PD-2 share the common source / drain structure 348 located between the gate structures 324 and 328.

[0107] refer to Figure 2 Method 200 proceeds to operation 206, wherein, according to some embodiments, a wet cleaning process is performed to remove contaminants from source / drain structures 342, 344, 346, 348. Figure 5A It is after the cleaning process. Figure 4A and Figure 4B A top view of the semiconductor structure. Figure 5B It is intercepted along line B-Bʹ. Figure 5A A cross-sectional view of the semiconductor structure.

[0108] In some embodiments, a cleaning solution containing ozone (O3) and deionized water (DIW) is applied to source / drain structures 342, 344, 346, and 348 to clean their surfaces, thereby removing any contaminants. In some embodiments, the cleaning solution consists essentially of ozone and DIW. The ozone concentration in the cleaning solution can range from about 20 parts per million (ppm) to about 70 ppm. In some embodiments, the ozone concentration in the ozone solution is about 50 ppm. If the ozone concentration is too low, the source / drain structures may not be adequately cleaned of contaminants. If the ozone concentration is too high, the oxide layer formed by ozone oxidation of the source / drain structures becomes too thick, resulting in grooves forming on the sidewalls of the patterned photoresist. The ozone wet cleaning process is performed in a temperature range of about 15°C to about 40°C. In some embodiments, the ozone wet cleaning process is performed at room temperature (e.g., about 25 °C). If the cleaning temperature is too low, contaminants in the source / drain structure may not be adequately cleaned. If the cleaning temperature is too high, the oxide layer formed by the ozone oxidation of the source / drain structure becomes too thick, resulting in grooves forming on the sidewalls of the patterned photoresist. The cleaning time can be controlled from about 5 seconds to about 20 seconds. In some embodiments, the ozone wet cleaning process is performed for about 10 seconds. If the cleaning time is too short, contaminants in the source / drain structure may not be adequately cleaned. If the cleaning time is too long, the oxide layer formed by the ozone oxidation of the source / drain structure becomes too thick, resulting in grooves forming on the sidewalls of the patterned photoresist. During the cleaning process, an ozone solution may be sprayed onto the surface of the source / drain structures 342, 344, 346, 348. Alternatively, the surface of the source / drain structures 342, 344, 346, 348 may be cleaned by applying an ozone solution to the surface of the source / drain structures 342, 344, 346, 348. Figure 5A and Figure 5B The semiconductor structure is immersed in a container containing ozone solution and comes into contact with the ozone solution.

[0109] Cleaning the surfaces of source / drain structures 342, 344, 346, and 348 with an ozone-containing solution also oxidizes the surfaces of source / drain structures 342, 344, 346, and 348, forming oxide layers 352, 354, 356, and 358 on their respective source / drain structures 342, 344, 346, and 348. In the case where the source / drain structures 342, 344, 346, and 348 comprise SiGe, the oxide layers 352, 354, 356, and 358 comprise silicon oxide. The thickness of the formed oxide layers 352, 354, 356, and 358 can range from about 0.1 angstrom (Å) to about 0.4 Å. In some embodiments, the thickness of the oxide layers 352, 354, 356, and 358 is about 0.26 Å. If the oxide layer thickness is too large, reflective grooves can be induced in the patterned photoresist.

[0110] Compared to conventional cleaning processes using a sulfate / peroxide mixture (SPM) comprising sulfuric acid (H2SO4) and hydrogen peroxide (H2O2) at relatively high temperatures of approximately 90 °C, the low-temperature ozone cleaning process facilitates the formation of an oxide layer less than half the thickness of the oxide layer formed by the SPM cleaning process. This relatively thin oxide layer results in less light reflection during subsequent photoresist patterning processes. Therefore, the ozone cleaning process helps prevent necking on the sidewalls of the patterned photoresist at the interface with the oxide layer.

[0111] refer to Figure 2 Method 200 proceeds to operation 208, in which, according to some embodiments, contact point regions 344B and 346B are formed in the mating ends of their respective source / drain structures 344 and 346. Figure 6A This refers to the formation of contact regions 344B and 346B at the mating ends of their respective source / drain structures 344 and 346. Figure 5A and Figure 5B A top view of the semiconductor structure. Figure 6B It is intercepted along line B-Bʹ. Figure 6A A cross-sectional view of the semiconductor structure.

[0112] refer to Figure 6A and Figure 6BA patterned photoresist layer 360 is formed to cover portions of the source / drain structures 344, 346 adjacent to their respective gate structures 322, 324, while simultaneously exposing portions of the source / drain structures 344, 346 away from their respective gate structures 322, 324. The patterned photoresist layer 360 is formed by applying a photoresist layer (not shown) over the substrate 302, exposing the photoresist layer to light with a predetermined pattern, performing post-exposure baking, and developing the photoresist. Because the oxide layers 354, 356 are made to have a thin thickness, the thin oxide reduces light scattering and reflection during photoresist exposure, thereby eliminating or minimizing the formation of notches caused by reflection at the bottom of the photoresist. The resulting sidewall profile of the patterned photoresist layer 360 is substantially straight, uniform, and without necking or notch configurations.

[0113] Subsequently, using a patterned photoresist layer 360 as an ion implantation mask, dopants are implanted into the exposed portions of source / drain structures 344 and 346, forming contact regions 344B in source / drain structure 344 and 346B in source / drain structure 346. The implanted dopants have different conductivity than the dopants in source / drain structures 344 and 346. For example, when source / drain structures 344 and 346 are doped with p-type dopants, n-type dopants are implanted into the exposed portions of source / drain structures 344 and 346, and vice versa. Since the patterned photoresist layer 360 has no necking defects, the risk of dopants being implanted through slots into the portions of source / drain structures 344 and 346 covered by the patterned photoresist layer 360 is eliminated. As a result, each pair of contact point regions 344B and 346B forms a sharp, steep contact surface with the corresponding source / drain structures 344 and 346.

[0114] After ion implantation, the patterned photoresist layer 360 is removed by, for example, ashing.

[0115] In some embodiments, a wet cleaning process, such as SPM, is used to remove residues from the patterned photoresist layer 360. In some embodiments, the cleaning process also removes oxide layers 352, 354, 356, and 358. The surfaces of the source / drain structures 342, 344, 346, and 348 are solid-exposed (not shown). In other embodiments, oxide layers 352, 354, 356, and 358 remain in the structure after the photoresist cleaning process.

[0116] refer to Figure 2 In the case where the gate stack (332, 334, 336) is a sacrificial gate stack, method 200 proceeds to operation 210. In operation 210, according to some embodiments, an interlevel dielectric (ILD) layer 364 is deposited on substrate 302. Figure 7A This occurs after the ILD layer 364 is formed above the substrate 302. Figure 6A and Figure 6B A top view of the semiconductor structure. Figure 7B It is intercepted along line B-Bʹ. Figure 7A A cross-sectional view of the semiconductor structure.

[0117] refer to Figure 7A and Figure 7B An ILD layer 364 is deposited over the substrate 302, surrounding the gate structures 322, 324, 326, and 328. The ILD layer 364 fills the gaps between the gate structures 322, 324, 326, and 328. In some embodiments, the ILD layer 364 comprises silicon oxide. Alternatively, in some embodiments, the ILD layer 364 comprises a low-k dielectric material having a dielectric constant (k) of less than 4. In some embodiments, the low-k dielectric material has a dielectric constant from about 1.2 to about 3.5. In some embodiments, the ILD layer 364 comprises tetraethylorthosilicate (TEOS) oxide, undoped silicon glass, or doped silicon glass, such as borophosphosilicate glass (BPSG), fluorosilica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, the ILD layer 364 is deposited by CVD, PECVD, PVD, or spin coating. In some embodiments, the ILD layer 364 is deposited to have a top surface over the topmost surface of the gate structures 322, 324, 326, and 328 (e.g., the top surface of the gate cap 336). The ILD layer 364 is then planarized, for example, by CMP and / or by using the gate cap 336 as a groove for polishing and / or etching termination. After planarization, the ILD layer 364 has a surface coplanar with the topmost surface of the gate structures 322, 324, 326, and 328.

[0118] refer to Figure 2 Method 200 proceeds to operation 212, wherein, according to some embodiments, the gate stack (332, 334, 336) is replaced with a functional gate stack (372, 374). Figure 8A This is after replacing the gate stack (332, 334, 336) with a functional gate stack (372, 374). Figure 7A and Figure 7B A top view of the semiconductor structure. Figure 8B It is intercepted along line B-Bʹ. Figure 8AA cross-sectional view of the semiconductor structure.

[0119] refer to Figure 8A and Figure 8B Each of the functional gate stacks (372, 374) includes a U-shaped gate dielectric 372 and a gate electrode 374 surrounded by the gate dielectric 372. In some embodiments, the gate dielectric 372 includes a high-k dielectric material having a dielectric constant greater than that of silicon oxide. Exemplary high-k dielectric materials include, but are not limited to, HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, and Y2O3. In some embodiments, a multilayer gate dielectric structure is formed comprising different gate dielectric materials (e.g., silicon oxide) and a high-k gate dielectric material. In some embodiments, the gate electrode 374 includes a conductive metal, such as W, Cu, Al, Co, or alloys thereof.

[0120] To form the functional gate stacks (372, 374), the gate stacks (332, 334, 336) are first removed to provide gate cavities (not shown). Various components of the gate stacks (332, 334, 336) can be selectively removed to active regions 312, 314, 316, and 318, gate spacer 338, and ILD layer 364 by at least one etch. The at least one etch can be a wet chemical etching (such as ammonia etching) or a dry etching (such as RIE). Each gate cavity occupies the volume from which the corresponding gate stack (332, 334, 336) is removed and is laterally constrained by the inner sidewalls of the gate spacer 338.

[0121] Subsequently, a conformal dielectric layer (not shown) is deposited on the bottom surface and sidewalls of the gate cavity and on the top surface of the ILD layer 364. In some embodiments, the gate dielectric layer is deposited by, for example, CVD or ALD. A gate electrode layer (not shown) is then deposited on the gate dielectric layer to fill the remaining volume of the gate cavity. In some embodiments, the gate electrode layer is deposited by, for example, CVD, PECVD, or ALD. A planarization process (such as CMP) is performed to remove portions of the gate electrode layer and the gate dielectric layer from the top surface of the ILD layer 364. The remaining portions of the gate electrode layer within each gate cavity constitute the gate electrode 374, and the remaining portions of the gate dielectric layer within each gate cavity constitute the gate dielectric 372.

[0122] In some embodiments, when the gate stacks (332, 334, 336) in the gate structures 322, 324, 326, 328 are functional gate stacks, operations 212 and 214 are omitted.

[0123] refer to Figure 2Method 200 proceeds to operation 214, in which, according to some embodiments, a contact-level dielectric layer 380 is deposited on the ILD layer 364 and gate structures 322, 324, 326 and 328. Figure 9A This occurs after the contact-level dielectric layer 380 is formed on the ILD layer 364 and the gate structures 322, 324, 326, and 328. Figure 8A and Figure 8B A top view of the semiconductor structure. Figure 9B It is intercepted along line B-Bʹ. Figure 9A A cross-sectional view of the semiconductor structure.

[0124] In some embodiments, the contact-level dielectric layer 380 includes a dielectric material, such as, for example, silicon dioxide, TEOS, undoped silicon glass, or doped silicon glass, such as BPSG, FSG, PSG, or BSG. In some embodiments, the contact-level dielectric layer 380 includes a dielectric material identical to the dielectric material of the ILD layer 364. In some embodiments, the contact-level dielectric layer 380 includes a dielectric material different from the dielectric material of the ILD layer 364. In some embodiments, the contact-level dielectric layer 380 is deposited using, for example, CVD, PECVD, PVD, or spin coating. In some embodiments, if the contact-level dielectric layer 380 is not self-planarized, the top surface of the contact-level dielectric layer 380 is planarized, for example, by CMP. The planarized top surface of the contact-level dielectric layer 380 is located above the top surfaces of the gate structures 322, 324, 326, and 328.

[0125] refer to Figure 2 Method 200 proceeds to operation 216, in which, according to some embodiments, various contact openings 382, ​​384 are formed in the contact-level dielectric layer 380 and the ILD layer 364. Figure 10A This occurs after various contact openings 382 and 384 are formed in the contact-level dielectric layer 380 and ILD layer 364. Figure 9A and Figure 9B A top view of the semiconductor structure. Figure 10B It is intercepted along line B-Bʹ. Figure 10A A cross-sectional view of the semiconductor structure.

[0126] refer to Figure 10A and Figure 10BThe source / drain contact opening 382 is formed to extend through the contact-level dielectric layer 380, the ILD layer 364, and the oxide layers 352, 354, 356, 358 (if present), wherein each exposes a portion of the source / drain contact regions 342C, 344C, 346C, 348C. The contact opening 384 is formed to extend through the contact-level dielectric layer 380, the ILD layer 364, and the oxide layers 356, 356 (if present), wherein each exposes a portion of the contact region 344B or 346B of one of the pull-up transistors PU-1 and PU-2 and a portion of the gate electrode 374 of the adjacent gate structure (e.g., gate structure 322 or 324).

[0127] In some embodiments, various contact openings 382, ​​384 are formed using a photolithography etching process. In some embodiments, forming contact openings 382, ​​384 includes using one or more etching processes, such as wet etching, dry etching such as RIE or plasma etching, or a combination thereof. In some embodiments, forming contact openings 382, ​​384 includes using one or more etchant materials. In some embodiments, forming contact openings 382, ​​384 includes using one or more of Cl2, SF6, HBr, HCl, CF4, CHF3, C2F6, C4F8, or other similar etchant materials. In some embodiments, a mask layer (not shown) is first deposited over the contact-level dielectric layer 380 and photolithographically patterned to form openings therein. The openings expose portions of the contact-level dielectric layer 380, where contact openings 382, ​​384 are formed. In some embodiments, the mask layer is a photoresist layer or a photoresist layer incorporating multiple hard mask layers. The pattern in the mask layer is transferred via a contact-level dielectric layer 380 and an ILD layer 364 to define contact openings 382, ​​384 therein. Subsequently, the patterned mask layer is removed, for example, using oxygen-based plasma etching.

[0128] refer to Figure 2 Method 200 proceeds to operation 218, wherein, according to some embodiments, various contacts including source / drain contacts 386 and pair contacts 388 are formed. Figure 11A This occurs after the source / drain contact 386 and the contact 388 are formed. Figure 10A and Figure 10B A top view of the semiconductor structure. Figure 11B It is intercepted along line B-Bʹ. Figure 11A A cross-sectional view of the semiconductor structure.

[0129] refer to Figure 11A and Figure 11BSource / drain contacts 386 are formed in source / drain contact openings 382. Source / drain contacts 386 are in direct contact with respective source / drain contact regions 342C, 344C, 346C, and 348C, thereby providing electrical connections to the respective source / drain structures 342, 344, 346, and 348 of transistors PU-1, PU-2, PD-1, PD-2, PG-1, and PG-2 in the SRAM cell. Pair contacts 388 are formed in pair contact openings 384. Pair contacts 388 are in direct contact with the respective pair contact regions 344B and 346B and the gate electrodes 374 of their respective gate structures 322 and 324. Pair contacts 388 form cross-coupled connections between their respective pair contact regions 344B and 346B and the gate structures 322 and 324 of transistors PU-1, PD-1, PU-2, and PD-2 in the SRAM cell. One pair of contacts 388 couples the source / drain structure 344 of transistor PU-1 to the gate structure 324 of transistors PU-2 and PD-2, while another pair of contacts 388 couples the source / drain structure 346 of transistor PU-2 to the gate structure 322 of transistors PU-1 and PD-1.

[0130] Each of the source / drain contacts 386 and the pair of contacts 388 includes a contact liner 392 and a contact plug 394 surrounded by the contact liner 392. In some embodiments, the contact liner 392 includes Ti, Ta, TiN, TaN, or combinations thereof. In some embodiments, the contact plug 394 includes a conductive material, such as, for example, W, Al, Cu, or alloys thereof.

[0131] In some embodiments, various contacts 386, 388 are formed by first depositing a contact liner layer (not shown) along the sidewalls and bottom surfaces of contact openings 382, ​​384 and the top surface of contact-level dielectric layer 380. In some embodiments, the contact liner layer is deposited using a conformal deposition process such as CVD or ALD. A conductive contact material layer (not shown) is then deposited on the contact liner layer to fill contact openings 382, ​​384. In some embodiments, the conductive contact material layer is deposited using CVD, PVD, electroplating, or other suitable deposition processes. A planarization process such as CMP is used to remove portions of the conductive contact material layer and contact liner layer located above the top surface of contact-level dielectric layer 380. The remaining portions of the contact liner layer within each of the contact openings 382, ​​384 constitute contact liner 392, while the remaining portions of the conductive contact material layer within each of the contact openings 382, ​​384 constitute contact plug 394.

[0132] Because the ozone wet cleaning method used in this disclosure helps to form patterned photoresist with improved profiles (the profiles have no slots on the sidewalls of the patterned photoresist layer 360), it eliminates the risk that dopants will be implanted via slots into the portions of the source / drain structures 344, 346 through the patterned photoresist layer 360 during the implantation process of contact regions 344C, 346C. As a result, leakage to contact 388 is avoided, thereby improving device stability.

[0133] One aspect of this specification relates to a method for forming a semiconductor structure. The method includes forming a gate structure over an active region of a substrate. The method further includes forming an epitaxial layer over a portion of the active region on an opposite side of the gate structure, the epitaxial layer containing a first dopant of a first conductivity type. The method further includes applying a cleaning solution containing ozone and deionized water to the epitaxial layer to form an oxide layer on the epitaxial layer. The method further includes forming a patterned photoresist layer over the oxide layer and the gate structure, exposing a portion of the oxide layer through the patterned photoresist layer. The method further includes forming contact regions in a portion of the epitaxial layer not covered by the patterned photoresist layer, the contact regions containing a second dopant of a second conductivity type opposite to the first conductivity type. The method further includes forming contacts covering the contact regions.

[0134] In one or more embodiments disclosed herein, the plurality of sidewalls of the patterned photoresist layer described above do not have slots at the bottom portion of the patterned photoresist layer.

[0135] In one or more embodiments disclosed herein, the first dopant is a p-type dopant and the second dopant is an n-type dopant.

[0136] In one or more embodiments disclosed herein, the oxide layer described above has a thickness ranging from about 0.1 Å to about 0.4 Å.

[0137] In one or more embodiments disclosed herein, the cleaning solution described above has an ozone concentration ranging from about 20 ppm to about 70 ppm.

[0138] In one or more embodiments disclosed herein, the cleaning solution described above is applied at a temperature ranging from about 15°C to about 40°C.

[0139] In one or more embodiments disclosed herein, the epitaxial layer described above comprises silicon germanium.

[0140] In one or more embodiments disclosed herein, the step of forming the contact area includes: using a patterned photoresist layer as an ion implantation mask to implant a second dopant into the portion of the epitaxial layer not covered by the patterned photoresist layer.

[0141] In one or more embodiments disclosed herein, the cleaning solution is essentially composed of ozone and deionized water.

[0142] In one or more embodiments disclosed herein, the step of forming a contact includes: depositing at least one dielectric layer over an oxide layer and a gate structure; etching at least one dielectric layer and an oxide layer to form a contact opening, the contact opening exposing a contact area; and forming a contact in the contact opening.

[0143] Another aspect of this specification relates to a method for forming a semiconductor structure. The method includes forming a first transistor, the first transistor including a first gate structure and a first source / drain structure on an opposite side of the first gate structure. The method further includes forming a second transistor, the second transistor including a second gate structure and a second source / drain structure on an opposite side of the second gate structure. The method further includes cleaning the surfaces of the first source / drain structure and the second source / drain structure with a cleaning solution containing ozone and deionized water, forming a first oxide layer on the surface of the first source / drain structure and a second oxide layer on the surface of the second source / drain structure. The method further includes forming a patterned photoresist layer to expose a portion of the first source / drain structure adjacent to the second gate structure and a portion of the second source / drain structure adjacent to the first gate structure. The method further includes implanting dopants into the exposed portions of the first source / drain structure and the exposed portions of the second source / drain structure to form a first pair of contact regions in the first source / drain structure and a second pair of contact regions in the second source / drain structure. The method further includes forming a first pair of contact points that contact the first pair of contact point regions and the second gate structure, and a second pair of contact points that contact the second pair of contact point regions and the first gate structure.

[0144] In one or more embodiments disclosed herein, the first oxide layer and the second oxide layer described above independently have a thickness ranging from about 0.1 Å to about 0.4 Å.

[0145] In one or more embodiments disclosed herein, the cleaning solution described above has an ozone concentration ranging from about 20 ppm to about 70 ppm.

[0146] In one or more embodiments disclosed herein, the cleaning solution described above is applied at a temperature of about 15°C to about 40°C.

[0147] In one or more embodiments disclosed herein, the first source / drain structure described above comprises a first semiconductor material, and the first oxide layer comprises an oxide of the first semiconductor material.

[0148] In one or more embodiments disclosed herein, the second source / drain structure described above comprises a second semiconductor material, and the first oxide layer comprises an oxide of the second semiconductor material.

[0149] In one or more embodiments disclosed herein, the first source / drain structure and the second source / drain structure described above include a plurality of dopants of a first conductivity type, and the first pair of contact point regions and the second pair of contact point regions include dopants of a second conductivity type opposite to the first conductivity type.

[0150] In one or more embodiments disclosed herein, the step of forming a patterned photoresist layer includes: depositing a photoresist layer over the first source / drain structure and the second source / drain structure, as well as the first gate structure and the second gate structure; exposing the photoresist layer to a predetermined pattern; and developing the photoresist layer to form a patterned photoresist layer, wherein a plurality of sidewalls of the patterned photoresist layer adjacent to the first source / drain structure and the second source / drain structure have no slots.

[0151] Another aspect of this specification relates to a method for forming a semiconductor structure. The method includes forming a first active region and a second active region on a substrate. The method further includes forming a first gate structure extending over the first active region and a second gate structure extending over the second active region. Each of the first and second gate stacks includes a sacrificial gate stack and gate spacers on the sidewalls of the sacrificial gate stack. The method further includes forming a first source / drain structure on a portion of the first active region not covered by the first gate structure, and forming a second source / drain structure on a portion of the second active region not covered by the second gate structure. The method further includes applying a cleaning solution containing ozone and deionized water to the surfaces of the first and second source / drain structures. Cleaning forms a first oxide layer on the surface of the first source / drain structure and a second oxide layer on the surface of the second source / drain structure. The method further includes forming a patterned photoresist layer to expose a portion of the first source / drain structure adjacent to the second gate structure and a portion of the second source / drain structure adjacent to the first gate structure. The method further includes forming a first pair of contact regions in an exposed portion of a first source / drain structure and a second pair of contact regions in an exposed portion of a second source / drain structure, the first and second pairs of contact regions comprising dopants having a conductivity type opposite to that of the dopants in the first and second source / drain structures. The method further includes depositing a first dielectric layer over a substrate to surround the first and second gate structures. The method further includes forming a functional gate stack to replace the sacrificial gate stack in each of the first and second gate structures. The method further includes depositing a second dielectric layer over the first dielectric layer and the first and second gate structures. The method further includes forming a first pair of contacts and a second pair of contacts within the first and second dielectric layers, the first pair of contacts connecting the first pair of contact regions to the second gate structure, and the second pair of contacts connecting the second pair of contact regions to the first gate structure.

[0152] In one or more embodiments disclosed herein, the method further includes: removing the patterned photoresist layer, wherein removing the patterned photoresist layer removes the first oxide layer and the second oxide layer.

[0153] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such and similar constructs are made without departing from the spirit and scope of this disclosure, and that such and similar constructs can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A method of forming a semiconductor structure, comprising: Comprising: forming a gate structure over an active region of a substrate; forming an epitaxial layer over portions of the active region on opposite sides of the gate structure, the epitaxial layer comprising first dopants of a first conductivity type; applying a cleaning solution comprising ozone and deionized water to the epitaxial layer, thereby forming an oxide layer on the epitaxial layer; forming a patterned photoresist layer over the oxide layer and the gate structure, the patterned photoresist layer exposing a portion of the oxide layer; forming a contact region in the portion of the epitaxial layer not covered by the patterned photoresist layer, the contact region comprising second dopants of a second conductivity type opposite the first conductivity type; and forming a contact overlying the contact region.

2. The method of claim 1, wherein, The sidewalls of the patterned photoresist layer are free of notches at a bottom portion of the patterned photoresist layer.

3. The method of claim 1, wherein, The first dopants are p-type dopants and the second dopants are n-type dopants.

4. The method of claim 1, wherein, The oxide layer has a thickness ranging from 0.1 A to 0.4 A.

5. The method of claim 1, wherein, The cleaning solution has an ozone concentration ranging from 20 ppm to 70 ppm.

6. The method of claim 1, wherein, The cleaning solution is applied at a temperature ranging from 15 °C to 40 °C.

7. The method of claim 1, wherein, The epitaxial layer comprises silicon germanium.

8. The method of claim 1, wherein, The step of forming the contact region comprises implanting the second dopants into the portion of the epitaxial layer not covered by the patterned photoresist layer using the patterned photoresist layer as an ion implantation mask.

9. The method of claim 1, wherein, The cleaning solution consists of ozone and deionized water.

10. The method of claim 1, wherein, The step of forming the contact comprises: depositing at least one dielectric layer over the oxide layer and the gate structure; etching the at least one dielectric layer and the oxide layer to form a contact opening, the contact opening exposing the contact region; and forming the contact in the contact opening.

11. A method of forming a semiconductor structure, comprising: Comprising: forming a first transistor comprising a first gate structure and a first source / drain structure on opposite sides of the first gate structure; forming a second transistor comprising a second gate structure and a second source / drain structure on opposite sides of the second gate structure; cleaning surfaces of the first source / drain structure and the second source / drain structure using a cleaning solution comprising ozone and deionized water, the cleaning forming a first oxide layer on the surfaces of the first source / drain structure and a second oxide layer on the surfaces of the second source / drain structure; forming a patterned photoresist layer to expose a portion of the first source / drain structure adjacent to the second gate structure and a portion of the second source / drain structure adjacent to the first gate structure; implanting dopants into the exposed portions of the first source / drain structure and the second source / drain structure to form a first pair of contact regions in the first source / drain structure and a second pair of contact regions in the second source / drain structure; and forming a first pair of contacts contacting the first pair of contact regions and the second gate structure and a second pair of contacts contacting the second pair of contact regions and the first gate structure.

12. The method of claim 11, wherein, The first oxide layer and the second oxide layer independently have a thickness in a range from 0.1 Å to 0.4 Å.

13. The method of claim 11, wherein, The cleaning solution has an ozone concentration in a range from 20 ppm to 70 ppm.

14. The method of claim 11, wherein, The cleaning solution is applied at a temperature in a range from 15 °C to 40 °C.

15. The method of claim 11, wherein, The first source / drain structure includes a first semiconductor material, and the first oxide layer includes an oxide of the first semiconductor material.

16. The method of claim 11, wherein, The second source / drain structure includes a second semiconductor material, and the first oxide layer includes an oxide of the second semiconductor material.

17. The method of claim 11, wherein, The first source / drain structure and the second source / drain structure include dopants of a first conductivity type, and the first contact region and the second contact region include dopants of a second conductivity type opposite the first conductivity type.

18. The method of claim 11, wherein, The step of forming the patterned photoresist layer includes: depositing a photoresist layer over the first source / drain structure and the second source / drain structure and the first gate structure and the second gate structure; exposing the photoresist layer to a predetermined pattern; and developing the photoresist layer to form the patterned photoresist layer, wherein sidewalls of the patterned photoresist layer adjacent to the first source / drain structure and the second source / drain structure are free of notches.

19. A method of forming a semiconductor structure, comprising: includes: forming a first active region and a second active region on a substrate; forming a first gate structure extending over the first active region and a second gate structure extending over the second active region, each of the first gate structure and the second gate structure including a sacrificial gate stack and gate spacers on sidewalls of the sacrificial gate stack; forming a first source / drain structure on portions of the first active region not covered by the first gate structure and a second source / drain structure on portions of the second active region not covered by the second gate structure; applying a cleaning solution including ozone and deionized water to surfaces of the first source / drain structure and the second source / drain structure, the cleaning forming a first oxide layer on the surfaces of the first source / drain structure and a second oxide layer on the surfaces of the second source / drain structure; forming a patterned photoresist layer to expose a portion of the first source / drain structure proximate to the second gate structure and a portion of the second source / drain structure proximate to the first gate structure; forming a first contact region in the exposed portion of the first source / drain structure and a second contact region in the exposed portion of the second source / drain structure, the first contact region and the second contact region including dopants having a conductivity type opposite dopants in the first source / drain structure and the second source / drain structure; depositing a first dielectric layer over the substrate to surround the first gate structure and the second gate structure; forming a functional gate stack to replace the sacrificial gate stack in each of the first gate structure and the second gate structure; depositing a second dielectric layer over the first dielectric layer and the first gate structure and the second gate structure; and forming a first pair of contacts and a second pair of contacts in the first dielectric layer and the second dielectric layer, the first pair of contacts connecting the first pair of contact regions to the second gate structure, and the second pair of contacts connecting the second pair of contact regions to the first gate structure.

20. The method of claim 19, wherein, further comprising: removing the patterned photoresist layer, wherein removing the patterned photoresist layer removes the first oxide layer and the second oxide layer.

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