A layout method for heterogeneous FPGA

Abstract

The present application discloses a layout method for heterogeneous FPGAs, and relates to the field of FPGA technology. The method converts a user input netlist into an equivalent netlist, and the module size difference between any two functional modules with a traction relationship in the equivalent netlist does not exceed the difference threshold. Then, under the constraints of the position constraint information of the equivalent modules in the equivalent netlist, the layout is solved using functional modules with similar module sizes according to the equivalent netlist, and the legal layout position of the original routable module is restored to complete the layout. The present application converts the problem of mixed layout of functional modules of different module sizes in heterogeneous FPGAs into the layout problem of functional modules of the same specification module size, thereby improving the accuracy of traction and force addition between functional modules, and then improving the layout quality.

Description

Technical Field

[0001] The present invention relates to the field of FPGA technology, and in particular to a layout method of a heterogeneous FPGA. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a chip that is widely used in daily household appliances, large machinery and even aerospace. The use of FPGA chips is inseparable from Electronic Design Automation (EDA) tools. Layout is an important part of EDA tools, which has a great impact on the running speed of the EDA tools themselves and the final quality of the processed circuits. In recent years, the circuit scale of FPGA chips has grown rapidly, making them more powerful, but it also brings challenges to the corresponding EDA tools.

[0003] The main function of layout is to map the instances in the user netlist one by one to the layout positions with actual physical coordinates of the FPGA chip under the optimization goal. The analytical layout algorithm has become one of the mainstream directions of today's layout algorithms because it can use mathematical methods to quickly obtain the global optimal solution.

[0004] However, during the layout process, the analytical layout algorithm will establish the movable modules that need to be laid out as nodes, and the signal connection relationship between the nodes as a point-to-point edge relationship, thereby establishing a force-directed layout algorithm model for iterative solution to complete the layout. But in fact, each module has a certain size, and in heterogeneous FPGAs, the sizes of different modules are also different. Therefore, it is not actually accurate to abstract the module into a node to represent it. In particular, it will lead to inaccurate force addition of the signal connection relationship in the force-directed layout algorithm model, resulting in poor layout quality. Summary of the invention

[0005] The applicant proposes a layout method for heterogeneous FPGAs to solve the problem that the conventional force-directed layout algorithm model directly abstracts each functional module as a node, which causes inaccurate force addition and affects the layout quality. The technical solution of this application is as follows:

[0006] A layout method for a heterogeneous FPGA, the method comprising:

[0007] Obtaining a user input netlist corresponding to the FPGA chip, wherein the user input netlist includes a number of original routable modules that do not have legal layout positions, and a module size difference between at least two of the original routable modules exceeds a difference threshold;

[0008] Convert the user input netlist into an equivalent netlist, wherein the module size difference between any two functional modules having a pulling relationship in the equivalent netlist does not exceed the difference threshold, and the equivalent netlist includes only equivalent modules, or the equivalent netlist includes equivalent modules and original routable modules; each equivalent module is obtained by equivalently obtaining one or more original routable modules in the user input netlist, and the pulling relationship between the functional modules in the equivalent netlist is consistent with the pulling relationship between the original routable modules in the user input netlist;

[0009] Determining position constraint information of each equivalent module in the equivalent netlist;

[0010] Under the constraints of the position constraint information of the equivalent module, the force-directed layout algorithm model is used to solve the layout of the FPGA chip based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout position of each functional module in the equivalent netlist;

[0011] The legal layout positions of the corresponding original routable modules are obtained from the legal layout positions of each equivalent module, and the legal layout positions of all the original routable modules in the user input netlist are obtained to complete the layout of the FPGA chip.

[0012] Its further technical solution is that the equivalent netlist includes a number of non-overlapping virtual small modules that are equivalently split from a large-size routable module and have a traction relationship with other functional modules. Each virtual small module forms an equivalent module. The position constraint information of each virtual small module is the legal layout position of the virtual small module on the FPGA chip. The large-size routable module is the original routable module in the user-input netlist whose module size exceeds the first predetermined size threshold.

[0013] A further technical solution is that the method for determining each virtual small module and its position constraint information in the equivalent netlist includes:

[0014] Based on the traction between the original routable modules, the force-directed layout algorithm model is used to solve the layout of the FPGA chip according to the user input netlist to obtain the initial layout result, and the large-size routable modules to be equivalently split are legalized based on the initial layout result to determine the legal layout position of each large-size routable module on the FPGA chip;

[0015] According to the predetermined splitting rules, each large-size routable module is equivalently split into several non-overlapping virtual small modules, and the legal layout position of each virtual small module on the FPGA chip is obtained based on the legal layout position of the large-size routable module and the relative relationship between each virtual small module and the large-size routable module.

[0016] A further technical solution is that, for a set of traction relationships between each large-size routable module and another functional module, the traction relationship acts on a virtual small module obtained by equivalently splitting the large-size routable module and whose physical position is at a force application point on the large-size routable module in the traction relationship;

[0017] On the basis that each virtual small module is fixed in its own legal layout position, the force-directed layout algorithm model is used based on the traction effect of each virtual small module and the layout of the FPGA chip is solved according to the equivalent netlist.

[0018] Its further technical solution is that the equivalent netlist includes a virtual large module obtained by equivalently merging multiple small-size routable modules, the virtual large module covers all small-size routable modules, the virtual large module forms an equivalent module, the position constraint information of each virtual large module is the relative layout position relationship of multiple original routable modules contained in the virtual large module, and the small-size routable module is an original routable module in the user-input netlist whose module size does not exceed a second predetermined size threshold.

[0019] A further technical solution is that, for a set of traction relationships between each small-size routable module and another functional module, the traction relationship acts on a virtual large module obtained by merging the small-size routable modules, and a force application point of the traction relationship on the virtual large module is located at a physical position of the small-size routable module in the virtual large module;

[0020] On the basis that the relative layout position relationship of each small-sized routable module within the virtual large module remains unchanged, the force-directed layout algorithm model is used based on the traction effect of each functional module and the layout of the FPGA chip is solved according to the equivalent netlist.

[0021] Its further technical solution is that the module sizes of all virtual small modules in the equivalent netlist are equal, or there are at least two virtual small modules with unequal module sizes; the two virtual small modules with unequal module sizes are obtained by equivalently splitting the same large-size routable module, or by equivalently splitting two different large-size routable modules.

[0022] A further technical solution is that the sum of the module areas of all equivalent modules obtained by splitting each large-size routable module is equal to or less than the module area of ​​the large-size routable module.

[0023] A further technical solution is that a large-sized deployable module can be equivalently split to obtain at least one empty small module without any traction relationship, and each empty small module forms an equivalent module.

[0024] A further technical solution is that the module size difference between each vacant small module and any other functional module in the equivalent netlist does not exceed a difference threshold; or the module size difference between the vacant small module and at least one other functional module in the equivalent netlist exceeds the difference threshold.

[0025] A further technical solution is that each small-size routable module that is merged into a virtual large module has at least one group of traction relationships with other functional modules; or, there is at least one small-size routable module on which no traction relationship is applied.

[0026] A further technical solution is that the method further comprises: placing a number of predetermined functional modules in the user input netlist at respective legal layout positions, wherein all functional modules in the user input netlist except the predetermined functional modules are original routable modules;

[0027] Then, under the constraints of the predetermined functional modules being fixed at their respective legal layout positions and the position constraint information of the equivalent modules, the force-directed layout algorithm model is used to solve the layout of the FPGA chip based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout positions of each functional module in the equivalent netlist.

[0028] A further technical solution is that the module size difference between any predetermined functional module and any functional module in the equivalent netlist does not exceed a difference threshold.

[0029] The beneficial effects of this application are:

[0030] The present application provides a layout method for a heterogeneous FPGA. To address the problem caused by the mixed layout of functional modules of different module sizes in a heterogeneous FPGA, the original routable modules are equivalently processed into equivalent modules to obtain an equivalent netlist, and the layout is solved according to the equivalent netlist using functional modules of similar module sizes, and then the legal layout positions of the original routable modules are restored to complete the layout. The problem of mixed layout of functional modules of different module sizes is converted into the layout problem of functional modules of the same specification and size, thereby improving the accuracy of traction and force addition between functional modules, and then improving the layout quality.

[0031] When performing equivalent processing on the original routable modules, the large-size routable modules can be equivalently split and / or the small-size routable modules can be equivalently merged. The equivalent methods are diverse and can meet the layout needs of different scenarios and different functional modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention is a flow chart of a method for layout of a heterogeneous FPGA according to an embodiment.

[0033] Figure 2 It is a schematic diagram of the arrangement structure of functional modules with different module sizes inside a heterogeneous FPGA.

[0034] Figure 3 It is a flow chart of a method for layout of a heterogeneous FPGA according to another embodiment.

[0035] Figure 4 It is a flow chart of a method for equivalently splitting a large-size deployable module into several equivalent modules.

[0036] Figure 5 It is a schematic diagram of the equivalent decomposition of a large-size routable module in an example.

[0037] Figure 6 This is an equivalent splitting diagram of a large-size routable module in another example.

[0038] Figure 7 This is an equivalent splitting diagram of a large-size routable module in another example.

[0039] Figure 8 This is an equivalent splitting diagram of a large-size routable module in another example.

[0040] Fig. 9 It is a flow chart of a method for equivalently merging multiple small-size deployable modules to obtain an equivalent module.

[0041] Fig.10 It is a schematic diagram of the equivalent decomposition of a small-size, routable module in an example. DETAILED DESCRIPTION

[0042] The specific implementation of the present application is further described below in conjunction with the accompanying drawings.

[0043] This application discloses a layout method for heterogeneous FPGAs. Please refer to Figure 1 The method comprises the following steps:

[0044] Step 100, obtaining a user input netlist corresponding to the FPGA chip.

[0045] The user input netlist includes several original routable modules, which are functional modules to be laid out that do not have a legal layout position in the user input netlist. There are at least two original routable modules in the user input netlist whose module size difference exceeds the difference threshold. Therefore, a heterogeneous FPGA can be obtained by completing the design on the FPGA chip according to the user input netlist. The difference threshold can be set by custom settings. If the module size difference exceeds the difference threshold, it means that the size difference between the two original routable modules is large. If the layout is performed according to the traditional method, the force between the two original routable modules will be inaccurate due to the large size difference.

[0046] When comparing the module sizes of two functional modules, the module size difference can be determined based on the module area difference and / or size specification difference of the two functional modules, wherein the module area difference reflects the difference in module areas of the two functional modules, and the absolute area difference and / or relative area difference can be used as the module area difference based on the module area. The size specification difference reflects the difference in size specifications of the two functional modules, and the absolute side length difference and / or relative side length difference can be obtained by comparing the width and height of the two functional modules respectively as the size difference.

[0047] Please refer to the structural diagram of the internal functional modules of a common FPGA chip shown in 2. The FPGA chip includes several functional modules, and the sizes of various functional modules may be the same or different. Generally, the module size of the IOB module and / or CLB module is small, while the module size of the DSP module, BRAM module, Carrychain module, GTH module, etc. is large. For example, the module size difference between the IOB module and the DSP module may exceed the difference threshold.

[0048] In one embodiment, before executing step 200, no legal layout position is specified for any functional module, and all functional modules in the user input netlist are original routable modules. In another embodiment, several predetermined functional modules in the user input netlist are first specified to be placed at their respective legal layout positions, that is, before executing step 200, legal layout positions are first specified for some functional modules, please refer to Figure 3 , then all the functional modules in the netlist input by the user except the predetermined functional modules are original routable modules.

[0049] Step 200, converting the user input netlist into an equivalent netlist, wherein the module size difference between any two functional modules having a pulling relationship in the equivalent netlist does not exceed a difference threshold. The equivalent netlist includes at least one equivalent module having a pulling relationship, each equivalent module is equivalently obtained by one or more original routable modules in the user input netlist, and the pulling relationship between the functional modules in the equivalent netlist is consistent with the pulling relationship between the original routable modules in the user input netlist, that is, when the original routable module is equivalently processed as an equivalent module, the pulling relationship it carries is also inherited to the equivalent module.

[0050] When the original routable modules are equivalent to the corresponding equivalent modules, these original routable modules exist in the equivalent netlist in the form of equivalent modules, and the original routable modules themselves are no longer retained in the equivalent netlist. In one embodiment, the equivalent netlist only includes functional modules belonging to equivalent modules, and does not include any functional modules belonging to original routable modules, that is, each original routable module in the user input netlist is processed as a corresponding equivalent module. In another embodiment, the equivalent netlist includes both equivalent modules and original routable modules, that is, a part of the original routable modules in the user input netlist are processed as corresponding equivalent modules, and the other part of the original routable modules remain unchanged.

[0051] Step 300, determining the position constraint information of each equivalent module in the equivalent netlist, the position constraint information including the constraint information of the absolute position of the functional module on the FPGA chip, and / or including the constraint information of the relative position between the functional modules.

[0052] Step 400, under the constraints of the position constraint information of the equivalent module, the force-directed layout algorithm model is used to solve the layout of the FPGA chip based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout position of each functional module in the equivalent netlist.

[0053] Since the module size differences of the functional modules with a pulling relationship in the equivalent netlist do not exceed the difference threshold, that is, the size difference between any two functional modules with a pulling relationship is small, it can be ensured that the force addition between the two functional modules is more accurate, so that the layout result is more accurate.

[0054] In one embodiment, if the operation of placing the predetermined functional modules at their respective legal layout positions is performed in advance, the module size difference between any predetermined functional module and any functional module in the equivalent netlist does not exceed the difference threshold, that is, since there will also be a traction relationship between the predetermined functional modules placed in advance and the original routable modules, in order to ensure the accuracy of the force between the predetermined functional modules and the functional modules in the equivalent netlist, it is also necessary to ensure that the size difference between the predetermined functional modules and the functional modules in the equivalent netlist is not too large. In addition, when solving the layout in this step, it is necessary to fix the predetermined functional modules at their respective legal layout positions and the position constraint information of the equivalent modules, and use the force-directed layout algorithm model to solve the layout of the FPGA chip based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout positions of each functional module in the equivalent netlist.

[0055] Step 500, the legal layout position of the corresponding original routable module is obtained from the legal layout position of each equivalent module, that is, according to the equivalent relationship between the equivalent module and the original routable module, the equivalent module is restored to the original routable module, and the legal layout position of the original routable module before equivalence can be obtained. If the equivalent netlist only includes equivalent modules, the legal layout positions of all the original routable modules in the user input netlist can be obtained after restoration. If the equivalent netlist includes the original routable modules in addition to the equivalent modules, the original routable modules retained in the equivalent netlist can also obtain the legal layout position through step 400, and combined with the legal layout position of the original routable modules restored from the equivalent modules, the legal layout positions of all the original routable modules in the user input netlist can also be obtained.

[0056] If there are any predetermined functional modules, then combined with the legal layout positions of the predetermined functional modules, the legal layout positions of all functional modules in the user input netlist can be obtained, thereby completing the layout of the FPGA chip.

[0057] In the above step 200, when the original routable module is equivalently processed into an equivalent module, there are mainly two situations: (1) a large-sized routable module is equivalently split into several small-sized virtual small modules. A large-sized routable module is an original routable module in the user-input netlist whose module size exceeds a first predetermined size threshold. The module size can also be measured using the module area and / or module size specification. (2) A large-sized virtual large module is obtained by equivalently merging multiple small-sized routable modules. A small-sized routable module is an original routable module in the user-input netlist whose module size does not exceed a second predetermined size threshold.

[0058] When performing equivalent processing on the original routable modules in the user-input netlist, it may include only the first case mentioned above, and only perform equivalent splitting operations on the original routable modules. Or it may include only the second case mentioned above, and only perform equivalent merging operations on the original routable modules. Or both the first case and the second case mentioned above exist, that is, equivalent splitting operations are performed on a part of the original routable modules, and equivalent merging operations are performed on another part of the original routable modules. The present application describes the equivalent processing operations of the first case and the second case mentioned above respectively in the following two embodiments. If the equivalent processing operations include both of the above cases, they can be obtained by combining the following two embodiments.

[0059] 1. When converting the user input netlist into an equivalent netlist, the large-size routable module is equivalently split into a number of small-size virtual small modules. This embodiment includes the following steps, please refer to Figure 4 :

[0060] Step 410, obtaining a user input netlist corresponding to the FPGA chip.

[0061] Step 420, based on the pulling effect between the original routable modules, a force-directed layout algorithm model is used to solve the layout of the FPGA chip according to the user input netlist to obtain an initial layout result.

[0062] This step solves and layouts all functional modules in the user input netlist. Therefore, when there is a predetermined functional module, this step solves and layouts the FPGA chip according to the user input netlist under the constraint that the predetermined functional module is laid out in the corresponding legal layout position to obtain the initial layout result. The guided layout algorithm model is a commonly used layout algorithm, and this application does not elaborate on its specific operation.

[0063] Step 430 , based on the initial layout result, legalization processing is performed on the large-size routable modules to be equivalently split, and the legal layout position of each large-size routable module on the FPGA chip is determined.

[0064] In the initial layout results, there is often a phenomenon that the layout positions of some functional modules overlap, and the layout positions of these functional modules in the initial layout results are illegal. Conventional layout methods require global legalization of all original routable modules in the initial layout results, and adjust the layout positions of each functional module so that each functional module has its own corresponding legal layout position. However, the present application does not do this. After obtaining the initial layout results, the present application temporarily does not consider other original routable modules, but first legalizes all large-sized routable modules that need to be equivalently split later, obtains the legal layout positions of each large-sized routable module, and fixes each large-sized routable module to the corresponding legal layout position. The specific legalization method can be implemented using conventional methods, which will not be elaborated in this application.

[0065] Step 440, according to a predetermined splitting rule, each large-size routable module is equivalently split into a number of virtual small modules that do not overlap and have a pulling relationship with other functional modules, and each virtual small module forms an equivalent module. And the module size difference between each virtual small module with a pulling relationship and other functional modules in the equivalent netlist does not exceed the difference threshold.

[0066] The virtual small modules obtained by splitting are within the range of the legal layout position of the large-size routable module. The relative relationship between each virtual small module and the large-size routable module is known during the equivalent splitting, that is, the relative position of the virtual small module within the large-size routable module is known, and the module size of each virtual small module can also be determined. For example, Figure 5In the splitting diagram shown, when the large-size routable module M is equivalently split into 8 virtual small modules according to the predetermined splitting rules, the relative relationship between these 8 virtual small modules and the large-size routable module M is known, and the module size of each virtual small module is also known.

[0067] There is at least one set of traction relationship between the large-size routable module and other functional modules, where the other functional modules include at least one of other original routable modules and predetermined functional modules. The large-size routable module can have a traction relationship with one or more other functional modules, for example, please refer to Figure 5 There is a traction relationship between the large-size deployable module M and the five other functional modules A, B, C, D, and E.

[0068] There can also be one or more pull relationships between the large-size deployable module and each other functional module. Figure 5 There are three groups of traction relations LA1, LA2 and LA3 between the large-size routable module M and the functional module A, two groups of traction relations LB1 and LB2 between the large-size routable module M and the functional module B, one group of traction relations LC1 between the large-size routable module M and the functional module C, one group of traction relations LD1 between the large-size routable module M and the functional module D. There is one group of traction relations LE1 between the large-size routable module M and the functional module E.

[0069] For any set of traction relationships between each large-size routable module and another functional module, the traction relationship acts on a force point on the large-size routable module. After completing the initial layout results, it is possible to determine the sets of traction relationships connected to the large-size routable modules and the force points of each set of traction relationships on the large-size routable modules. For example Figure 5 It can be seen that the various groups of traction relationships between the large-size deployable module M and other functional modules A, B, C, D, and E are at the force application points on the large-size deployable module M, that is, the connection points with the large-size deployable module M in the figure.

[0070] The traction relationship between other functional modules and the large-size routable module acts on the virtual small modules obtained by splitting. Specifically, for a set of traction relationships between each large-size routable module and another functional module, the traction relationship acts on the virtual small module obtained by equivalent splitting of the large-size routable module, which is physically located at the force application point of the traction relationship on the large-size routable module. For example Figure 5 In the splitting schematic diagram shown, there is a set of traction relationship LD1 between the large-size routable module M and the functional module D, which acts on the virtual small module 5.

[0071] A virtual module has one or more traction relationships. When a virtual module has multiple traction relationships, these multiple traction relationships are used to connect the same or different functional modules. Figure 5 In the figure, two sets of traction relationships LA2 and LB1 are applied to the virtual small module 2 obtained by splitting. The two sets of traction relationships are used to connect two different other functional modules A and B respectively.

[0072] Step 450, obtain the legal layout position of each virtual small module on the FPGA chip based on the legal layout position of the large-size routable module and the relative relationship between each virtual small module and the large-size routable module, and determine that the position constraint information of each virtual small module is the legal layout position of the virtual small module on the FPGA chip.

[0073] Based on the known legal layout positions of the large-size routable modules on the FPGA chip, the legal layout positions of each virtual small module can be determined in combination with the relative relationship between the virtual small module and the large-size routable modules. In this embodiment, the legal layout position of each virtual small module on the FPGA chip is the position constraint information of the virtual small module, which is the absolute position constraint information.

[0074] Step 460, on the basis of each virtual small module being fixed at its own legal layout position, the force-directed layout algorithm model is used based on the traction effect of each virtual small module to solve the layout of the FPGA chip according to the equivalent netlist, so as to obtain the legal layout position of each functional module in the equivalent netlist.

[0075] The legal layout position of each virtual small module is fixed, and each virtual small module is abstracted as a node, and other functional modules are also abstracted as a node respectively. Then, the layout can be solved according to the equivalent netlist using the force-directed layout algorithm model, so that other functional modules can be solved and laid out under the traction of virtual small modules of the same module size. The traction relationship between functional modules is more accurate, thereby making the layout result better.

[0076] When there are predetermined functional modules, the predetermined functional modules and virtual small modules are fixed at their respective legal layout positions, and the FPGA chip is solved and laid out according to the equivalent netlist to obtain the legal layout positions of each functional module in the equivalent netlist.

[0077] Step 470, restore each virtual small module to a large-size routable module before equivalent splitting, obtain the legal layout positions of all original routable modules in the user input netlist, and complete the layout of the FPGA chip.

[0078] In step 440 of this embodiment, in one case, a large-sized routable module is equivalently split only to obtain virtual small modules with traction relationship, such as Figure 7 As shown, the large-size routable module M is split into equivalent modules 1, 2, 3, 4, 5, and 6. These equivalent modules are all virtual small modules that have at least one set of traction relationships. In another case, a large-size routable module is not only split into equivalent small virtual modules with traction relationships, but also split into at least one vacant small module without any traction relationship, and each vacant small module forms an equivalent module. For example Figure 5 and 6 The large-size deployable module M is split into equivalent modules 1 to 8, among which equivalent modules 1, 2, 3, 4, 5, and 6 all have at least one set of traction relationships and are virtual small modules, while equivalent modules 7 and 8 do not have any traction relationships and are vacant small modules.

[0079] Since the virtual small modules have a pulling relationship, in order to ensure that the functional modules in the equivalent netlist that have a pulling relationship are of comparable size and accurate force application, the module size difference between each virtual small module and other functional modules in the equivalent netlist that have a pulling relationship does not exceed the difference threshold. Since the vacant small modules do not have a pulling relationship, they actually have almost no effect on the force application accuracy of the pulling relationship between functional modules when resolving the layout. Therefore, in one optional embodiment, the module size difference between each vacant small module that does not have any pulling relationship and any other functional module in the equivalent netlist does not exceed the difference threshold; or the module size difference between the vacant small module and at least one other functional module in the equivalent netlist exceeds the difference threshold. For example, it can be as follows Figure 5 As shown in FIG. 6 , the control modules 7 and 8 are similar in size to the virtual modules, or can be Figure 8 As shown, the module size of the vacant small module 7 is relatively large, that is, the vacant small module does not have a strong module size constraint, and its module size will hardly affect the subsequent layout quality.

[0080] exist Figure 4 In the illustrated embodiment, each equivalent module obtained by splitting a large-size routable module has a certain module size and covers a certain layout area. The relationship between the multiple equivalent modules obtained by the equivalent splitting and the module area of ​​the original large-size routable module is as follows: (1) The sum of the module areas of all equivalent modules obtained by splitting each large-size routable module is equal to the module area of ​​the large-size routable module, for example Figure 5As shown in the figure, the large-size routable module M is split into equivalent modules 1 to 8. These 8 virtual small modules each have a certain module size and are arranged adjacent to each other. The sum of the module areas of the 8 equivalent modules is equal to the module area of ​​the large-size routable module M. (2) The sum of the module areas of all equivalent modules obtained by splitting each large-size routable module is less than the module area of ​​the large-size routable module. For example Figure 6 As shown in Figure 2, the large-size deployable module M is also decomposed into equivalent modules 1 to 8. Each of these 8 equivalent modules has a certain module size, but compared to Figure 5 , there is a predetermined distance between two equivalent modules, so that the sum of the module areas of the eight equivalent modules is smaller than the module area of ​​the large-size deployable module M. Figure 7 As shown, the large-size deployable module M is only split at the force application point to obtain virtual small modules 1 to 6. These 6 virtual small modules are also adjacent to each other, but do not cover the entire area of ​​the large-size deployable module M, so that the sum of the module areas of the 6 virtual small modules is smaller than the module area of ​​the large-size deployable module M.

[0081] contrast Figure 5-8 It can be seen that there are multiple predetermined splitting rules for a large-sized routable module. The number, physical position and module size of equivalent modules obtained by equivalent splitting can be determined according to actual conditions, but it is necessary to ensure that there is a virtual small module at each force application point of each group of traction relationships of the large-sized routable module. Therefore, the module sizes of the virtual small modules obtained by splitting a large-sized routable module are equal, such as Figure 4 Alternatively, there are at least two virtual small modules whose module sizes are not equal, such as Figure 5 , the module sizes of the virtual small module 2 and the virtual small module 8 are equal and larger than the sizes of other virtual small modules.

[0082] As described above, a method for performing an equivalent splitting operation on a large-size routable module is introduced. In actual application, the user inputs one or more large-size routable modules in the netlist on which the equivalent splitting operation is performed. When multiple large-size routable modules are included, the predetermined splitting rules used to perform the equivalent splitting operation on each large-size routable module are the same, or the predetermined splitting rules used to perform the equivalent splitting operation on at least two large-size routable modules are different. Ultimately, in the equivalent netlist, the module sizes of all virtual small modules are equal, or there are at least two virtual small modules with unequal module sizes, and the two virtual small modules with unequal module sizes are equivalently split from the same large-size routable module, or are equivalently split from two different large-size routable modules. For example, for a BRAM, it can be divided into two virtual small modules according to the following formula: Figure 5 The predetermined splitting rules shown in the figure are used for equivalent splitting, and for another BRAM, the Figure 6 The predetermined splitting rules shown in the figure are used for equivalent splitting. For one DSP, Figure 7 The predetermined splitting rules shown perform equivalent splitting.

[0083] 2. When converting the user input netlist into an equivalent netlist, several small-size routable modules are equivalently merged into a virtual large module. This embodiment includes the following steps, please refer to Fig. 9 :

[0084] Step 910, obtaining a user input netlist corresponding to the FPGA chip.

[0085] Step 920, multiple small-sized routable modules in the netlist input by the user are equivalently merged into a virtual large module, and the obtained virtual large module covers all small-sized routable modules, and one virtual large module forms an equivalent module. When the virtual large module is merged, the relative relationship between each small-sized routable module and the virtual large module is known, and the coverage area of ​​the merged virtual large module can also be determined.

[0086] The equivalent merging situation can be regarded as the opposite of the equivalent splitting. Therefore, similarly, when the virtual large module covers all the small-sized routable modules, the module area is equal to or greater than the sum of the module areas of all the small-sized routable modules. In one embodiment, each small-sized routable module that is merged into a virtual large module has at least one group of traction relationships with other functional modules; or, there is at least one small-sized routable module that does not have any traction relationship. Fig.10 As shown, the small-size routable modules 1 to 8 are equivalently merged to obtain a virtual large module M. A traction relationship acts on the small-size routable modules 1 to 6, while no traction relationship acts on the small-size routable modules 7 and 8.

[0087] For a set of traction relationships between each small-sized routable module and another functional module, the traction relationship acts on the virtual large module obtained by merging the small-sized routable modules. Specifically, the force application point of the traction relationship on the virtual large module is located at the physical position of the small-sized routable module in the virtual large module before equivalent merging.

[0088] Step 930, determine the relative layout position relationship of the multiple original routable modules contained in each virtual large module as the position constraint information of the virtual large module. The multiple small-sized routable modules equivalently merged into one virtual large module are generally functional modules with related functions. The relative layout position relationship between these small-sized routable modules needs to remain unchanged during layout, and the relative layout position relationship of these multiple small-sized routable modules is pre-set.

[0089] For example, a typical application is to merge multiple small-sized routable modules within a Macro, Block, or IP into a virtual large module, thereby realizing the layout of the Macro, Block, or IP, ensuring that the relative layout position relationship and timing relationship between the small-sized routable modules within the constraint area remain unchanged.

[0090] Step 940, on the basis of the relative layout position relationship of each small-sized routable module in the virtual large module remains unchanged, the FPGA chip is solved and laid out according to the equivalent netlist using the force-directed layout algorithm model based on the pulling effect of each functional module. When solving the layout, this step solves the layout of the equivalent large module as a whole. When the layout position of the equivalent large module changes, the layout position of its corresponding small-sized routable module also changes accordingly. In the process of changing the layout position of the equivalent large module, the relative layout position of each small-sized routable module remains unchanged.

[0091] Step 950, restore each virtual large module to a small-size routable module before equivalent splitting, obtain the legal layout positions of all original routable modules in the user input netlist, and complete the layout of the FPGA chip.

[0092] Through step 940, the legal layout position of the virtual large module can be obtained, and combined with the relative relationship between each small-size routable module and the virtual large module, the legal layout position of each small-size routable module on the FPGA chip can be determined.

Claims

1. A layout method for heterogeneous FPGA, characterized in that: The method comprises: Obtaining a user input netlist corresponding to the FPGA chip, wherein the user input netlist includes a number of original routable modules that do not have legal layout positions, and a module size difference between at least two of the original routable modules exceeds a difference threshold; Convert the user input netlist into an equivalent netlist, wherein the module size difference between any two functional modules having a pulling relationship in the equivalent netlist does not exceed the difference threshold, and the equivalent netlist includes only equivalent modules, or the equivalent netlist includes equivalent modules and original routable modules; each equivalent module is obtained by equivalently obtaining one or more original routable modules in the user input netlist, and the pulling relationship between the functional modules in the equivalent netlist is consistent with the pulling relationship between the original routable modules in the user input netlist; Determining position constraint information of each equivalent module in the equivalent netlist; Under the constraints of the position constraint information of the equivalent module, the force-directed layout algorithm model is used to solve the layout of the FPGA chip based on the traction effect of each functional module in the equivalent netlist to obtain the legal layout position of each functional module in the equivalent netlist; The legal layout positions of the corresponding original routable modules are obtained from the legal layout positions of the equivalent modules, and the legal layout positions of all the original routable modules in the user input netlist are obtained to complete the layout of the FPGA chip.

2. The method according to claim 1, characterized in that The equivalent netlist includes a number of non-overlapping virtual small modules that are equivalently split from a large-size routable module and have a traction relationship with other functional modules. Each virtual small module forms an equivalent module. The position constraint information of each virtual small module is the legal layout position of the virtual small module on the FPGA chip. The large-size routable module is the original routable module in the user-input netlist whose module size exceeds the first predetermined size threshold.

3. The method according to claim 2, characterized in that The method for determining each virtual small module and its position constraint information in the equivalent netlist includes: Based on the traction between the original routable modules, the force-directed layout algorithm model is used to solve the layout of the FPGA chip according to the user input netlist to obtain an initial layout result, and based on the initial layout result, the large-size routable modules to be equivalently split are legalized to determine the legal layout position of each large-size routable module on the FPGA chip; Each large-size routable module is equivalently split into a number of non-overlapping virtual small modules according to a predetermined splitting rule, and the legal layout position of each virtual small module on the FPGA chip is obtained according to the legal layout position of the large-size routable module and the relative relationship between each virtual small module and the large-size routable module.

4. The method according to claim 2, characterized in that: For a set of traction relations between each large-size routable module and one other functional module, the traction relations act on virtual small modules obtained by equivalent decomposition of the large-size routable module and whose physical position is at the force application point of the traction relations on the large-size routable module; On the basis that each virtual small module is fixed at its own legal layout position, the FPGA chip is solved and laid out according to the equivalent netlist using a force-directed layout algorithm model based on the traction effect of each virtual small module.

5. The method according to claim 1, characterized in that The equivalent netlist includes a virtual large module obtained by equivalently merging multiple small-size routable modules, the virtual large module covers all small-size routable modules, the virtual large module forms an equivalent module, the position constraint information of each virtual large module is the relative layout position relationship of multiple original routable modules contained in the virtual large module, and the small-size routable module is an original routable module whose module size in the user-input netlist does not exceed a second predetermined size threshold.

6. The method according to claim 5, characterized in that For a set of traction relationships between each small-sized routable module and one other functional module, the traction relationship acts on a virtual large module obtained by merging the small-sized routable modules, and a force application point of the traction relationship on the virtual large module is located at a physical position of the small-sized routable module in the virtual large module; Then, on the basis that the relative layout position relationship of each small-sized routable module within the virtual large module remains unchanged, the force-directed layout algorithm model is used based on the traction effect of each functional module and the layout of the FPGA chip is solved according to the equivalent netlist.

7. The method according to claim 2, characterized in that The module sizes of all virtual small modules in the equivalent netlist are equal, or there are at least two virtual small modules with unequal module sizes; the two virtual small modules with unequal module sizes are obtained by equivalently splitting the same large-size routable module, or by equivalently splitting two different large-size routable modules.

8. The method according to claim 2, characterized in that: The sum of the module areas of all equivalent modules obtained by splitting each large-size routable module is equal to or less than the module area of ​​the large-size routable module.

9. The method according to claim 2, characterized in that: A large-sized deployable module can also be equivalently split to obtain at least one empty small module without any traction relationship, and each empty small module forms an equivalent module.

10. The method according to claim 9, characterized in that The module size difference between each vacant small module and any other functional module in the equivalent netlist does not exceed the difference threshold; or the module size difference between the vacant small module and at least one other functional module in the equivalent netlist exceeds the difference threshold.

11. The method according to claim 5, characterized in that Each small-sized routable module that is combined into a virtual large module is respectively subjected to at least one group of traction relationships with other functional modules; Alternatively, there is at least one small-sized routable module on which no pulling relationship is applied.

12. The method according to claim 1, characterized in that The method further comprises: placing a plurality of predetermined functional modules in the user input netlist at respective legal layout positions, wherein all functional modules in the user input netlist except the predetermined functional modules are original routable modules; Then, with the predetermined functional modules fixed at their respective legal layout positions and under the constraints of the position constraint information of the equivalent modules, the FPGA chip is solved and laid out using a force-directed layout algorithm model based on the traction of each functional module in the equivalent netlist to obtain the legal layout positions of each functional module in the equivalent netlist.

13. The method according to claim 12, characterized in that A module size difference between any one of the predetermined functional modules and any one of the functional modules in the equivalent netlist does not exceed a difference threshold.

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