A display device

Abstract

The present application discloses a display device, including: a controller, a power management circuit and N display modules; each display module includes M driving circuits and M display arrays, each driving circuit is used to drive the display array connected to itself, and each display array includes at least one display lamp; the power management circuit is used to output the voltage specified by the voltage control signal to each display array to power each display array; the M driving circuits in any one display module are cascaded through serial control lines; the controller is used to address and read data of each driving circuit through each serial control line, and send information to each driving circuit through each shared data line to control each driving circuit and each display lamp; each shared data line represents different data through different duty cycles. By applying the scheme of the present application, a distributed display device is realized, and the complexity of circuit design and data transmission method is reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a display device. Background Art

[0002] In recent years, display devices with distributed drivers have been increasingly widely used. For example, distributed LED display devices are commonly used, which usually use common command lines and serial communication lines to complete IC addressing, configuration and operation mode control. The line design and data transmission methods are relatively complex.

[0003] In summary, how to effectively realize a distributed display device and reduce the complexity of circuit design and data transmission methods is a technical problem that those skilled in the art urgently need to solve. Summary of the invention

[0004] An object of the present invention is to provide a display device to effectively realize a distributed display device and reduce the complexity of circuit design and data transmission method.

[0005] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0006] A display device comprises: a controller, a power management circuit and N display modules;

[0007] Each of the display modules comprises: M driving circuits and M display arrays respectively connected to the M driving circuits, each driving circuit is used to drive the display array connected to itself, wherein each display array comprises at least one display light, and M and N are both positive integers;

[0008] The power management circuit is connected to the controller and each of the display arrays respectively, and is used to receive a voltage control signal sent by the controller and output a voltage specified by the voltage control signal to each of the display arrays to supply power to each of the display arrays;

[0009] For any one of the display modules, the M driving circuits in the display module are cascaded through a serial control line corresponding to the display module, and are connected to corresponding IO ports of the controller through the serial control line, and the M driving circuits in the display module are all connected to the controller through a shared data line corresponding to the display module;

[0010] The controller is used to address and read data of each driving circuit in the corresponding display module through each of the serial control lines, and to send information to each driving circuit in the corresponding display module through each shared data line to control each driving circuit and each display light, and different data are represented by different duty cycles on any one of the shared data lines.

[0011] Preferably, it also includes: a plurality of display arrays and a scanning drive circuit;

[0012] Each driving circuit in each of the display modules is connected to K display arrays, and each driving circuit is used to drive the K display arrays connected to itself, where K is a positive integer not less than 2;

[0013] The scan drive circuit is respectively connected to the power management circuit, the controller and each of the display arrays, and is used to receive power from the power management circuit, and determine the scan timing according to the scan control signal output by the controller, and cyclically output the voltage specified by the voltage control signal through K output terminals in sequence, so that the K display arrays connected to any drive circuit can be cyclically powered.

[0014] Preferably, the types of information transmitted on any one of the shared data lines include data packets and command packets, wherein the data packets include SoT, CID, DW and DATA; and the command packets include SoT, CID, CW and CMD;

[0015] Among them, Sot represents the set transmission start data, CID represents the address of the packet specified object, CW represents the set command flag, DW represents the set data flag, CMD represents the command content of the command packet, and DATA represents the data content of the data packet.

[0016] Preferably, when the controller reads data from each driving circuit in the corresponding display module through each serial control line, it is specifically used to:

[0017] For any display module, after writing a data read instruction to the shared data line corresponding to the display module, data of the M driving circuits in the display module are read through the serial control line corresponding to the display module in the order of the first driving circuit to the Mth driving circuit in the display module, or in the order of the Mth driving circuit to the first driving circuit in the display module.

[0018] Preferably, when the controller addresses each driving circuit in the corresponding display module through each serial control line, it is specifically used to:

[0019] For any one display module, addressing of M driving circuits in the display module is performed in the order of the first driving circuit to the Mth driving circuit in the display module, or in the order of the Mth driving circuit to the first driving circuit in the display module;

[0020] Furthermore, for any one driving circuit, when the driving circuit receives a pulse signal through the connected serial control line and receives an addressing packet through the connected shared data line, the driving circuit uses the address carried in the addressing packet as the address allocated to the driving circuit and stores it;

[0021] The addressed packet includes an address packet header and an address in a set format.

[0022] Preferably, each of the driving circuits comprises:

[0023] A serial input / output interface, used to connect corresponding serial control lines and shared data lines, so that the controller addresses and reads data from the drive circuit through the serial control lines, and the controller sends information to the drive circuit through the shared data lines;

[0024] A timing control unit connected to the serial input / output interface, used for decoding and deserializing data and storing the decoded and deserialized display data in a first storage unit, and controlling the output of a pulse amplitude modulation unit and a pulse width modulation unit through the data in the first storage unit, so as to control each display lamp connected to the drive circuit;

[0025] A first storage unit connected to the timing control unit and used for data storage;

[0026] A second storage unit connected to the timing control unit and used for address storage;

[0027] A pulse amplitude modulation unit connected to the timing control unit, used for outputting a Y-channel PAM signal under the control of the timing control unit;

[0028] A pulse width modulation unit connected to the timing control unit, used for outputting a Y-channel PWM signal under the control of the timing control unit;

[0029] A gain-adjustable current source driving unit connected to the pulse amplitude modulation unit and the pulse width modulation unit, respectively, for outputting Y-channel current driving signals according to the control of Y-channel PAM signals and Y-channel PWM signals, so as to drive a display array connected to the driving circuit, wherein the power of each channel of current driving signals is jointly controlled by a corresponding 1-channel PAM signal and 1-channel PWM signal;

[0030] The channel status monitoring circuit is used to monitor the circuit information of each current driving signal of the Y channel.

[0031] Preferably, the gain adjustable current source driving unit is specifically used for:

[0032] Performing global current setting of Y groups of current sources through a first current adjustment instruction, and performing respective current setting of the Y groups of current sources through Y second current adjustment instructions to complete current correction;

[0033] According to the control of Y-channel PAM signal and Y-channel PWM signal, Y-channel current driving signal is output to drive the display array connected to the driving circuit, wherein the power of each current driving signal is jointly controlled by the corresponding 1-channel PAM signal and 1-channel PWM signal.

[0034] Preferably, the controller is also used for:

[0035] The circuit information monitored by each of the channel status monitoring circuits is read, and the output voltage of the power management circuit is adjusted so that the output voltage of the power management circuit reaches the minimum voltage value required to power each of the display arrays.

[0036] Preferably, the controller is also used for:

[0037] The monitoring mode of each channel status monitoring circuit is adjusted through the monitoring mode adjustment instruction; wherein the adjustable items of the monitoring mode include: a first adjustable item for indicating the monitoring trigger timing, and the monitoring trigger timing includes: periodic monitoring, monitoring when receiving a monitoring instruction, and monitoring when receiving a monitoring instruction and in a standby state; a second adjustable item for indicating the duration of a single monitoring, and a third adjustable item for indicating the selection of a monitoring channel.

[0038] Preferably, the controller is also used for:

[0039] Reading the circuit information monitored by each of the channel status monitoring circuits and performing brightness correction on the display device to obtain a brightness correction result;

[0040] Based on the brightness correction result, information is sent to each driving circuit in the corresponding display module through each shared data line to complete the brightness correction of each display lamp.

[0041] Preferably, the controller is also used for:

[0042] The circuit information monitored by each of the channel status monitoring circuits is read and fault detection is performed to obtain a fault detection result.

[0043] Preferably, the controller is also used for:

[0044] A low power consumption command is sent to each driving circuit in the corresponding display module through each shared data line, so that the value of each current driving signal is 0.

[0045] By applying the technical solution provided in the embodiment of the present invention, the power management circuit 20 is connected to the controller 10 and each display array respectively, and can receive the voltage control signal sent by the controller 10 and output the voltage specified by the voltage control signal to each display array to power each display array. Each display module 30 includes: M driving circuits, and M display arrays respectively connected to the M driving circuits, each driving circuit is used to drive the display array connected to itself, and each display array includes at least one display light. Therefore, it can be seen that the solution of the present application realizes a distributed display device, and under the control of the controller 10, each display array can be powered by the power management circuit 20. For any one display module 30, the M driving circuits in the display module 30 are cascaded through the serial control line corresponding to the display module 30. For any one display module 30, the controller 10 can address and read data of each driving circuit in the display module 30 through the serial control line corresponding to the display module 30. Therefore, it can be seen that the addressing and data reading of each driving circuit in the display device can be conveniently realized through each serial control line, and the circuit design is simple. When the controller 10 sends information to each driving circuit in the corresponding display module 30 through each shared data line, in the scheme of the present application, different data are represented by different duty cycles on any one shared data line, so only N shared data lines are needed to send information to N display modules 30, the circuit design is simple, and the complexity of the data transmission method is reduced. In summary, the present application effectively realizes a distributed display device and reduces the complexity of the circuit design and the data transmission method. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1 A schematic diagram of the structure of the display device in the present invention;

[0048] Figure 2a is another structural schematic diagram of the display device in the present invention;

[0049] Figure 2b A schematic diagram of a scanning sequence in a specific embodiment of the present invention;

[0050] Figure 3 It is a structural schematic diagram of a driving circuit in a specific implementation manner of the present invention;

[0051] Figure 4 A functional schematic diagram of a gain-adjustable current source driving unit performing global current setting and current correction in a specific implementation manner of the present invention;

[0052] Figure 5 A schematic diagram of duty cycle coding in a specific implementation manner of the present invention;

[0053] Figure 6 A schematic diagram of format settings of a data packet and a command packet in a specific implementation mode of the present invention;

[0054] Figure 7a A timing diagram of reading back through SIOP in a specific implementation manner of the present invention;

[0055] Figure 7b A timing diagram of reading back through SION in a specific implementation manner of the present invention;

[0056] Figure 8a A first timing diagram of addressing each driving circuit of a display module in a specific implementation manner of the present invention;

[0057] Figure 8b A second timing diagram of addressing each driving circuit of a display module in a specific implementation manner of the present invention;

[0058] Figure 9a A schematic diagram of a timing sequence for monitoring when receiving a monitoring instruction in a specific implementation mode of the present invention;

[0059] Figure 9b A timing diagram of selecting periodic monitoring in a specific implementation manner of the present invention;

[0060] Fig.10 This is a flowchart of adjusting VLED in a specific implementation mode of the present invention;

[0061] Fig.11 The figure is a flowchart of the implementation of brightness correction in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0062] The core of the present invention is to provide a display device, which effectively realizes a distributed display device and reduces the complexity of circuit design and data transmission mode.

[0063] In order to enable those skilled in the art to better understand the scheme of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] Please refer to Figure 1 , Figure 1 Schematic diagram of the structure of a display device in the present invention, the display device may include: a controller 10, a power management circuit 20 and N display modules 30;

[0065] Each display module 30 includes: M driving circuits and M display arrays respectively connected to the M driving circuits, each driving circuit is used to drive the display array connected to itself, wherein each display array includes at least one display light, and M and N are both positive integers;

[0066] The power management circuit 20 is connected to the controller 10 and each display array respectively, and is used to receive the voltage control signal sent by the controller 10 and output the voltage specified by the voltage control signal to each display array to power each display array;

[0067] For any one display module 30, the M driving circuits in the display module 30 are cascaded through the serial control line corresponding to the display module 30, and are connected to the corresponding IO port of the controller 10 through the serial control line, and the M driving circuits in the display module 30 are connected to the controller 10 through the shared data line corresponding to the display module 30;

[0068] The controller 10 is used to address and read data of each driving circuit in the corresponding display module 30 through each serial control line, and send information to each driving circuit in the corresponding display module 30 through each shared data line to control each driving circuit and each display light, and on any one shared data line, different data is represented by different duty cycles.

[0069] In the solution of the present application, different duty cycles are used to represent different data on any shared data line. Therefore, the controller 10 needs to have a duty cycle encoding function. Through N shared data lines, the controller 10 can provide control instructions and display data to N display modules 30. Figure 1 DATA <1> To DATA <n>It represents N shared data lines, which are respectively connected to N display modules 30 .

[0070] Each display array includes at least one display light. The specific type of the display light can be set as needed, and can usually be set to an LED display light. The following text of this application will take the LED display light as an example for explanation.

[0071] The voltage control signal output by the controller 10 to the power management circuit 20 is used to specify the voltage output by the power management circuit 20, that is, to specify Figure 1 For any display array, the anode of each LED of the display array is connected to VLED, and the cathode is grounded, and the brightness is generated by the voltage drop provided by VLED. Figure 1 The VCC and VSS in the circuit are used to provide power supply and grounding for each driving circuit.

[0072] For any one display module 30, the M driving circuits in the display module 30 are cascaded via the serial control line corresponding to the display module 30. Figure 1 Taking the first display module 30 in the example, the M driving circuits in the first display module 30 need to be provided with a serial input and output interface to realize cascading, and the serial port used to connect the front stage circuit is called the P terminal, and the serial port used to connect the back stage circuit is called the N terminal. Figure 1 In the first display module 30, for example, the driving circuit closest to the controller 10 is called the first driving circuit, and the driving circuit farthest from the controller 10 is called the Mth driving circuit. The P end of the first driving circuit is connected to the controller 10, and the line segment is marked as SIOP. <1> The N end of the Mth driving circuit is connected to the controller 10, and this line is marked as SION <1> The N-terminal of the first drive circuit is connected to the P-terminal of the subsequent circuit, that is, the N-terminal of the first drive circuit is connected to the P-terminal of the second drive circuit, and this section of the line is marked as S1_1. Similarly, the N-terminal of the second drive circuit is connected to the P-terminal of the third drive circuit, and this section of the line is marked as S1_2. The N-terminal of the M-1 drive circuit is connected to the P-terminal of the M drive circuit, and this section of the line is marked as S1_(M-1).

[0073] The controller 10 is used to address and read data of each driving circuit in the corresponding display module 30 through each serial control line, that is, through SIOP and SION, the addressing and read-back functions can be realized.

[0074] The M driving circuits have M display arrays connected to each other. Each driving circuit can provide an output current of one or more channels to control the driving of a corresponding number of display lights, usually by controlling the on and off of corresponding switching tubes. Figure 1 In the figure, the first driving circuit is used to drive the first display array, and the connection circuit is marked as C1_1. Correspondingly, the Mth driving circuit is used to drive the Mth display array, and the connection circuit is marked as C1_M.

[0075] See also Figure 2a , in a specific embodiment of the present invention, it may also include: a plurality of display arrays, a scanning driving circuit 40;

[0076] Each driving circuit in each display module 30 is connected to K display arrays, and each driving circuit is used to drive the K display arrays connected to itself, where K is a positive integer not less than 2;

[0077] The scan drive circuit 40 is respectively connected to the power management circuit 20, the controller 10 and each display array, and is used to receive the power supply of the power management circuit 20, and determine the scan timing according to the scan control signal output by the controller 10, and cyclically output the voltage specified by the voltage control signal through K output terminals in sequence, so that the K display arrays connected to any drive circuit can be cyclically powered.

[0078] Compared to Figure 1 The implementation method, in Figure 2a In the implementation manner, each driving circuit is connected to K display arrays, so that a single driving circuit can drive and control K display arrays, thereby reducing the number of required driving circuits. Similarly, each display array may include one or more LED lamps.

[0079] In this implementation, the controller 10 is required to provide a scan control signal to the scan driving circuit 40. The scan driving circuit 40 can determine the scan timing according to the scan control signal output by the controller 10. For example, Figure 2b In a specific implementation manner, the scanning sequence is SCAN1, SCAN2, ... until SCANK, which means that in each cycle, the scanning driving circuit 40 outputs the voltage specified by the voltage control signal through the first output terminal, so that the first display array among the K display arrays driven by each driving circuit is powered by the scanning driving circuit 40, and then the scanning driving circuit 40 outputs the voltage specified by the voltage control signal through the second output terminal, so that the second display array among the K display arrays driven by each driving circuit is powered by the scanning driving circuit 40, and so on. Finally, the scanning driving circuit 40 outputs the voltage specified by the voltage control signal through the Kth output terminal, so that the Kth display array among the K display arrays driven by each driving circuit is powered by the scanning driving circuit 40. After one round is over, the scanning driving circuit 40 outputs the voltage specified by the voltage control signal through the first output terminal again.

[0080] The scanning timing can be determined by the scanning control signal. In the previous example, it is the timing from SCAN1 to SCANK. In other specific scenarios, other timings can be set as needed. It should also be noted that in addition to specifying the order of the cycle, the scanning timing can also specify the cycle period, that is, Figure 2b The duration of LEDon and LEDoff of a single SCAN can be set by the scan control signal.

[0081] The specific structure of the driving circuit of the present application can be set and adjusted according to actual needs, and the driving control and communication functional requirements of the driving circuit of the present application can be achieved. Figure 3 In a specific embodiment of the present invention, each driving circuit includes:

[0082] A serial input / output interface, used to connect corresponding serial control lines and shared data lines, so that the controller 10 can address the drive circuit and read data through the serial control lines, and can send information to the drive circuit through the shared data lines;

[0083] A timing control unit connected to the serial input and output interface, used for decoding and deserializing data and storing the decoded and deserialized display data in a first storage unit, and controlling the output of the pulse amplitude modulation unit and the pulse width modulation unit through the data in the first storage unit to control each display lamp connected to the driving circuit;

[0084] A first storage unit connected to the timing control unit and used for data storage;

[0085] A second storage unit connected to the timing control unit and used for address storage;

[0086] A pulse amplitude modulation unit connected to the timing control unit, used for outputting a Y-channel PAM signal under the control of the timing control unit;

[0087] A pulse width modulation unit connected to the timing control unit, used for outputting a Y-channel PWM signal under the control of the timing control unit;

[0088] A gain-adjustable current source driving unit connected to the pulse amplitude modulation unit and the pulse width modulation unit, respectively, is used to output Y-channel current driving signals according to the control of the Y-channel PAM signal and the Y-channel PWM signal to drive the display array connected to the driving circuit, wherein the power of each channel of current driving signal is jointly controlled by the corresponding 1-channel PAM signal and 1-channel PWM signal;

[0089] The channel status monitoring circuit is used to monitor the circuit information of each Y-channel current driving signal.

[0090] The serial input and output interface specifically needs to provide two interfaces to connect to the serial control line, and needs to provide one interface to connect to the shared data line. Figure 3 In the implementation mode, Y is set to 4, that is, the gain adjustable current source driving unit can output 4 current driving signals, plus the power input terminal VCC and the ground terminal VSS, Figure 3 The driving circuit in the embodiment includes 9 external interfaces. The driving circuit can usually be designed as a uIC (micro chip) to reduce space occupation.

[0091] The controller 10 sends information to the driving circuit through the shared data line DATA, and the display data can be decoded and deserialized by the timing control unit, so as to be stored in the first storage unit. When the display data is different, the outputs of the pulse amplitude modulation unit and the pulse width modulation unit are different, and it should be noted that when the gain adjustable current source driving unit outputs the Y-channel current driving signal according to the control of the Y-channel PAM signal and the Y-channel PWM signal, the current driving signals of each channel are independent of each other. Figure 3 In the implementation manner, Y=4, that is, each display array may include 4 display lamps, which are respectively controlled by the 4 current driving signals to achieve respective power regulation.

[0092] Figure 3 In the solution, the current driving signal is controlled by a pulse amplitude modulation unit and a pulse width modulation unit, which has high flexibility.

[0093] also, Figure 3 The timing control unit in the display device also has grayscale calibration and refresh rate control functions. Grayscale calibration can improve the uniformity of the brightness of the display device, and refresh rate control can adjust the refresh rate of the display device. Figure 3 The gain-adjustable current source drive unit is also equipped with a pre-emphasis circuit and a ghost elimination circuit. The pre-emphasis circuit can accelerate the channel opening, that is, reduce the channel opening time consumption, and the ghost elimination circuit can effectively eliminate the influence of the routing of the current channel IOUT1~4 and the LED parasitic capacitance.

[0094] The channel status monitoring circuit can monitor the circuit information of each Y-channel current driving signal. The specific content of the circuit information is set based on needs. For example, a more convenient way is to monitor and record the voltage drop of each current driving signal, and the recorded circuit information can be sent back to the controller 10 through the readback function of SIOP and SION.

[0095] In a specific implementation of the present invention, the gain adjustable current source driving unit can be specifically used for:

[0096] Performing global current setting of Y groups of current sources through a first current adjustment instruction, and performing respective current setting of the Y groups of current sources through Y second current adjustment instructions to complete current correction;

[0097] According to the control of Y-channel PAM signal and Y-channel PWM signal, Y-channel current driving signal is output to drive the display array connected to the driving circuit, wherein the power of each current driving signal is jointly controlled by the corresponding 1-channel PAM signal and 1-channel PWM signal.

[0098] See also Figure 4 , Figure 4 In the example, the first current adjustment instruction is a 5-bit first current adjustment instruction, which is used to implement global current setting of the four groups of current sources. Through four 4×8-bit second current adjustment instructions, the current settings of the four groups of current sources can be performed separately to complete current calibration, thereby improving current accuracy.

[0099] As described above, this application uses different duty cycles to represent different data on any shared data line. Figure 5 FIG. 1 is a schematic diagram of a duty cycle encoding in a specific implementation. In practical applications, the duty cycle encoded DATA can enter a period decoding circuit after passing through a Schmitt trigger, and deserialize the serial bit streams with different duty cycles into parallel data streams, which are stored in a first storage unit, which is usually a register. Figure 5 In the implementation method, when the duty cycle is 12.5%, 25%, 37.5%, 62.5%, 75%, and 87.5%, they are defined as data symbol 0, data symbol 1, data symbol 2, data symbol 3, data symbol 4, and data symbol 5, respectively, for a total of 6 data symbols. A duty cycle of 50% is defined as SoT (Start of Transmission), which is used as a separator between each data or command. Figure 4 In the example, the data transmission rate I (unit: bps) can be expressed as: I=S×log2A, where S represents the operating frequency of DATA (unit: Hz), and A is the number of data symbols. Under 6 data symbols, the data transmission rate is approximately 2.58 times the DATA frequency.

[0100] In a specific embodiment of the present invention, the types of information transmitted on any one shared data line include data packets and command packets, the data packet includes SoT, CID, DW and DATA; the command packet includes SoT, CID, CW and CMD;

[0101] Among them, Sot represents the set transmission start data, CID represents the address of the packet specified object, CW represents the set command flag, DW represents the set data flag, CMD represents the command content of the command packet, and DATA represents the data content of the data packet.

[0102] The solution of the present application transmits information via a shared data line, and the specific communication protocol can be set as needed. In this implementation, the structures of the data packet and the command packet are relatively simple, which is conducive to improving the efficiency of information transmission.

[0103] It should also be noted that the data packet includes SoT, CID, DW and DATA, and the specific order of CID, DW and DATA is not limited in this application. Similarly, the specific order of CID, CW and CMD in the command packet is not limited in this application.

[0104] Whether it is a data packet or a command packet, the object of the packet is specified by CID (chip identity). That is to say, when the driver circuit detects SoT, it will compare CID with its own address. If the CID comparison result is consistent, it will store the command content CMD (Command) of the command packet or the data content DATA of the data packet into the corresponding register according to the received CW (Command Write) or DW (Data Write). Of course, if the CID comparison result is inconsistent, it means that the object of the packet is not itself, and the current packet can be ignored.

[0105] exist Figure 6 In an implementation manner, for command packets, it is allowed to write to all driving circuits at the same time without waiting for VSYNC, that is, for some commands, a special CID can be set so that such command packets can be written to each driving circuit at the same time.

[0106] Figure 6 In the example, the object of data DATA1 is the first drive circuit, that is, data DATA1 needs to be written into the first drive circuit. After writing, the first drive circuit can wait for the VSYNC signal and output 0. The output 0 here means that before writing DATA1, no display data is stored in the first storage unit of the first drive circuit. It can be understood that when the first drive circuit receives the VSYNC signal, it can perform output control according to the DATA1 stored in the first storage unit, that is, control the output of each current drive signal according to DATA1. In other words, each time the VSYNC signal is received, the first drive circuit will update the output of each current drive signal according to the storage content in the first storage unit.

[0107] Accordingly, in Figure 6 In the example, when data DATA1 is written to the first driving circuit, the remaining M-1 driving circuits are in a state of waiting for writing. For example, if the target of the next data packet is the second driving circuit, DATA2 is written to the second driving circuit.

[0108] In a specific embodiment of the present invention, when the controller 10 reads data from each driving circuit in the corresponding display module 30 through each serial control line, it is specifically used to:

[0109] For any display module 30, after writing a data read instruction to the shared data line corresponding to the display module 30, data of the M driving circuits in the display module 30 are read through the serial control line corresponding to the display module 30 in the order of the 1st driving circuit to the Mth driving circuit in the display module 30, or in the order of the Mth driving circuit to the 1st driving circuit in the display module 30.

[0110] When the controller 10 performs readback, it can read back through SIOP or SION. Figure 7a When reading back through SIOP, after the controller 10 writes a data read instruction to the shared data line corresponding to any one of the specified display modules 30, the first driving circuit sends the data in the first driving circuit to the controller 10 through the shared data line. At the same time, the second driving circuit sends the data in the second driving circuit to the first driving circuit through the shared data line, and the third driving circuit sends the data in the third driving circuit to the second driving circuit through the shared data line, and so on. Finally, the controller 10 can read the data sent by the first to M-th driving circuits in sequence through the shared data line.

[0111] See also Figure 7b When reading back through SION, the controller 10 can read the data sent by the Mth to the 1st driving circuits in sequence through the shared data line.

[0112] Figure 7a and Figure 7b And the following Figure 8a and Figure 8b In FIG. 1 , X1 to Xm respectively represent the first to Mth driving circuits in any display module 30. In addition, no matter the driving circuit is transmitting data or is in a NOP (No operation performed) state, the controller is allowed to perform readback.

[0113] In a specific embodiment of the present invention, when the controller 10 addresses each driving circuit in the corresponding display module 30 through each serial control line, it is specifically used to:

[0114] For any one display module 30, addressing of the M driving circuits in the display module 30 is performed in the order of the first driving circuit to the Mth driving circuit in the display module 30, or in the order of the Mth driving circuit to the first driving circuit in the display module 30;

[0115] Furthermore, for any one driving circuit, when the driving circuit receives a pulse signal through the connected serial control line and receives an addressing packet through the connected shared data line, the driving circuit uses the address carried in the addressing packet as the address allocated to the driving circuit and stores it;

[0116] The address packet includes an address packet header and an address in a set format.

[0117] See also Figure 8a , is a timing diagram of addressing each driving circuit in the display module 30 in a specific implementation manner. Figure 8a In the embodiment, the address packet includes 5 SoTs in the set format. In other implementations, the address packet header may be in other forms.

[0118] Taking the first display module 30 as an example, Figure 8a In the embodiment, the first driving circuit is specifically configured to pass SIOP <1> After receiving the pulse signal sent by the controller 10, and then receiving 5 SoTs and CID1 on the shared data line, the first driving circuit writes CID1 into its own second storage unit as the address assigned to the first driving circuit by the controller 10. Correspondingly, after the address of the first driving circuit is assigned, a pulse signal is sent to the second driving circuit through S1_1, and then when the second driving circuit receives 5 SoTs and CID2 sent by the controller 10 on the shared data line, the second driving circuit writes CID2 into its own second storage unit as the address assigned to the second driving circuit by the controller 10. This process is repeated until all M driving circuits have completed addressing.

[0119] In addition, it should be emphasized that when a driving circuit completes addressing, if the next driving circuit does not receive the addressing packet sent by the controller 10, the driving circuit will wait until it receives the addressing packet. In other words, in the solution of the present application, intervals are allowed to occur during the addressing process.

[0120] Figure 8b In the embodiment, the Mth driving circuit is configured to <1> After receiving the pulse signal sent by the controller 10 and then receiving 5 SoTs and CID1 on the shared data line, the Mth driving circuit writes CID1 into its own second storage unit as the address assigned to the Mth driving circuit by the controller 10. This process is repeated until all M driving circuits have completed addressing.

[0121] It can be seen that Figure 8a The implementation method is to start addressing from the drive circuit closest to the controller 10, and so on, and finally the drive circuit farthest from the controller 10 completes the addressing. Figure 8b The addressing is performed from the driving circuit farthest from the controller 10 to the driving circuit closest to the controller 10 .

[0122] In a specific embodiment of the present invention, the controller 10 may also be used for:

[0123] The circuit information monitored by each channel status monitoring circuit is read, and the output voltage of the power management circuit 20 is adjusted so that the output voltage of the power management circuit 20 reaches the minimum voltage value required to power each display array.

[0124] In this embodiment, the circuit information monitored by each channel status monitoring circuit may be voltage information, and other embodiments may include other types of information. After reading, the controller 10 may perform data analysis to adjust the output voltage of the power management circuit 20. In practical applications, multiple adjustments may be made to achieve the purpose so that VLED reaches the most appropriate value.

[0125] It is understandable that the lower the output voltage of the power management circuit 20, the higher the efficiency of the display device. However, when the output voltage of the power management circuit 20 is too low, the LED cannot be turned on. Therefore, in this embodiment, the output voltage of the power management circuit 20 is adjusted so that the output voltage of the power management circuit 20 reaches the minimum voltage value required to power each display array, thereby maximizing efficiency.

[0126] In practical applications, the controller 10 can also be used for:

[0127] The monitoring mode of each channel status monitoring circuit is adjusted through the monitoring mode adjustment instruction; wherein the adjustable items of the monitoring mode include: a first adjustable item for indicating the monitoring trigger timing, and the monitoring trigger timing includes: periodic monitoring, monitoring when receiving a monitoring instruction, and monitoring when receiving a monitoring instruction and in a standby state; a second adjustable item for indicating the duration of a single monitoring, and a third adjustable item for indicating the selection of a monitoring channel.

[0128] For the first adjustable item of monitoring trigger timing, when periodic monitoring is selected, after the display device enters the normal working state, the channel status monitoring circuit will periodically monitor. When monitoring upon receiving monitoring instructions is selected, if the controller 10 needs to read the circuit information monitored by each channel status monitoring circuit, the controller 10 needs to send a command first to let the channel status monitoring circuit monitor the circuit information once, and after waiting for a certain period of time, for example, after waiting for 2 frames, the controller 10 can read the circuit information monitored by each channel status monitoring circuit. For example Figure 9a In the implementation mode, the monitoring is performed when receiving the monitoring instruction, and Figure 9b The implementation method is to monitor periodically.

[0129] When the selection is to monitor when receiving a monitoring instruction and being in a standby state, it is necessary to issue a monitoring instruction when VSYNC is at a low level so that the channel status monitoring circuit monitors the circuit information once.

[0130] The second adjustable item controls the duration of a single monitoring. In addition, in actual applications, refer to Figure 9a and Figure 9b , usually the monitoring duration is set in units of PWM intervals, that is, the monitoring duration can be set to a number of PWM intervals, and the maximum value that can be set is the number of PWMs in each frame. The third adjustable item can select the monitoring channel. For example, in the example above, there are IOUT1 to 4, that is, a total of 4 selectable monitoring channels, and you can choose to monitor 1 or more channels as needed.

[0131] See also Fig.10 , is a flowchart for adjusting VLED in a specific implementation. In this implementation, after startup, the controller 10 can execute step S1: turn on the channel state monitoring circuit. Then execute step S2: monitoring mode selection. That is, determine the currently set monitoring mode. In this implementation, only two monitoring modes are set, wherein mode 1 is monitoring when receiving a monitoring instruction, and mode 2 is periodic detection. After determining that the monitoring mode is mode 1, step S3: normal operation instruction can be executed, that is, the controller 10 issues a normal operation instruction so that each driving circuit in each display module works normally. Then execute step S4: channel state monitoring trigger instruction. This step indicates that the controller 10 will issue a channel state monitoring trigger instruction when necessary so that the channel state monitoring circuit performs a circuit information monitoring. Step S5: data reading instruction. The controller 10 can read the circuit information monitored by each channel state monitoring circuit by sending a data reading instruction. Step S6: whether VLED reaches the most appropriate value. If it reaches, then execute step S8: determine the required VLED, that is, the current VLED is the most appropriate value, and the current VLED can be maintained. If it is not reached, step S7 needs to be performed: adjusting VLED. Through one or more rounds of adjustment, the output voltage of the power management circuit 20 eventually reaches the minimum voltage value required for powering each display array.

[0132] After determining that the monitoring mode is mode 2, step S9 can be executed: normal operation instructions, that is, the controller 10 issues normal operation instructions so that each driving circuit in each display module works normally. Then execute step S10: data reading instructions. By sending data reading instructions, the controller 10 can read the circuit information monitored by each channel status monitoring circuit. Step S11: Whether VLED reaches the most suitable value. If it does, execute step S8: determine the required VLED, otherwise execute step S12: adjust VLED. It can be seen that the main difference between mode 2 and mode 1 is whether the controller 10 needs to send a channel status monitoring trigger instruction to actively let the channel status monitoring circuit monitor the circuit information.

[0133] In a specific embodiment of the present invention, the controller 10 may also be used for:

[0134] Reading circuit information monitored by each channel status monitoring circuit and performing brightness correction on the display device to obtain a brightness correction result;

[0135] Based on the brightness correction result, information is sent to each driving circuit in the corresponding display module 30 through each shared data line to complete the brightness correction of each display lamp.

[0136] Similar to setting the monitoring mode of the channel status monitoring circuit in the above text, in this implementation, when it is necessary to use the circuit information monitored by the channel status monitoring circuit and perform brightness correction on the display device, various adjustable items of the monitoring mode can be set.

[0137] When performing brightness correction, the brightness correction can be performed by the brightness correction algorithm preset in the controller 10. The specific brightness correction algorithm can be set according to actual needs, for example, brightness correction can be performed through the LUT function. After obtaining the brightness correction result, the controller 10 can complete the brightness correction of each display light by sending the corresponding display data to each driving circuit. Since the controller 10 performs brightness correction by obtaining the circuit information monitored by the channel status monitoring circuit, that is to say, the display device does not need to realize brightness correction by traditional optical photography, but only needs to complete brightness correction through channel detection and readback. The implementation process is simple and convenient, and the cost is low.

[0138] See also Fig.11 , is a flowchart of brightness correction in a specific implementation. In this implementation, after startup, the controller 10 can execute step S101: turn on the channel status monitoring circuit. Then execute step S102: monitoring mode selection. That is, determine the currently set monitoring mode. In this implementation, only two monitoring modes are set, wherein mode 1 is monitoring when receiving a monitoring instruction, and mode 2 is periodic detection. After determining that the monitoring mode is mode 1, step S103: normal operation instruction can be executed, that is, the controller 10 issues a normal operation instruction so that each driving circuit in each display module works normally. Then execute step S104: channel status monitoring trigger instruction. This step indicates that the controller 10 will issue a channel status monitoring trigger instruction when necessary so that the channel status monitoring circuit performs a circuit information monitoring. Step S105: data reading instruction. The controller 10 can read the circuit information monitored by each channel status monitoring circuit by sending a data reading instruction. Step S106: brightness correction is performed through the LUT function. The controller 10 can obtain a brightness correction result by performing brightness correction. Finally, step S107 is executed: information is sent to each driving circuit in the corresponding display module through each shared data line, so that the brightness correction of each display lamp can be completed. If the determined monitoring mode is mode 2, step S108 can be executed: normal operation instruction. Then step S109: data reading instruction. It means that the controller 10 can read the circuit information monitored by each channel status monitoring circuit by sending a data reading instruction.

[0139] In a specific embodiment of the present invention, the controller 10 may be further used for:

[0140] The circuit information monitored by each channel status monitoring circuit is read and fault detection is performed to obtain the fault detection result. The fault detection result may include information such as the fault type and fault location, so as to assist the staff in fault repair. Of course, in some cases, a restart can be performed when a fault is detected to eliminate some types of faults.

[0141] In a specific embodiment of the present invention, the controller 10 may be further used for:

[0142] A low power command is sent to each driving circuit in the corresponding display module 30 through each shared data line, so that the value of each current driving signal is 0. This implementation allows the display device to enter a low power mode, so that the value of each current driving signal is 0, effectively achieving energy saving. Of course, in the low power mode in other implementations, the value of the current driving signal can also be set to other smaller values, so that the brightness of the display device is at a lower level.

[0143] By applying the technical solution provided in the embodiment of the present invention, the power management circuit 20 is connected to the controller 10 and each display array respectively, and can receive the voltage control signal sent by the controller 10 and output the voltage specified by the voltage control signal to each display array to power each display array. Each display module 30 includes: M driving circuits, and M display arrays respectively connected to the M driving circuits, each driving circuit is used to drive the display array connected to itself, and each display array includes at least one display light. Therefore, it can be seen that the solution of the present application realizes a distributed display device, and under the control of the controller 10, each display array can be powered by the power management circuit 20. For any one display module 30, the M driving circuits in the display module 30 are cascaded through the serial control line corresponding to the display module 30. For any one display module 30, the controller 10 can address and read data of each driving circuit in the display module 30 through the serial control line corresponding to the display module 30. Therefore, it can be seen that the addressing and data reading of each driving circuit in the display device can be conveniently realized through each serial control line, and the circuit design is simple. When the controller 10 sends information to each driving circuit in the corresponding display module 30 through each shared data line, in the scheme of the present application, different data are represented by different duty cycles on any one shared data line, so only N shared data lines are needed to send information to N display modules 30, the circuit design is simple, and the complexity of the data transmission method is reduced. In summary, the present application effectively realizes a distributed display device and reduces the complexity of the circuit design and the data transmission method.

[0144] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0145] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0146] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the technical solution and core ideas of the present invention. It should be pointed out that for ordinary technicians in this technical field, the present invention can also be improved and modified without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.< / n>

Claims

1. A display device, characterized in that: include: Controller, power management circuit and N display modules; Each of the display modules comprises: M driving circuits and M display arrays respectively connected to the M driving circuits, each driving circuit is used to drive the display array connected to itself, wherein each display array comprises at least one display light, and M and N are both positive integers; The power management circuit is connected to the controller and each of the display arrays respectively, and is used to receive a voltage control signal sent by the controller and output a voltage specified by the voltage control signal to each of the display arrays to supply power to each of the display arrays; For any one of the display modules, the M driving circuits in the display module are cascaded through a serial control line corresponding to the display module, and are connected to corresponding IO ports of the controller through the serial control line, and the M driving circuits in the display module are all connected to the controller through a shared data line corresponding to the display module; The controller is used to address and read data of each driving circuit in the corresponding display module through each serial control line, and send information to each driving circuit in the corresponding display module through each shared data line to control each driving circuit and each display lamp, and different duty cycles are used to represent different data on any one of the shared data lines; Each of the driving circuits comprises: A serial input / output interface, used to connect corresponding serial control lines and shared data lines, so that the controller addresses and reads data from the drive circuit through the serial control lines, and the controller sends information to the drive circuit through the shared data lines; A timing control unit connected to the serial input / output interface, used for decoding and deserializing data and storing the decoded and deserialized display data in a first storage unit, and controlling the output of a pulse amplitude modulation unit and a pulse width modulation unit through the data in the first storage unit, so as to control each display lamp connected to the drive circuit; A first storage unit connected to the timing control unit and used for data storage; A second storage unit connected to the timing control unit and used for address storage; A pulse amplitude modulation unit connected to the timing control unit, used for outputting a Y-channel PAM signal under the control of the timing control unit; A pulse width modulation unit connected to the timing control unit, used for outputting a Y-channel PWM signal under the control of the timing control unit; A gain-adjustable current source driving unit connected to the pulse amplitude modulation unit and the pulse width modulation unit, respectively, for outputting Y-channel current driving signals according to the control of Y-channel PAM signals and Y-channel PWM signals, so as to drive a display array connected to the driving circuit, wherein the power of each channel of current driving signals is jointly controlled by a corresponding 1-channel PAM signal and 1-channel PWM signal; The channel status monitoring circuit is used to monitor the circuit information of each current driving signal of the Y channel.

2. The display device according to claim 1, characterized in that Also includes: Multiple display arrays, scan drive circuits; Each driving circuit in each of the display modules is connected to K display arrays, and each driving circuit is used to drive the K display arrays connected to itself, where K is a positive integer not less than 2; The scan drive circuit is respectively connected to the power management circuit, the controller and each of the display arrays, and is used to receive power from the power management circuit, and determine the scan timing according to the scan control signal output by the controller, and cyclically output the voltage specified by the voltage control signal through K output terminals in sequence, so that the K display arrays connected to any drive circuit can be cyclically powered.

3. The display device according to claim 1, characterized in that The types of information transmitted on any one of the shared data lines include data packets and command packets, wherein the data packets include SoT, CID, DW and DATA; the command packets include SoT, CID, CW and CMD; Among them, Sot represents the set transmission start data, CID represents the address of the packet specified object, CW represents the set command flag, DW represents the set data flag, CMD represents the command content of the command packet, and DATA represents the data content of the data packet.

4. The display device according to claim 1, characterized in that When the controller reads data from each driving circuit in the corresponding display module through each serial control line, it is specifically used to: For any display module, after writing a data read instruction to the shared data line corresponding to the display module, data of the M driving circuits in the display module are read through the serial control line corresponding to the display module in the order of the first driving circuit to the Mth driving circuit in the display module, or in the order of the Mth driving circuit to the first driving circuit in the display module.

5. The display device according to claim 1, characterized in that When the controller addresses each driving circuit in the corresponding display module through each serial control line, it is specifically used to: For any one display module, addressing of M driving circuits in the display module is performed in the order of the first driving circuit to the Mth driving circuit in the display module, or in the order of the Mth driving circuit to the first driving circuit in the display module; Furthermore, for any one driving circuit, when the driving circuit receives a pulse signal through the connected serial control line and receives an addressing packet through the connected shared data line, the driving circuit uses the address carried in the addressing packet as the address allocated to the driving circuit and stores it; The addressed packet includes an address packet header and an address in a set format.

6. The display device according to claim 1, characterized in that: The gain adjustable current source driving unit is specifically used for: Performing global current setting of Y groups of current sources through a first current adjustment instruction, and performing respective current setting of the Y groups of current sources through Y second current adjustment instructions to complete current correction; According to the control of Y-channel PAM signal and Y-channel PWM signal, Y-channel current driving signal is output to drive the display array connected to the driving circuit, wherein the power of each current driving signal is jointly controlled by the corresponding 1-channel PAM signal and 1-channel PWM signal.

7. The display device according to claim 1, characterized in that: The controller is also used for: The circuit information monitored by each of the channel status monitoring circuits is read, and the output voltage of the power management circuit is adjusted so that the output voltage of the power management circuit reaches the minimum voltage value required to power each of the display arrays.

8. The display device according to claim 1, characterized in that: The controller is also used for: The monitoring mode of each channel status monitoring circuit is adjusted through the monitoring mode adjustment instruction; wherein the adjustable items of the monitoring mode include: a first adjustable item for indicating the monitoring trigger timing, and the monitoring trigger timing includes: periodic monitoring, monitoring when receiving a monitoring instruction, and monitoring when receiving a monitoring instruction and in a standby state; a second adjustable item for indicating the duration of a single monitoring, and a third adjustable item for indicating the selection of a monitoring channel.

9. The display device according to claim 1, characterized in that: The controller is also used for: Reading the circuit information monitored by each of the channel status monitoring circuits and performing brightness correction on the display device to obtain a brightness correction result; Based on the brightness correction result, information is sent to each driving circuit in the corresponding display module through each shared data line to complete the brightness correction of each display lamp.

10. The display device according to claim 1, characterized in that The controller is also used for: The circuit information monitored by each of the channel status monitoring circuits is read and fault detection is performed to obtain a fault detection result.

11. The display device according to claim 1, characterized in that: The controller is also used for: A low power consumption command is sent to each driving circuit in the corresponding display module through each shared data line, so that the value of each current driving signal is 0.

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