Vector data processor, instruction processing method, system on chip and computing device

Abstract

The embodiment of the invention provides a vector data processor, an instruction processing method, a system on chip and computing equipment, the vector data processor comprises a data access unit and a vector floating point unit, the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register; the data memory access unit is used for responding to a vector memory access instruction, performing memory access of target vector data on a memory and updating a temporary register based on the target vector data, and the vector memory access instruction is obtained by splitting a mask vector memory access instruction; and the vector floating point unit is used for reading the target vector data from the temporary register and writing back the corresponding target element in the target vector data to the vector register based on the mask vector. The hardware design is optimized, the complexity is effectively reduced, the power consumption is controlled, the performance frequency is effectively improved, the area of a vector data processor is reduced, and the innovative scheme provided by the embodiment of the specification can be used for an RISC-V instruction set chip.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of hardware development and design, and in particular to a vector data processor, an instruction processing method, a system on chip, and a computing device. The innovative solutions proposed in the embodiments of this specification can be used for RISC-V instruction set chips. Background Art

[0002] With the development of semiconductor technology and processor architecture technology, vector data processors have been widely used in different fields such as high-performance computing, artificial intelligence, and edge computing due to their high performance and low power consumption.

[0003] At present, in vector data processors, the masked vector load / store method is used to selectively access (load) or store (store) vector operations on elements in vector data, thereby improving data processing efficiency, vector operation flexibility and resource utilization efficiency.

[0004] However, in the process of executing masked vector memory access, in order to complete the transmission of masked vector (MaskedVector or V0) between the data access unit (Load / Store Unit, LSU) and the vector floating-point unit (Vector & Floating-Point Unit, VFPU), it is necessary to build a dedicated port on the data access unit, and after the masked vector is transmitted to the data access unit, the masked value (Masked Value) must be calculated to determine which elements in the vector need to be written back to the vector register (Vector Processing Register, VPR). That is, the two operations of accessing data from the memory and writing back to the vector register are deeply bound, which increases the complexity and power consumption, reduces the performance frequency of the vector data processor, and the dedicated port increases the area of ​​the vector data processor. Summary of the invention

[0005] In view of this, an embodiment of the present specification provides a vector data processor. One or more embodiments of the present specification also relate to an instruction processing method, a system on a chip and a computing device to solve the technical defects existing in the prior art.

[0006] According to a first aspect of an embodiment of this specification, there is provided a vector data processor, comprising a data access unit and a vector floating point unit, wherein the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register; A data access unit, configured to access target vector data from a memory in response to a vector access instruction, and update a temporary register based on the target vector data, wherein the vector access instruction is obtained by splitting a mask vector access instruction; The vector floating point unit is used for reading the target vector data from the temporary register and writing the corresponding target elements in the target vector data back to the vector register based on the mask vector.

[0007] According to a second aspect of an embodiment of this specification, an instruction processing method is provided, which is applied to a vector data processor, wherein the vector data processor includes a data access unit and a vector floating point unit, the data access unit includes a temporary register, and the vector floating point unit includes a vector register, including: In response to a vector memory access instruction, access target vector data from a memory, wherein the vector memory access instruction is obtained by splitting a mask vector memory access instruction; Based on the target vector data, update the temporary register; Read the target vector data from the temporary register; Based on the mask vector, write the corresponding target elements in the target vector data back to the vector register.

[0008] According to a third aspect of an embodiment of this specification, a system on chip is provided, including: a control unit and a plurality of on-chip components, the plurality of on-chip components including a vector data processor; The control unit is used to control and manage multiple on-chip components, and the vector data processor is used to execute computer programs / instructions. When the computer programs / instructions are executed by the vector data processor, the steps of the above instruction processing method are implemented.

[0009] According to a fourth aspect of an embodiment of this specification, a computing device is provided, including: Memory and System-on-Chip; The memory is used to store computer programs / instructions, and the system on chip is used to execute the computer programs / instructions. When the computer program / instructions are executed by the system on chip, the steps of the above instruction processing method are implemented.

[0010] In one embodiment of the present specification, a vector data processor is provided, in which a data access unit updates a temporary register only based on target vector data, and does not need to calculate and store mask values. A vector floating-point unit reads data from a temporary register and writes the target element back to the vector register according to the mask vector. That is, the two operations of loading data from a memory and writing it back to a vector register are decoupled, and there is no need to configure an additional read port to process mask vector access. This optimizes the hardware design, effectively reduces complexity and controls power consumption, effectively improves performance frequency, and reduces the area of ​​the vector data processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a schematic diagram of the architecture of a vector data processor; Figure 2 It is a data processing schematic diagram of a vector data processor; Figure 3 is a schematic diagram of the structure of a vector data processor provided by an embodiment of this specification; Figure 4 is a schematic diagram of the architecture of a vector data processor provided by an embodiment of this specification; Figure 5 is a data processing schematic diagram of a vector data processor provided by an embodiment of this specification; Figure 6 is a flow chart of an instruction processing method provided by an embodiment of this specification; Figure 7 is a schematic diagram of the structure of a system on a chip provided by an embodiment of this specification; Figure 8 It is a structural diagram of a computing device provided by an embodiment of this specification. DETAILED DESCRIPTION

[0012] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0013] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0014] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0015] In addition, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0016] First, the terms involved in one or more embodiments of this specification are explained.

[0017] Vector data or vector data (Vector): An ordered collection of multiple data elements, usually used to represent a one-dimensional or multi-dimensional array. In computer architecture, vector data is often used to efficiently process large amounts of data, especially in scientific computing, image processing, and machine learning.

[0018] Mask Vector or Masked Vector (V0): A binary vector (Boolean vector: 1 or 0) of the same length as the vector data, where each bit corresponds to a vector element, indicating whether the element participates in a specific vector operation. In masked vector access, the mask vector is used to control which elements should be loaded from or stored to memory.

[0019] Masked vector access or masked vector memory access: A memory access mechanism that allows a program to selectively choose which elements should be accessed or stored when performing vector operations.

[0020] RISC-V instruction set (Reduced Instruction Set Computer-Five, fifth generation reduced instruction set): an open standard instruction set architecture (ISA) that aims to provide an open and extensible hardware design specification. The design goal of the RISC-V architecture is to simplify processor design and improve performance frequency and energy efficiency.

[0021] RISC-V instruction set chip: a processor chip designed based on the RISC-V architecture. These chips usually have the characteristics of high performance, low power consumption and high flexibility, and are widely used in embedded systems, IoT devices, high-performance computing and other fields.

[0022] SIMD (Single Instruction Multiple Data): A parallel computing technology that allows multiple data elements to be processed at the same time using the same instruction. SIMD technology is often used to accelerate data-intensive tasks such as multimedia processing, image processing, and scientific computing.

[0023] SIMD processor: A processor that supports SIMD technology and can perform the same operation on multiple data elements in a single clock cycle. SIMD processors significantly improve data processing efficiency through parallel processing capabilities.

[0024] GPU (Graphics Processing Unit): A processor specially designed to process graphics and image data. GPU has powerful parallel computing capabilities and is widely used in graphics rendering, scientific computing, machine learning and other fields.

[0025] NPU (Neural Processing Unit): A processor designed specifically to accelerate machine learning algorithms, especially in the field of deep learning. NPU can efficiently handle complex neural network computing tasks and increase the speed of model training and reasoning.

[0026] VPU (Vision Processing Unit): A processor that focuses on computer vision tasks, such as image recognition, object detection, etc. VPUs usually integrate multiple hardware accelerators to optimize the processing efficiency of visual data.

[0027] SoC (System on Chip): A system-level hardware device on a chip that contains all the contents of a complete system and embedded software.

[0028] Data access (Load / Store): refers to the process of the processor loading data from memory to registers (Load) or storing data from registers to memory (Store). Data access is one of the basic operations in computer architecture and is crucial for data processing and program execution.

[0029] Masked Value: A value calculated during a masked vector access to determine which elements of a vector need to be accessed from or stored in memory. Each bit in the masked value corresponds to a vector element, indicating whether the element participates in the memory access operation.

[0030] Register: A high-speed storage unit inside a processor that is used to temporarily store data and instructions. Registers are accessed much faster than memory, so when the processor executes instructions, registers are often used to store intermediate results and key data.

[0031] UOP (Micro-Operation): It is the smallest execution unit that the processor decomposes when executing complex instructions. In modern processors, complex instructions are decomposed into a series of micro-operations, which are executed one by one by the execution unit of the processor. The use of UOP can improve the execution efficiency and flexibility of the processor.

[0032] Reorder Buffer (ROB) is an important component in modern high-performance processors to support out-of-order execution. Its main function is to ensure that instructions are committed in the original program order after execution, thereby maintaining the correctness of the program.

[0033] Specifically, Figure 1 A schematic diagram of the architecture of a vector data processor is shown: The functions of each unit in this high-performance vector data processor are described as follows: Front-End: used for instruction fetch and branch prediction. The front-end fetches instructions from memory and predicts the jump direction of branch instructions to reduce pipeline stalls caused by branch instructions.

[0034] Instruction decoding unit (Decoder): used to decode the fetched instructions into micro-operations (UOPs) so that the subsequent execution units can understand and execute these instructions.

[0035] Rename unit: used to rename registers to resolve resource conflicts between instructions. The registers involved in renaming include: Scalar Integer Register, Vector Register, and Scalar Floating Point Register.

[0036] Instruction dispatch unit (Dispatch): used to distribute decoded instructions to different execution units to ensure that the instructions can be correctly processed and executed by hardware resources.

[0037] Issue Queues: used to issue instructions, sending instructions from the dispatch unit to different execution units in a certain time sequence. The issue unit can manage multiple issue queues to ensure that instructions are sent to the corresponding execution units at the correct time and order.

[0038] Integer Processing Register (IPR): used to store integer data and intermediate results, supporting integer operations and logical operations.

[0039] Miscellaneous Registers (MISC Regs): Generally, processors can implement some small register files for renaming certain registers. For example, for the ARM instruction set, the NZCV Flag (Negative, Zero, Carry, Overflow flag) can use these small register files for renaming to improve performance and reduce resource conflicts.

[0040] Arithmetic Logic Units (ALUs): Used to perform integer arithmetic and logic operations such as addition, subtraction, shift, logical AND, logical OR, etc.

[0041] Vector & Floating-Point Execution Unit (VFPU): used to perform vector and floating-point operations, including vector addition, vector multiplication, floating-point addition, floating-point multiplication, etc. VFPU supports efficient parallel computing and is particularly suitable for applications such as scientific computing, image processing, and machine learning.

[0042] Vector Processing Register (VPR): used to store vector data and intermediate results, supporting vector operations. Vector registers usually have a large capacity and can hold multiple data elements to support efficient parallel processing.

[0043] Floating-Point Register (FPR): used to store floating-point data and intermediate results, supporting floating-point operations. Floating-point registers usually have higher precision and range, and are suitable for applications that require high-precision calculations.

[0044] Data access unit (Load / Store Unit, LSU for short): used for data access (Load) and storage (Store) operations, reading data from memory to registers or writing data from registers back to memory. LSU supports efficient memory access and ensures fast data transfer between the processor and memory.

[0045] For Masked Vector Load / Store, see Figure 2 Data processing operations between various units in Figure 2 A data processing schematic diagram of a vector data processor is shown: The vector register in the vector floating-point execution unit transmits the mask vector to the data access unit through a dedicated read port. The data access unit calculates the mask value based on the mask vector, puts it into the data access queue (Load Data Queue, LDQ for short), and obtains the address information of the data elements to be accessed from the integer register: the access start address (SRC0) and the access offset (SRC1), and then completes the data access in the future.

[0046] Among them, the mask vector can determine which data elements are accessed.

[0047] For example, for a masked vector access operation, before performing the masked vector access operation: The vector data in the vector register is: vector_register = [0, 0, 0, 0]; Mask vector: V0 = [1, 0, 1, 0]; The vector data in memory is: memory_location = [10, 20, 30, 40]; After performing a masked vector access operation: The vector data in the vector register is: vector_register = [10, 0, 30, 0]; Among them, the data elements with a value of "1" in the mask vector are written back from the memory to the vector register, and the data elements with a value of "0" in the mask vector are not written back from the memory to the vector register.

[0048] For another example, for a mask vector storage operation, before performing the mask vector storage operation: The vector data in the vector register is: vector_register = [10, 20, 30, 40]; Mask vector: V0 = [1, 0, 1, 0]; The vector data in memory is: memory_location = [0, 0, 0, 0]; After performing the mask vector store operation: The vector data in memory is: memory_location = [10, 0, 30, 0]; Among them, the data elements with a value of "1" in the mask vector are written from the vector register to the memory, and the data elements with a value of "0" in the mask vector are not written from the vector register to the memory.

[0049] However, such a design has the following problems: 1. Since the mask vector needs to be transmitted to the data access memory unit through a dedicated read port, a dedicated read port needs to be allocated to the mask vector on the data access memory unit, which increases the area of ​​the vector data processor.

[0050] 2. When the data length of the vector data is large, a wider data path is also required to transmit from the vector floating-point unit to the data access unit, which occupies more data transmission resources and may increase signal transmission delay, thereby reducing the performance frequency of the processor.

[0051] 3. After the data access unit reads the mask vector, it needs to calculate the mask value based on the mask vector, which increases the computational burden of the data access unit, prolongs the delay of data processing, increases the complexity, and reduces the performance frequency.

[0052] 4. In some out-of-order processor cores, a mask value needs to be reserved for each mask vector memory access instruction, which increases the overhead of the instruction buffer and reorder buffer. The additional resource occupation not only limits the concurrent processing capability of the processor, but may also cause resource competition and lead to a decrease in performance frequency.

[0053] In view of the above problems, a vector data processor is provided in this specification. This specification also relates to an instruction processing method, a system on a chip and a computing device, which are described in detail one by one in the following embodiments.

[0054] See also Figure 3 , Figure 3 A schematic diagram of the structure of a vector data processor provided by an embodiment of the present specification is shown, the vector data processor 300 includes a data access memory unit 310 and a vector floating point unit 320, wherein the data access memory unit 310 includes a temporary register, and the vector floating point unit 320 includes a vector register; A data access unit 310 is used to access target vector data from a memory in response to a vector access instruction, and to update a temporary register based on the target vector data, wherein the vector access instruction is obtained by splitting a mask vector access instruction; The vector floating point unit 320 is used to read the target vector data from the temporary register and write the corresponding target element in the target vector data back to the vector register based on the mask vector.

[0055] The vector data processor 300 is a processor specially designed for efficient processing of vector data. It significantly improves data processing efficiency compared to traditional data processors by processing multiple data elements in parallel. The vector data processor 300 includes multiple functional units, such as a data access unit 310, a vector floating point unit 320, etc., and multiple units work together to achieve efficient vector data processing. For example, RISC-V instruction set chips, SIMD processors, high-performance graphics processing units (GPUs), neural network processing units (NPUs), and visual processing units (VPUs).

[0056] The data access unit 310 is a key component in the vector data processor 300, which is used for access (Load) and storage (Store) operations of vector data, reading vector data from the memory to the register or writing vector data from the register to the memory. The data access unit 310 supports efficient memory access and ensures that data is quickly transferred between the processor and the memory. The data access unit 310 includes a temporary register for temporarily storing data read from the memory.

[0057] The vector floating point unit 320 is a key component in the vector data processor, which is used to perform vector and floating point operations. The vector floating point unit 320 supports efficient parallel computing and can perform operations such as addition, subtraction, multiplication, and division on multiple data elements at the same time. The vector floating point unit 320 includes vector registers for storing vector data.

[0058] The temporary register (temporal register, referred to as temp) is a high-speed storage unit in the data access unit 310, which is used to temporarily store the target vector data read from the memory. The temporary register can reduce the delay of data transmission and improve the efficiency of data processing. The temporary register is used to store the target vector data read from the memory for further processing by the vector floating point unit 320. For example, when performing a mask vector access operation, the data access unit 310 stores the target vector data read from the memory in the temporary register.

[0059] The vector register (VPR) is a high-speed storage unit in the vector floating-point unit 320 for storing vector data. Vector registers usually have a large capacity and can accommodate multiple data elements, supporting efficient parallel processing. Vector registers are used to store final vector data (target elements or mask values) for subsequent vector operations. For example, when performing a mask vector storage operation, the vector floating-point unit 320 reads data from the vector register and writes the target element to the memory according to the mask vector.

[0060] Vector memory access instructions (Vector Load / Store) are micro-operation instructions for vector data access and storage. They instruct the processor to load vector data from memory to vector registers or store vector data from vector registers to memory. Vector memory access instructions usually include vector access instructions (Vector Load) and vector store instructions (Vector Store), supporting efficient vector data transmission. Vector memory access instructions are obtained by splitting mask vector memory access instructions.

[0061] Masked Vector Load / Store instructions are used to selectively access or store data elements in vector data. Masked Vector Load / Store instructions control which data elements participate in the vector access operation through a mask vector. Masked Vector Load / Store instructions generally include a mask vector and address information of the target vector data, instructing the vector data processor 300 to selectively access or store vector data according to the mask vector. Masked Vector Load / Store instructions generally include masked vector load instructions and masked vector store instructions, supporting selective vector data transfer.

[0062] The target vector data is the vector data to be read from the memory or to be written to the memory. In the mask vector memory access operation, the target vector data refers to the vector data that needs to be selectively loaded or stored according to the mask vector. For example, when performing a vector load operation, the target vector data is the vector data read from the memory: [10, 20, 30, 40].

[0063] The mask vector is a binary vector of the same length as the target vector data, where each bit corresponds to a data element, indicating whether the data element participates in a specific vector operation. In mask vector memory access, the mask vector is used to control which elements should be accessed from or stored to memory. Each bit in the mask vector is 1, indicating that the element participates in the operation, and 0, indicating that the element does not participate in the operation (and vice versa). For example, the mask vector V0 = [1, 0, 1, 0] indicates that the first and third data elements participate in the memory access operation, and the second and fourth data elements do not participate in the memory access operation.

[0064] The target element is the data element of the target vector data that needs to be loaded from the memory to the vector register or stored from the vector register to the memory, determined based on the mask vector. In the mask vector memory access operation, the target element is the element whose corresponding bit in the mask vector is 1 (and vice versa). For example, when performing a mask vector access operation, because the first and third bits in the mask vector V0 = [1, 0, 1, 0] are 1, the target element is read from the memory [10, 30].

[0065] In response to the vector memory access instruction, the target vector data is accessed from the memory. One optional method is: in response to the vector memory access instruction, the target vector data is directly accessed from the memory. For example, the data memory access unit 310 directly reads the target vector data from the memory according to the address information in the vector memory access instruction. Another optional method is: in response to the vector memory access instruction, the target vector data is accessed from the memory using a cache mechanism. For example, the data memory access unit 310 first stores the target vector data in a cache queue and then reads it from the cache queue. This is not limited here.

[0066] Based on the target vector data, the temporary register is updated. One optional method is to write the target vector data directly into the temporary register. Another optional method is to write the target vector data into the temporary register in segments. For example, the data access unit 310 first writes the data element [10, 20] in the target vector data [10, 20, 30, 40] into the temporary register, and then writes the data element [30, 40] into the temporary register. Another optional method is to write the target vector data into the temporary register in parallel. For example, the data access unit 310 simultaneously writes the data elements [10, 20] and [30, 40] in the target vector data [10, 20, 30, 40] into the temporary register through two write ports. This is not limited here.

[0067] Based on the mask vector, the corresponding target element in the target vector data is written back to the vector register. An optional method is: based on the mask vector, the corresponding target element in the target vector data is determined, and the target element is written back to the vector register, which is not limited here.

[0068] Exemplarily, for a masked vector access operation, Initial state: Vector data in vector register: vector_register = [0, 0, 0, 0]; Vector data in temporary register: temporal_register = [0, 0, 0, 0]; Vector data in memory: memory_location = [10, 20, 30, 40]; The data memory access unit 310, in response to the vector memory access instruction, reads the target vector data [10, 20, 30, 40] from the memory and updates the temporary register: temporal_register = [10, 20, 30, 40].

[0069] The vector floating point unit 320 reads the target vector data from the temporary register and writes the target element [10, 30] back to the vector register according to the mask vector V0 = [1, 0, 1, 0]: vector data in the vector register: vector_register = [10, 0, 30, 0].

[0070] Through the above example, it can be understood that the data access unit 310 normally performs memory access operations, the mask calculation and processing operations are completely placed in the vector floating point unit 320, and the two operations of loading data from the memory and writing back to the vector register are decoupled.

[0071] In the embodiments of the present specification, the data access unit only updates the temporary register based on the target vector data, and there is no need to calculate and store the mask value. The vector floating-point unit reads data from the temporary register and writes the target element back to the vector register according to the mask vector. That is, the two operations of loading data from the memory and writing it back to the vector register are decoupled, and there is no need to additionally configure a read port to handle mask vector access. This optimizes the hardware design, effectively reduces complexity and controls power consumption, effectively improves performance frequency, and reduces the area of ​​the vector data processor.

[0072] At present, when an error occurs in a data element and an exception needs to be reported, it is also necessary to determine whether to report the exception based on the mask vector: if an error occurs in a masked data element, no exception is reported; if an error occurs in an unmasked data element, an exception needs to be reported. However, this approach has the following problems: 1. Increased complexity: The analysis of mask vectors and the judgment of abnormal reporting are performed in the data access unit, which increases the complexity of the data access unit and makes the hardware design more complicated.

[0073] 2. Increased latency and reduced performance frequency: The data access unit needs to perform abnormal judgment and reporting after each memory access operation, which increases the latency of data processing and affects the overall performance frequency.

[0074] 3. Resource usage: The data access unit requires additional hardware resources to support the exception reporting function, which increases the area and power consumption of the vector data processor.

[0075] In view of the above problem, in an optional embodiment of the present specification, the vector data processor 300 further includes an instruction decoding unit and an exception handling unit; An instruction decoding unit, used for splitting the mask vector memory access instruction to obtain a vector memory access instruction and an exception reporting instruction; The data access unit 310 is further configured to respond to the vector access instruction and, if an error element occurs in the target vector data, write the error element into the error status register and write the error cause of the error element into the error cause register; The vector floating point unit 320 is further configured to respond to the exception reporting instruction and report the corresponding abnormal element and the error cause of the abnormal element in the error element to the exception handling unit based on the mask vector.

[0076] The instruction decoding unit (Decoder, or Instruction Decoding Unit, referred to as IDU) is a key component in the vector data processor 300, which is used to decode the fetched instructions into micro-operations (UOPs) so that the subsequent execution units can understand and execute these instructions. In the embodiment of this specification, the instruction decoding unit is used to split the masked vector memory access instruction to obtain the vector memory access instruction and the exception reporting instruction. This split can simplify the work of the subsequent processing units and improve the execution efficiency of the processor. For example, the masked vector memory access instruction is vmasked_load, and the instruction decoding unit splits it into vload (vector memory access instruction) and vmerge (exception reporting instruction).

[0077] The exception handling unit is a component in the vector data processor 300, which is used to handle and manage various exceptions, such as data errors, illegal instructions, etc. In the embodiment of the present specification, the exception handling unit receives an exception report from the vector floating point unit 320, and handles the exception element and its error cause. For example, when the vector floating point unit 320 detects that an error occurs in a data element, the error element and its error cause are reported to the exception handling unit, and the exception handling unit records the error information and triggers the corresponding exception handling process.

[0078] Vector memory access instructions generally include vector access instructions (Vector Load) and vector storage instructions (VectorStore), which support efficient vector data transmission.

[0079] For example, for the unit stride access mode (Unit Stride Load), the vector memory access instruction is: vle8.vtemp, (rs1), which means loading continuous byte (8-bit) data from the memory into the vector register temp, and the base address is provided by the general register rs1.

[0080] For the stride / index access mode (Stride / Index Load), the vector memory access instruction is: vlse8.v temp, (rs1) / / byte 0, indicating that the byte (8-bit) data with the stride (stride) is loaded from the memory into the vector register temp. The base address is provided by the general register rs1, and the stride is 1.

[0081] For the unit-stride segment access mode (Unit-Stride Segment Load), the vector memory access instruction is: vle64.v temp0, (rs1) / / segment 0, indicating that a continuous 64-bit data segment is loaded from the memory into the vector register temp0, and the base address is provided by the general register rs1.

[0082] For the unit stride storage mode (Unit Stride Store), the vector memory access instruction is: vse8.v vd, (rs1), vm, which means that the byte (8-bit) data in the vector register vd is stored in the memory. The base address is provided by the general register rs1, and the storage operation is controlled by the mask vector vm.

[0083] For the stride / index store mode, the vector memory access instruction is: vse8.v vd, (rs1), vm / / byte 0, which means that the byte (8-bit) data in the vector register vd is stored in the memory. The base address is provided by the general register rs1. The storage operation is controlled by the mask vector vm, and the stride is 1.

[0084] For the unit stride segment storage mode (Unit Stride Segment Store), the vector memory access instruction is: vse.v temp, (rs1), vm, which means that the 64-bit data segment in the vector register temp is stored in the memory. The base address is provided by the general register rs1, and the storage operation is controlled by the mask vector vm.

[0085] Exception reporting instructions (Vmerge, Vcheck, and Vshuffle) are micro-operation instructions used to process and report error elements detected during vector data access. These instructions handle exceptions in different ways to ensure that the processor can correctly identify and handle errors. Usually including Vmerge, Vcheck, and Vshuffle, the following are three common exception reporting instructions and their explanations: 1. Vmerge: used to merge the error elements and their error causes into the exception handling unit. It determines which error elements need to be reported based on the mask vector.

[0086] 2. Vcheck: used to check the error elements in the vector data and determine which error elements need to be reported based on the mask vector.

[0087] 3. Vshuffle: It is used to rearrange the elements in vector data to better handle abnormal situations. It can rearrange the error elements and their error causes to the specified position to facilitate subsequent processing.

[0088] For example, for the unit stride access mode (Unit Stride Load), the exception reporting instruction is: vmerge vd, temp, vm, which means reading the error elements and their error causes from the source register temp, determining which error elements need to be reported based on the mask vector vm, merging these error elements and their error causes into the target register vd, and reporting them to the exception handling unit.

[0089] For the stride / index load access mode, the exception reporting instruction is: vcheck vm / / check byte 0 fault, which indicates that data elements and their error causes are read from the memory, and each data element is checked for errors, especially errors in byte 0. The error elements that need to be reported are determined based on the mask vector vm, and these error elements and their error causes are reported to the exception handling unit.

[0090] For the unit-stride segment load access mode, the exception reporting instruction is: vshuffle vd, temp0, temp1, vm, which indicates that the data elements and their error causes are read from the source registers temp0 and temp1, and the elements that need to be rearranged are determined according to the mask vector vm, and these elements and their error causes are rearranged to the specified positions in the target register vd, and the rearranged data is written to the target register vd.

[0091] For the unit stride storage mode (Unit Stride Store), the exception reporting instruction is: vcheck vm, which indicates reading data elements and their error causes from the vector register, checking whether each data element has an error, determining which error elements need to be reported based on the mask vector vm, and reporting these error elements and their error causes to the exception handling unit.

[0092] For the stride / index storage mode (Stride / Index Store), the exception reporting instruction is: vcheck vm / / check byte 0 fault, which indicates that the data elements and their error causes are read from the vector register, and each data element is checked for errors, especially the error in byte 0. The error elements that need to be reported are determined according to the mask vector vm, and these error elements and their error causes are reported to the exception handling unit.

[0093] For the unit stride segment store mode (Unit Stride Segment Store), the exception reporting instruction is: vcheck vm / / check byte 0 fault, which indicates that the data segment and its error cause are read from the vector register, and each data segment is checked for errors, especially the error of byte 0. According to the mask vector vm, it is determined which error elements need to be reported, and these error elements and their error causes are reported to the exception handling unit.

[0094] An error element is a data element that has an error during data access. An error element may be caused by a memory error, data corruption, etc. In the embodiment of the present specification, after the data access unit detects an error element, it writes it into the error status register and records the error cause. For example, the vector data in the memory is [10, 20, 30, 40], where data element 20 has an error, then 20 is an error element.

[0095] The error cause of the error element is the specific reason that caused the data element to have an error, such as a memory error, data corruption, etc. The error cause is usually recorded in a certain coded form to facilitate subsequent exception handling. In the embodiment of this specification, the data access unit writes the error cause into the error cause register. For example, a memory error occurs in data element 20, and the error cause can be coded as 0x01, indicating a memory error.

[0096] The error status register is a register specifically used to store error elements, and may be an existing register of the vector data processor 300 or a specially set dedicated register, which is not limited here.

[0097] The error cause register is a register specifically used to store the error cause of the error element, and can be an existing register of the vector data processor 300, or a specially set dedicated register, which is not limited here. The error cause register can be the same register as the error status register, or can be a different register, which is not limited here.

[0098] The abnormal element is an error element that needs to be reported based on the mask vector. The error element that is not masked based on the mask vector will be reported as an abnormal element. For example, the mask vector V0 = [1, 0, 1, 0], the error element is [20, 40], because the mask bit corresponding to 20 is 1, the abnormal element is 20.

[0099] The error cause of the abnormal element is the specific cause of the error of the abnormal element, such as memory error, data corruption, etc. For example, the error cause of abnormal element 20 is memory error, which is coded as 0x01.

[0100] An optional way to write the error element into the error status register is to write the error element directly into the error status register, and another optional way is to write the error element into the error status register in segments, which is not limited here.

[0101] The error cause of the error element is written into the error cause register. One optional way is to write the error cause of the error element directly into the error cause register. Another optional way is to write the error cause of the error element into the error cause register in segments, which is not limited here.

[0102] In response to the exception reporting instruction, based on the mask vector, the corresponding abnormal element in the error element and the error cause of the abnormal element are reported to the exception handling unit. An optional method is: in response to the exception reporting instruction, based on the mask vector, the corresponding abnormal element is determined from the error element, and the abnormal element and the error cause of the abnormal element are reported to the exception handling unit.

[0103] For example, the initial state: Vector data in vector register: vector_register = [0, 0, 0, 0]; Vector data in temporary register: temporal_register = [0, 0, 0, 0]; Vector data in memory: memory_location = [10, 20, 30, 40]; Mask vector: V0 = [1, 0, 1, 0]; The masked vector memory access instruction is: vle8.v vd, (rs1), vm, which indicates that continuous byte (8-bit) data is loaded from the memory into the vector register vd. The base address is provided by the general register rs1, and the load operation is controlled by the masked vector vm.

[0104] The instruction decoding unit splits the masked vector memory access instruction to obtain the vector memory access instruction: vle8.vtemp, (rs1), and the exception reporting instruction: vmerge vd, temp, vm.

[0105] The data memory access unit 310, in response to the vector memory access instruction (vle8.v temp, (rs1)), calculates the memory address, address = rs1 + 0. Starting from the calculated address, it continuously loads multiple bytes of data into the temporary register temp, checks if a memory error occurs in the loaded data element 20, writes the error element 20 in segments into the error status register error_status_register, and writes the error reason 0x01 in segments into the error reason register error_reason_register.

[0106] The vector floating point unit 320, in response to the exception reporting instruction (vmerge vd, temp, vm), reads the mask vector V0 = [1, 0, 1, 0] from the vector register, reads the error element 20 from the error status register error_status_register, reads the error reason 0x01 from the error reason register error_reason_register, determines the exception element 20 and its error reason 0x01 to be reported based on the mask vector V0 = [1, 0, 1, 0], and reports the exception element 20 and its error reason 0x01 to the exception handling unit.

[0107] In the embodiments of the present specification, on the basis of ensuring whether to report an exception based on the mask vector, the mask vector is parsed and the judgment of the exception reporting is directly performed in the vector floating-point unit, thereby reducing the complexity. The data access unit does not need to perform exception judgment and reporting after each memory access operation, thereby reducing the delay in data processing and improving the overall performance frequency. The data access unit does not need additional hardware resources to support the exception reporting function, thereby reducing the area and power consumption of the vector data processor.

[0108] Since data elements may be misaligned during vector memory access operations, the method of writing erroneous elements in different misaligned parts in high and low bit segments can be used to ensure the integrity and accuracy of the error information.

[0109] In an optional embodiment of the present specification, the data access unit 310 is specifically used to write the error element into the high space and low space of the error status register when an error element appears in the target vector data and the error element is not aligned, and write the error cause of the error element into the high space and low space of the error cause register; or, When an error element appears in the target vector data and the error element is aligned, the error element is written into the low-order space of the error status register, and the error cause of the error element is written into the low-order space of the error cause register.

[0110] Specifically, when the error element is misaligned, the data access unit writes the high-order part of the error element into the high-order space of the error status register, writes the low-order part into the low-order space, and writes the corresponding error cause into the high-order space and the low-order space of the error cause register respectively. This can avoid the loss of some error information caused by misalignment, ensure that the exception handling unit can obtain complete error information, and thus handle exceptions more effectively.

[0111] The high-order space of the error status register is used to store the high-order part of the misaligned error element. For example, if the high-order space is the high 32 bits, the error element is 0x12345678, and it is misaligned, and the high-order part is 0x1234, then the high-order space stores 0x1234.

[0112] The low-order space of the error status register is used to store the low-order part of the unaligned error element or the aligned error element. For example, if the low-order space is the lower 32 bits, the error element is 0x12345678, and it is unaligned, and the low-order part is 0x5678, then the low-order space stores 0x5678. If the error element is aligned, the low-order space stores 0x12345678.

[0113] The high-order space of the error cause register is used to store the error cause of the high-order part of the misaligned error element. For example, the high-order space is the high 5 bits. The error cause of the high-order part 0x1234 of the error element 0x12345678 is 0x01, and the high-order space stores 0x01.

[0114] The low-order space of the error cause register is used to store the error cause of the low-order part of the unaligned error element or the error cause of the aligned error element. For example, the low-order space is the lower 5 bits, and the error cause of the low-order part 0x5678 of the error element 0x12345678 is 0x02, then the low-order space stores 0x02. If the error element is aligned, the error cause of the error element 0x12345678 is 0x01, then the low-order space stores 0x01.

[0115] In the embodiments of the present specification, the unaligned error elements are segmented and written into the high and low spaces of the error status register, and the corresponding error causes are respectively written into the high and low spaces of the error cause register, thereby avoiding the loss of some error information due to misalignment, ensuring that the exception handling unit can obtain complete error information, thereby more effectively handling exceptions, ensuring the integrity and accuracy of the error information, thereby improving the reliability of exception handling, and enhancing the robustness and security of the vector data processor.

[0116] Considering the misalignment, when executing the exception reporting instruction, it is also necessary to judge the exception, specifically: In an optional embodiment of the present specification, the vector floating point unit 320 is specifically used to report the corresponding abnormal element and the error cause of the abnormal element in the partially misaligned error element to the exception handling unit based on the mask vector when an error element appears in the target vector data and the error element is partially misaligned; or When error elements appear in the target vector data and all the error elements are misaligned, all the misaligned error elements are screened according to their priority, and based on the mask vector, the corresponding abnormal elements and the error causes of the abnormal elements in the screened error elements are reported to the exception handling unit.

[0117] Partially misaligned error elements are in an error element, only part of the data bits are misaligned. This situation usually occurs on the boundary of multi-byte data elements, part of the data is located at the end of a memory address, and the other part of the data is located at the beginning of the next memory address. Partially misaligned error elements require special processing because they cannot be read directly from the memory at one time, but need to be read and combined in segments. In the vector data processor 300, in this case, the high-order part and the low-order part of the error element need to be written into the high-order space and the low-order space of the error status register respectively. For example, the vector data in the memory is [0x12, 0x34, 0x56, 0x78], the error element is 0x12345678, and the high-order part 0x1234 of the element is located at the end of a memory address, and the low-order part 0x5678 is located at the beginning of the next memory address. In this case, the high-order part 0x1234 and the low-order part 0x5678 are written into the high-order space and the low-order space of the error status register respectively.

[0118] All unaligned error elements are all data bits of the entire error element are unaligned. This situation usually occurs when multi-byte data elements span multiple memory address boundaries, resulting in the inability to read complete data at one time. All unaligned error elements need special processing because they need to be read and combined from multiple memory addresses. In the vector data processor 300, in this case, it is necessary to write the various parts of the error element into different spaces of the error status register respectively, and filter them according to priority. For example, the vector data in the memory is [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC], the error element is 0x123456789ABC, and the error element spans multiple memory addresses. In this case, it is necessary to read data from multiple memory addresses, and write the various parts into different spaces of the error status register respectively.

[0119] The priority of an error element is a priority order determined according to a certain rule among multiple error elements. Error elements with high priority will be processed and reported first. In the vector data processor 300, when multiple error elements appear at the same time, they need to be screened according to the priority to determine which error elements need to be reported first. The priority can be based on the severity of the error, the time sequence of occurrence, or other factors. For example, the vector data in the memory is [0x12, 0x34, 0x56, 0x78, 0x9A, 0xBC], the error elements are 0x12345678 and 0x9ABC, and both elements are not aligned. Assume that the error cause of 0x12345678 is 0x01 (memory error), and the error cause of 0x9ABC is 0x02 (data corruption). According to the priority rule, the priority of memory error is higher than data corruption, so 0x12345678 is reported first.

[0120] Based on the mask vector, the corresponding abnormal elements in the partially misaligned error elements and the error causes of the abnormal elements are reported to the exception handling unit. An optional method is: based on the mask vector, the corresponding abnormal elements in the partially misaligned error elements are determined, and the abnormal elements and the error causes of the abnormal elements are reported to the exception handling unit.

[0121] Based on the mask vector, the corresponding abnormal elements in the filtered error elements and the error causes of the abnormal elements are reported to the exception handling unit. An optional method is: based on the mask vector, the corresponding abnormal elements in the filtered error elements are determined, and the abnormal elements and the error causes of the abnormal elements are reported to the exception handling unit.

[0122] In the embodiments of the present specification, by writing partially misaligned and fully misaligned error elements into the high and low spaces of the error status register respectively, and filtering and reporting the abnormal elements according to priority rules and mask vectors, the loss of some error information is avoided, the integrity and accuracy of the error information are ensured, the reliability of exception handling is improved, and the robustness and security of the vector data processor are enhanced.

[0123] In an optional embodiment of the present specification, the vector data processor 300 further includes miscellaneous registers, and the vector floating point unit 320 further includes floating point registers, wherein the error status register is a floating point register, and the error cause register is a miscellaneous register.

[0124] The floating-point register (FPR) is used as an error status register to record whether each data element in the target vector data is an error element. Optionally, when the data element is not aligned, the high-order space of the FPR stores the high-order part of the error element, and the low-order space stores the low-order part of the error element. This can make full use of the existing floating-point registers, avoid adding new hardware resources, and reduce area overhead. For example, the vector data in the memory is [0x12, 0x34, 0x56, 0x78], the error element is 0x12345678, and the high-order part 0x1234 of the element is located at the end of a memory address, and the low-order part 0x5678 is located at the beginning of the next memory address. In this case, the high-order space of the FPR stores 0x1234 and the low-order space stores 0x5678.

[0125] Miscellaneous Registers (MISC Regs) are used as error cause registers to record the error cause of the error element. Optionally, when the data element is not aligned, the high-order space of MISC Regs stores the error cause of the high-order part of the error element, and the low-order space stores the error cause of the low-order part of the error element. In this way, the existing miscellaneous registers can be fully utilized, the addition of new hardware resources can be avoided, and the area overhead can be reduced. For example, the error cause of the high-order part 0x1234 of the error element 0x12345678 is 0x01, and the error cause of the low-order part 0x5678 is 0x01. In this case, the high-order space of MISC Regs stores 0x01, and the low-order space stores 0x01.

[0126] In the embodiments of this specification, two existing storage units, namely floating point register and miscellaneous register, are reused to report exceptions, thereby improving the hardware utilization of the vector data processor without increasing any area.

[0127] For the convenience of subsequent description, the subsequent instructions are explained here and will not be repeated in the subsequent embodiments: Vector access instructions: Unit stride load: vle8.v vd, (rs1), vm: used to load 8-bit width data from memory into vector register vd, and the loading process is controlled by mask register vm. The unit stride here means that the address interval between each data element is 1 byte.

[0128] Stride / Index Load: vlse8.v vd, (rs1), vm: This instruction is used to load 8-bit width data from memory into vector register vd at a specified stride (or index), and the loading process is also controlled by mask register vm. Stride / index mode allows fixed address offsets between data elements.

[0129] Unit-Stride Segment Load: vlseg3e64.v vd, (rs1), vm: An instruction for loading multiple consecutive segments of vector data, each containing 64-bit width data. vd represents the destination vector register, rs1 provides the base address, and vm is the mask register that controls the load operation. This instruction is suitable for accessing structured data, such as members in a structure array.

[0130] Vector store instructions: Unit Stride Store: vse8.v vd, (rs1), vm: used to store 8-bit width data from vector register vd to memory, the storage process is controlled by mask register vm. Unit stride means that the address interval between each data element is 1 byte.

[0131] Stride / Index Store: vsse8.v vd, (rs1), vm: Similar to vlse8.v, but for storing data. It stores 8-bit wide data from vector register vd to memory at the specified stride (or index) according to mask vm.

[0132] Unit-Stride Segment Store: vsseg3e64.v vd, (rs1), vm: corresponds to vlseg3e64.v, and is used to store 64-bit width data of multiple consecutive segments from vector register vd to memory. The storage process is controlled by the mask register vm.

[0133] Abnormal reporting instructions: vmerge vd, temp, vm: merge the data in the temporary register temp into the target vector register vd according to the mask vm. If an exception occurs, the vmerge instruction will be used to handle the reporting of the abnormal element.

[0134] vcheck vm: Checks whether any exception occurs in the mask vector vm, and reports the abnormal element and its error cause to the exception handling unit.

[0135] vshuffle vd, temp0, temp1, vm: is used to rearrange or mix the data in two source vector registers temp0 and temp1 and store the result in the destination vector register vd, under the control of the mask register vm. This instruction is particularly useful when dealing with segment accesses or stores, as it can help reorganize the data to match the memory layout.

[0136] Regarding the processing of the masked vector load instruction (Masked Vector Load), in an optional embodiment of the present specification, the instruction decoding unit is specifically used to split the masked vector load instruction to obtain a vector access instruction and an exception reporting instruction; The data access unit 310 is specifically used to load target vector data from the memory in response to a vector access instruction, and update the temporary register based on the target vector data, wherein the vector access instruction is obtained by splitting the mask vector access instruction; The vector floating-point unit 320 is specifically used to respond to the exception reporting instruction and report the corresponding exception element and the error cause of the exception element in the error element to the exception handling unit based on the mask vector; or, read the target vector data from the temporary register and write the corresponding target element in the target vector data back to the vector register based on the mask vector.

[0137] The vector access instruction (Vector Load) is a micro-operation instruction for vector data access. It instructs the vector data processor 300 to load vector data from the memory to the vector register. The vector access instruction supports efficient vector data transmission. The vector access instruction is a part obtained by splitting the mask vector access instruction.

[0138] The masked vector load instruction is used to selectively access data elements in vector data. The masked vector load instruction controls which data elements participate in the vector access operation through the mask vector. The masked vector load instruction usually includes the mask vector and the address information of the target vector data, and instructs the vector data processor 300 to selectively access the vector data according to the mask vector. The masked vector load instruction supports selective vector data transmission.

[0139] In response to a vector access instruction, target vector data is loaded from the memory. One optional method is: in response to the vector access instruction, the target vector data is directly loaded from the memory. For example, the data access unit 310 directly loads the target vector data from the memory according to the address information in the vector access instruction. Another optional method is: in response to the vector access instruction, the target vector data is loaded from the memory using a cache mechanism. For example, the data access unit 310 first stores the target vector data in a cache queue and then loads it from the cache queue. This is not limited here.

[0140] The other steps in the embodiments of this specification have been described in detail in the above embodiments of the specification and will not be repeated here.

[0141] Exemplarily, for the unit stride access mode (Unit Stride Load), the masked vector access instruction is: vle8.v vd, (rs1), vm.

[0142] The instruction decoding unit splits the masked vector access instruction into vector access instructions (vle8.v temp, (rs1)) and exception reporting instructions (vmerge vd, temp, vm).

[0143] The data access unit 310 executes vle8.v temp (vs1) to load the target vector data from the memory and update temporary registers (eg, floating point registers, miscellaneous registers, and vector registers) based on the target vector data.

[0144] The vector floating point unit 320 executes vmerge vd,temp,vm, determines the abnormal element from the error elements recorded in the error status register based on the mask vector, reports the abnormal element and the error cause of the abnormal element; or, based on the mask vector, writes the corresponding target element in the target vector data back to the vector register.

[0145] Exemplarily, for the stride / index access mode (Stride / Index Load), the masked vector access instruction is: vlse8.v vd, (rs1), vm.

[0146] The instruction decoding unit splits the masked vector access instruction to obtain vector access instructions (vlse8.vtemp, (rs1) / / byte 0; vlse8.v temp, (rs1) / / byte 31) and exception reporting instructions (vcheck vm / / check byte 0 fault; vcheck vm / / check byte 31 fault; vmerge vd, temp, vm), among which vlse8.v temp, (rs1) / / byte 0 needs to update the temporary register according to the error situation, vcheck vm / / checkbyte 0 fault needs to decide whether to report an exception according to the error status, vlse8.v temp, (rs1) / / byte 31; vcheck vm / / check byte 31 fault; vmerge vd, temp, vm does not need to report an exception, but only needs to update the vector register.

[0147] The data access unit 310 executes vlse8.v temp (rs1) to load the target vector data from the memory and update temporary registers (eg, floating point registers, miscellaneous registers, and vector registers) based on the target vector data.

[0148] The vector floating point unit 320 executes vcheck vm and vmerge vd, temp, vm. vcheck vm determines the abnormal element from the error elements recorded in the error status register based on the mask vector, and reports the abnormal element and the error cause of the abnormal element; or, vmerge vd, temp, vm writes the corresponding target element in the target vector data back to the vector register based on the mask vector.

[0149] Exemplarily, for the unit-stride segment load mode, the masked vector access instruction is: vlseg3e64.v vd, (rs1), vm.

[0150] The instruction decoding unit splits the masked vector access instruction to obtain vector access instructions (vle64.vtemp0, (rs1) / / segment 0; vle64.v temp1, (rs1) / / segment 1; vle64.v temp0, (rs1) / / segment 2; vle64.v temp1, (rs1) / / segment 3) and exception reporting instructions (vshuffle vd, temp0, temp1, vm; vshuffle vd+1, temp0, temp1, vm; vshuffle vd+2, temp0, temp1, vm; vshufflevd, temp0, temp1, vm; vshuffle vd+1, temp0, temp1, vm; vshuffle vd+2, temp0, temp1, vm), among which vle64.v temp0, (rs1) / / segment 0 needs to update the temporary register according to the error situation, vle64.vtemp1, (rs1) / / segment 1; vshuffle vd, temp0, temp1, vm needs to decide whether to report an exception based on the error status, vshuffle vd+1, temp0, temp1, vm; vshuffle vd+2, temp0, temp1, vm; vle64.vtemp0, (rs1) / / segment 2; vle64.v temp1, (rs1) / / segment 3; vshuffle vd, temp0, temp1, vm; vshuffle vd+1, temp0, temp1, vm; vshuffle vd+2, temp0, temp1, vm does not need to report an exception, only needs to update the vector register.

[0151] The data access unit 310 executes vle64.v temp0, (rs1) to load the target vector data from the memory, and updates temporary registers (eg, floating point registers, miscellaneous registers, and vector registers) based on the target vector data.

[0152] The vector floating point unit 320 executes vshuffle, determines the abnormal element from the error elements recorded in the error status register based on the mask vector, reports the abnormal element and the error cause of the abnormal element; or, based on the mask vector, writes the corresponding target element in the target vector data back to the vector register.

[0153] In the embodiments of this specification, during the access process, there is no need to configure an additional read port to process mask vector access, which optimizes the hardware design, effectively reduces complexity and controls power consumption, effectively improves performance frequency, and reduces the area of ​​the vector data processor.

[0154] Regarding the processing of the Masked Vector Store instruction, in an optional embodiment of the present specification, the instruction decoding unit is specifically used to split the Masked Vector Store instruction to obtain a vector store instruction and an exception reporting instruction; The data access unit 310 is specifically configured to respond to the vector storage instruction and write the corresponding target element in the target vector data into the memory based on the mask vector, and when an error element appears in the target vector data, write the error element into the error status register, and write the error cause of the error element into the error cause register; The vector floating point unit 320 is specifically configured to respond to the exception reporting instruction and report the corresponding abnormal element and the error cause of the abnormal element in the error element to the exception handling unit based on the mask vector.

[0155] The Masked Vector Store instruction is used to selectively store data elements in vector data. The Masked Vector Store instruction controls which data elements participate in the vector store operation through a mask vector. The Masked Vector Store instruction generally includes a mask vector and address information of the target vector data, and instructs the vector data processor 300 to selectively store the vector data according to the mask vector. The Masked Vector Store instruction supports selective vector data transfer.

[0156] In an optional embodiment of the present specification, the vector data processor 300 further includes a mask register; The data access unit 310 is further configured to read the mask vector from the mask register in response to a vector store instruction.

[0157] The mask register is a register in the vector data processor 300 for storing a mask vector, and may be an existing register of the vector data processor 300 or a specially set dedicated register, which is not limited here.

[0158] Write the corresponding target elements in the target vector data into the memory. An optional method is: write the corresponding target elements in the target vector data directly into the memory. For example, the data access unit 310 writes the corresponding target elements in the target vector data directly into the memory according to the address information in the vector storage instruction. Another optional method is: use the cache mechanism to write the corresponding target elements in the target vector data directly into the memory. For example, the data access unit 310 first stores the corresponding target elements in the target vector data in the cache queue, and then writes them from the cache queue into the memory. This is not limited here.

[0159] The other steps in the embodiments of this specification have been described in detail in the above embodiments of the specification and will not be repeated here.

[0160] Exemplarily, for the unit stride store mode (Unit Stride Store), the mask vector store instruction is: vse8.v vd, (rs1), vm.

[0161] The instruction decoding unit splits the mask vector storage instruction to obtain the vector storage instruction (vse8.v vd, (rs1), vm) and the exception reporting instruction (vcheck vm).

[0162] The data access unit 310 executes vse8.v vd, (rs1), vm, reads the mask vector from the mask register, writes the corresponding target element in the target vector data into the memory based on the mask vector, and when an error element appears in the target vector data, writes the error element into the error status register (floating point register), and writes the error cause of the error element into the error cause register (miscellaneous register).

[0163] The vector floating point unit 320 executes vcheck vm, and reports the corresponding abnormal element in the error element and the error cause of the abnormal element to the exception handling unit based on the mask vector.

[0164] Exemplarily, for the Stride / Index Store mode, the mask vector store instruction is: vsse8.v vd, (rs1), vm.

[0165] The instruction decoding unit splits the masked vector storage instruction to obtain vector storage instructions (vse8.v vd, (rs1), vm / / byte 0; vse8.v vd, (rs1), vm / / byte 31) and exception reporting instructions (vcheck vm / / check byte 0 fault; vcheck vm / / check byte 31 fault; vcheck vm), among which, vse8.v vd, (rs1), vm / / byte 0 needs to update the temporary register according to the error situation, vcheck vm / / check byte 0 fault needs to decide whether to report the exception according to the error status, vse8.v vd, (rs1), vm / / byte 31; vcheck vm / / check byte 31 fault; vcheck vm does not need to report the exception, but only needs to update the vector register.

[0166] The data access unit 310 executes vse8.v vd, (rs1), vm, reads the mask vector from the mask register, writes the corresponding target element in the target vector data into the memory based on the mask vector, and when an error element appears in the target vector data, writes the error element into the error status register (floating point register), and writes the error cause of the error element into the error cause register (miscellaneous register).

[0167] The vector floating point unit 320 executes vcheck vm, and reports the corresponding abnormal element in the error element and the error cause of the abnormal element to the exception handling unit based on the mask vector.

[0168] Exemplarily, for the unit-stride segment store mode (Unit-Stride Segment Store), the mask vector access instruction is: vsseg3e64.v vd, (rs1), vm.

[0169] The instruction decoding unit splits the mask vector storage instruction to obtain vector storage instructions (vse.v temp, (rs1), vm / / segment 0; vse.v temp, (rs1), vm / / segment 3) and exception reporting instructions (vshuffletemp, vd, vd+1; vshuffle temp, temp, vd+2; vcheck vm / / check byte 0 fault; vshuffletemp, vd, vd+1; vshuffle temp, temp, vd+2; vcheck vm / / check byte 3 fault), among which, vshuffle temp, vd, vd+1; vshuffle temp, temp, vd+2; vse.v temp, (rs1), vm / / segment 0 needs to update the temporary register according to the error situation, and vcheck vm / / check byte 0 fault needs to decide whether to report the exception according to the error status, vshuffle temp, vd, vd+1; vshuffle temp, temp, vd+2; vse.v temp, (rs1), vm / / segment 0 needs to decide whether to report the exception according to the error status, vshuffle temp, vd, vd+1; vshuffle temp, temp, vd+2; vse.v temp, (rs1), vm / / segment 3; vcheck vm / / check byte 3 fault does not need to report an exception, only needs to update the vector register.

[0170] The data access unit 310 executes vse.v temp, (rs1), vm, reads the mask vector from the mask register, writes the corresponding target element in the target vector data into the memory based on the mask vector, and when an error element appears in the target vector data, writes the error element into the error status register (floating point register), and writes the error cause of the error element into the error cause register (miscellaneous register).

[0171] The vector floating point unit 320 executes vcheck vm, and reports the corresponding abnormal element in the error element and the error cause of the abnormal element to the exception handling unit based on the mask vector.

[0172] In the embodiments of this specification, during the storage process, there is no need to configure an additional read port to process mask vector storage, which optimizes the hardware design, effectively reduces complexity and controls power consumption, effectively improves performance frequency, and reduces the area of ​​the vector data processor.

[0173] Refer to the above Figure 3 Example, Figure 4 A schematic diagram of the architecture of a vector data processor provided by an embodiment of this specification is shown: In the vector data processor, the instruction decoding unit splits the mask vector memory access instruction to obtain the vector memory access instruction and the exception reporting instruction. After renaming and distribution by the instruction distribution unit, the corresponding unit is determined to execute the two micro-operation instructions. The exception reporting instruction is transmitted to the vector floating-point execution unit in the vector floating-point unit through the instruction issuance unit, and the vector memory access instruction is transmitted to the data memory access unit. The data memory access unit reads the address information from the integer register: the access start address and the access offset, and performs the vector access operation based on the address information. The data memory access unit writes the temporary result to the vector register in the vector floating-point unit, writes the error element to the floating-point register in the vector floating-point unit, and writes the error cause to the miscellaneous register. Inside the vector floating-point unit, the vector floating-point execution unit reads the temporary result and the mask vector from the vector register, and reads the error element from the floating-point register. Between the vector floating-point unit and the miscellaneous register, the vector floating-point execution unit reads the error cause from the miscellaneous register. The vector floating-point execution unit makes an error judgment, and reports an exception if there is no masked error element. Since the whole process is the processing of vector data, the arithmetic logic unit does not participate.

[0174] Figure 4 The vector data processor architecture in has the following effects: 1. When the mask vector memory access instruction is executed in the data memory access unit, there is no need to calculate the mask value or store the mask value, which reduces the hardware complexity and hardware overhead.

[0175] 2. The existing storage units, floating point registers and miscellaneous registers, are reused to report exceptions, which improves hardware utilization without increasing any area.

[0176] 3. The vector register does not need to configure an additional read port for the mask vector memory access instruction, which reduces the complexity of hardware implementation and effectively guarantees performance and power consumption.

[0177] 4. The effect is particularly evident in vector data processors with two levels: sustained performance and power efficiency.

[0178] Refer to the above Figure 3 and Figure 4 Example, Figure 5 A data processing schematic diagram of a vector data processor provided by an embodiment of this specification is shown: The floating-point register is used as an error status register. The upper and lower 32 bits are used to record the bitmaps of the misaligned error elements of different parts: the upper 32 bits are used to record the bitmap of the misaligned error elements of the first part, and the lower 32 bits are used to record the bitmap of the misaligned error elements of the second part.

[0179] The miscellaneous register is used as an error cause register, and the upper and lower 5 bits are used to record the error causes of the error elements of different parts that are not aligned: the upper 5 bits are used to record the error causes of the error elements of the first part that are not aligned, and the lower 5 bits are used to record the error causes of the error elements of the second part that are not aligned.

[0180] A plurality of access unit write-back paths are established between the data access unit and the floating-point register: a write-back path of access unit 0, a write-back path of access unit 1, and a write-back path of access unit 2.

[0181] A miscellaneous register write-back path is also established between the data access unit and the miscellaneous register.

[0182] When the data access unit updates and executes the exception reporting instruction, in response to the exception reporting instruction, the mask vector is read from the vector register, the error element is read from the floating point register, and the error cause is read from the miscellaneous register. Based on the mask vector, the corresponding exception element and the error cause of the exception element in the error element are reported: the trap event is reported through the sorting buffer.

[0183] Corresponding to the above-mentioned embodiment of the vector data processor, this specification also provides an embodiment of an instruction processing method. Figure 6 A flowchart of an instruction processing method provided by an embodiment of the present specification is shown, and the method is applied to a vector data processor, wherein the vector data processor includes a data access unit and a vector floating point unit, the data access unit includes a temporary register, and the vector floating point unit includes a vector register, and includes the following specific steps: Step 602: In response to a vector memory access instruction, access target vector data from a memory, wherein the vector memory access instruction is obtained by splitting a mask vector memory access instruction.

[0184] Step 604: Update the temporary register based on the target vector data.

[0185] Step 606: Read the target vector data from the temporary register.

[0186] Step 608: Based on the mask vector, write the corresponding target element in the target vector data back to the vector register.

[0187] The above is a schematic scheme of an instruction processing method of this embodiment. It should be noted that the technical scheme of the instruction processing method and the technical scheme of the above-mentioned vector data processor belong to the same concept, and the details not described in detail in the technical scheme of the instruction processing method can be referred to the description of the technical scheme of the above-mentioned vector data processor.

[0188] In the embodiments of the present specification, the temporary register is updated only based on the target vector data, and there is no need to calculate and store the mask value. The vector floating-point unit reads data from the temporary register and writes the target element back to the vector register according to the mask vector. That is, the two operations of loading data from the memory and writing it back to the vector register are decoupled, which simplifies the data processing flow, effectively reduces complexity, improves data processing efficiency and flexibility, and optimizes resource utilization efficiency.

[0189] Corresponding to the above-mentioned embodiment of the instruction processing method, this specification also provides an embodiment of the system on chip, Figure 7 A schematic diagram of the structure of a system on chip provided by an embodiment of the present specification is shown. The system on chip 700 includes but is not limited to a control unit 710 and multiple on-chip components 720 . The multiple on-chip components 720 include a vector data processor 7210 .

[0190] The control unit 710 is used to control and manage multiple on-chip components 720 .

[0191] The vector data processor 7210 is used to execute computer programs / instructions, which implement the steps of the above instruction processing method when executed by the vector data processor 7210.

[0192] The system on chip 700 is a system-level hardware device on a chip that integrates a control unit 710 and multiple on-chip components 720. It usually integrates a control unit 710, a central processor, a digital signal processor, a vector data processor, and an input / output interface (I / O) and other multiple on-chip components 720. The system on chip 700 can improve performance, reduce power consumption and reduce physical size, and can be applied to a variety of scenarios such as mobile devices, Internet of Things devices, and embedded systems. The specific embodiments of this application do not limit the specific implementation of the system on chip.

[0193] The control unit 710 is a core component of the system on chip 700, responsible for decoding instructions, controlling the execution process, and coordinating with multiple on-chip components 720. The control unit 710 controls and manages the workflow of multiple on-chip components 720 by sending control signals to ensure that each on-chip component can correctly complete the task in a predetermined order and logic.

[0194] The plurality of on-chip components 720 are various functional hardware components in the system on chip 700, which work together to complete specific tasks or functions. The plurality of on-chip components 720 may include, but are not limited to, a central processing unit, a digital signal processor, a vector data processor, and an input-output interface.

[0195] The above is a schematic scheme of a system on chip of this embodiment. It should be noted that the technical scheme of the system on chip and the technical scheme of the above instruction processing method belong to the same concept, and the details not described in detail in the technical scheme of the system on chip can be referred to the description of the technical scheme of the above instruction processing method.

[0196] Corresponding to the above-mentioned instruction processing method and the embodiment of the system on chip, this specification also provides an embodiment of a computing device, Figure 8 The schematic diagram of the structure of a computing device provided by an embodiment of the present specification is shown. The computing device 800 includes but is not limited to a memory 810 and a system on chip 820 .

[0197] The memory 810 is used to store computer programs / instructions.

[0198] The system on chip 820 is used to execute the following computer program / instruction, which implements the steps of the above instruction processing method when executed by the system on chip 820.

[0199] The computing device 800 is an electronic device with computing capabilities, capable of running various software programs to complete specific functions or tasks. The computing device 800 generally includes a memory 810 and a hardware device for performing tasks. In the embodiments of this specification, the computing device 800 includes but is not limited to a system on chip 820 and a memory 810. The specific embodiments of this application do not limit the specific implementation of the computing device.

[0200] The memory 810 is a component in the computing device 800 for storing data and computer programs / instructions, and is generally divided into two types: volatile and non-volatile. Volatile memory (such as RAM) will lose data after power failure and is mainly used for temporary storage of running programs and data; non-volatile memory (such as ROM, flash memory) can still retain data after power failure and is used to store firmware and persistent data.

[0201] The above is a schematic scheme of a computing device of this embodiment. It should be noted that the technical scheme of the computing device and the technical scheme of the above instruction processing method belong to the same concept, and the details not described in detail in the technical scheme of the computing device can be referred to the description of the technical scheme of the above instruction processing method.

[0202] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0203] The computer program / instructions include computer program code, which may be in source code form, object code form, executable file, or some intermediate form.

[0204] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0205] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0206] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A vector data processor, comprising a data access unit and a vector floating point unit, wherein: The data access unit includes a temporary register, and the vector floating point unit includes a vector register; The data access unit is used to access the target vector data from the memory in response to the vector access instruction, and update the temporary register based on the target vector data, wherein the vector access instruction is obtained by splitting the mask vector access instruction; The vector floating point unit is used to read the target vector data from the temporary register and, based on a mask vector, write back corresponding target elements in the target vector data to the vector register.

2. The vector data processor according to claim 1, further comprising an instruction decoding unit and an exception handling unit; The instruction decoding unit is used to split the mask vector memory access instruction to obtain the vector memory access instruction and the exception reporting instruction; The data access unit is further configured to, in response to the vector access instruction, write an error element into an error status register and write an error cause of the error element into an error cause register when an error element appears in the target vector data; The vector floating point unit is further configured to respond to the exception reporting instruction and report the corresponding abnormal element in the error element and the error cause of the abnormal element to the exception handling unit based on the mask vector.

3. The vector data processor according to claim 2, wherein the data access unit is specifically configured to, when an error element appears in the target vector data and the error element is not aligned, write the error element into the high-order space and the low-order space of the error status register, and write the error cause of the error element into the high-order space and the low-order space of the error cause register; or When an error element appears in the target vector data and the error element is aligned, the error element is written into the low-order space of the error status register, and the error cause of the error element is written into the low-order space of the error cause register.

4. The vector data processor according to claim 2 or 3, wherein the vector floating point unit is specifically configured to report, based on a mask vector, the abnormal element corresponding to the partially misaligned erroneous element and the error cause of the abnormal element to the exception handling unit when an erroneous element appears in the target vector data and the erroneous element is partially misaligned; or When error elements appear in the target vector data and all the error elements are misaligned, all the misaligned error elements are screened according to their priority, and based on the mask vector, the corresponding abnormal elements in the screened error elements and the error causes of the abnormal elements are reported to the exception handling unit.

5. The vector data processor according to claim 2 further comprises miscellaneous registers, and the vector floating point unit further comprises floating point registers, wherein: The error status register is the floating point number register, and the error cause register is the miscellaneous register.

6. The vector data processor according to claim 2, wherein the instruction decoding unit is specifically used to split the mask vector access instruction to obtain the vector access instruction and the exception reporting instruction; The data access unit is specifically used to load target vector data from the memory in response to the vector access instruction, and update the temporary register based on the target vector data, wherein: The vector access instruction is obtained by splitting the mask vector access instruction; The vector floating-point unit is specifically used to respond to the exception reporting instruction and, based on a mask vector, report the corresponding exception element in the error element and the error cause of the exception element to the exception handling unit; or, read the target vector data from the temporary register and, based on a mask vector, write back the corresponding target element in the target vector data to the vector register.

7. The vector data processor according to claim 2, wherein the instruction decoding unit is specifically used to split the mask vector storage instruction to obtain the vector storage instruction and the exception reporting instruction; The data access unit is specifically configured to respond to the vector storage instruction and write the corresponding target element in the target vector data into the memory based on the mask vector, and when an error element appears in the target vector data, write the error element into the error status register, and write the error cause of the error element into the error cause register; The vector floating point unit is specifically configured to respond to the exception reporting instruction and report the corresponding abnormal element in the error element and the error cause of the abnormal element to the exception handling unit based on a mask vector.

8. The vector data processor according to claim 7, further comprising a mask register; The data access unit is further configured to read the mask vector from the mask register in response to a vector store instruction.

9. An instruction processing method, applied to a vector data processor, wherein: The vector data processor comprises a data access unit and a vector floating point unit, the data access unit comprises a temporary register, and the vector floating point unit comprises a vector register, including: In response to a vector memory access instruction, access target vector data from a memory, wherein the vector memory access instruction is obtained by splitting a mask vector memory access instruction; Based on the target vector data, updating the temporary register; Reading the target vector data from the temporary register; Based on the mask vector, corresponding target elements in the target vector data are written back to the vector register.

10. A system on chip, comprising: a control unit and a plurality of on-chip components, the plurality of on-chip components including a vector data processor; The control unit is used to control and manage the multiple on-chip components, and the vector data processor is used to execute computer programs / instructions. When the computer programs / instructions are executed by the vector data processor, the steps of the method according to claim 9 are implemented.

11. A computing device comprising: Memory and System-on-Chip; The memory is used to store computer programs / instructions, and the system on chip is used to execute the computer programs / instructions. When the computer program / instructions are executed by the system on chip, the steps of the method according to claim 9 are implemented.

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