Reference voltage buffer circuit of high-precision analog-to-digital converter and calibration method of reference voltage buffer circuit

Abstract

The invention provides a reference voltage buffer circuit of a high-precision analog-to-digital converter and a calibration method of the reference voltage buffer circuit, and the reference voltage buffer circuit is characterized in that the inverted input end of a first operational amplifier is connected with a reference voltage, and the output end of the first operational amplifier is in feedback connection with the in-phase input end through a first driving tube and a voltage division circuit; the inverted input end of the third driving tube is connected with the second voltage dividing node, the output end of the third driving tube is connected with grid electrodes of a plurality of third driving tubes and second driving tubes, and drain electrodes of the third driving tubes are connected to the first voltage dividing node through switches; the width-to-length ratios of the second driving tube and the plurality of third driving tubes are in a linear relationship; logic control signals are input into the plurality of switches and are used for controlling the states of the switches to perform linear calibration of the reference voltage. Linear calibration of the output reference voltage is controlled through binary coding, the total resistance is greatly reduced by designing the linear relation between the resistors, and the effects of reducing the chip area and reducing the cost are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a reference voltage buffer circuit of a high-precision analog-to-digital converter and a calibration method thereof. Background Art

[0002] In the process of high-precision signal chain conversion, it is usually necessary to determine the reference voltage of the data converter first, so as to connect the corresponding relationship between the digital code value and the physical quantity in the real environment. Especially in the field of high-precision measurement, accurate and stable reference voltage is a prerequisite for obtaining accurate analog signals in the process of high-precision analog-to-digital conversion. In the analog-to-digital converter (ADC), in order to obtain a larger ADC input range and meet the requirements of fast signal establishment and conversion, the reference voltage usually needs to be followed by a buffer to amplify the reference voltage and provide a stronger driving capability. The voltage output by the buffer will be used as the new reference voltage of the analog-to-digital converter. The output voltage also needs to meet the performance indicators such as accuracy and stability of the reference voltage. However, since the performance of the ADC reference voltage usually affects the gain error, noise and dynamic error in the analog-to-digital conversion process, and the signal is very sensitive to changes in gain error or noise error in many signal chain applications, the reference output voltage in the signal chain is usually required to be the most accurate voltage available to the data converter. In order to meet the above requirements for the reference voltage, it is usually required to calibrate the DC error of the buffer output voltage to achieve accurate amplification of the reference voltage; at the same time, it is necessary to eliminate or reduce the influence of non-ideal factors such as mismatch and temperature drift to achieve the performance of the reference voltage; on this basis, the cost of the buffer circuit must also be considered, including the mass production test cost and the chip area cost.

[0003] See also Figure 1 , Figure 1 It is a traditional buffer circuit for high-precision analog-to-digital converters, which includes an operational amplifier (OPA), a common-source PMOS transistor MP1, and a negative feedback network composed of a resistor divider. The negative input terminal of the OPA is connected to a reference voltage signal Vbg, and the reference voltage Vbg is a low-temperature drift and high-precision voltage generated by a bandgap reference circuit. The output terminal of the OPA is connected to the gate of the common-source PMOS transistor MP1, and the drain terminal of the common-source PMOS tube is grounded through series resistors R1 and R2, and the voltage divided by resistors R1 and R2 is fed back to the positive input terminal of the OPA to form a negative feedback loop. According to the virtual short and virtual break characteristics of the operational amplifier and the characteristics of the negative feedback network, the output voltage VREF of the buffer circuit can be obtained as:

[0004]

[0005] The resistor R1 is a variable resistor, and the output voltage VREF can be adjusted by adjusting the value of the resistor R1.

[0006] See also Figure 2 In high-precision analog-to-digital converter applications, the reference voltage is usually required to have a very high accuracy to ensure that the code value of the input signal after analog-to-digital conversion represents the accurate input value. Figure 2 Based on the above buffer circuit, the calibration circuit adjusts the reference voltage output by digitally adjusting the resistance value of resistor R1. The resistor R1 is composed of resistor R0 and k resistors Rs in series, each resistor Rs is connected in parallel with a complementary metal oxide semiconductor (CMOS) switch tube, and the switch tube is controlled by signals T(1) to T(k). If the impedance of the CMOS switch tube is ignored, the resistor R1 of the calibration circuit can be obtained as follows:

[0007] R1=R0+k*R S (2)

[0008] Substituting formula (2) into formula (1), we can obtain:

[0009]

[0010] The linear adjustment of VREF is achieved by adjusting the value of the thermometer code T(1)~T(k). From formula (3), it can be seen that the accuracy r of the linear adjustment is:

[0011]

[0012] For a high-precision reference voltage, the accuracy requirement is less than 0.05%, so the adjustment accuracy must be at least 0.025%. For example, assuming that the ADC reference voltage VREF is 3V and the reference voltage Vbg is 1.2V, we can get the following equation (4):

[0013]

[0014] Next, substituting equations (1) and (5) into equation (3) yields R0≈2400Rs. In order to reduce the impact of resistor temperature drift and obtain good matching, R0, R2, and Rs are usually made to have the same root resistance. If Rs is taken as the smallest root resistance, the entire trimming network needs to be composed of at least 4000 Rs. At this time, since the area of ​​the resistor trimming network is proportional to the area of ​​Rs, it consumes a large chip area.

[0015] Furthermore, considering that the CMOS switch in parallel with Rs in the calibration circuit is not an ideal switch and has an equivalent on-resistance, the actual output voltage of the buffer circuit after correction is obtained as follows:

[0016]

[0017] Where N is the bit width of the thermometer code, k is the code value of the thermometer code, R SW is the switch on-resistance, R SW The size of is a quantity that changes with temperature and voltage.

[0018] It can be seen that due to the influence of substrate bias effect on CMOS switch, its equivalent on-resistance changes with the change of source voltage, which leads to the nonlinear relationship between the actual adjustment change value and resistance Rs, that is, the adjustment of output voltage VREF of buffer circuit is nonlinear. Therefore, it can be seen from formula (6) that in order to achieve linear adjustment of output voltage VREF in order to simplify calibration process and time, it is necessary to design the equivalent on-resistance R of CMOS switch tube. SW This requires that the width-to-length ratio of the CMOS switch be extremely large or the length of the resistor Rs be extremely large, which requires more chip area and further increases the cost. At the same time, in order to ensure that the mismatch between Rs is small, the size of Rs also needs to be increased, which further increases the chip area consumed. In addition, due to the switch on-resistance R SW The temperature drift coefficient of is different from the temperature drift coefficient of the resistor R2, and their ratio cannot offset each other, resulting in the temperature stability of the output voltage VREF becoming worse.

[0019] Based on the above situation, if a low-cost two-point calibration method is used, a large deviation will occur. The two-point calibration method is to configure the calibration code twice and obtain two measurement values ​​of the output buffer voltage in mass production testing. The calibration code value required for the target value can be calculated through the linear characteristics. Compared with the binary method and the traversal method, it can save mass production testing time and reduce costs.

[0020] In summary, the shortcomings of the prior art are:

[0021] 1. The ratio of the non-adjustable resistors R0 and R2 to the adjusted resistor Rs is large, which consumes a large chip area and has a high cost.

[0022] 2. The digitally controlled CMOS switch in parallel with the trimming resistor Rs in the calibration circuit has an equivalent impedance, which changes with the signal, resulting in trimming nonlinearity, and is not suitable for the low-cost calibration solution of two-point calibration.

[0023] 3. There is a large mismatch between large-ratio resistors, which requires increasing the resistor size and further increasing the cost.

[0024] 4. The control logic of thermometer code adjustment is complex and requires a logic circuit to convert binary code to thermometer code.

[0025] Therefore, there is a need for a reference voltage buffer circuit and a calibration method thereof that can ensure trimming linearity, reduce resistance area, be suitable for low-cost two-point calibration requirements, and have a simple logic control circuit. Summary of the invention

[0026] The present invention provides a reference voltage buffer circuit for a high-precision analog-to-digital converter and a calibration method thereof, which are mainly used to solve the problems of the existing reference voltage buffer circuit, such as the large area of ​​the resistor trimming network, the nonlinearity of the trimming, and the inability to apply a low-cost two-point calibration method, thereby achieving the effect of ensuring the linearity of the trimming, reducing the resistor area, being applicable to the low-cost two-point calibration requirements, and having a simple logic control circuit.

[0027] The present invention achieves the above-mentioned purpose through the following technical solutions:

[0028] A reference voltage buffer circuit for a high-precision analog-to-digital converter, comprising:

[0029] A first operational amplifier, a first driving tube and a voltage divider circuit, wherein the inverting input terminal of the first operational amplifier is connected to a reference voltage, and the output terminal thereof is connected to the gate of the first driving tube. The output terminal of the first driving tube is used to output a reference voltage, and after voltage division by the voltage divider circuit, the output terminal is fed back to the non-inverting input terminal of the first operational amplifier through a first voltage division node.

[0030] It also includes a second-stage negative feedback circuit and a current adjustment circuit. The second-stage negative feedback circuit includes a second operational amplifier and a second driving tube. The non-inverting input terminal of the second operational amplifier is connected to the first voltage-dividing node, and the inverting input terminal is connected to the second voltage-dividing node of the voltage-dividing circuit. The current adjustment circuit includes a plurality of third driving tubes and a plurality of switches. The gates of the plurality of third driving tubes and the second driving tube are all connected to the output terminal of the second operational amplifier, and the sources thereof are all grounded. The drain of the second driving tube is feedback-connected to the non-inverting input terminal of the second operational amplifier, and the drain of each of the third driving tubes is connected to the first voltage-dividing node through one of the switches.

[0031] The width-to-length ratios of the second driving tube and the third driving tubes are in a linear relationship.

[0032] Wherein, a plurality of the switches are all input with a logic control signal, and are used to control the switch state according to the logic control signal so as to realize the linear calibration of the reference voltage.

[0033] A further solution is that the first driving tube is a PMOS tube, and the second driving tube and the third driving tubes are all NMOS tubes.

[0034] A further solution is that the voltage divider circuit includes a first resistor, a second resistor and a third resistor connected in series, one end of the first resistor is connected to the output end of the first driving tube, and the connection point between the other end and the second resistor is the first voltage divider node, the connection point between one end of the third resistor and the second resistor is the second voltage divider node, and the other end is grounded.

[0035] A further solution is that the second feedback circuit also includes a fourth resistor and a fifth resistor, the non-inverting input terminal of the second operational amplifier is connected to the first voltage dividing node through the fourth resistor, and the inverting input terminal thereof is connected to the second voltage dividing node through the fifth resistor.

[0036] A further solution is that the sizes of the plurality of third driving tubes are increased proportionally according to a proportionality coefficient, and are respectively connected to the first voltage dividing node in sequence through the switches connected in series therewith to form a parallel network.

[0037] The proportional coefficient is determined according to the target adjustment range.

[0038] A further solution is that, assuming that the width-to-length ratio of the second driving tube is m times the length-to-width ratio of the third driving tube with the smallest size in the parallel network, the current adjustment accuracy r is:

[0039]

[0040] Among them, V bg is the reference voltage, V ref is the reference voltage, and R1 to R4 are resistance values ​​of the first resistor to the fourth resistor respectively.

[0041] A further solution is that the logic control signal is encoded in binary, and the reference voltage is:

[0042]

[0043] Wherein, k is the code value of the binary code.

[0044] A further solution is that the resistance values ​​of the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor are determined according to different proportional coefficients based on the same root resistor.

[0045] A further solution is to use the second resistor as the root resistor, determine the resistance values ​​of the first resistor and the third resistor according to the adjustment range, determine the resistance value of the fourth resistor according to the optimal number of resistors in the circuit, and determine the resistance value of the fifth resistor according to the impedance adaptation rate of the second feedback circuit.

[0046] A calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter, applied to the reference voltage buffer circuit of the high-precision analog-to-digital converter, comprises:

[0047] S1: Determine a trimming accuracy according to the accuracy of a target reference voltage, and obtain a circuit relationship equation related to the trimming accuracy.

[0048] S2: Inputting the width-to-length ratio relationship between the second driving tube and the third driving tube, the base voltage, the reference voltage and the trimming accuracy value into the circuit relationship equation to obtain the resistance relationship equation between the first resistor to the fourth resistor.

[0049] S3: Select a root resistor, and determine the resistance values ​​of the first resistor to the fourth resistor and the number of the third driving tubes in the current trimming circuit according to the target trimming range, the root resistor and the resistance relationship.

[0050] S4: configuring binary code by a two-point calibration method, and controlling corresponding switch actions according to the binary code, so as to perform linear calibration on the reference voltage output by the first driving tube.

[0051] It can be seen that the present invention has the following beneficial effects:

[0052] 1. The present invention controls the switch state through binary coding, thereby controlling the current flowing from the driving tube MP0 through the resistor R1 to change proportionally, so that the voltage change value across the first resistor changes linearly with the switch S1~Sj signals, thereby achieving linear calibration of the output reference voltage; and by designing the linear relationship of the resistors in the second negative feedback circuit and the voltage divider circuit, the total resistance of the present invention is greatly reduced compared with the traditional circuit under the premise of meeting the same adjustment accuracy requirements, achieving the effect of greatly reducing the chip area and reducing the cost while ensuring the linearity of the adjustment.

[0053] 2. The resistors of the present invention can be determined by taking the same root resistor, so that the resistance value deviation caused by the resistor due to temperature and process angle deviation can offset each other, and the reference voltage and the base voltage can achieve the same level of accuracy and stability.

[0054] 3. The present invention determines the resistance value of the fifth resistor according to the resistance value of the fourth resistor and the impedance matching rate of the second feedback circuit, thereby avoiding the need to increase the resistor size due to large mismatch between large-proportion resistors, further reducing the total resistance, thereby further reducing the chip area and reducing costs.

[0055] 4. The resistance value of the present invention can be flexibly selected according to the adjustment range, and the number of current mirrors in the current adjustment network can also be flexibly selected according to the adjustment range, thereby improving the flexibility and applicability of the circuit.

[0056] 5. The present invention greatly simplifies the control circuit by performing logic control through binary coding. The control logic is simple and the area of ​​the control circuit is much smaller than that of a thermometer coding circuit with the same bit width, further reducing the chip area and reducing the cost.

[0057] 6. The adjustment linearity of the reference voltage of the present invention is determined by the linearity of the current mirror formed by the second driving tube MN0 and the driving tubes MN1~MNj. Conventional layout matching means can be used to achieve higher linearity to meet the low-cost two-point calibration requirements in chip mass production. Compared with the traditional binary method and traversal method, it can save mass production test time and reduce costs.

[0058] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 The invention is a circuit schematic diagram of a reference voltage buffer circuit in the prior art.

[0060] Figure 2 It is a schematic diagram of calibration of reference voltage in the prior art.

[0061] Figure 3 It is a circuit principle diagram of the reference voltage buffer circuit of the present invention.

[0062] Figure 4 The present invention is a flow chart of a calibration method for a reference voltage buffer circuit. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0064] A reference voltage buffer circuit for a high-precision analog-to-digital converter and a calibration method thereof

[0065] See also Figure 3 The present invention relates to a reference voltage buffer circuit of a high-precision analog-to-digital converter, comprising a first operational amplifier 101, a first driving tube MP0 and a voltage dividing circuit. The inverting input terminal of the first operational amplifier 101 is connected to a reference voltage Vbg, and the output terminal thereof is connected to a gate of the first driving tube MP0. The output terminal of the first driving tube MP0 is used to output a reference voltage Vref, and after voltage division by the voltage dividing circuit, the reference voltage Vref is fed back to the non-inverting input terminal of the first operational amplifier 101 through a first voltage dividing node.

[0066] It also includes a second-stage negative feedback circuit S02 and a current adjustment circuit. The second-stage negative feedback circuit S02 includes a second operational amplifier 102 and a second driving tube MN0. The in-phase input terminal of the second operational amplifier 102 is connected to the first voltage-dividing node, and the inverting input terminal thereof is connected to the second voltage-dividing node of the voltage-dividing circuit; the current adjustment circuit includes a plurality of third driving tubes MN1~MNj and a plurality of switches S1~Sj. The gates of the plurality of third driving tubes MN1~MNj and the second driving tube MN0 are all connected to the output terminal of the second operational amplifier 102, and their sources are all grounded; the drain of the second driving tube MN0 is feedback-connected to the in-phase input terminal of the second operational amplifier 102, and the drain of each of the third driving tubes is connected to the first voltage-dividing node through one of the switches.

[0067] The width-to-length ratios of the second driving tube MN0 and the third driving tubes MN1 -MNj are in a linear relationship.

[0068] The switches S1 -Sj are all input with logic control signals, and are used to control the switch states according to the logic control signals so as to achieve linear calibration of the reference voltage.

[0069] Specifically, the present embodiment adopts a two-stage negative feedback circuit, wherein the first operational amplifier 101, the first driving tube MP0 and the voltage divider circuit constitute the first stage negative feedback circuit S01, the reference voltage Vref is output through the drain of the first driving tube MP0, and the first driving tube MP0 provides a strong driving capability; the second operational amplifier 102, the second driving tube MN0, the fourth resistor R4 and the fifth resistor R5 constitute the second stage negative feedback circuit S02. By introducing negative feedback, the nonlinear distortion of the amplifier circuit is improved, the linearity is improved, and the fluctuation of the output voltage signal can be effectively reduced to make the circuit more stable and reliable, and the noise and interference inside the circuit can be suppressed, and the signal-to-noise ratio and clarity of the signal can be further improved.

[0070] In this embodiment, the first driving transistor MP0 is a PMOS transistor, and the second driving transistor MN0 and a plurality of third driving transistors MN1 ˜MNj are NMOS transistors.

[0071] In this embodiment, the voltage divider circuit includes a first resistor R1, a second resistor R2 and a third resistor R3 connected in series, one end of the first resistor R1 is connected to the output end of the first driving tube MP0, and the connection point between the other end and the second resistor R2 is the first voltage divider node, the connection point between one end of the third resistor R3 and the second resistor R2 is the second voltage divider node, and the other end is grounded.

[0072] In this embodiment, the second feedback circuit further includes a fourth resistor R4 and a fifth resistor R5, the non-inverting input terminal of the second operational amplifier 102 is connected to the first voltage dividing node through the fourth resistor R4, and the inverting input terminal thereof is connected to the second voltage dividing node through the fifth resistor R5.

[0073] In this embodiment, the sizes of the third driving transistors MN1 -MNj are increased proportionally according to the proportional coefficient, and are respectively connected to the first voltage dividing node in sequence through the switches connected in series therewith to form a parallel network.

[0074] The proportional coefficient is determined according to the target adjustment range.

[0075] Specifically, in this embodiment, the current trimming circuit is a current trimming network S03 composed of j driving tubes MN1-MNj and j switches S1-Sj, wherein the driving tubes MN1-MNj and the second driving tube MN0 form a current mirror image relationship, the proportional coefficient is 2, and the driving tubes MN1-MNj are proportionally amplified according to a relationship of 2. The bits of the binary code correspond to the switches S1-Sj in order from low to high.

[0076] Here, we take j=3 as an example to explain the control logic, as shown in the following table, where I trim is the minimum trimming current.

[0077] Table 1 Binary coding to achieve linear adjustment control logic table

[0078] S3 S2 S1 The total trimming current flowing through R1 0 0 0 <![CDATA[0*I trim ]]> 0 0 1 <![CDATA[1*I trim ]]> 0 1 0 <![CDATA[2*I trim ]]> 0 1 1 <![CDATA[3*I trim ]]> 1 0 0 <![CDATA[4*I trim ]]> 1 0 1 <![CDATA[5*I trim ]]> 1 1 0 <![CDATA[6*I trim ]]> 1 1 1 <![CDATA[7*I trim ]]>

[0079] As can be seen from Table 1, by controlling the switching states of the switches S1 to S3 through binary coding, the current flowing from the first driving tube MP0 through the first resistor R1 can be controlled to change proportionally, so that the voltage change value across the first resistor R1 changes linearly with the switching states of the switches S1 to S3, thereby achieving linear calibration of the output reference voltage Vref.

[0080] Specifically, in this embodiment, the width-to-length ratio of the second driving tube MN0 is m times the width-to-length ratio of the third driving tube with the smallest size in the parallel network. trim It is equal to 1 / m times of the drain current flowing through the second drive tube MN0. According to the virtual short and virtual break characteristics of the operational amplifier and Kirchhoff's law of the circuit, the drain current I of the second drive tube MN0 can be obtained. MN0 for:

[0081]

[0082] Among them, V bg is the reference voltage, and R2-R4 are the resistance values ​​of the second resistor R2-the fourth resistor R4 respectively.

[0083] From formula 1-1, we can get the minimum trimming current I of the current trimming network S03: trim for:

[0084]

[0085] In this embodiment, assuming that the width-to-length ratio of the second driving tube MN0 is m times the length-to-width ratio of the third driving tube with the smallest size in the parallel network, the current adjustment accuracy r is:

[0086]

[0087] Among them, V bg is the reference voltage, V ref is a reference voltage, and R1 - R4 are resistance values ​​of the first resistor R1 - the fourth resistor R4 respectively.

[0088] Specifically, in this embodiment, since the adjustment range of the general reference voltage Vref is very small, the reference voltage Vref can be obtained as follows:

[0089]

[0090] Specifically, in this embodiment, V bg =1.2V, V ref =3V as an example, substituting into equation 1-4, we can get:

[0091]

[0092] Substituting equation 1-5 into equation 1-3, the current adjustment accuracy r is:

[0093]

[0094] The accuracy requirement for the reference voltage of a high-precision digital-to-analog converter is less than 0.05%, so the adjustment accuracy must be at least 0.025%. Substituting r = 0.025% into equation 1-6, we get:

[0095]

[0096]

[0097] Substituting m=32 into equation 1-7, we get R4=75*R2. Taking R2 as the root resistor, select R1, R3, and R4. For impedance matching of the second operational amplifier 102, select R5=R4.

[0098] Specifically, it can be seen from Formulas 1-7 that the total resistance required to achieve the same trimming accuracy is greatly reduced compared to the traditional circuit in the present invention, thereby achieving a significant reduction in chip area while ensuring the linearity of the trimming, thereby reducing costs; in addition, the values ​​of R1 and r3 can be flexibly selected according to the trimming range, and the number of current mirrors in the current trimming network S03 can also be flexibly selected according to the trimming range, thereby improving the flexibility and applicability of the circuit; logical control through binary coding greatly simplifies the control circuit, the control logic is simple, and the area of ​​the control circuit is much smaller than that of a thermometer encoding circuit with the same bit width, thereby further reducing the chip area and reducing costs.

[0099] Specifically, in this embodiment, it can be seen from Table 1 that the circuit access size of the driving tube controlled by S1 to Sj can be enlarged in proportion according to the binary code, and the reference voltage Vref output by the binary code with the code value k is:

[0100]

[0101] The above formula can be rearranged to obtain:

[0102]

[0103] In this embodiment, the resistance values ​​of the first resistor R1 , the second resistor R2 , the third resistor R3 , the fourth resistor R4 , and the fifth resistor R5 are determined according to different proportional coefficients based on the same root resistor.

[0104] In this embodiment, the second resistor R2 is used as the root resistor, the resistance values ​​of the first resistor R1 and the third resistor R3 are determined according to the adjustment range, the resistance value of the fourth resistor R4 is determined according to the optimal number of resistors in the circuit, and the resistance value of the fifth resistor R5 is determined according to the impedance adaptation rate in the second feedback circuit.

[0105] It can be seen from formula 1-8 that the reference voltage Vref is in linear proportion to the reference voltage Vbg, and is related to the ratio of each resistor, but has little to do with the absolute value of the resistor. Therefore, each resistor can be made to have the same root resistance, so that the resistance value offset caused by the temperature and process angle deviation caused by the resistor can offset each other, so that the reference voltage Vref and the reference voltage Vbg can achieve the same level of accuracy and stability; and the adjustment linearity of the reference voltage Vref is determined by the linearity of the current mirror formed by the second driving tube MN0 and the driving tubes MN1~MNj, and conventional layout matching means can be used to achieve higher linearity to meet the low-cost two-point calibration requirements in chip mass production.

[0106] A method for calibrating a reference voltage buffer circuit of a high-precision analog-to-digital converter

[0107] See also Figure 4The present invention relates to a calibration method for a reference voltage buffer circuit of a high-precision analog-to-digital converter, which is applied to the reference voltage buffer circuit of the high-precision analog-to-digital converter, and comprises:

[0108] S1: Determine a trimming accuracy according to the accuracy of a target reference voltage, and obtain a circuit relationship equation related to the trimming accuracy.

[0109] S2: Input the width-to-length ratio relationship between the second driving tube MN0 and the third driving tube, the base voltage Vbg, the reference voltage Vref and the adjustment accuracy value into the circuit relationship equation to obtain the resistance relationship equation between the first resistor R1 to the fourth resistor R4.

[0110] S3: Select a root resistor, and determine the resistance values ​​of the first resistor R1 to the fourth resistor R4 and the number of third driving tubes in the current trimming circuit according to the target trimming range, the root resistor and the resistance relationship.

[0111] S4: configuring binary code by using a two-point calibration method, and controlling corresponding switch actions according to the binary code, so as to perform linear calibration on the reference voltage Vref output by the first driving tube MP0.

[0112] Specifically, step S3 of this embodiment further includes:

[0113] S31: determining the resistance value of the fifth resistor R5 according to the value of the fourth resistor R4 and the impedance adaptation rate of the second feedback circuit.

[0114] Specifically, the two-point calibration method in step S4 of this embodiment further includes:

[0115] S41: configuring the binary code twice, controlling corresponding switch actions according to the binary code twice, and obtaining two measurement values ​​of the reference voltage Vref;

[0116] S42: Calculating a target code value of binary code required to reach a target reference voltage according to the linear characteristics of the above two measured values;

[0117] S43: Reconfigure the binary code according to the target code value.

[0118] The above-mentioned embodiments are only preferred embodiments of the present invention and cannot be used to limit the scope of protection of the present invention. Any non-substantial changes and substitutions made by technicians in this field on the basis of the present invention shall fall within the scope of protection required by the present invention.

Claims

1. A reference voltage buffer circuit for a high-precision analog-to-digital converter, comprising a first operational amplifier, a first driving tube and a voltage divider circuit, wherein the inverting input terminal of the first operational amplifier is connected to a reference voltage, and the output terminal thereof is connected to a gate of the first driving tube, and the output terminal of the first driving tube is used to output a reference voltage, and after voltage division by the voltage divider circuit, the reference voltage is fed back to the non-inverting input terminal of the first operational amplifier through a first voltage division node, characterized in that: Also includes: A second-stage negative feedback circuit and a current trimming circuit, wherein the second-stage negative feedback circuit comprises a second operational amplifier and a second driving tube, wherein the non-inverting input terminal of the second operational amplifier is connected to the first voltage-dividing node, and the inverting input terminal thereof is connected to the second voltage-dividing node of the voltage-dividing circuit; the current trimming circuit comprises a plurality of third driving tubes and a plurality of switches, wherein the gates of the plurality of third driving tubes and the second driving tube are all connected to the output terminal of the second operational amplifier, and the sources thereof are all grounded; the drain of the second driving tube is feedback-connected to the non-inverting input terminal of the second operational amplifier, and the drain of each of the third driving tubes is connected to the first voltage-dividing node through one of the switches; Wherein, the width-to-length ratio between the second driving tube and the plurality of third driving tubes is in a linear relationship; Wherein, a plurality of the switches are all input with a logic control signal, and are used to control the switch state according to the logic control signal so as to realize the linear calibration of the reference voltage.

2. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 1, characterized in that: The first driving tube is a PMOS tube, and the second driving tube and a plurality of the third driving tubes are NMOS tubes.

3. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 1, characterized in that: The voltage divider circuit includes a first resistor, a second resistor and a third resistor connected in series, one end of the first resistor is connected to the output end of the first driving tube, and the connection point between the other end and the second resistor is the first voltage divider node, the connection point between one end of the third resistor and the second resistor is the second voltage divider node, and the other end is grounded.

4. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 3, characterized in that: The second feedback circuit also includes a fourth resistor and a fifth resistor. The non-inverting input terminal of the second operational amplifier is connected to the first voltage-dividing node through the fourth resistor, and the inverting input terminal thereof is connected to the second voltage-dividing node through the fifth resistor.

5. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 4, characterized in that: The sizes of the plurality of third driving tubes are increased proportionally according to the proportional coefficient, and are connected to the first voltage dividing node in sequence through the switches connected in series therewith to form a parallel network; The proportional coefficient is determined according to the target adjustment range.

6. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 5, characterized in that: Assuming that the width-to-length ratio of the second driving tube is m times the length-to-width ratio of the third driving tube with the smallest size in the parallel network, the current adjustment accuracy r is: Among them, V bg is the reference voltage, V ref is the reference voltage, and R1 to R4 are resistance values ​​of the first resistor to the fourth resistor respectively.

7. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 6, characterized in that: The logic control signal is encoded in binary, and the reference voltage is: Wherein, k is the code value of the binary code.

8. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to any one of claims 1 to 7, characterized in that: The resistance values ​​of the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor are determined according to different proportional coefficients based on the same root resistor.

9. The reference voltage buffer circuit of the high-precision analog-to-digital converter according to claim 8, characterized in that: Taking the second resistor as the root resistor, the resistance values ​​of the first resistor and the third resistor are determined according to the adjustment range, the resistance value of the fourth resistor is determined according to the optimal number of resistors in the circuit, and the resistance value of the fifth resistor is determined according to the impedance adaptation rate of the second feedback circuit.

10. A method for calibrating a reference voltage buffer circuit of a high-precision analog-to-digital converter, characterized in that: A reference voltage buffer circuit for a high-precision analog-to-digital converter according to any one of claims 1 to 9, comprising: S1: determining a trimming accuracy according to the accuracy of a target reference voltage, and obtaining a circuit relationship equation for the trimming accuracy; S2: inputting the width-to-length ratio relationship between the second driving tube and the third driving tube, the base voltage, the reference voltage and the adjustment accuracy value into the circuit relationship equation to obtain the resistance relationship equation between the first resistor to the fourth resistor; S3: selecting a root resistor, and determining resistance values ​​of the first resistor to the fourth resistor and the number of third driving tubes in the current trimming circuit according to the target trimming range, the root resistor and the resistance relationship; S4: configuring binary code by a two-point calibration method, and controlling corresponding switch actions according to the binary code, so as to perform linear calibration on the reference voltage output by the first driving tube.

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