Image signal transmission device and signal output circuit

Abstract

The present application discloses an image signal transmission device and a signal output circuit having a DC gain maintenance mechanism, which are applied to the image signal transmission device and include: a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous-time linear equalizer with a variable capacitor, and is configured to receive a digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The post-stage driving circuit includes a continuous-time linear equalizer without a variable capacitor, and is configured to perform a DC gain boost on the pre-stage output signal to compensate for the decrease in the DC gain of the pre-stage output signal relative to the digital input signal, thereby further generating a post-stage output signal to the image signal receiving device.

Description

Technical Field

[0001] The present invention relates to a signal output technology, and in particular to an image signal transmission device and a signal output circuit thereof with a DC gain maintaining mechanism. Background Art

[0002] High Definition Multimedia Interface (HDMI) is a fully digital audio and video interface capable of transmitting uncompressed audio and video signals. Because it can transmit both audio and video signals over the same cable, HDMI's transmission technology greatly simplifies system wiring installation.

[0003] Systems using this transmission technology include a source for transmitting audio and video signals and a receiver for receiving them. The source relies on the configuration of the signal output circuit to properly adjust the audio and video signals to ensure high-quality audio and video signals at the receiver. However, signal output circuits often sacrifice DC gain performance in order to increase AC gain. Summary of the Invention

[0004] In view of the problems in the prior art, an object of the present invention is to provide an image signal transmission device and a signal output circuit thereof with a DC gain maintaining mechanism to improve the prior art.

[0005] The present invention includes a signal output circuit with a DC gain maintenance mechanism, which is applied to an image signal transmission device (TX), including: a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous time linear equalizer (CTLE) with a variable capacitor, and is configured to receive a digital input signal and perform high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The post-stage driving circuit includes a continuous time linear equalizer without a variable capacitor, and is configured to perform DC gain boost on the pre-stage output signal to compensate for the DC gain drop of the pre-stage output signal relative to the digital input signal, further generating a post-stage output signal to an image signal receiving device (RX).

[0006] The present invention further includes an image signal transmission device, which is used in an image signal transmission system and includes: a digital signal processing circuit and a signal output circuit. The digital signal processing circuit is configured to generate a digital input signal. The signal output circuit includes: a pre-stage driving circuit and a post-stage driving circuit. The pre-stage driving circuit includes a continuous-time linear equalizer and is configured to receive a digital input signal for high-frequency enhancement to increase the bandwidth of the digital input signal, thereby generating a pre-stage output signal. The post-stage driving circuit includes a continuous-time linear equalizer without a variable capacitor and is configured to perform a DC gain boost on the pre-stage output signal to compensate for the DC gain drop of the pre-stage output signal relative to the digital input signal, thereby further generating a post-stage output signal to the image signal receiving device.

[0007] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram showing an image signal transmission system according to an embodiment of the present invention; and

[0009] Figure 2 A circuit diagram showing a front-stage driving circuit in one embodiment of the present invention;

[0010] Figure 3 A schematic diagram showing the frequency response of a pre-stage driving circuit according to an embodiment of the present invention;

[0011] Figure 4 A circuit diagram showing a post-stage driving circuit in one embodiment of the present invention;

[0012] Figure 5 A schematic diagram showing the frequency response of a post-stage driving circuit in one embodiment of the present invention; and

[0013] Figure 6 A schematic diagram showing the frequency response of a post-stage output signal after a digital input signal is processed by a pre-stage driving circuit and a post-stage driving circuit in one embodiment of the present invention.

[0014]

Explanation of symbols

[0015] 100: Image signal transmission system

[0016] 110: Image signal transmission device

[0017] 120: Image signal receiving device

[0018] 130: Digital signal processing circuit

[0019] 140:Signal output circuit

[0020] 150: Pre-stage drive circuit

[0021] 160: Post-stage drive circuit

[0022] C1, C2: load capacitance

[0023] C3: variable capacitor

[0024] Cd, Cs: capacitance value

[0025] GND: Ground terminal

[0026] I1, I2: current source

[0027] MN1, MN2: input transistors

[0028] O1, O2: output terminals

[0029] Vip, Vin: digital input signal

[0030] Vop1, Von1: pre-stage output signal

[0031] Vop2, Von2: output signal of the post-stage

[0032] R1, R2: load resistors

[0033] R3: variable resistor

[0034] Rd, Rs: resistance value

[0035] ω P1 、ω P2 :pole

[0036] ω Z :Zero o'clock DETAILED DESCRIPTION

[0037] One object of the present invention is to provide an image signal transmission device and a signal output circuit thereof having a DC gain maintenance mechanism. The DC gain is increased by configuring a post-stage driving circuit to compensate for the DC gain drop caused by the pre-stage driving circuit, thereby increasing the bandwidth of the output signal without sacrificing DC gain.

[0038] Please refer to Figure 1 . Figure 1 FIG1 is a block diagram of a video signal transmission system 100 according to an embodiment of the present invention. The video signal transmission system 100 includes a video signal transmitter (TX) 110 and a video signal receiver (RX) 120 .

[0039] In one embodiment, the video signal transmission system 100 is a system for transmitting video and audio using a high-definition multimedia interface. The video signal transmission device 110 is a source, such as, but not limited to, a set-top box, a DVD player, or a computer. The video signal reception device 120 is a sink, such as, but not limited to, a television, a projector, or other display device. The video signal transmission device 110 is configured to process the video and audio signals and transmit them to the video signal reception device 120 for playback.

[0040] The video signal transmitting device 110 includes a digital signal processing circuit 130 and a signal output circuit 140 .

[0041] The digital signal processing circuit 130 is configured to generate differential digital input signals Vip and Vin. The signal output circuit 140 has a DC gain maintenance mechanism to enhance the output of the digital input signals Vip and Vin. The signal output circuit 140 includes a pre-stage driver circuit 150 and a post-stage driver circuit 160.

[0042] The pre-stage driving circuit 150 is configured to receive the digital input signals Vip and Vin and perform high frequency enhancement to increase the bandwidth of the digital input signals Vip and Vin, thereby generating pre-stage output signals Vop1 and Von1. The pre-stage output signals Vop1 and Von1 are also differential signals.

[0043] Please refer to Figure 2 . Figure 2 A circuit diagram of a pre-driver circuit 150 according to one embodiment of the present invention is shown. In one embodiment, the pre-driver circuit 150 includes a continuous-time linear equalizer with a variable capacitor. Specifically, the continuous-time linear equalizer includes two input transistors MN1 and MN2, two load resistors R1 and R2, two load capacitors C1 and C2, a variable resistor R3, a variable capacitor C3, and two current sources I1 and I2.

[0044] Each input transistor MN1 and MN2 includes a gate, a drain, and a source. The gate of input transistor MN1 is configured to receive a digital input signal Vip. The gate of input transistor MN2 is configured to receive a digital input signal Vin. The drain of input transistor MN1 is electrically coupled to output terminal O1, and the drain of input transistor MN2 is electrically coupled to output terminal O2.

[0045] The drain of the input transistor MN1 is configured to generate a pre-stage output signal Vop1 to the output terminal O1 , and the drain of the input transistor MN2 is configured to generate a pre-stage output signal Von1 to the output terminal O2 .

[0046] Load resistor R1 is electrically coupled between the drain of input transistor MN1 and operating voltage source VDD. Load resistor R2 is electrically coupled between the drain of input transistor MN2 and operating voltage source VDD. Load capacitor C1 is electrically coupled between the drain of input transistor MN1 and operating voltage source VDD. Load capacitor C2 is electrically coupled between the drain of input transistor MN2 and operating voltage source VDD.

[0047] The variable resistor R3 and the variable capacitor C3 are electrically connected in parallel between the sources of the input transistors MN1 and MN2. The current source I1 is electrically coupled between the source of the input transistor MN1 and the ground terminal GND. The current source I2 is electrically coupled between the source of the input transistor MN2 and the ground terminal GND.

[0048] In one embodiment, the zero point and the two poles of the frequency response of the pre-stage driver circuit 150 are determined by a plurality of circuit parameter values ​​of the pre-stage driver circuit 150 .

[0049] Please also refer to Figure 3 . Figure 3 A schematic diagram showing the frequency response of the pre-stage driver circuit 150 according to one embodiment of the present invention is shown. The horizontal axis represents frequency, and the vertical axis represents gain. In this embodiment, the gain corresponding to the horizontal axis represents the original gain of the digital input signals Vip and Vin.

[0050] In one embodiment, the circuit parameters of the pre-driver circuit 150 include the transconductance of the transistors, the resistance values ​​of the resistors, and the capacitance values ​​of the capacitors. For example, the transconductance of the input transistors MN1 and MN2 is gm, the resistance values ​​of the load resistors R1 and R2 are Rd, the capacitance values ​​of the load capacitors C1 and C2 are Cd, the resistance value of the variable resistor is 2Rs, and the capacitance value of the variable capacitor is Cs.

[0051] Therefore, in terms of the frequency response of the pre-stage driving circuit 150, the conversion function H(s) for converting the digital input signals Vip and Vin into the pre-stage output signals Vop1 and Von1 can be expressed as follows:

[0052] H(s)=(gmRd)(1+sRsCs) / (1+sRcCs+gmRs)(1+sRdCd))

[0053] Furthermore, the DC gain of the pre-stage driving circuit 150 can be expressed as follows:

[0054] (gmRd) / (1+(gmRs))

[0055] Zero ω on the frequency response Z It can be expressed as follows:

[0056] ωZ =1 / (RsCs)

[0057] One of the extreme points ω P1 It can be expressed as follows:

[0058] ω P1 =(1+gmRs) / (RsCs)

[0059] Another extreme point P2 It can be expressed as follows:

[0060] ω P2 =1 / (RdCd)

[0061] Therefore, by adjusting the aforementioned circuit parameters, the zero point and the two poles of the frequency response of the pre-stage driving circuit 150 can be changed accordingly, thereby achieving different degrees of improvement in the DC gain and the high frequency part.

[0062] It should be noted that after being processed by the pre-stage driving circuit 150 , the DC gain of the pre-stage output signals Vop1 and Von1 relative to the digital input signals Vip and Vin is reduced.

[0063] The post-stage driving circuit 160 is configured to receive the front-stage output signals Vop1 and Von1, perform DC gain boosting on the front-stage output signals Vop1 and Von1, and compensate for the DC gain reduction of the front-stage output signals Vop1 and Von1 relative to the digital input signals Vip and Vin, and further generate post-stage output signals Vop2 and Von2 to the image signal receiving device 120. The post-stage output signals Vop2 and Von2 are also differential signals.

[0064] Please refer to Figure 4 . Figure 4 A circuit diagram of a post-stage driver circuit 160 is shown in one embodiment of the present invention. In one embodiment, post-stage driver circuit 160 comprises a continuous-time linear equalizer (CTL) without a variable capacitor. Specifically, the CTL includes two input transistors MN1 and MN2, two load resistors R1 and R2, two load capacitors C1 and C2, a variable resistor R3, and two current sources I1 and I2. Note that since post-stage driver circuit 160 is structurally similar to pre-stage driver circuit 150, corresponding components are not numbered.

[0065] Aside from not including a variable capacitor, the connection and operation of the other components of the post-stage driver circuit 160 are substantially similar to those of the pre-stage driver circuit 150 , and therefore, the similarities will not be further described. In this embodiment, the gate of the input transistor MN1 of the post-stage driver circuit 160 is configured to receive the pre-stage output signal Vop1 . The gate of the input transistor MN2 is configured to receive the pre-stage output signal Von1 . Furthermore, the drain of the input transistor MN1 is configured to generate a post-stage output signal Vop2 to the output terminal O1 , and the drain of the input transistor MN2 is configured to generate a post-stage output signal Von2 to the output terminal O2 .

[0066] In one embodiment, the frequency response of the post-stage driving circuit 160 includes only a single pole, and the pole is determined by a plurality of circuit parameter values ​​of the post-stage driving circuit 160 .

[0067] Please also refer to Figure 5 . Figure 5 A schematic diagram showing the frequency response of the post-stage driving circuit 160 in one embodiment of the present invention is shown. The horizontal axis represents frequency, and the vertical axis represents gain. In this embodiment, the gain corresponding to the horizontal axis represents the original gain of the pre-stage output signals Vop1 and Von1.

[0068] Similar to the pre-stage driver circuit 150, the circuit parameters of the post-stage driver circuit 160 include the transconductance of the transistors, the resistance values ​​of each resistor, and the capacitance values ​​of each capacitor. However, these circuit parameters differ from the circuit parameters of the pre-stage driver circuit 150. More specifically, the transconductance of the input transistors MN1 and MN2 is gm, the resistance value of each load resistor R1 and R2 is Rs, the capacitance value of each load capacitor C1 and C2 is Cd, and the resistance value of the variable resistor is 2Rd.

[0069] Therefore, in terms of the frequency response of the subsequent-stage driving circuit 160, the conversion function H(s) for converting the previous-stage output signals Vop1 and Von1 into the subsequent-stage output signals Vop2 and Von2 can be expressed as follows: The conversion function H(s) can be expressed as follows:

[0070] H(s)=(gmRs) / (1+gmRd)(1+sRsCd)

[0071] Furthermore, the DC gain of the subsequent driving circuit 160 can be expressed as follows:

[0072] (gmRs) / (1+(gmRd))

[0073] Single extreme point ω P2 It can be expressed as follows:

[0074] ω P2 =1 / (RsCd)

[0075] It should be noted that after being processed by the post-stage driving circuit 160 , the DC gain of the post-stage output signals Vop2 and Von2 relative to the pre-stage output signals Vop1 and Von1 increases.

[0076] Please refer to Figure 6 . Figure 6 A schematic diagram showing the frequency response of the digital input signals Vip and Vin after being processed by the pre-stage driving circuit 150 and the post-stage driving circuit 160 to output the post-stage output signals Vop2 and Von2 in one embodiment of the present invention. More specifically, Figure 6 The waveform is equivalent to Figure 3 and Figure 5 The result of superimposing the waveforms.

[0077] Since the DC gain of the pre-stage driving circuit 150 is (gmRd) / (1+(gmRs)), and the DC gain of the post-stage driving circuit 160 is (gmRs) / (1+(gmRd)), the DC gain of the post-stage output signals Vop2 and Von2 relative to the digital input signals Vip and Vin can be expressed as follows:

[0078] ((gmRd)(gmRs)) / ((1+(gmRs))(1+(gmRd)))

[0079] In one embodiment, when the product of the transconductance and the resistance of the load resistor (i.e., gmRd and gmRs) of the pre-stage driver circuit 150 and the post-stage driver circuit 160 is significantly greater than 1, the DC gains generated by the pre-stage driver circuit 150 and the post-stage driver circuit 160 cancel each other out. More specifically, under such conditions, the DC gains of the post-stage output signals Vop2 and Von2 relative to the digital input signals Vip and Vin are 1.

[0080] While the signal output circuit achieves AC gain amplification and bandwidth increases when processed by the pre-stage driver circuit, it also reduces DC gain. Therefore, the signal output circuit of the present invention can increase DC gain by configuring the post-stage driver circuit to compensate for the DC gain reduction caused by the pre-stage driver circuit, thereby increasing the output signal bandwidth without sacrificing DC gain.

[0081] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0082] In summary, the image signal transmission device and its signal output circuit with a DC gain maintenance mechanism in the present invention can increase the DC gain by configuring a post-stage driving circuit to compensate for the DC gain drop caused by the pre-stage driving circuit, thereby increasing the bandwidth of the output signal without sacrificing DC gain.

[0083] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. A person having ordinary knowledge in the technical field may make changes to the technical features of the present application based on the explicit or implicit content of the present application. All such changes may fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be based on that defined in the claims of this specification.

Claims

1. A signal output circuit with a DC gain maintenance mechanism, applied to an image signal transmission device, characterized in that: include: A pre-stage driving circuit includes a continuous time linear equalizer having a variable capacitor and is configured to receive a digital input signal and perform high frequency enhancement to increase a bandwidth of the digital input signal, thereby generating a pre-stage output signal; as well as a post-stage driving circuit, comprising the continuous-time linear equalizer without the variable capacitor, and configured to perform a DC gain boost on the pre-stage output signal to compensate for a DC gain drop of the pre-stage output signal relative to the digital input signal, and further generate a post-stage output signal to an image signal receiving device; Wherein, the pre-stage driving circuit includes: Two input transistors, each comprising: a gate configured to receive the digital input signal; a drain electrically coupled to an output terminal and configured to generate the pre-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; a variable resistor and the variable capacitor electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and a ground terminal; The subsequent driving circuit includes: Two input transistors, each comprising: a gate configured to receive the pre-stage output signal; a drain electrically coupled to an output terminal and configured to generate the post-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; a variable resistor electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal; wherein a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values ​​of the pre-stage driving circuit, wherein the plurality of circuit parameters include the resistance value Rd of each of the two load resistors, the capacitance value Cd of each of the two load capacitors, the resistance value 2Rs of the variable resistor, and the capacitance value Cs of the variable capacitor; A transconductance of the two input transistors is gm, the zero point is 1 / (RsCs), the two poles are (1+gmRs) / (RsCs) and 1 / (RdCd), a transfer function between the digital input signal and the pre-stage output signal is (gmRd)(1+sRsCs) / (1+sRcCs+gmRs)(1+sRdCd)), and a DC gain of the pre-stage driver circuit is (gmRd) / (1+(gmRs)).

2. The signal output circuit according to claim 1, wherein: The digital input signal, the front-stage output signal and the rear-stage output signal are respectively differential signals.

3. The signal output circuit according to claim 1, wherein: The pre-stage driving circuit receives the digital input signal from a digital signal processing circuit included in the image signal transmitting device.

4. The signal output circuit of claim 1 , wherein a pole of the frequency response of the post-stage driving circuit is determined by a plurality of circuit parameters of the post-stage driving circuit, the plurality of circuit parameters comprising a resistance value Rs of each of the two load resistors, a capacitance value Cd of each of the two load capacitors, and a resistance value 2Rd of the variable resistor; A transconductance of the two input transistors is gm, the pole is 1 / (RsCd), a transfer function between the digital input signal and the previous stage output signal is (gmRs) / (1+gmRd)(1+sRsCd), and a DC gain of the subsequent stage driving circuit is (gmRs) / (1+(gmRd)).

5. The signal output circuit as claimed in claim 1, wherein the DC gains of the pre-stage driving circuit and the post-stage driving circuit cancel each other when the product of a corresponding transconductance and a resistance value of a load resistor is much greater than 1.

6. An image signal transmission device, used in an image signal transmission system, comprising: a digital signal processing circuit configured to generate a digital input signal; as well as A signal output circuit comprising: a pre-stage driving circuit comprising a continuous time linear equalizer having a variable capacitor, and configured to receive a digital input signal and perform high frequency enhancement to increase a bandwidth of the digital input signal, thereby generating a pre-stage output signal; and a post-stage driving circuit, comprising the continuous-time linear equalizer without the variable capacitor, and configured to perform a DC gain boost on the pre-stage output signal to compensate for a DC gain drop of the pre-stage output signal relative to the digital input signal, and further generate a post-stage output signal to an image signal receiving device; Wherein, the pre-stage driving circuit includes: Two input transistors, each comprising: a gate configured to receive the digital input signal; a drain electrically coupled to an output terminal and configured to generate the pre-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; a variable resistor and the variable capacitor electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and a ground terminal; The subsequent driving circuit includes: Two input transistors, each comprising: a gate configured to receive the pre-stage output signal; a drain electrically coupled to an output terminal and configured to generate the post-stage output signal to the output terminal; and a source; two load resistors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; two load capacitors, each electrically coupled between the drain of one of the two input transistors and an operating voltage source; a variable resistor electrically connected in parallel between the sources of the two input transistors; and two current sources, each electrically coupled between the source of one of the two input transistors and the ground terminal; wherein a zero point and two poles of the frequency response of the pre-stage driving circuit are determined by a plurality of circuit parameter values ​​of the pre-stage driving circuit, wherein the plurality of circuit parameters include the resistance value Rd of each of the two load resistors, the capacitance value Cd of each of the two load capacitors, the resistance value 2Rs of the variable resistor, and the capacitance value Cs of the variable capacitor; A transconductance of the two input transistors is gm, the zero point is 1 / (RsCs), the two poles are (1+gmRs) / (RsCs) and 1 / (RdCd), a transfer function between the digital input signal and the pre-stage output signal is (gmRd)(1+sRsCs) / (1+sRcCs+gmRs)(1+sRdCd)), and a DC gain of the pre-stage driver circuit is (gmRd) / (1+(gmRs)). 7 . The image signal transmission device as claimed in claim 6 , wherein the DC gains of the pre-stage driving circuit and the post-stage driving circuit cancel each other out when the product of a corresponding transconductance and a resistance value of a load resistor is much greater than 1.

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