Wafer-level cooling system and generation method thereof, data processing method, and storage medium

Abstract

The present disclosure provides a wafer-level cooling system and a generation method thereof, a data processing method, and a storage medium. The system includes: a first wafer and a second wafer that are stacked, the first wafer includes a plurality of uncut processing chips, the second wafer includes a plurality of uncut interconnected chips and a micro-guiding layer; the processing chip is used to perform processing tasks; there is a corresponding relationship between the interconnected chip and the processing chip, which is used to achieve communication connection between the processing chips; the micro-guiding layer is located on the side opposite to the interconnected chip layer, and micro-channels are provided in the micro-guiding layer for accommodating heat dissipation liquid to dissipate heat for the wafer-level cooling system, wherein the interconnected chip layer is the layer where the plurality of interconnected chips are located. According to the embodiments of the present disclosure, a high-performance wafer-level cooling system can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a wafer-level cooling system, a method for generating a wafer-level cooling system, a data processing method, and a computer-readable storage medium. Background Art

[0002] In related technologies, chips are usually packaged with the help of a redistribution layer (RDL), which is an interposer made of metal or polymer dielectric materials and contains copper wires or traces for electrical connections between various parts of the package. The bare dies of the chips can be stacked in the package and communicate with each other through the redistribution layer, thereby reducing the I / O spacing of large chipsets. Summary of the invention

[0003] The present disclosure provides a wafer-level cooling system, a method for generating a wafer-level cooling system, a data processing method, and a computer-readable storage medium.

[0004] In a first aspect, the present disclosure provides a wafer-level cooling system, the system comprising:

[0005] A first wafer and a second wafer are stacked, wherein the first wafer includes a plurality of uncut processing chips, and the second wafer includes a plurality of uncut interconnect chips and a micro-guiding layer;

[0006] The processing chip is used to perform processing tasks;

[0007] There is a corresponding relationship between the interconnection chip and the processing chip, which is used to realize the communication connection between the processing chips;

[0008] The micro-guiding layer is located on the side opposite to the interconnected chip layer, and micro-channels are arranged in the micro-guiding layer for containing heat dissipation liquid so as to dissipate heat for the wafer-level cooling system, wherein the interconnected chip layer is the layer where the multiple interconnected chips are located.

[0009] In some embodiments, the second wafer further includes an insulating layer, and the insulating layer is located between the interconnect chip layer and the micro-guiding layer, and is used to separate the interconnect chip layer from the micro-guiding layer.

[0010] In some embodiments, the plurality of processing chips and the plurality of interconnection chips are arranged in an array, and each interconnection chip corresponds to a plurality of adjacent processing chips, and is used to implement communication connection between the plurality of adjacent processing chips.

[0011] In some embodiments, the processing chip is provided with a first bonding boss, the interconnection chip is provided with a second bonding boss, the first bonding boss is bonded with the second bonding boss, and the first bonding boss and the second bonding boss are made of conductive material.

[0012] In some embodiments, the first wafer and the second wafer are bonded via a bonding layer in regions outside the first bonding protrusion and the second bonding protrusion, and the bonding layer is made of an adhesive insulating material.

[0013] In a second aspect, the present disclosure provides a method for generating a wafer-level cooling system, the method comprising:

[0014] Obtain a first wafer and a second wafer, wherein the first wafer has a plurality of uncut processing chips, and the second wafer has a plurality of uncut interconnect chips;

[0015] Wherein, a first bonding boss is arranged on the processing chip, a second bonding boss is arranged on the surface of the interconnection chip, the positions of the first bonding boss and the second bonding boss have a corresponding relationship, and the first bonding boss and the second bonding boss are made of conductive material;

[0016] sequentially generating an insulating layer and a micro-guiding layer on a side of the second wafer opposite to the interconnected chip layer, and generating micro-channels in the micro-guiding layer, wherein the interconnected chip layer is a layer where the plurality of interconnected chips are located;

[0017] Coating a bonding layer on a surface area of ​​the second wafer outside the second bonding protrusion, wherein the bonding layer is made of an adhesive insulating material;

[0018] Bonding the first wafer and the second wafer face to face to obtain a wafer bonding structure, wherein the corresponding first bonding bosses are bonded to the second bonding bosses, and the first wafer and the second wafer are bonded to each other through the bonding layer at surface areas outside the first bonding bosses and the second bonding bosses;

[0019] According to the wafer bonding structure, the wafer-level cooling system is obtained.

[0020] Wherein, the processing chips are communicatively connected to each other via the interconnection chip.

[0021] In some embodiments, there is a matching gap between the bonding layer and the second bonding boss, wherein the first wafer and the second wafer are bonded face to face to obtain a wafer bonding structure, including:

[0022] The first wafer and the second wafer are stacked face to face, wherein the corresponding first bonding bosses are in contact with the surface of the second bonding bosses;

[0023] Pressure is applied to the first wafer and the second wafer so that the corresponding first bonding bosses are bonded with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the second bonding bosses are spatially deformed to fill the fitting gap.

[0024] In some embodiments, the wafer-level cooling system is obtained according to the wafer bonding structure, including:

[0025] The wafer bonding structure is packaged to obtain the wafer-level cooling system.

[0026] In a third aspect, the present disclosure provides a data processing method, which is applied to a processing chip in the above-mentioned wafer-level cooling system, wherein the wafer-level cooling system comprises a first wafer and a second wafer which are stacked, wherein the first wafer comprises a plurality of uncut processing chips, and the second wafer comprises a plurality of uncut interconnection chips and a micro-guiding layer, wherein the interconnection chip is used to realize communication connection between the processing chips; the micro-guiding layer is located on a side opposite to the interconnection chip layer where the plurality of interconnection chips are located, and a micro-channel is provided in the micro-guiding layer for accommodating a heat dissipation liquid so as to dissipate heat for the wafer-level cooling system, wherein the method comprises:

[0027] During the period when the processing chip executes the processing task, the processing chip sends processing data to other processing chips through the interconnection chip connected to the processing chip; and / or receives processing data sent by other processing chips through the interconnection chip connected to the processing chip.

[0028] In a fourth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the above-mentioned data processing method when executed by a processing chip.

[0029] In the embodiment provided by the present disclosure, a first wafer including a processing chip and a second wafer including an interconnection chip are stacked and arranged. The processing chip is communicated through the interconnection chip to achieve high-bandwidth interconnection between the wafers, thereby realizing a high-performance wafer-level cooling system; and a micro-guiding layer is arranged in the wafer where the interconnection chip is located. The micro-pipes in the micro-guiding layer are used to accommodate heat dissipation liquid, thereby improving the heat dissipation effect of the entire system.

[0030] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the present disclosure and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent to those skilled in the art by describing detailed example embodiments with reference to the accompanying drawings, in which:

[0032] Figure 1 A schematic diagram of a wafer-level cooling system provided in an embodiment of the present disclosure.

[0033] Figure 2 A schematic diagram of a second chip provided in an embodiment of the present disclosure.

[0034] Figure 3 A flow chart of a method for generating a wafer-level cooling system provided in an embodiment of the present disclosure.

[0035] Figure 4a and Figure 4b A schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure.

[0036] Figure 5a and Figure 5b A schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure.

[0037] Figure 6 A schematic diagram of bonding a first wafer and a second wafer provided in an embodiment of the present disclosure.

[0038] Figure 7 A schematic diagram of a second chip provided in an embodiment of the present disclosure.

[0039] Figure 8 A schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure.

[0040] Fig. 9 A flowchart of a data processing method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, those of ordinary skill in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted in the following description.

[0042] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0043] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "the" are also intended to include plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "including" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0046] In the related art, chips are usually packaged with the help of a redistribution layer (RDL). The bare dies of the chips can be stacked in the package and communicate with each other through the redistribution layer, thereby reducing the I / O spacing of the large chipset. However, under this packaging method, the redistribution layer is generated based on the substrate. The process precision of the substrate is low, and it is impossible to generate a finer structure (for example, a size of 100nm); and the dielectric constant of the insulating layer in the substrate is difficult to reduce, resulting in a large RC delay (RC Delay) of the generated structure, affecting the performance of the entire packaging system. In addition, this packaging method still requires cutting the chips in the wafer, and the processing process is relatively complicated.

[0047] If semiconductor processes are used to generate interconnect structures between chips, a finer structure can be achieved, and a lower dielectric constant can be achieved. Even a vacuum air gap can be made for insulation, thereby increasing the flexibility of the entire system design and improving system performance.

[0048] According to the embodiment of the present disclosure, a wafer-level packaging method is adopted to directly bond a wafer including a processing chip and a wafer including an interconnection chip face-to-face, so that the processing chip can achieve communication connection through the interconnection chip, thereby improving design flexibility and improving performance. In addition, the embodiment of the present disclosure also provides a micro-guiding layer in the wafer where the interconnection chip is located, and the micro-channels in the micro-guiding layer are used to accommodate heat dissipation liquid, thereby improving the heat dissipation effect of the entire system.

[0049] Figure 1 A schematic diagram of a wafer-level cooling system provided in an embodiment of the present disclosure.

[0050] According to an embodiment of the present disclosure, a wafer-level cooling system is provided, such as Figure 1 As shown, the system includes:

[0051] A first wafer 11 and a second wafer 12 are stacked, wherein the first wafer includes a plurality of uncut processing chips 111, and the second wafer includes a plurality of uncut interconnect chips 121 and a micro-guiding layer 124;

[0052] The processing chip is used to perform processing tasks;

[0053] There is a corresponding relationship between the interconnection chip and the processing chip, which is used to realize the communication connection between the processing chips.

[0054] The micro-guiding layer is located on the side opposite to the interconnected chip layer, and micro-channels 125 are provided in the micro-guiding layer for containing heat dissipation liquid to dissipate heat for the wafer-level cooling system, wherein the interconnected chip layer is the layer where the multiple interconnected chips are located.

[0055] For example, the first chip 11 and the second chip 12 can be completely uncut wafers; they can also be partially cut wafers, for example, wafers are cut into rectangular wafers according to the design size and shape of the wafer-level cooling system, the number of chips required by the wafer-level cooling system, etc.; they can also be wafers that have been processed by thinning, etc., and the present disclosure does not impose any restrictions on this.

[0056] In some embodiments, the first wafer 11 includes a plurality of uncut processing chips 111, and the processing chips 111 are used to perform processing tasks, such as performing various operations in the processing tasks, data interaction, etc. The processing tasks may be, for example, image processing tasks, voice processing tasks, text processing tasks, video processing tasks, etc., and the present disclosure does not limit the specific types of processing tasks.

[0057] In some embodiments, the processing chip 111 may be a multi-core chip, including multiple processing cores. The processing core may also be referred to as a "core" or "core", which is the smallest unit in the multi-core chip that can be independently scheduled and has complete computing capabilities. Each processing core has its own storage and computing resources. The present disclosure does not limit the specific chip type and chip structure of the processing chip.

[0058] In some embodiments, the second wafer 12 includes a plurality of uncut interconnect chips 121, and the interconnect chip 121 may be an interconnect structure generated based on a semiconductor process, including metal interconnect lines and an insulating layer, etc. A small number of processing devices, storage devices, etc. may also be provided in the interconnect chip 121, and the present disclosure does not limit the materials, processes, and specific structures of the interconnect chip.

[0059] In some embodiments, the plurality of processing chips and the plurality of interconnection chips are arranged in an array, that is, a processing chip array and an interconnection chip array, respectively. The first wafer 11 and the second wafer 12 can be arranged in a face-to-face stacking manner, so that each interconnection chip and each processing chip can be connected to each other.

[0060] In some embodiments, there is a corresponding relationship between the interconnection chip and the processing chip, which is used to realize the communication connection between each processing chip. Each interconnection chip may correspond to multiple adjacent processing chips, which is used to realize the communication connection between multiple adjacent processing chips. For example, one interconnection chip corresponds to four adjacent processing chips, and connects the four adjacent processing chips so that these chips can communicate with each other through the interconnection chip.

[0061] In this case, the number of processing chips is different from the number of interconnect chips. Figure 1 As shown in the figure, the number of processing chips included in the cross section of the first wafer 11 is 5, indicating that there are 5 rows or 5 columns of processing chips; the number of interconnection chips included in the cross section of the second wafer 12 is 4, indicating that there are 4 rows or 4 columns of interconnection chips.

[0062] By arranging the interconnection chips and the processing chips in a staggered manner corresponding to each other, the interconnection chips can realize communication connection between multiple adjacent processing chips, thereby improving the connection efficiency between the processing chips.

[0063] In some embodiments, Figure 1 As shown, the processing chip is provided with a first bonding boss 112, and the interconnection chip is provided with a second bonding boss 122. The first bonding boss 112 is engaged with the second bonding boss 122 to achieve electrical connection between the processing chip and the interconnection chip.

[0064] The first bonding boss and the second bonding boss are made of a conductive material. The conductive material includes any one of copper, aluminum, and gold. The present disclosure does not limit the specific type of the conductive material.

[0065] In some embodiments, the first wafer and the second wafer are bonded via a bonding layer 123 in an area outside the first bonding boss and the second bonding boss, and the bonding layer is used for packaging and fixing to achieve a bonding connection between the first wafer and the second wafer.

[0066] The bonding layer is made of an adhesive insulating material. The insulating material includes any one of silicon carbide, epoxy resin, polyimide, and tetraethyl silicate. The present disclosure does not limit the specific type of the insulating material.

[0067] In some embodiments, there are many devices in the processing chip 111, and the remaining available substrate (e.g., silicon Si) space in the first wafer 11 is limited. If a micro-conducting layer for heat dissipation is provided in the first wafer 11, the performance of each processing chip 111 may be affected. However, there are fewer devices in the interconnect chip 121, and there is more available substrate space in the second wafer 12. The micro-conducting layer provided in the second wafer 12 has less impact on the performance, and can improve the heat dissipation capacity of the entire wafer-level cooling system.

[0068] The substrate material of the first wafer 11 and the second wafer 12 may be silicon, or silicon carbide SiC, or any other type of substrate material, which is not limited in the present disclosure.

[0069] In some embodiments, Figure 1 As shown, the micro-guiding layer 124 is located on the side opposite to the interconnected chip layer where the multiple interconnected chips are located, and a micro-channel 125 is provided in the micro-guiding layer to contain the heat dissipation liquid so as to dissipate heat for the wafer-level cooling system. The micro-channel 125 is provided with an inlet and an outlet respectively, so that the heat dissipation liquid can flow in the micro-channel 125 through the microfluidic technology, so that the heat dissipation liquid flows in from the inlet and flows out from the outlet. In this way, the heat dissipation effect of the wafer-level cooling system can be improved.

[0070] Figure 2 Schematic diagram of a second chip provided by an embodiment of the present disclosure. Figure 2 As shown, in some embodiments, the second chip includes not only the interconnect chip layer 126 and the micro-guiding layer 124, but also an insulating layer 127. The insulating layer 127 is located between the interconnect chip layer 126 and the micro-guiding layer 124, and is used to separate the interconnect chip layer 126 from the micro-guiding layer 124, reduce the mutual influence between the interconnect chip layer and the micro-guiding layer, and thus reduce the influence of the micro-pipes on the performance of the interconnect chips in the interconnect chip layer.

[0071] The material of the insulating layer 127 can be silicon dioxide SiO 2 , or other types of insulating materials. The present disclosure does not limit this.

[0072] like Figure 2 As shown, in some embodiments, the micro-channels 125 in the micro-guiding layer 124 may be serpentine and may include multiple inlets and outlets to improve the heat dissipation effect of the wafer-level cooling system. The present disclosure does not limit the specific shape of the micro-channels and the number of inlets and outlets.

[0073] According to the wafer-level cooling system of the embodiment of the present disclosure, a first wafer including a processing chip and a second wafer including an interconnection chip are stacked and arranged, and the processing chips are communicated through the interconnection chip, thereby realizing high-bandwidth interconnection between the chips and realizing a high-performance wafer-level cooling system; and the second wafer is provided with a micro-guiding layer, and the micro-pipes in the micro-guiding layer are used to accommodate heat dissipation liquid, thereby improving the heat dissipation effect of the entire wafer-level cooling system.

[0074] The generation process of the wafer-level cooling system is described below.

[0075] Figure 3 A flow chart of a method for generating a wafer-level cooling system provided in an embodiment of the present disclosure.

[0076] According to an embodiment of the present disclosure, a method for generating a wafer-level cooling system is provided, such as Figure 3 As shown, the method includes:

[0077] Step S31, obtaining a first wafer and a second wafer, wherein the first wafer has a plurality of uncut processing chips, and the second wafer has a plurality of uncut interconnect chips;

[0078] Wherein, a first bonding boss is arranged on the surface of the processing chip, and a second bonding boss is arranged on the surface of the interconnection chip, the positions of the first bonding boss and the second bonding boss have a corresponding relationship, and the first bonding boss and the second bonding boss are made of a conductive material;

[0079] Step S32, sequentially generating an insulating layer and a micro-guiding layer on the side of the second wafer opposite to the interconnected chip layer, and generating micro-channels in the micro-guiding layer, wherein the interconnected chip layer is a layer where the plurality of interconnected chips are located;

[0080] Step S33, coating a bonding layer on the surface area outside the second bonding protrusion of the second wafer, wherein the bonding layer is made of an adhesive insulating material;

[0081] Step S34, bonding the first wafer and the second wafer face to face to obtain a wafer bonding structure, wherein the corresponding first bonding bosses are bonded to the second bonding bosses, and the first wafer and the second wafer are bonded to each other through the bonding layer at the surface areas outside the first bonding bosses and the second bonding bosses;

[0082] Step S35, obtaining the wafer-level cooling system according to the wafer bonding structure,

[0083] Wherein, the processing chips are communicatively connected to each other via the interconnection chip.

[0084] For example, in step S31, a first wafer and a second wafer may be obtained respectively, the first wafer having a plurality of uncut processing chips, and the second wafer having a plurality of uncut interconnected chips. A preset semiconductor process may be used to generate a wafer having a plurality of processing chips and a wafer having a plurality of interconnected chips respectively, and the generated wafers may be directly used as the first wafer and the second wafer; the wafers may also be further processed (for example, cut into a preset rectangle) to obtain the first wafer and the second wafer, and the present disclosure does not limit this.

[0085] Figure 4a and Figure 4b A schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure. Figure 4a A first wafer 31 is shown, on which are a plurality of processing chips 311; Figure 4b A second wafer 32 is shown, on which are a plurality of interconnected chips 321 .

[0086] In some embodiments, the processing chip may be, for example, an artificial intelligence (AI) many-core chip, which includes multiple processing cores for implementing corresponding AI processing tasks; it may also be other types of processing chips, which are not limited in this disclosure.

[0087] In some embodiments, the plurality of processing chips of the first wafer are not interconnected, so as to save the space occupied by the interconnection structure, reduce the size of the processing chip, or integrate more devices under the same chip size to improve performance.

[0088] In some embodiments, the interconnection chip may be a custom-designed interconnection structure corresponding to the processing chip, including metal interconnection lines and insulating layers, etc. A small number of processing devices, storage devices, etc. may also be provided in the interconnection chip, and the present disclosure does not limit the materials, processes, and specific structures of the interconnection chip used.

[0089] In some embodiments, there is a corresponding relationship between the interconnection chip and the processing chip to achieve communication connection between each processing chip. Each interconnection chip may correspond to multiple adjacent processing chips and is used to achieve communication connection between multiple adjacent processing chips.

[0090] In some embodiments, at least one first bonding boss is disposed on the processing chip, and at least one second bonding boss is disposed on the interconnection chip. The positions of the first bonding boss and the second bonding boss have a corresponding relationship, and the first bonding boss and the second bonding boss are both made of conductive materials, such as copper, aluminum, gold, etc.

[0091] Figure 5a and Figure 5b Schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure. Figure 5a As shown, each processing chip of the first wafer 41 is provided with a first bonding protrusion 411, the number of first bonding protrusions on the processing chips in the non-edge area is relatively small, and the number of first bonding protrusions on the processing chips in the edge area is relatively large. Figure 5b As shown, each interconnected chip of the second wafer 42 is provided with a second bonding boss 421. The positions of the first bonding boss 411 and the second bonding boss 421 correspond to each other.

[0092] Figure 6 Schematic diagram of bonding the first wafer and the second wafer provided in the embodiment of the present disclosure. Figure 6 As shown, the positions of the first bonding bosses of the first wafer and the second bonding bosses of the second wafer correspond to each other. When the first wafer 51 and the second wafer 52 are bonded, the corresponding first bonding bosses are engaged with the second bonding bosses to realize the electrical connection between the processing chip and the interconnection chip.

[0093] In some embodiments, in step S32, after obtaining the second wafer, an insulating layer and a micro-guiding layer may be sequentially generated on the side of the second wafer opposite to the interconnected chip layer, and micro-channels may be generated in the micro-guiding layer. For example, the insulating layer may be generated by oxidation, and then the micro-guiding layer and the micro-channels in the micro-guiding layer may be generated by deposition and etching. The present disclosure does not limit the process steps used to generate the insulating layer and the micro-guiding layer.

[0094] In some embodiments, the wafer where the second wafer is located can also be directly processed to generate an insulating layer and a micro-guiding layer; and then the wafer is further processed (for example, cut into a preset rectangle) to obtain a second wafer. The present disclosure does not limit the specific processing sequence.

[0095] Figure 7 Schematic diagram of a second chip provided by an embodiment of the present disclosure. Figure 7As shown, one side of the second wafer 42 is an interconnected chip layer, including multiple interconnected chips, each of which is provided with a second bonding boss 421; the other side is a micro-guiding layer, including micro-channels 422. The micro-channels 422 are serpentine, located below the multiple interconnected chips, and have an inlet and an outlet, so that the heat dissipation liquid can flow in the micro-channels through the microfluidic technology, so that the heat dissipation liquid flows in from the inlet and flows out from the outlet, thereby achieving heat dissipation of the entire system.

[0096] In some embodiments, in step S33, a bonding layer may be coated on the surface area outside the second bonding boss of the second wafer, and the bonding layer is used for packaging and fixing to achieve a bonding connection between the first wafer and the second wafer. The bonding layer is made of an adhesive insulating material. The insulating material includes silicon carbide, epoxy resin, polyimide, tetraethyl silicate, etc., and the present disclosure does not limit the specific type of the insulating material.

[0097] Figure 8 Schematic diagram of a first chip and a second chip provided in an embodiment of the present disclosure. Figure 8 As shown, the first wafer 11 includes a plurality of processing chips 111, on which a first bonding boss 112 is disposed; the second wafer 12 includes a plurality of interconnection chips 121, on which a second bonding boss 122 is disposed. A bonding layer 123 is coated on the surface area outside the second bonding boss of the second wafer 12. The second wafer 12 also includes a micro-guiding layer 124, on which a micro-channel 125 is disposed.

[0098] In some embodiments, Figure 8 As shown, there is a matching gap between the bonding layer and the second bonding boss, which can leave space for the first bonding boss and the second bonding boss to deform. The present disclosure does not limit the specific size of the matching gap.

[0099] In some embodiments, in step S34, the first wafer and the second wafer may be bonded face to face to obtain a wafer bonding structure, wherein the corresponding first bonding bosses are bonded to the second bonding bosses, and the first wafer and the second wafer are bonded to the surface area outside the first bonding bosses and the second bonding bosses through a bonding layer.

[0100] In some embodiments, step S34 may include:

[0101] The first wafer and the second wafer are stacked face to face, wherein the corresponding first bonding bosses are in contact with the surface of the second bonding bosses;

[0102] Pressure is applied to the first wafer and the second wafer so that the corresponding first bonding bosses are bonded with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the second bonding bosses are spatially deformed to fill the fitting gap.

[0103] That is, the first wafer and the second wafer can be stacked face to face, the corresponding first bonding bosses are aligned with the second bonding bosses, and the surfaces of the two are in contact; then, pressure is applied to the first wafer and the second wafer, for example, the first wafer and the second wafer are placed on an operating table, and the first wafer and the second wafer are pressed down by a corresponding device, so as to apply uniform pressure to the first wafer and the second wafer, so that the corresponding first bonding bosses and the second bonding bosses are spatially deformed, filling Figure 8 The matching clearance in the Figure 1 In this way, the bonding of the first wafer and the second wafer is achieved, so that the processing chips can be connected to each other through the interconnection chip.

[0104] It should be understood that those skilled in the art may set the bonding method between the first wafer and the second wafer according to actual conditions, and the present disclosure does not limit this.

[0105] In some embodiments, in step S35, a wafer-level cooling system may be obtained based on the wafer bonding structure. The wafer bonding structure may be directly used as a wafer-level cooling system; or the wafer bonding structure may be subjected to subsequent processing, such as thinning, packaging, etc., to obtain a wafer-level cooling system.

[0106] In some embodiments, step S35 may include: performing packaging processing on the wafer bonding structure to obtain the wafer-level cooling system.

[0107] That is, the wafer bonding structure can be sealed by packaging materials, such as ceramics, and corresponding pins are provided so that the wafer bonding structure can be connected to an external circuit, such as being welded to a board. After the packaging process, the final wafer-level cooling system can be obtained. The present disclosure does not limit the specific packaging process.

[0108] According to the method for generating a wafer-level cooling system in an embodiment of the present disclosure, a wafer-level cooling system can be generated based on a first wafer and a second wafer by face-to-face bonding. By directly connecting the wafers, the docking during connection is more precise, and a large-bandwidth interconnection between the wafers can be achieved to obtain a high-performance wafer-level cooling system. Furthermore, by generating an insulating layer and a micro-guiding layer on the second wafer and generating micro-pipes in the micro-guiding layer, the heat dissipation effect of the entire wafer-level cooling system can be improved.

[0109] Fig. 9 A flowchart of a data processing method provided in an embodiment of the present disclosure.

[0110] According to an embodiment of the present disclosure, a data processing method is also provided, which is applied to the processing chip in the above-mentioned wafer-level cooling system. The wafer-level cooling system includes a first wafer and a second wafer which are stacked, the first wafer includes a plurality of uncut processing chips, the second wafer includes a plurality of uncut interconnection chips and a micro-guiding layer, the interconnection chip is used to realize the communication connection between the processing chips; the micro-guiding layer is located on the side opposite to the interconnection chip layer where the plurality of interconnection chips are located, and micro-channels are arranged in the micro-guiding layer for accommodating heat dissipation liquid to dissipate heat for the wafer-level cooling system.

[0111] In some embodiments, Fig. 9 As shown, the method includes:

[0112] Step S91, during the execution of the processing task by the processing chip, sending processing data to other processing chips through the interconnection chip connected to the processing chip; and / or receiving processing data sent by other processing chips through the interconnection chip connected to the processing chip.

[0113] For example, the processing chip can be used to perform processing tasks, such as performing various operations in the processing tasks, data interaction, etc. The processing tasks can be, for example, image processing tasks, voice processing tasks, text processing tasks, video processing tasks, etc. The present disclosure does not limit the specific types of processing tasks.

[0114] In some embodiments, for any processing chip in the wafer-level cooling system, during the period when the processing chip performs a processing task, it may be necessary to perform data interaction with other processing chips in the wafer-level cooling system, such as sending the processing result of the processing chip to other processing chips, sending processing instructions to other processing chips, receiving data processing results of other processing chips, etc. The present disclosure does not limit the type and method of data interaction.

[0115] In some embodiments, while the processing chip is executing a processing task, it can send processing data, such as processing results, processing instructions, data acquisition requests, etc., to other processing chips through an interconnection chip connected to the processing chip; similarly, the processing chip can also receive processing data sent by other processing chips through an interconnection chip connected to the processing chip, such as processing results, processing instructions, data acquisition requests, etc. of other processing chips.

[0116] In this way, data interaction between processing chips can be achieved through interconnected chips, the bandwidth and speed of data interaction can be improved, thereby achieving high-speed connection and interaction with large bandwidth.

[0117] In some embodiments, during the operation of multiple processing chips in the wafer-level cooling system, microfluidic technology (for example, setting a micropump corresponding to the microchannel) is used to control the flow of heat dissipation liquid in the microchannels of the second chip, so that the heat dissipation liquid flows into the inlet and flows out of the outlet, thereby achieving heat dissipation for each processing chip of the wafer-level cooling system.

[0118] According to the embodiments of the present disclosure, the interconnection structure between chips can be generated by using semiconductor technology, and the wafer-level packaging method is adopted to directly bond the wafer including the processing chip and the wafer including the interconnection chip face to face, so that the processing chip can achieve a high-speed connection with a large bandwidth through the interconnection chip, and a high-performance wafer-level cooling system is realized. In addition, a micro-guiding layer is set on the wafer where the interconnection chip is located, and the micro-channels in the micro-guiding layer are used to accommodate the heat dissipation liquid, thereby improving the heat dissipation effect of the entire wafer-level cooling system.

[0119] The present disclosure also provides a computer-readable storage medium on which a computer program is stored, wherein the computer program implements the above-mentioned data processing method when executed by a processing chip. The computer-readable storage medium may be a volatile or non-volatile computer-readable storage medium.

[0120] The embodiments of the present disclosure also provide a computer program product, including a computer-readable code, or a non-volatile computer-readable storage medium carrying the computer-readable code. When the computer-readable code runs in a processor or a processing chip of an electronic device, the processor or the processing chip in the electronic device executes the above-mentioned data processing method.

[0121] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In a hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable storage medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium).

[0122] As is known to those of ordinary skill in the art, the term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable program instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. In addition, it is known to those of ordinary skill in the art that communication media typically contain computer-readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0123] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0124] The computer program instructions for performing the operation of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be customized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present disclosure.

[0125] The computer program product described herein may be implemented in hardware, software, or a combination thereof. In one optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), etc.

[0126] Various aspects of the present disclosure are described herein with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box in the flowchart and / or block diagram and the combination of each box in the flowchart and / or block diagram can be implemented by computer-readable program instructions.

[0127] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0128] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0129] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous square boxes can actually be executed substantially in parallel, and they can sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or action, or can be implemented with a combination of special hardware and computer instructions.

[0130] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly noted, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A wafer-level cooling system, characterized in that: include: A first wafer and a second wafer are stacked, wherein the first wafer includes a plurality of uncut processing chips, and the second wafer includes a plurality of uncut interconnect chips and a micro-guiding layer; The processing chip is used to perform processing tasks; There is a corresponding relationship between the interconnection chip and the processing chip, and is used to realize the communication connection between the processing chips, wherein the multiple processing chips and the multiple interconnection chips are arranged in an array manner, each interconnection chip corresponds to a plurality of adjacent processing chips, and is used to realize the communication connection between the plurality of adjacent processing chips, and the plurality of interconnection chips are used to realize the communication connection between all processing chips; The micro-guiding layer is located on the side opposite to the interconnected chip layer, and micro-channels are arranged in the micro-guiding layer for containing heat dissipation liquid so as to dissipate heat for the wafer-level cooling system, wherein the interconnected chip layer is the layer where the multiple interconnected chips are located.

2. The system according to claim 1, characterized in that The second wafer further includes an insulating layer, which is located between the interconnect chip layer and the micro-guiding layer and is used to separate the interconnect chip layer from the micro-guiding layer.

3. The system according to claim 1, characterized in that The processing chip is provided with a first bonding boss, and the interconnection chip is provided with a second bonding boss. The first bonding boss is bonded with the second bonding boss, and the first bonding boss and the second bonding boss are made of conductive material.

4. The system according to claim 3, characterized in that The first wafer and the second wafer are bonded via a bonding layer in regions outside the first bonding protrusions and the second bonding protrusions. The bonding layer is made of an adhesive insulating material.

5. A method for generating a wafer-level cooling system, characterized in that: include: Obtain a first wafer and a second wafer, wherein the first wafer has a plurality of uncut processing chips, and the second wafer has a plurality of uncut interconnect chips; Wherein, a first bonding boss is arranged on the processing chip, a second bonding boss is arranged on the surface of the interconnection chip, the positions of the first bonding boss and the second bonding boss have a corresponding relationship, and the first bonding boss and the second bonding boss are made of conductive material; sequentially generating an insulating layer and a micro-guiding layer on a side of the second wafer opposite to the interconnected chip layer, and generating micro-channels in the micro-guiding layer, wherein the interconnected chip layer is a layer where the plurality of interconnected chips are located; Coating a bonding layer on a surface area of ​​the second wafer outside the second bonding protrusion, wherein the bonding layer is made of an adhesive insulating material; Bonding the first wafer and the second wafer face to face to obtain a wafer bonding structure, wherein the corresponding first bonding bosses are bonded to the second bonding bosses, and the first wafer and the second wafer are bonded to each other through the bonding layer at surface areas outside the first bonding bosses and the second bonding bosses; According to the wafer bonding structure, the wafer-level cooling system is obtained. The processing chips are communicatively connected to each other via the interconnection chip, the multiple processing chips and the multiple interconnection chips are arranged in an array, each interconnection chip corresponds to multiple adjacent processing chips and is used to realize communication connection between multiple adjacent processing chips, and the multiple interconnection chips are used to realize communication connection between all processing chips.

6. The method according to claim 5, characterized in that There is a matching gap between the bonding layer and the second bonding boss, wherein the first wafer and the second wafer are bonded face to face to obtain a wafer bonding structure, including: The first wafer and the second wafer are stacked face to face, wherein the corresponding first bonding bosses are in contact with the surface of the second bonding bosses; Pressure is applied to the first wafer and the second wafer so that the corresponding first bonding bosses are bonded with the second bonding bosses to obtain the wafer bonding structure, wherein the corresponding first bonding bosses and the second bonding bosses are spatially deformed to fill the fitting gap.

7. The method according to claim 5, characterized in that The wafer-level cooling system is obtained according to the wafer bonding structure, including: The wafer bonding structure is packaged to obtain the wafer-level cooling system.

8. A data processing method, characterized in that: A processing chip used in a wafer-level cooling system as described in any one of claims 1 to 4, wherein the wafer-level cooling system comprises a first wafer and a second wafer arranged in a stacked manner, wherein the first wafer comprises a plurality of uncut processing chips, and the second wafer comprises a plurality of uncut interconnection chips and a micro-guiding layer, wherein the interconnection chip is used to realize communication connection between the processing chips; the micro-guiding layer is located on a side opposite to the interconnection chip layer where the plurality of interconnection chips are located, and micro-channels are provided in the micro-guiding layer for accommodating heat dissipation liquid so as to dissipate heat for the wafer-level cooling system, wherein the plurality of processing chips and the plurality of interconnection chips are arranged in an array, each interconnection chip corresponds to a plurality of adjacent processing chips, and is used to realize communication connection between a plurality of adjacent processing chips, and the plurality of interconnection chips are used to realize communication connection between all processing chips, Wherein, the method comprises: During the period when the processing chip executes the processing task, the processing chip sends processing data to other processing chips through the interconnection chip connected to the processing chip; and / or receives processing data sent by other processing chips through the interconnection chip connected to the processing chip.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program implements the data processing method according to claim 8 when executed by a processing chip.

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