Method for fabricating nanoscale channel structures
Through multi-step deposition and etching technology, a nano-scale channel structure is formed, which solves the problem that the channel geometry cannot be reproduced in the prior art, and realizes high-precision and stability of nano-scale channel manufacturing, suitable for a variety of micro-micro Fluid applications.
Patent Information
- Application Number
- CN202180015397.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-02-21
- Filing Date
- 2021-02-15
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2041-02-15
AI Technical Summary
The prior art is difficult to effectively manufacture nano-scale channel structures, and conventional methods lead to the inability to reproduce the channel geometry well, and are limited by time-dependent etching and coating enclosure, which affects its accuracy and reliability.
Using a multi-step approach, including deposition and construction of the first and second sacrificial layers, using an etch mask layer and wall layer, precisely forming a nano-scale channel structure through anisotropic and isotropic etching techniques, ensuring the width and height of the channel, Use the same material layer structure to avoid rounding and closure.
It realizes high-precision reproducibility of nano-scale channel structures and is suitable for large-scale production, ensuring the stability and reliability of the channel geometry, and is suitable for applications such as DNA sequencers and gas sensors.
Smart Images
Figure CN115066389B_ABST
Abstract
Description
[0001] The present invention relates to a method for manufacturing a nanoscale channel structure. Furthermore, the present invention relates to a computer program for executing each step of the method and a machine-readable storage medium storing the computer program. Finally, the present invention relates to an electronic controller arranged to execute the method. Prior art
[0002] Nanoscale channels are required for microfluidic applications. For example, nanochannels are used in genome sequencers to guide DNA chains as close as possible to the reading electrode and decode them at the same time. In gas chromatography, nanochannels are advantageous in the separation of gas species due to their high surface area / volume ratio, because the separation occurs through specific wall interactions. In both cases, the precise geometry of the nanochannel is particularly important. However, conventional methods for manufacturing nanoscale channel structures result in channel geometries that cannot be well reproduced. This is based on the fact that these methods use time-dependent etching or lateral etching (Unterätzung), or the opened channels are closed due to layer deposition, in which the walls of the channel are also partially coated therewith. Some methods are also subject to strong geometric restrictions. Rounding in the coating also impairs the manufacture of nanoscale channel structures.
[0003] DE 20 2017 107 858 U1 relates to a device for a protein corona sensor array for early detection of diseases. Here, a sample can pass through the sensor array through a nanochannel. The channel can be formed by etching a sacrificial layer. Here, photolithography is used to structure a material on a substrate. This material is covered by another material with different chemical properties. It can be subjected to a photolithography process and an etching process or other processing processes. The substrate is then exposed to a chemical agent that selectively removes the first material. A channel is formed in the second material, wherein a cavity remains where the first material was present before the etching process. Since the geometry of the channel is determined by photolithography, they cannot be manufactured with good reproducibility in this method either.
[0004] Invention Disclosure
[0005] The method for producing a nanoscale channel structure comprises at least eight method steps (a to h):
[0006] In a first method step (step a), a first sacrificial layer is deposited and structured on a substrate. In this case, the substrate can be either a bulk material or a layer base structure on which a first sacrificial layer is deposited. The first sacrificial layer can also be referred to as a "gate layer". Suitable deposition methods are in particular chemical low-pressure vapor deposition (low-pressure chemical vapor deposition; LPCVD), plasma enhanced chemical vapor deposition (plasma enhanced chemical vapor deposition; PECVD) or atomic layer deposition (atomic layer deposition; ALD). Suitable materials for the first sacrificial layer are in particular silicon or silicon nitride. Here, the first sacrificial layer made of polycrystalline silicon is preferably deposited by LPCVD or ALD, and the first sacrificial layer made of silicon nitride is preferably deposited by PECVD. Structure is understood to mean that the first sacrificial layer is completely stripped off in certain areas so that the substrate is exposed again. The edge between the constructed first sacrificial layer and the substrate area from which the first sacrificial layer is removed defines the extension of the nanoscale channel structure.
[0007] In the second method step (step b), a second sacrificial layer is deposited on the substrate and on the first sacrificial layer. The second sacrificial layer can also be referred to as a "channel layer". The thickness of the second sacrificial layer defines the height of the nanoscale channel. It is therefore preferably deposited with a thickness of less than 100 nm, particularly preferably with a thickness of less than 10 nm. For depositing the second sacrificial layer, the same method as that used to deposit the first sacrificial layer is preferred. In addition, for depositing the second sacrificial layer, the same material as that used to deposit the first sacrificial layer is also preferred. The first sacrificial layer and the second sacrificial layer are particularly preferably deposited from the same material. This enables the first sacrificial layer and the second sacrificial layer to be removed later using the same method.
[0008] In the third method step (step c), an etching mask layer is deposited on the second sacrificial layer. The etching mask layer can also be referred to as a "spacer layer". It can optionally be structured after deposition. Suitable deposition methods are in particular PECVD or ALD. Suitable materials for the etching mask layer are in particular oxides. The thickness of the etching mask layer defines the width of the nanoscale channel. Therefore, it is preferably deposited with a thickness of at least 1 nm. Its maximum thickness is preferably less than 100 nm, particularly preferably less than 20 nm. This achieves a favorable width of the nanoscale channel structure. In addition, the thickness of the etching mask layer is preferably less than the thickness of the first sacrificial layer. It is particularly preferably at least as low as 1 / 3 of the thickness of the first sacrificial layer. It is very particularly preferably at least as low as 1 / 30 of the thickness of the first sacrificial layer. In this way, it is ensured that the mesa structure formed by the first sacrificial layer and the second sacrificial layer is coated in a particularly conformal manner without rounding.
[0009] In a fourth method step (step d), the etching mask layer and the second sacrificial layer are partially removed. A suitable method for partially removing the etching mask layer and the second sacrificial layer is anisotropic etching, for example, in particular reactive ion etching (reactive ion etching; RIE). If the etching mask layer applied on the first sacrificial layer and the second sacrificial layer applied on the first sacrificial layer are etched back in this method step, the second sacrificial layer applied on the substrate and the etching mask layer applied thereon are also mainly etched back. Only where the side of the first sacrificial layer is covered by the second sacrificial layer and the etching mask layer, the second sacrificial layer and the etching mask layer are not completely etched back.
[0010] In a fifth method step (step e), the first sacrificial layer is removed and further parts of the second sacrificial layer are removed. This can preferably be done using the same method as for removing the layers in step d, in particular when the first sacrificial layer and the second sacrificial layer consist of the same material. As a result, only the remainder of the second sacrificial layer within the width of the planned nanoscale channel structure and the remainder of the etching mask layer located above it remain. In this case, the etching mask layer protects the second sacrificial layer located below it within a width that corresponds to the thickness of the etching mask layer and therefore to the width of the planned channel structure.
[0011] In the sixth method step (step f), a wall layer is deposited on the etching mask layer and on the substrate. This wall layer, which can also be called a "restriction layer", forms the walls of the nanoscale channel structure. It is preferably deposited from the same material as the etching mask layer. As a result, the remaining part of the etching mask layer and the wall layer are fused into a structure consisting of the same material.
[0012] In a seventh method step (step g), access to the second sacrificial layer is formed. This can be done by forming a wall layer.
[0013] In an eighth method step (step h), the remaining second sacrificial layer in the trench region is removed. This can be done in particular by isotropic etching, for example with xenon difluoride (XeF 2 ) or sulfur hexafluoride (SF 6 These substances can contact the second sacrificial layer through the inlet constructed in step g.
[0014] In this way, a nanoscale channel structure is obtained, which is accessible via an inlet in the wall layer. Since the height of the channel is defined by the thickness of the second sacrificial layer and the width of the channel is defined by the thickness of the etching mask layer, and since the layer thicknesses can be adjusted with very high precision during the deposition process, the method enables the production of nanoscale channel structures with very good reproducibility and in a manner suitable for large-scale production.
[0015] The computer program is configured to perform each step of the method when it is run on a computer or electronic controller. In addition, the computer or electronic controller can control the device that performs the deposition step, the construction step and the removal step of the method. The computer program enables different embodiments of the method to be implemented on the controller of the manufacturing device for the nanoscale channel structure without having to change its construction. For this purpose, it is stored on a machine-readable storage medium.
[0016] By loading a computer program onto a conventional electronic controller, such an electronic controller is obtained which is arranged to produce a nanoscale channel structure by means of the method when it controls a suitable production device for this purpose. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Exemplary embodiments of the invention are shown in the drawings and are explained in more detail in the following description.
[0019] Figure 1 A cross-sectional view of a substrate on which a first sacrificial layer has been deposited and structured is shown.
[0020] Figure 2 The second sacrificial layer is deposited on the substrate and the first sacrificial layer according to Figure 1 Cross-sectional view of the substrate.
[0021] Figure 3 After depositing an etching mask layer on the second sacrificial layer, Figure 2 Cross-sectional view of the substrate.
[0022] Figure 4 After partially removing the etching mask layer and the second sacrificial layer, Figure 3 Cross-sectional view of the substrate.
[0023] Figure 5 After removing the first sacrificial layer, Figure 4 Cross-sectional view of the substrate.
[0024] Figure 6 The etching mask layer and the wall layer are deposited on the substrate according to Figure 5 Cross-sectional view of the substrate.
[0025] Figure 7 After removing the second sacrificial layer, Figure 6 Cross-sectional view of the substrate.
[0026] Embodiments of the present invention
[0027] In an embodiment of the present invention, a first sacrificial layer 2 made of polysilicon with a thickness of 150 nm is deposited on the substrate 1. It is structured so that the substrate 1 is partially exposed again. Figure 1 Shown in.
[0028] Then, a second sacrificial layer 3 also composed of polysilicon is deposited by LPCVD so that it covers the exposed surface of the substrate 1, the surface of the first sacrificial layer 2, and the side of the first sacrificial layer 2 with a thickness of 5 nm. Since the first sacrificial layer 2 and the second sacrificial layer 3 are composed of the same material, they are fused together, as shown in FIG. Figure 2 shown.
[0029] like Figure 3 As shown, an oxide layer is then deposited as an etching mask layer 4, for example, by PECVD, so that it covers the surface and side surfaces of the 5 nm thick second sacrificial layer 3 with a thickness of 10 nm.
[0030] Anisotropic RIE etching is then performed as an etch back until the substrate 1 is partially exposed again. This means that in areas not covered by the first sacrificial layer 2, the etching mask layer 4 and the second sacrificial layer 3 beneath it are completely removed. Here, the layer structure formed by the second sacrificial layer 3 and the etching mask layer 4 applied above the first sacrificial layer 2 is also removed. Here, the parts of the etching mask layer 4 covering the side surfaces of the first sacrificial layer 2 are not removed, since the anisotropic etching is performed only from top to bottom. These remaining parts of the etching mask layer 4 can therefore protect the parts of the second sacrificial layer 3 located underneath from etching back. The parts of the second sacrificial layer 3 arranged between the first sacrificial layer 2 and the etching mask layer 4 are also not removed. This Figure 4 Shown in.
[0031] Now, the parameters of the RIE etching are changed so that in the further etching process, only the first sacrificial layer 2 and the second sacrificial layer 3 are etched, and the etching mask layer 4 is no longer etched. As a result, the first sacrificial layer 2 is completely removed, wherein the remaining part of the etching mask layer 4 and the remaining part of the second sacrificial layer 3 protected thereby remain on the substrate 1, as shown in FIG. Figure 5 shown.
[0032] Now a wall layer 5 is deposited by PECVD with a thickness of 200 nm, for example from oxide. Figure 6 As shown, the wall layer 5 is fused with the remaining part of the etching mask layer 4 , since the two layers consist of the same material. As a result, a protrusion on the wall layer 5 is present above the remaining part of the etching mask layer 4 . Figure 6 It is shown what layer structure is produced if the elevation has been partially smoothed by structuring, so that only a hint remains on the top side of the wall layer 5 where the remainder of the second sacrificial layer 3 and thus where the extension of the nanoscale trench is in the finished trench structure.
[0033] An access opening is now formed to the remaining part of the second sacrificial layer 3 and XeF is introduced through the access opening. 2This is done until the remainder of the second sacrificial layer 3 is completely removed by isotropic etching. Thus, a nanoscale channel 6 is left at the location where the remainder of the second sacrificial layer 3 previously existed. It can be reached through the inlet. The width of the nanoscale channel corresponds to the previous thickness of the etching mask layer 4 and is therefore 10 nm. The height of the nanoscale channel corresponds to the previous thickness of the second sacrificial layer and is therefore 5 nm. The nanoscale channel structure thus obtained can be used, for example, in a DNA sequencer or in a gas sensor.
Claims
1. A method for manufacturing a nanoscale channel structure, comprising the following steps: a) depositing and structuring a first sacrificial layer (2) on a substrate (1), b) depositing a second sacrificial layer (3) on the substrate (1) and on the first sacrificial layer (2), wherein the thickness of the second sacrificial layer defines the height of the nanoscale channel, c) depositing an etching mask layer (4) on the second sacrificial layer (3), wherein the thickness of the etching mask layer defines the width of the nanoscale channel, d) partially removing the etching mask layer (4) and the second sacrificial layer (3), wherein in the area not covered by the first sacrificial layer (2), the etching mask layer (4) and the second sacrificial layer (3) thereunder are completely removed, and the layer structure formed by the second sacrificial layer (3) and the etching mask layer (4) applied above the first sacrificial layer (2) is also removed, but the part of the etching mask layer (4) covering the side surface of the first sacrificial layer (2) is not removed, e) removing the first sacrificial layer (2) and further partially removing the second sacrificial layer (3), wherein in a further etching process, only the first sacrificial layer (2) and the second sacrificial layer (3) are further etched, and the etching mask layer (4) is no longer etched, thereby the first sacrificial layer (2) is completely removed, and the remaining part of the etching mask layer (4) and the remaining part of the second sacrificial layer (3) protected thereby remain on the substrate (1), f) depositing a wall layer (5) on the etching mask layer (4) and on the substrate (1), g) constructing access to the second sacrificial layer (3), and h) Completely removing the remaining second sacrificial layer (3), thereby leaving nanoscale channels (6) where the remaining portions of the second sacrificial layer (3) previously existed.
2. The method according to claim 1, characterized in that The second sacrificial layer (3) is deposited with a thickness of less than 100 nm.
3. The method according to claim 1 or 2, characterized in that: The first sacrificial layer (2) and the second sacrificial layer (3) are deposited from the same material.
4. The method according to claim 1 or 2, characterized in that: The etching mask layer (4) is deposited with a smaller thickness than the first sacrificial layer (2).
5. The method according to claim 1 or 2, characterized in that: The partial removal of the etching mask layer (4) and the second sacrificial layer (3) as well as the removal of the first sacrificial layer (2) and the further partial removal of the second sacrificial layer (3) are performed by anisotropic etching.
6. The method according to claim 1 or 2, characterized in that: The wall layer (5) is deposited from the same material as the etching mask layer (4).
7. The method according to claim 1 or 2, characterized in that: The removal of the remaining second sacrificial layer (3) is performed by isotropic etching.
8. A computer program product arranged to perform each step of the method according to any one of claims 1 to 7.
9. A machine-readable storage medium storing the computer program product according to claim 8.
10. An electronic controller configured to manufacture a nanoscale channel structure by the method of any one of claims 1 to 7.