LDMOS device and manufacturing method thereof

Abstract

The present invention discloses an LDMOS device. A first shallow trench isolation (STI) is included in a drift region field oxide. A doped region shielding layer, heavily doped with a first conductivity type, is formed at a second bottom corner of the first STI near the bottom of a second side surface of the drain region, encapsulating the second bottom corner. When the heavily doped drain region is connected to an operating voltage, the doped region shielding layer is not depleted, thereby reducing the electric field strength at the second bottom corner of the drift region field oxide and improving device reliability. The present invention also discloses a method for manufacturing the LDMOS device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an LDMOS device; the present invention also relates to a manufacturing method of the LDMOS device. Background Art

[0002] Power semiconductor devices are capable of power management and processing, serving as a bridge between weak current and strong current. High-voltage gate driver integrated circuits, with their advantages of fast response time, low power consumption, high integration, and high reliability, are widely used in motor drives, automotive electronics, electronic ballasts, switch-mode power supplies, and other fields. 600V high-voltage LDMOS transistors are used as level-shifting transistors and as high-voltage isolation areas between high-end and low-end devices.

[0003] For 12-inch wafers, considering issues such as stress and wafer warpage, the only solution for manufacturing BCD (Bipolar-CMOS-DMOS) products is shallow trench isolation (STI) field oxide (Field OX).

[0004] When ultra-high voltage is applied to the drain of a 600V high-voltage LDMOS device, the electric field is most concentrated at the junction edge of the drain's N+ implant region and at the STI corner in the drift region near the drain. Therefore, breakdown is more likely to occur at the STI corner. This susceptibility to breakdown at the STI corner results in poor HCI reliability. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an LDMOS device that can improve the reliability of the device. To this end, the present invention also provides a method for manufacturing the LDMOS device.

[0006] To solve the above technical problems, the LDMOS device provided by the present invention includes:

[0007] A drift region doped with a first conductivity type and a body region doped with a second conductivity type are formed in selected areas of the first epitaxial layer.

[0008] A drift region field oxide is formed in a selected area of ​​the drift region; the drift region field oxide includes a first shallow trench isolation formed in a first shallow trench.

[0009] A gap exists between the first side surface of the first shallow trench and the body region.

[0010] The gate structure covers a surface of a selected area of ​​the body region and extends from a first side surface of the drift region field oxide to a top surface of the drift region field oxide.

[0011] A source region heavily doped with a first conductivity type is formed in the body region and is self-aligned with the first side surface of the gate structure.

[0012] The drain region heavily doped with the first conductivity type is self-aligned with the second side surface of the field oxygen in the drift region.

[0013] A doped region shielding layer of the first conductive type is formed in the drift region at the second bottom corner of the first shallow trench and completely covers the second bottom corner. The second bottom angle of the first shallow trench is the bottom angle of the bottom of the second side surface of the first shallow trench. The first bottom angle of the first shallow trench is the bottom angle of the bottom of the first side surface of the first shallow trench. The second bottom angle of the first shallow trench is also the second bottom angle of the drift region field oxygen.

[0014] When the drain region is connected to the operating voltage, the first conductivity type of the doped region shielding layer is heavily doped so that the doped region shielding layer will not be depleted, thereby reducing the electric field strength of the second bottom corner of the drift region field oxygen and improving the reliability of the device.

[0015] A further improvement is that the doped region shielding layer also completely covers the second side surface of the first shallow trench and contacts the drain region at the top of the second side surface of the first shallow trench.

[0016] A further improvement is that the first epitaxial layer has a first conductivity type doping, and the drift region is composed of the first epitaxial layer between the body region and the drain region.

[0017] A further improvement is that the top surface of the first shallow trench isolation is flush with the top surface of the first epitaxial layer, a second step oxide layer is formed on the top of the first shallow trench isolation, and the drift region field oxygen is formed by the superposition of the first shallow trench isolation and the second step oxide layer.

[0018] A further improvement is that the first side surface of the second step oxide layer is aligned with the first side surface of the first shallow trench isolation, and the second side surface of the second step oxide layer is aligned with the second side surface of the first shallow trench isolation.

[0019] A further improvement is that the gate structure includes a gate dielectric layer and a polysilicon gate stacked in sequence, and the polysilicon gate extending to the top surface of the drift region field oxide forms a polysilicon shielding layer.

[0020] A further improvement is that the source region is connected to a source electrode composed of a front metal layer through a contact hole at the top, and the metal of the source electrode also extends above the field oxygen of the drift region and forms a source metal shielding layer.

[0021] The drain region is connected to a drain electrode formed by a front metal layer through a contact hole at the top. The metal of the drain electrode also extends above the field oxygen in the drift region and forms a drain metal shielding layer.

[0022] A further improvement is that a body contact region heavily doped with the second conductivity type is formed on the surface of the body region, and the body contact region is also connected to the source through a contact hole.

[0023] To solve the above technical problems, the present invention provides a method for manufacturing an LDMOS device, comprising the following steps:

[0024] Step 1: providing a first epitaxial layer and forming a drift region doped with a first conductivity type in a selected region of the first epitaxial layer.

[0025] Step 2: forming a drift region field oxide in a selected area of ​​the drift region, wherein the drift region field oxide includes a first shallow trench isolation; the formation process of the first shallow trench isolation includes:

[0026] Step 21. Etch a selected area of ​​the first epitaxial layer to form a first shallow trench; the first side of the first shallow trench is close to the side of the body region to be formed subsequently and there is a gap between the body regions, and the second side of the first shallow trench is close to the side of the drain region to be formed subsequently; the first bottom angle of the first shallow trench is the bottom angle of the bottom of the first side of the first shallow trench, and the second bottom angle of the first shallow trench is the bottom angle of the bottom of the second side of the first shallow trench; the second bottom angle of the first shallow trench is also the second bottom angle of the drift region field oxygen.

[0027] Step 22 : Perform first conductivity type heavily doped ion implantation to form a doped region shielding layer in the drift region at the second bottom corner of the first shallow trench, wherein the doped region shielding layer completely covers the second bottom corner.

[0028] Step 23: Fill the first shallow trench with an oxide layer to form the first shallow trench isolation.

[0029] Step three: forming a body region doped with a second conductivity type in a selected area of ​​the first epitaxial layer.

[0030] Step 4: forming a gate structure, wherein the gate structure covers a surface of a selected area of ​​the body region and extends from a first side surface of the drift region field oxide to a top surface of the drift region field oxide.

[0031] Step 5: Perform heavily doped source and drain implantation of the first conductivity type to form source and drain regions. The source region is formed in the body region and self-aligned with the first side of the gate structure; the drain region is self-aligned with the second side of the drift region field oxygen.

[0032] When the drain region is connected to the operating voltage, the first conductivity type of the doped region shielding layer is heavily doped so that the doped region shielding layer will not be depleted, thereby reducing the electric field strength of the second bottom corner of the drift region field oxygen and improving the reliability of the device.

[0033] A further improvement is that the doped region shielding layer also completely covers the second side surface of the first shallow trench and contacts the drain region at the top of the second side surface of the first shallow trench.

[0034] A further improvement is that the first epitaxial layer has a first conductivity type doping, and the drift region is composed of the first epitaxial layer between the body region and the drain region.

[0035] A further improvement is that the top surface of the first shallow trench isolation is flush with the top surface of the first epitaxial layer; in step 2, after step 23 is completed, the step further includes:

[0036] A step of forming a second step oxide layer on top of the first shallow trench isolation by using an oxide layer deposition and patterned etching process, wherein the drift region field oxide is formed by superposition of the first shallow trench isolation and the second step oxide layer.

[0037] A further improvement is that the first side surface of the second step oxide layer is aligned with the first side surface of the first shallow trench isolation, and the second side surface of the second step oxide layer is aligned with the second side surface of the first shallow trench isolation.

[0038] A further improvement is that in step 4, the gate structure includes a gate dielectric layer and a polysilicon gate stacked in sequence, and the polysilicon gate extending to the top surface of the drift region field oxide forms a polysilicon shielding layer.

[0039] A further improvement is that after step five, the process of forming an interlayer film, a contact hole and a front metal layer is also included.

[0040] The contact hole passes through the interlayer film.

[0041] The source region is connected to a source electrode formed by the front metal layer through a contact hole at the top. The metal of the source electrode also extends above the field oxygen in the drift region and forms a source metal shielding layer.

[0042] The drain region is connected to a drain electrode formed by the front metal layer through a contact hole at the top. The metal of the drain electrode also extends above the field oxygen in the drift region and forms a drain metal shielding layer.

[0043] The drift region field oxygen of the present invention has a first shallow trench isolation, and a doping region shielding layer heavily doped with the first conductive type is formed at the second bottom corner of the first shallow trench isolation close to the drain region. Since the doping region shielding layer and the drain region have the same doping type and are heavily doped, when a high voltage is applied to the drain region, the doping region shielding layer will not be depleted, so it will have a shielding effect on the electric field, so that the second bottom corner of the drift region field oxygen will not be affected by the electric field of high electric field strength, and the second bottom corner of the drift region field oxygen will not withstand high voltage. In this way, the reliability of the second bottom corner of the drift region field oxygen can be improved, thereby improving the reliability of the entire device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0045] Figure 1 1 is a schematic structural diagram of an LDMOS device according to an embodiment of the present invention;

[0046] Figure 2A-2F Schematic diagram of the device structure in each step of the manufacturing method of the LDMOS device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] like Figure 1 FIG. 1 is a schematic diagram of the structure of an LDMOS device according to an embodiment of the present invention. The LDMOS device according to an embodiment of the present invention includes:

[0048] A drift region doped with a first conductivity type and a body region 108 doped with a second conductivity type are formed in selected areas of the first epitaxial layer 102 .

[0049] In the embodiment of the present invention, the first epitaxial layer 102 is formed on the surface of the semiconductor substrate 101. The first epitaxial layer 102 has a first conductivity type doping, and the drift region is composed of the first epitaxial layer 102 between the body region 108 and the drain region 111.

[0050] The semiconductor substrate 101 includes a silicon substrate. The first epitaxial layer 102 includes a silicon epitaxial layer.

[0051] A drift region field oxide 107 is formed in a selected area of ​​the drift region; the drift region field oxide 107 includes a first shallow trench isolation 105 formed in the first shallow trench 103. The first shallow trench 103 and the first shallow trench isolation 105 are respectively as follows: Figure 2A and Figure 2C shown.

[0052] In an embodiment of the present invention, the top surface of the first shallow trench isolation 105 is flush with the top surface of the first epitaxial layer 102. A second step oxide layer 106 is further formed on top of the first shallow trench isolation 105. The drift region field oxide 107 is formed by the superposition of the first shallow trench isolation 105 and the second step oxide layer 106. In some preferred embodiments, the first side surface of the second step oxide layer 106 is aligned with the first side surface of the first shallow trench isolation 105, and the second side surface of the second step oxide layer 106 is aligned with the second side surface of the first shallow trench isolation 105.

[0053] In this embodiment of the present invention, a shallow trench 103a and shallow trench isolation 105a are also formed outside the drift region. Shallow trenches and shallow trench isolations not formed in the drift region are indicated by 103a and 105a, respectively. A step oxide layer is also formed on top of the shallow trench isolation 105a, overlapping to form a field oxide 107a outside the drift region. Including the shallow trench isolation 105a in the field oxide 107a helps reduce stress on the wafer. The wafer is comprised of the semiconductor substrate 101.

[0054] The first side surface 1031 and the second side surface 1032 of the first shallow trench 103 are as follows: Figure 2A As shown, a gap exists between the first side surface 1031 of the first shallow trench 103 and the body region 108 .

[0055] The gate structure covers a surface of a selected area of ​​the body region 108 and extends from a first side surface of the drift region field oxide 107 to a top surface of the drift region field oxide 107 .

[0056] In the embodiment of the present invention, the gate structure includes a gate dielectric layer (not shown) and a polysilicon gate 109 stacked in sequence, and the polysilicon gate 109 extending to the top surface of the drift region field oxide 107 forms a polysilicon shielding layer 109 a.

[0057] A heavily doped source region 110 of the first conductivity type is formed in the body region 108 and is self-aligned with the first side surface of the gate structure.

[0058] The drain region 111 heavily doped with the first conductivity type is self-aligned with the second side surface of the drift region field oxide 107 .

[0059] A doped region shielding layer 104 heavily doped with the first conductive type is formed in the drift region at the second bottom corner of the first shallow trench 103 and completely covers the second bottom corner. The second bottom angle of the first shallow trench 103 is the bottom angle of the bottom of the second side surface 1032 of the first shallow trench 103. The first bottom angle of the first shallow trench 103 is the bottom angle of the bottom of the first side surface 1031 of the first shallow trench 103. The second bottom angle of the first shallow trench 103 is also the second bottom angle of the drift region field oxygen 107.

[0060] In the embodiment of the present invention, the doped region shielding layer 104 further completely covers the second side surface 1032 of the first shallow trench 103 and contacts the drain region 111 at the top of the second side surface 1032 of the first shallow trench 103 .

[0061] When the drain region 111 is connected to the operating voltage, the first conductivity type of the doped region shielding layer 104 is heavily doped so that the doped region shielding layer 104 will not be depleted, thereby reducing the electric field strength at the second bottom corner of the drift region field oxygen 107 and improving the reliability of the device.

[0062] In the embodiment of the present invention, the source region 110 is connected to a source electrode formed by a front metal layer through a contact hole 113a at the top. The metal of the source electrode also extends to above the drift region field oxide 107 and forms a source metal shielding layer 114a.

[0063] The drain region 111 is connected to a drain electrode formed by a front metal layer through a contact hole 113 b at the top. The metal of the drain electrode also extends to above the drift region field oxide 107 and forms a drain metal shielding layer 114 b.

[0064] A body contact region 112 heavily doped with the second conductivity type is further formed on the surface of the body region 108 . The body contact region 112 is also connected to the source through a contact hole 113 a .

[0065] In the embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the LDMOS device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0066] The drift region field oxygen 107 of the embodiment of the present invention has a first shallow trench isolation 105, and a doping region shielding layer 104 heavily doped with the first conductive type is formed at the second bottom corner of the first shallow trench isolation 105 close to the drain region 111. Since the doping region shielding layer 104 and the drain region 111 have the same doping type and are heavily doped, when a high voltage is applied to the drain region 111, the doping region shielding layer 104 will not be depleted, so it will have a shielding effect on the electric field, so that the second bottom corner of the drift region field oxygen 107 will not be affected by the electric field of high electric field strength, and the second bottom corner of the drift region field oxygen 107 will not withstand high voltage. In this way, the reliability of the second bottom corner of the drift region field oxygen 107 can be improved, thereby improving the reliability of the entire device.

[0067] like Figures 2A to 2F FIG2 is a schematic diagram of the device structure in each step of the manufacturing method of the LDMOS device according to an embodiment of the present invention. The manufacturing method of the LDMOS device according to an embodiment of the present invention includes the following steps:

[0068] Step 1: Figure 2A As shown, a first epitaxial layer 102 is provided and a drift region doped with a first conductivity type is formed in a selected region of the first epitaxial layer 102 .

[0069] In the embodiment of the present invention, the first epitaxial layer 102 is formed on the surface of the semiconductor substrate 101. The first epitaxial layer 102 has a first conductivity type doping, and the drift region is composed of the first epitaxial layer 102 between the subsequently formed body region 108 and the drain region 111.

[0070] Step 2: forming a drift region field oxide 107 in a selected area of ​​the drift region, wherein the drift region field oxide 107 includes a first shallow trench isolation 105; the formation process of the first shallow trench isolation 105 includes:

[0071] Step 21: Figure 2A As shown, a selected area of ​​the first epitaxial layer 102 is etched to form a first shallow trench 103; a first side surface 1031 of the first shallow trench 103 is close to one side of a body region 108 to be formed subsequently and there is a gap between the body regions 108, and a second side surface 1032 of the first shallow trench 103 is close to one side of a drain region 111 to be formed subsequently; a first bottom angle of the first shallow trench 103 is a bottom angle of the bottom of the first side surface 1031 of the first shallow trench 103, and a second bottom angle of the first shallow trench 103 is a bottom angle of the bottom of the second side surface 1032 of the first shallow trench 103; the second bottom angle of the first shallow trench 103 is also a second bottom angle of the drift region field oxygen 107.

[0072] In the method of the embodiment of the present invention, a shallow trench 103 a is also formed outside the drift region. The shallow trench not formed in the drift region is indicated by a mark 103 a .

[0073] Step 22: Figure 2B As shown, first conductive type heavily doped ions are implanted to form a doped region shielding layer 104 in the drift region at the second bottom corner of the first shallow trench 103 , and the doped region shielding layer 104 completely covers the second bottom corner.

[0074] In the method of the embodiment of the present invention, the doped region shielding layer 104 also completely covers the second side surface 1032 of the first shallow trench 103 and contacts the subsequently formed drain region 111 at the top of the second side surface 1032 of the first shallow trench 103 .

[0075] Step 23: Figure 2C As shown, an oxide layer is filled in the first shallow trench 103 to form the first shallow trench isolation 105 .

[0076] In the method of the embodiment of the present invention, shallow trench isolation 105 a is also formed in the shallow trench 103 a outside the drift region.

[0077] The oxide layer in the first shallow trench 103 is usually deposited by a high density plasma (HDP) CVD process, and then a chemical mechanical polishing (CMP) process is performed after the HDP CVD process is completed to achieve planarization.

[0078] In some preferred embodiments, the top surface of the first shallow trench isolation 105 is flush with the top surface of the first epitaxial layer 102 .

[0079] like Figure 2D As shown, after step 23 is completed, the following steps are also included:

[0080] A second step oxide layer 106 is formed on top of the first shallow trench isolation 105 using an oxide layer deposition and patterned etching process, wherein the drift region field oxide 107 is formed by stacking the first shallow trench isolation 105 and the second step oxide layer 106. A first side surface of the second step oxide layer 106 is aligned with a first side surface of the first shallow trench isolation 105, and a second side surface of the second step oxide layer 106 is aligned with a second side surface of the first shallow trench isolation 105.

[0081] A step oxide layer is also stacked on the top of the shallow trench isolation 105 a to form a field oxide 107 a .

[0082] Step 3: Figure 2D As shown, a body region 108 doped with a second conductivity type is formed in a selected region of the first epitaxial layer 102 .

[0083] The body region 108 is usually formed by a high-voltage well region process.

[0084] Step 4: Figure 2E As shown, a gate structure is formed, which covers the surface of a selected area of ​​the body region 108 and extends from the first side surface of the drift region field oxide 107 to the top surface of the drift region field oxide 107 .

[0085] In the embodiment of the present invention, the gate structure includes a gate dielectric layer and a polysilicon gate 109 stacked in sequence, and the polysilicon gate 109 extending to the top surface of the drift region field oxide 107 forms a polysilicon shielding layer 109 a.

[0086] The gate dielectric layer is usually formed by using an oxide layer and a thermal oxidation process.

[0087] After the gate dielectric layer is formed, polysilicon is deposited, and then pattern etching is performed to simultaneously form the polysilicon gate 109 and the polysilicon shielding layer 109a.

[0088] Step 5: Figure 2F As shown, a source region 110 and a drain region 111 are formed by heavily doping the source and drain regions with the first conductivity type. The source region 110 is formed in the body region 108 and is self-aligned with the first side of the gate structure. The drain region 111 is self-aligned with the second side of the drift region field oxide 107.

[0089] When the drain region 111 is connected to the operating voltage, the first conductivity type of the doped region shielding layer 104 is heavily doped so that the doped region shielding layer 104 will not be depleted, thereby reducing the electric field strength at the second bottom corner of the drift region field oxygen 107 and improving the reliability of the device.

[0090] After step 5, if Figure 1 As shown, the process of forming an interlayer film (not shown), contact holes and a front metal layer is also included.

[0091] The contact hole passes through the interlayer film. The source region 110 is connected to the source electrode formed by the front metal layer through the contact hole 113a at the top. The metal of the source electrode also extends to the top of the drift region field oxide 107 and forms a source metal shielding layer 114a.

[0092] The drain region 111 is connected to the drain electrode formed by the front metal layer through a contact hole 113 b at the top. The metal of the drain electrode also extends to above the drift region field oxide 107 and forms a drain metal shielding layer 114 b.

[0093] A contact hole (not shown) is also formed on the top of the polysilicon gate 109 and is connected to a gate metal layer (not shown).

[0094] In the embodiment of the present invention, the LDMOS device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the LDMOS device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0095] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. An LDMOS device, characterized in that: include: a drift region doped with a first conductivity type and a body region doped with a second conductivity type formed in selected areas of the first epitaxial layer; A drift region field oxide is formed in a selected area of ​​the drift region; the drift region field oxide includes a first shallow trench isolation formed in a first shallow trench; There is a gap between the first side surface of the first shallow trench and the body region; A gate structure covers a surface of a selected area of ​​the body region and extends from a first side of the drift region field oxide to a top surface of the drift region field oxide; A source region heavily doped with a first conductivity type is formed in the body region and self-aligned with the first side surface of the gate structure; A drain region heavily doped with the first conductivity type is self-aligned with a second side of the field oxygen in the drift region; the drain region is formed in a surface region of the drift region; A doped region shielding layer of a first conductive type heavily doped layer is formed in the drift region at a second bottom corner of the first shallow trench and completely covers the second bottom corner, wherein the second bottom corner of the first shallow trench is the bottom angle of the second side surface of the first shallow trench, and the first bottom angle of the first shallow trench is the bottom angle of the first side surface of the first shallow trench; the second bottom angle of the first shallow trench is also the second bottom angle of the drift region field oxygen; When the drain region is connected to the operating voltage, the first conductivity type of the doped region shielding layer is heavily doped so that the doped region shielding layer will not be depleted, thereby reducing the electric field strength of the second bottom corner of the drift region field oxygen and improving the reliability of the device.

2. The LDMOS device according to claim 1, wherein: The doped region shielding layer also completely covers the second side surface of the first shallow trench and contacts the drain region at the top of the second side surface of the first shallow trench.

3. The LDMOS device according to claim 1, wherein: The first epitaxial layer has a first conductivity type doping, and the drift region is composed of the first epitaxial layer between the body region and the drain region.

4. The LDMOS device according to claim 1, wherein: The top surface of the first shallow trench isolation is flush with the top surface of the first epitaxial layer. A second step oxide layer is formed on the top of the first shallow trench isolation. The drift region field oxide is formed by stacking the first shallow trench isolation and the second step oxide layer.

5. The LDMOS device according to claim 4, wherein: A first side surface of the second step oxide layer is aligned with a first side surface of the first shallow trench isolation, and a second side surface of the second step oxide layer is aligned with a second side surface of the first shallow trench isolation.

6. The LDMOS device according to claim 1, wherein: The gate structure includes a gate dielectric layer and a polysilicon gate stacked in sequence, and the polysilicon gate extending to the top surface of the drift region field oxide forms a polysilicon shielding layer.

7. The LDMOS device according to claim 6, wherein: The source region is connected to a source electrode composed of a front metal layer through a contact hole at the top, and the metal of the source electrode also extends above the field oxygen of the drift region and forms a source metal shielding layer; The drain region is connected to a drain electrode formed by a front metal layer through a contact hole at the top. The metal of the drain electrode also extends above the field oxygen in the drift region and forms a drain metal shielding layer.

8. The LDMOS device according to claim 7, wherein: A body contact region heavily doped with the second conductivity type is also formed on the surface of the body region, and the body contact region is also connected to the source through a contact hole.

9. A method for manufacturing an LDMOS device, characterized in that: The steps include: Step 1: providing a first epitaxial layer and forming a drift region doped with a first conductivity type in a selected region of the first epitaxial layer; Step 2: forming a drift region field oxide in a selected area of ​​the drift region, wherein the drift region field oxide includes a first shallow trench isolation; The process for forming the first shallow trench isolation includes: Step 21: Etching a selected area of ​​the first epitaxial layer to form a first shallow trench; a first side surface of the first shallow trench is close to a side of a body region to be formed subsequently, with a gap between the body regions, and a second side surface of the first shallow trench is close to a side of a drain region to be formed subsequently; a first bottom angle of the first shallow trench is the bottom angle of the first side surface of the first shallow trench, and a second bottom angle of the first shallow trench is the bottom angle of the second side surface of the first shallow trench; the second bottom angle of the first shallow trench is also the second bottom angle of the drift region field oxygen; Step 22: Performing first conductivity type heavily doped ion implantation to form a doped region shielding layer in the drift region at the second bottom corner of the first shallow trench, wherein the doped region shielding layer completely covers the second bottom corner; Step 23: Filling the first shallow trench with an oxide layer to form the first shallow trench isolation; Step 3: forming a body region doped with a second conductivity type in a selected area of ​​the first epitaxial layer; Step 4: forming a gate structure, wherein the gate structure covers a surface of a selected area of ​​the body region and extends from a first side surface of the drift region field oxide to a top surface of the drift region field oxide; Step 5: performing heavily doped source and drain implantation of the first conductivity type to form a source region and a drain region, wherein the source region is formed in the body region and self-aligned with the first side surface of the gate structure; the drain region is formed in the surface region of the drift region and self-aligned with the second side surface of the drift region field oxide; When the drain region is connected to the operating voltage, the first conductivity type of the doped region shielding layer is heavily doped so that the doped region shielding layer will not be depleted, thereby reducing the electric field strength of the second bottom corner of the drift region field oxygen and improving the reliability of the device.

10. The method for manufacturing an LDMOS device according to claim 9, wherein: The doped region shielding layer also completely covers the second side surface of the first shallow trench and contacts the drain region at the top of the second side surface of the first shallow trench.

11. The method for manufacturing an LDMOS device according to claim 9, wherein: The first epitaxial layer has a first conductivity type doping, and the drift region is composed of the first epitaxial layer between the body region and the drain region.

12. The method for manufacturing an LDMOS device according to claim 9, wherein: A top surface of the first shallow trench isolation is flush with a top surface of the first epitaxial layer; In step 2, after step 23 is completed, the following steps are also included: A step of forming a second step oxide layer on top of the first shallow trench isolation by using an oxide layer deposition and patterned etching process, wherein the drift region field oxide is formed by superposition of the first shallow trench isolation and the second step oxide layer.

13. The method for manufacturing an LDMOS device according to claim 12, wherein: A first side surface of the second step oxide layer is aligned with a first side surface of the first shallow trench isolation, and a second side surface of the second step oxide layer is aligned with a second side surface of the first shallow trench isolation.

14. The method for manufacturing an LDMOS device according to claim 9, wherein: In step 4, the gate structure includes a gate dielectric layer and a polysilicon gate stacked in sequence, and the polysilicon gate extending to the top surface of the drift region field oxide forms a polysilicon shielding layer.

15. The method for manufacturing an LDMOS device according to claim 14, wherein: After step five, the process of forming an interlayer film, contact holes and a front metal layer is also included; The contact hole passes through the interlayer film; The source region is connected to a source electrode formed by the front metal layer through a contact hole at the top, and the metal of the source electrode also extends above the field oxygen of the drift region and forms a source metal shielding layer; The drain region is connected to a drain electrode formed by the front metal layer through a contact hole at the top. The metal of the drain electrode also extends above the field oxygen in the drift region and forms a drain metal shielding layer.

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