Antifuse unit, antifuse storage device and manufacturing method thereof

Abstract

This invention provides an antifuse cell, an antifuse memory device, and a method for manufacturing the same. The method for manufacturing the antifuse memory device includes: providing a substrate; forming an antifuse gate structure on a first well region; forming a patterned mask layer covering the antifuse gate structure and the first well regions on both sides; performing a lightly doped ion implantation process; removing the first mask layer; and performing a source / drain ion implantation process to form source / drain doped regions in the first well regions on both sides of the antifuse gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region. In this invention, by directly forming source / drain doped regions in the well regions on both sides of the antifuse gate structure without forming lightly doped source / drain regions, and utilizing these doped regions to form a through-hole, the read current is increased, thereby reducing defects caused by low read current and improving manufacturing yield. Compared to other solutions, this method is simple, easy to implement, and low-cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an antifuse unit, an antifuse storage device, and a method for manufacturing the same. Background Technology

[0002] Memory devices can generally be divided into volatile memory devices and non-volatile memory devices. Non-volatile memory devices can be further divided into read-only memory (ROM), one-time programmable memory (OTP memory), and rewritable memory. Among them, OTP memory can be classified into fuse-type and anti-fuse-type.

[0003] Antifuse memory devices are widely used due to their superior performance. A typical small memory cell consists of an antifuse cell and a select transistor. The working principle of antifuse memory is to store data 1 or 0 based on whether the antifuse gate dielectric layer is broken down.

[0004] Specifically, such as Figure 1 As shown, a storage region 10a' and a logic region 10b' are provided on the substrate 10'. A series-connected antifuse unit 21' and a select transistor 22' are formed on the well region of the storage region 10a'. A logic unit 23' is formed on the well region of the logic region 10b'. The antifuse unit 21', the select transistor 22' and the logic unit 23' are standard transistors of different specifications. Taking the antifuse unit 21' as an example, the gate structure of the antifuse unit 21' is located on the well region. The well regions on both sides of the gate structure of the antifuse unit 21' have source / drain doped regions 43', lightly doped source / drain regions 41' and pocket injection regions 42'.

[0005] However, the aforementioned antifuse memory suffers from a low yield due to its low read current, and existing solutions to this problem are costly, which seriously affects the market competitiveness of antifuse memory devices. Summary of the Invention

[0006] The purpose of this invention is to provide an antifuse unit, an antifuse storage device, and a method for manufacturing the same, thereby solving the defects caused by the small readout current at a lower cost.

[0007] To solve the above-mentioned technical problems, the present invention provides a method for manufacturing an antifuse memory device, comprising: providing a substrate, the substrate comprising a memory region having a first well region and a logic region having a second well region;

[0008] An antifuse gate structure is formed on the first well region, and a logic gate structure is formed on the second well region;

[0009] A patterned mask layer is formed, which covers the antifuse grid structure and the first well regions on both sides of the antifuse grid structure;

[0010] A lightly doped ion implantation process is performed to form lightly doped source and drain regions in the second well regions on both sides of the logic gate structure;

[0011] Remove the patterned mask layer and perform a source / drain ion implantation process to form source / drain doped regions in the first well regions on both sides of the antifuse gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region.

[0012] Optionally, the lightly doped ion implantation process includes lightly doped ion implantation perpendicular to the surface direction of the substrate and lightly doped ion implantation inclined to the surface direction of the substrate.

[0013] Optionally, after removing the patterned mask layer and before performing the source / drain ion implantation process, a sidewall structure is formed on the sidewalls of the antifuse gate structure and the logic gate structure.

[0014] Optionally, the width of the antifuse gate structure is smaller than the width of the logic gate structure.

[0015] Optionally, the width of the antifuse grid structure is less than or equal to 0.12 micrometers.

[0016] Optionally, a selector grid structure is also formed on the storage area, the width of which is greater than the width of the antifuse grid structure.

[0017] Optionally, the lightly doped ion implantation process and the source / drain ion implantation process are performed on the first well regions on both sides of the selected gate structure.

[0018] Optionally, the source / drain ion implantation process is performed on the first well regions on both sides of the selected gate structure.

[0019] According to another aspect of the present invention, an antifuse storage device is also provided, which is manufactured using the antifuse storage device manufacturing method described above.

[0020] According to another aspect of the present invention, an antifuse unit is also provided, comprising: a substrate having a well region thereon; an antifuse gate structure disposed on the well region; and source / drain doped regions located in the well regions on both sides of the antifuse gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region.

[0021] In summary, this invention forms a patterned mask layer covering the antifuse gate structure and its two sides' first well regions before the lightly doped ion implantation process. This prevents the formation of lightly doped source / drain regions in the first well regions on both sides of the antifuse gate structure. Furthermore, after the source / drain ion implantation process, the doped source / drain regions on both sides of the antifuse gate structure form a through-hole in the first well region beneath the antifuse gate structure. This not only facilitates the generation of a large current during programming to improve the programming efficiency of the antifuse memory device, but also increases the read current when data is available. This reduces the manufacturing difficulty of the antifuse memory device in terms of read current under the same design standards, thereby reducing defects caused by low read current and improving yield. At the same time, compared to other solutions, this embodiment is simple, easy to implement, and low-cost. Attached Figure Description

[0022] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0023] Figure 1 This is a schematic diagram of the structure of an existing antifuse storage device;

[0024] Figure 2 This is a flowchart of a method for manufacturing an antifuse storage device provided in Embodiment 1 of this application;

[0025] Figures 3a-3e A schematic diagram of the structure corresponding to the manufacturing method of the antifuse storage device provided in Embodiment 1 of this application;

[0026] Figure 4 This is a flowchart of a method for manufacturing an antifuse storage device provided in Embodiment 2 of this application.

[0027] Figure 1 middle:

[0028] 10' - Substrate; 10a' - Storage region; 10b' - Logic region; 21' - Antifuse cell; 22' - Select transistor; 23' - Logic gate cell; 41' - Lightly doped source / drain regions; 42' - Pocket implantation region; 43' - Doped source / drain regions.

[0029] Figures 3a to 3e middle:

[0030] 10-Substrate; 10a-Memory region; 10b-Logic region; 11-First well region; 12-Second well region; 21-Antifuse gate structure; 21a-Antifuse gate dielectric layer; 21b-Antifuse control gate layer; 22-Selector gate structure; 22a-Selector gate dielectric layer; 22b-Selector control gate layer; 23-Logic gate structure; 23a-Logic gate dielectric layer; 23b-Logic control gate layer; 31-First mask layer; 41-First lightly doped source / drain region; 42-Second lightly doped source / drain region; 43-Source / drain doped region; 44-Sidewall structure; 45-Punch-through region. Detailed Implementation

[0031] To make the objectives, advantages, and features of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to facilitate and clarify the explanation of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structures. In particular, different figures may emphasize different aspects and may sometimes use different scales.

[0032] As used in this invention, the singular forms “a,” “an,” and “the” include plural objects; the term “or” is generally used to mean “and / or”; the term “a number” is generally used to mean “at least one”; and the term “at least two” is generally used to mean “two or more”. Furthermore, the terms “first,” “second,” and “third” are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as “first,” “second,” or “third” may explicitly or implicitly include one or at least two of that feature, unless otherwise expressly indicated.

[0033] Example 1

[0034] Figure 2 This is a flowchart of the manufacturing method of the antifuse storage device provided in Embodiment 1 of this application.

[0035] like Figure 1 As shown, the manufacturing method of the antifuse storage device provided in this embodiment includes:

[0036] S01: A substrate is provided, the substrate including a memory region having a first well region and a logic region having a second well region;

[0037] S02: An antifuse gate structure and a selector gate structure are formed on the first well region, and a logic gate structure is formed on the second well region;

[0038] S03: Form a first mask layer, the first mask layer covering the antifuse grid structure and the first well regions on both sides of the antifuse grid structure;

[0039] S04: Perform a light-doped ion implantation process to form lightly doped source / drain regions in the first well regions on both sides of the selected gate structure and the second well regions on both sides of the logic gate structure; and

[0040] S05: Remove the first mask layer and perform a source / drain ion implantation process to form source / drain doped regions in the first well regions on both sides of the antifuse gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region.

[0041] Figures 3a-3d This is a schematic diagram of the structure corresponding to the steps of the manufacturing method of the antifuse storage device provided in the embodiments of this application. The following will be combined with Figures 3a to 3d The manufacturing method of the antifuse storage device provided in this embodiment is described in detail.

[0042] Please refer to Figure 3a Step S01 is executed, providing a substrate 10, which includes a storage region 10a having a first well region 11 and a logic region 10b having a second well region.

[0043] The substrate 10 can be any suitable semiconductor substrate, such as a silicon-based semiconductor or a silicon-on-insulator (SOI) substrate 10. An epitaxial layer may also be formed on the surface of the substrate 10, and subsequent device structures are formed in the epitaxial layer. A memory region 10a and a logic region 10b defined by an isolation structure (e.g., an STI structure) are formed on the substrate 10. The memory region 10a is used to form antifuse memory cells, and the logic region 10b is used to form logic cells. Specifically, a first well region 11 formed by ion implantation is formed in the memory region 10a, and a second well region 12 formed by ion implantation is formed in the logic region 10b. Electrical isolation is achieved by utilizing the fact that the conductivity type of the well region is opposite to the conductivity type of the source and drain structure of the transistor (including antifuse cells, select transistors, and logic cells).

[0044] In this embodiment, taking a silicon substrate 10 and NMOS transistors as an example, the doping type of both the substrate 10 and the epitaxial layer is P-type, and the first well region 11 and the second well region 12 have the same conductivity type and are both P-type (P-WELL).

[0045] Please refer to Figure 3b In step S02, an antifuse gate structure 21 and a selector gate structure 22 are formed on the first well region 11 of the logic region 10b, and a logic gate structure 23 is formed on the second well region 12 of the logic region 10b.

[0046] Gate structures for corresponding transistors are formed on the first well region 11 and the second well region 12. The gate structure includes a gate dielectric layer and a gate conductive layer located on the gate dielectric layer. For example, an antifuse gate structure 21 and a select gate structure 22 are formed on the first well region 11, and a logic gate structure 23 is formed on the second well region 12. The antifuse gate structure 21 includes an antifuse gate dielectric layer 21a and an antifuse control gate layer 21b, the select gate structure 22 includes a select gate dielectric layer 22a and a select gate control gate layer 22b, and the logic gate structure 23 includes a logic gate dielectric layer 23a and a logic control gate layer 23b.

[0047] Furthermore, the aforementioned gate structure can have different parameters depending on design requirements (e.g., operating voltage), such as the length of the conductive channel (width of the gate structure) and the thickness of the gate dielectric layer. In this embodiment, the antifuse gate structure 21 can be a low-voltage cell (below 3.3V), the selector gate structure 22 can be a high-voltage cell (greater than 3.3V), and the logic gate structure 23 can be a low-voltage cell. Correspondingly, the width of the antifuse gate structure 21 is smaller than the width of the selector gate structure 22, and the thickness of the antifuse gate dielectric layer 21a is smaller than the thickness of the selector gate dielectric layer 22a. Those skilled in the art are familiar with the methods for forming transistor gate structures, which will not be elaborated here.

[0048] Please refer to Figure 3c Step S03 is executed to form a first mask layer 31, which covers the antifuse grid structure 21 and the first well regions 11 on both sides of the antifuse grid structure 21.

[0049] The first mask layer 31 can be any mask layer suitable for serving as an ion implantation barrier layer. It can be a single-layer structure or at least a two-layer structure, and may include an amorphous carbon layer or a silicon oxide layer in addition to the photoresist layer. The first mask layer 31 (patterned mask layer) covers the antifuse gate structure 21 and the first well regions 11 on both sides of the antifuse gate structure 21 to prevent the covered area from being implanted with ions during the source / drain lightly doped ion implantation process.

[0050] Among them, such as Figure 3cAs shown, the antifuse gate structure 21 is adjacent to (connected to) the selector gate structure 22. The first well regions 11 located on both sides of the antifuse gate structure 21 may include a first region and a second region. The first well region 11 on the side of the antifuse gate structure 21 away from the selector gate structure 22 can be the first region, and the first well region 11 on the side of the antifuse gate structure 21 closer to the selector gate structure 22 can be the second region. That is, the second region is the connection region (common region) between the antifuse gate structure 21 and the selector gate structure 22. The first mask layer 31 covers the first region and the antifuse gate structure 21, and extends to cover a portion of the second region, so that the source / drain lightly doped ion implantation process can be performed on the selector later. The size or proportion of the first mask layer 31 covering the second region can be calculated according to the design parameters of the selector. In this embodiment, the first mask layer 31 may, for example, cover the middle position of the second region.

[0051] Please refer to Figure 3d In step S04, using the first mask layer 31 as a mask, a lightly doped ion implantation process is performed to form source-drain lightly doped regions (LDDs) on the first well region 11 on both sides of the select gate structure 22 and the second well region 12 on both sides of the logic gate structure 23.

[0052] Preferably, the light-doped ion implantation process may include light-doped ion implantation perpendicular to the substrate surface and light-doped ion implantation inclined to the substrate surface. Light-doped ion implantation perpendicular to the substrate surface can form a first source / drain light-doped region 41 of a certain depth (relatively shallow) in the first well region 11 and part of the second well region 12 on both sides of the select gate structure 22 and the logic gate structure 23. Light-doped ion implantation inclined to the substrate surface can form a second source / drain light-doped region 42 (pocket implantation region) in the first well region 11 and part of the second well region 12 on both sides of the select gate structure 22 and under the logic gate structure 23. The ion implantation type of the light-doped ion implantation process is opposite to the ion implantation type of the corresponding well region, and the ion concentration of the first source / drain light-doped region 41 and the second source / drain light-doped region 42 is lower than the ion concentration of the corresponding well region. It is easy to understand that due to the presence of the first mask layer 31, the first well region 11 (including the first region and the second region) on both sides of the antifuse gate structure 21 does not form a source / drain light-doped region.

[0053] Please refer to Figure 3e In step S05, the first mask layer 31 is removed and a source / drain ion implantation process is performed to form source / drain doped regions 43 in the first well regions 11 on both sides of the antifuse gate structure 21. The source / drain doped regions 43 form a through-hole in the first well region 11 under the antifuse gate structure 21.

[0054] The specific formation process may include, for example, the following steps: first, removing the first mask layer 31; then, forming a sidewall structure 44 on the sidewall of the gate structure (including the antifuse gate structure 21, the select gate structure 22, and the logic gate structure 23); then, performing a source / drain ion implantation process on the substrate 10 to form the source / drain doped regions 43 of the transistors; and then, performing an annealing process.

[0055] The sidewall structure 44 can be a single-layer ON structure or a multi-layer ON structure, and the ON structure can be a silicon oxide layer and a silicon nitride layer. The conductivity type of the doped ions in the source / drain ion implantation process is opposite to that of the corresponding well region, with a higher ion implantation concentration and greater depth (the junction depth is deeper than the depth of the first lightly doped source / drain region 41). Taking the first well region 11 and the second well region 12 in this embodiment as both being P-type, source / drain ion implantation processes can be performed simultaneously in the memory region 10a and the logic region 10b, and the ion type in the source / drain ion implantation process is N-type. The annealing process can be a rapid thermal annealing process or laser annealing, etc.

[0056] It should be noted that in this embodiment, since no lightly doped source / drain regions are formed under the antifuse gate structure 21, the source / drain doped regions 43 on both sides of the antifuse gate structure 21 are connected to the depletion layer of the first well region 11 of the antifuse gate structure 21 to form a punch-through. That is, a punch-through region 45 is formed in the conductive channel under the antifuse gate structure 21. This punch-through makes it easier for the antifuse memory device to form a large current to break down the antifuse gate dielectric layer 21a during programming, thereby improving the programming efficiency of the antifuse memory device. More importantly, it also increases the read current when data is readable, thereby reducing the manufacturing difficulty of the antifuse memory device under the same design standards (specification requirements), improving its fault tolerance, and reducing defects caused by the small read current, thereby improving the yield. In addition, the PN junction formed by the source / drain doped regions 43 and the first well region 11 can also be used to prevent current leakage from the substrate, thereby reducing the current.

[0057] Preferably, where design allows, the conductive channel length (width of the antifuse gate structure) of the antifuse unit can be shortened as much as possible. For example, the width of the antifuse gate structure should be at least smaller than the width of the logic gate structure. This ensures that the source and drain of the logic unit do not punch through, while utilizing the short-channel effect to allow the source and drain of the antifuse unit to punch through. In one specific embodiment, when the width of the antifuse gate structure is less than or equal to 0.12 micrometers, performing a source and drain ion implantation process on the antifuse unit will allow the source and drain of the antifuse unit to punch through.

[0058] Example 2

[0059] Figure 4 This is a flowchart of a method for manufacturing an antifuse storage device provided in Embodiment 2 of this application.

[0060] like Figure 4 As shown, the manufacturing method of the antifuse storage device provided in this embodiment includes:

[0061] S01: A substrate is provided, the substrate including a memory region having a first well region and a logic region having a second well region;

[0062] S02: An antifuse gate structure and a selector gate structure are formed on the first well region of the logic region, and a logic gate structure is formed on the second well region of the logic region;

[0063] S03: Form a second mask layer, the second mask layer covering the storage area;

[0064] S04: Perform a lightly doped ion implantation process to form lightly doped source / drain regions in the second well region of the logic gate structure;

[0065] S05: Remove the second mask layer and perform a source / drain ion implantation process to form source / drain doped regions in the first well regions on both sides of the antifuse gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region.

[0066] The manufacturing method provided in this embodiment is basically the same as that provided in Embodiment 1, except for the difference in step S03. In this embodiment, the second mask covers the entire storage region, including the antifuse gate structure, the select gate structure, and the first well regions on both sides, thereby eliminating the need to form lightly doped source / drain regions in the antifuse gate structure and the first well regions on both sides of the select gate structure. Therefore, the source / drain doped regions on both sides of the antifuse gate structure can be connected to the depletion layer of the first well region to form a punch-through. It should be understood that because the channel length of the select transistor is relatively large, even if lightly doped source / drain regions are not formed in the first well regions on both sides of the select gate structure, the source / drain doped regions of the select transistor will not be punched through.

[0067] Example 3

[0068] Example 3 provides an antifuse memory device manufactured using the antifuse memory device manufacturing method described above. The antifuse memory device includes a storage region and a logic region. An antifuse cell and a select transistor are formed in the storage region, and logic cells are formed in the logic region. The source / drain doped regions (source / drain structures) of the antifuse cells form a through-hole in the channel under their gate structure to increase the read current of the antifuse cells.

[0069] Example 4

[0070] This embodiment provides an antifuse unit, which includes a substrate, an antifuse gate structure, and source / drain doped regions. A well region is provided on the substrate, the antifuse gate structure is disposed on the well region, and the source / drain doped regions are located in the well regions on both sides of the antifuse gate structure. Furthermore, the source / drain doped regions of the antifuse unit form a through-hole in the well region under the antifuse gate structure.

[0071] In summary, this invention forms a patterned mask layer covering the antifuse gate structure and its two sides' first well regions before the lightly doped ion implantation process. This prevents the formation of lightly doped source / drain regions in the first well regions on both sides of the antifuse gate structure. Furthermore, after the source / drain ion implantation process, the doped source / drain regions on both sides of the antifuse gate structure form a through-hole in the first well region beneath the antifuse gate structure. This not only facilitates the generation of a large current during programming to improve the programming efficiency of the antifuse memory device, but also increases the read current when data is available. This reduces the manufacturing difficulty of the antifuse memory device in terms of read current under the same design standards, thereby reducing defects caused by low read current and improving yield. At the same time, compared to other solutions, this embodiment is simple, easy to implement, and low-cost.

[0072] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for manufacturing an antifuse storage device, characterized in that, include: A substrate is provided, the substrate including a memory region having a first well region and a logic region having a second well region; An antifuse gate structure and a selector gate structure are formed on the first well region, and a logic gate structure is formed on the second well region. The width of the selector gate structure is greater than the width of the antifuse gate structure, and the width of the antifuse gate structure is less than the width of the logic gate structure. A patterned mask layer is formed, which covers the first well region; A lightly doped ion implantation process is performed to form lightly doped source and drain regions in the second well regions on both sides of the logic gate structure; Remove the patterned mask layer and perform a source / drain ion implantation process to form source / drain doped regions in the first well regions on both sides of the antifuse gate structure and the selector gate structure, wherein the source / drain doped regions on both sides of the antifuse gate structure form a through-hole in the first well region.

2. The method for manufacturing the antifuse storage device according to claim 1, characterized in that, The lightly doped ion implantation process includes lightly doped ion implantation perpendicular to the surface direction of the substrate and lightly doped ion implantation inclined to the surface direction of the substrate.

3. The method for manufacturing the antifuse storage device according to claim 1, characterized in that, After removing the patterned mask layer and before performing the source / drain ion implantation process, a sidewall structure is formed on the sidewalls of the antifuse gate structure and the logic gate structure.

4. The method for manufacturing the antifuse storage device according to claim 1, characterized in that, The width of the antifuse grid structure is less than or equal to 0.12 micrometers.

5. An antifuse storage device, characterized in that, The antifuse storage device is manufactured using the manufacturing method of an antifuse storage device as described in any one of claims 1 to 4.

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