A phase synchronization system of a regional distribution network inverter

Abstract

This invention belongs to the field of power equipment control technology, specifically relating to a phase synchronization system for inverters in a regional distribution network. The system places a centralized controller at the regional power supply inlet to measure voltage phase. Based on this measurement result, it performs phase-locked synchronization on the inverters to obtain more accurate synchronization results. The centralized controller establishes a correspondence between voltage phase and communication timestamp through a communication timestamp counter. It then sends phase synchronization frames to the inverter controller via the communication network. The inverter controller, based on the processing of its communication physical layer receiver, achieves phase-locked synchronization using the communication timestamp. This, combined with the local phase-locked result, recovers the local synchronized voltage phase and performs PWM control accordingly. This provides a reliable and stable instantaneous synchronized phase for the group control operation of inverters in the regional distribution network system. While reducing synchronization phase errors, it uses continuous local synchronized instantaneous voltage phase data output, facilitating instantaneous PWM modulation control and avoiding operational oscillation faults in AC inverters within the region.

Description

Technical Field

[0001] This invention belongs to the field of power equipment control technology, and specifically relates to a phase synchronization system for a regional distribution network inverter. Background Technology

[0002] With the widespread application of new energy equipment such as photovoltaics and wind power, as well as energy storage equipment, the coordinated synchronization control of multiple inverters connected to the AC side of the power grid through AC-DC conversion or AC-AC conversion has become a very serious problem.

[0003] Traditional inverters use the voltage phase at the connection point as the basis for calculating the pulse modulation (PWM) signal. This approach assumes that the grid-side impedance at the connection point is very small and negligible, thus assuming the connection point voltage is interference-free and stable. However, with the increasing number of AC inverters installed in regional power distribution systems, the impedance of transformers, lines, and switches between the transmission lines and the AC inverters cannot be ignored. Furthermore, the PWM modulation control method of the inverter itself generates harmonic interference, affecting the voltage quality at the inverter's AC connection point. This leads to unstable inverter output and impacts output performance.

[0004] For example, traditional phase-locked loop (PLL) methods based on voltage zero-crossing are prone to inaccurate acquisition due to the vulnerability of the zero-crossing point to harmonic interference, resulting in low reliability of the obtained voltage phase. PLL methods based on voltage waveforms are also susceptible to phase output fluctuations caused by voltage amplitude interference. More seriously, if the AC inverter in a regional distribution network system experiences synchronization phase errors due to interference from itself or other equipment at its AC connection point, these errors can create positive feedback in the inverter's control logic, leading to control system oscillations, complete inverter failure, and severe malfunctions. Summary of the Invention

[0005] The purpose of this invention is to provide a phase synchronization system for regional distribution network inverters, which solves the problem that the phase synchronization of existing regional distribution network inverters is easily affected by line interference, resulting in large phase errors and causing oscillation faults in inverter control.

[0006] To achieve the above objectives, the present invention provides a phase synchronization system for a regional distribution network inverter, comprising a centralized controller and an inverter controller; or comprising a centralized controller, an inverter controller, and a repeater.

[0007] The centralized controller is located at the regional power supply inlet and includes at least an AC voltage phase-locked loop (PLL) section, a time counter, and a physical layer transmitter. The AC voltage PLL section is used to phase-lock the measured voltage phase at the regional power supply inlet to obtain the instantaneous voltage phase. The time counter is used to generate the time counter value corresponding to the locked instantaneous phase and the time counter value transmitted by the physical layer of the centralized controller. The physical layer transmitter is used to transmit the locked instantaneous phase directly or through a repeater to the inverter controller according to the set communication interval in the phase synchronization frame format.

[0008] The phase synchronization frame communication signal includes at least a frame control part, which includes a time stamp count value sent by the physical layer of the centralized controller, a time stamp count value corresponding to the locked instantaneous phase, an instantaneous voltage phase, and the number of clock points in the power frequency cycle.

[0009] The inverter controller includes at least a local counter, a physical layer receiver, a time-stamped phase-locked loop (PLL) section, a synchronization phase calculation section, and a PWM modulation section. The physical layer receiver is used to obtain and parse the phase synchronization frame communication signal from the central controller or repeater. When the frame control part information is parsed, it immediately generates a locking signal and sends it to the local counter of the inverter controller. The local counter is used to obtain the local count value locked by the local counter of the repeater and set it as the local count value. The time-stamped phase-locked loop (PLL) section is used to calculate the local time-stamped phase-locked loop count of the inverter controller based on the local count value and the frame control part information parsed by the physical layer receiver. The synchronization phase calculation section is used to calculate the local synchronization instantaneous voltage phase corresponding to the local time-stamped phase-locked loop count based on the frame control part information parsed by the physical layer receiver. The PWM modulation section is used to generate a PWM pulse width modulation control signal output based on the local synchronization instantaneous voltage phase.

[0010] The system first measures the voltage phase at the power supply inlet using a centralized controller located at the regional power supply inlet, obtaining more accurate and stable phase measurement results. Then, it establishes a correspondence between the voltage phase and the communication time stamp through a communication time stamp counter. Using the communication network, it sends the phase synchronization frame data of the centralized controller to the inverter controller. By using communication time stamp phase-locking, the phase measurement results are synchronized to each inverter controller. Therefore, it can provide a more reliable and stable instantaneous synchronization phase for the group control operation of multiple AC inverters in the regional distribution network system, thereby reducing the error of the PWM modulation control synchronization phase of the inverter.

[0011] Furthermore, the time-stamped phase-locked loop (PSL) section is used to obtain the local time-stamped phase-locked loop count of the inverter controller by performing time-stamped phase-locked loop processing based on the local count value and the time-stamped count value parsed by the physical layer receiver.

[0012] Furthermore, the synchronization phase calculation section is used to parse the time stamp count value, instantaneous voltage phase, and power frequency cycle clock point number corresponding to the locked instantaneous phase of the frame control section from the physical layer receiver of the inverter controller, and obtain the local synchronization instantaneous voltage phase corresponding to the local time stamp phase-locked count of the inverter controller through synchronization phase calculation processing.

[0013] The local synchronization instantaneous voltage phase of the inverter controller obtained from the above parameters can integrate the time scale and phase relationship information of the centralized controller and the inverter, making the voltage phase of the inverter controller more accurate and reliable.

[0014] Furthermore, to avoid excessive instantaneous errors in the local time-scale phase-locked loop (PLL) count, which could lead to the inability to achieve phase synchronization control, when the inverter controller's local time-scale PLL is stable, the error between the inverter controller's local time-scale PLL count value and the centralized controller's time-scale count value at the same moment must be less than the minimum accuracy requirement for phase control. The specific formula is as follows:

[0015] |C sd -C m | <N E =N m (j)×E ph / 2π

[0016] Among them, C sd C is the local time-stamped phase-locked loop counter value of the inverter controller; m N is the time-stamped count value of the centralized controller; m (j) represents the number of clock points in the power frequency cycle; N E This is an intermediate variable with no practical meaning; j is the sequence number of the phase synchronization frame data prepared by the central controller each time, incremented by 1 each time data is prepared; E ph This represents the minimum accuracy requirement for phase control.

[0017] Furthermore, the time-scale phase-locked loop (PLL) processing performed by the time-scale phase-locked loop (PLL) section of the inverter controller is as follows:

[0018] ① The synchronization error d(i) is obtained by calculating the following formula:

[0019]

[0020] Where C' sd (i) The inverter controller receives the locking signal generated by the phase synchronization frame to lock the uncompensated local time-stamped phase-locked count value, C. d (i) is the local counter value locked by the lock signal, C m (i) and C m (i-1) represents the time stamp count value sent by the physical layer of the central controller in the current phase synchronization frame and the previous phase synchronization frame;

[0021] ② Perform proportional-integral control calculations on the synchronization error d(i) to obtain the clock error e. S (i); Proportional clock error e in proportional-integral control P (i) Calculate according to the following formula:

[0022]

[0023] Among them, K P It is the proportional control coefficient, e Pmax and e Pmin These are the upper and lower threshold values ​​for the proportional clock error, set according to the clock requirements of the communication equipment. The calculation in the above formula starts from i=2, e P (i) Initial value is e P (0)=e P (1) = 0; the integral clock error e in proportional-integral control I (i) Calculate according to the following formula:

[0024]

[0025] Among them, K I It is the proportional control coefficient, e Imax and e Imin These are the upper and lower threshold values ​​for the proportional clock error, set according to the clock requirements of the communication equipment. The calculation in the above formula starts from k=2, e I (i) Initial value is e I (0) = 0,

[0026] Ultimately, the clock error e of the proportional-integral control output S (i) Calculate according to the following formula:

[0027] e S (i)=e P (i)+e I (i)

[0028] ③ Clock error e S (i) After adding 1, according to the clock f clk_d After counting and accumulating and rounding, the uncompensated local time-scaled phase-locked loop count C' is obtained. sd ;

[0029] ④ If the delay between the instant the physical layer receiver generates the receive lock signal and the lock time of the physical layer transmitter transmitting the phase synchronization frame is fixed at N, then... d And set the average number of count errors to M. d Then the final output of the time-stamped phase-locked loop (PLL) processing is the local time-stamped PLL count value:

[0030]

[0031] The above time-scaled phase-locked loop processing steps constitute a feedback tracking system, the discrete form of which is:

[0032] C' sd (i)=C' sd (i-1)+(C m (i)-C m (i-1))·(1+e S (i-1)).

[0033] Furthermore, the synchronization phase calculation process of the synchronization phase calculation section of the inverter controller is divided into the following two cases:

[0034] When C sd (j) <C sd ≤C sd (j)+N J hour,

[0035]

[0036]

[0037]

[0038] When C sd (j)+N J <C sd ≤C sd When (j+1),

[0039]

[0040] Among them, C sd C is the local time-stamped phase-locked loop counter value of the inverter controller; sd (j), φ mL (j) and N m (j) represents the local time-stamped phase-locked count value, instantaneous voltage phase, and power frequency cycle clock point corresponding to the locked instantaneous phase of the frame control part parsed by the physical layer receiver; C m The time-stamped count value of the centralized controller; φ sd The local synchronization instantaneous voltage phase corresponds to the local time-stamped phase-locked loop counter of the inverter controller; j is the sequence number of the phase synchronization frame data prepared by the centralized controller each time data is prepared, incrementing by 1 each time; N J It is the number of synchronization phase smoothing adjustment points set to remove abrupt changes in the synchronization phase.

[0041] In the process of synchronous phase calculation, in order to avoid the first few synchronous phase points from jumping due to untimely phase tracking, fast tracking is first performed when the local time scale phase-locked count value is small, i.e., the first processing case is adopted. Then, the normal phase tracking process is performed, i.e., the second processing case is adopted.

[0042] Furthermore, the repeater includes at least a physical layer receiver, a local counter, a time-stamped phase-locked loop (PLL) section, and a physical layer transmitter;

[0043] The physical layer receiver of the repeater is used to receive the phase synchronization frame communication signal from the central controller or the previous level repeater, parse out the frame control part information in it, and immediately generate a lock signal to send to the local counter; the local counter is used to obtain the local counter value locked by the local counter of the repeater;

[0044] The time-stamped phase-locked loop (PSLL) section of the repeater is used to obtain the local PSLL count of the repeater by processing the local count value and the time-stamped count value parsed from the physical layer receiver of the previous repeater. If the phase synchronization frame communication signal received by the repeater comes from the central controller, the time-stamped count value used by the repeater is the time-stamped count value parsed by the physical layer receiver of the central controller.

[0045] The physical layer transmitter of the repeater is used to relay the phase synchronization frame. The phase synchronization frame includes at least the time stamp count value corresponding to the locked instantaneous phase received from the central controller, the instantaneous voltage phase, and the number of power frequency cycle clock points, as well as the physical layer transmission time stamp count value. The physical layer transmission time stamp count value refers to the local time stamp phase-locked count output value locked at the moment when the physical layer transmitter of the repeater transmits the phase synchronization frame.

[0046] Furthermore, the frame control portion of the phase synchronization frame communication signal has a fixed time length.

[0047] The frame control communication signal of the phase synchronization frame has a fixed duration, which ensures a fixed processing delay under the premise that the received data is correct. This ensures that the time when the physical layer receiver generates the lock signal corresponds to the time when the physical layer transmitter locks the phase synchronization frame. Therefore, this transmission delay can be compensated for, thus ensuring that the error between the local time-stamped phase-locked count value and the time-stamped count value of the centralized controller at the same time does not include the transmission delay of the physical layer. Attached Figure Description

[0048] Figure 1 This is a basic principle structure diagram of a phase synchronization system for a regional distribution network inverter according to the present invention;

[0049] Figure 2This is a schematic diagram of the all-digital AC voltage phase-locked loop principle used in the centralized controller of the system embodiment of the present invention;

[0050] Figure 3 This is a schematic diagram of the repeater in a system embodiment of the present invention;

[0051] Figure 4 This is a schematic diagram of the principle structure of time-scale phase-locked loop processing in the repeater and inverter controller in the system embodiment of the present invention. Detailed Implementation

[0052] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0053] An embodiment of a phase synchronization system for a regional distribution network inverter

[0054] This embodiment provides a phase synchronization system for a regional distribution network inverter, such as Figure 1 As shown below, the system is applied to several communities under the same 10kV distribution line, with photovoltaic inverters, energy storage and reactive power compensators installed on the 380V side. The phase synchronization group control operation of the system is explained below.

[0055] The system mainly includes a centralized controller, repeaters, and inverter controllers. The centralized controller is installed at the busbar inlet of the 10kV distribution network. This centralized controller communicates with the AC inverters of the photovoltaic inverters, energy storage, and reactive power compensators in the distribution area using high-speed power line carrier technology. The centralized controller is the master node, and the other AC inverters are slave nodes. Repeaters are installed in the transmission lines. In this embodiment, the centralized controller sends phase synchronization frames to the repeaters and AC inverters at adjustable intervals between 0.5 and 10 seconds based on power line carrier communication. The phase synchronization frame communication signal consists of a preamble of fixed length, a frame control of fixed length, and a variable-length load data portion transmitted by other functional parts of the centralized controller.

[0056] Because the centralized controller is installed at the regional power supply inlet, this location corresponds to a relatively smaller grid impedance at the regional power supply inlet, and the grid voltage is less affected by the load and AC inverter, which is beneficial for obtaining stable and accurate instantaneous voltage phase and power frequency cycle measurement results. Furthermore, the frame control part of the phase synchronization frame is set to a fixed time length, ensuring that the inverter controller has a fixed processing delay for the frame control part, provided the received data is correct. This ensures that the moment the lock signal is generated from the physical layer receiver corresponds to the moment the phase synchronization frame is locked from the physical layer transmitter, thus ensuring a fixed delay. Therefore, this transmit / receive delay can be compensated in the inverter controller's time-stamped phase-locked loop processing, ensuring that the error between the inverter controller's local time-stamped phase-locked loop count value and the centralized controller's time-stamped count value at the same moment does not include the physical layer's transmit / receive delay.

[0057] For the specific structure of the centralized controller, please refer to Figure 1 It mainly includes an AC voltage phase-locked loop section, a time counter, and a physical layer transmitter for the communication section. The frame control part of the phase synchronization frame transmitted through its physical layer transmitter contains the physical layer transmission time counter value C. m (i) Lock the time stamp count value C corresponding to the instantaneous phase. m (j) Instantaneous voltage phase φ mL (j) and the number of clock points in the power frequency cycle N m (j). Among them, C m (i) The output value of the time-locked time counter for the phase synchronization frame transmitted by the physical layer transmitter of the centralized controller; the time counter is at frequency f clk_m The time stamp counter increments by 1 under clock control, and the output time stamp count value C is calculated. m ; i is the sequence number of the phase synchronization frame, incremented by 1 with each transmission; C m (j) The time stamp count value locked when preparing the phase synchronization frame for the central controller; φ mL (j) The instantaneous voltage phase of the L-phase output of the AC voltage phase-locked loop section when preparing the phase synchronization frame for the centralized controller, where the L-phase corresponds to several phases of the three phases A, B, and C, φ mL (j) corresponds to the instantaneous voltage phase of these several phases, where j is the sequence number of the phase synchronization frame data prepared by the centralized controller each time, incrementing by 1 each time data is prepared. Because the time of sending the phase synchronization frame is after the time of preparing the phase synchronization frame data, we have C m (i)>C m (j);N m (j) The average number of power frequency periodic clock points of the corresponding time-stamped counting clock locked when preparing a phase synchronization frame for the centralized controller, and N m (j) has a number of decimal places.

[0058] Specifically, the centralized controller adopts Figure 2 The phase-locked loop (PLL) algorithm, implemented using an FPGA and based on nonlinear equations, obtains the instantaneous phase φ of phase A by sampling the input phase A AC voltage, performing phase detection processing, loop filtering, and phase integration. mA (j). Further, based on its instantaneous angular frequency ω(t), the average number of clock points N of the power frequency cycle is obtained through averaging and conversion. m (j).

[0059] The structure of the inverter controller is as follows Figure 1 The right-hand section, as shown, mainly includes a local counter, a physical layer receiver, a time-stamped phase-locked loop (PLL) section, a synchronization phase calculation section, and a PWM modulation section. It obtains the phase synchronization frame from the centralized controller through the physical layer receiver in its communication section. When the physical layer receiver parses the frame control information, it immediately generates a locking signal and sends it to the local counter. The inverter controller's local counter operates at a frequency of f... clk_d The counter increments by 1 under the control of its local clock. This local clock has the same nominal value as the time-marked counter clock of the centralized controller, but there is a certain error. The local counter is locked to a local count value of C. d (i).

[0060] The time-scaled phase-locked loop (PLL) section in the inverter controller is based on the local count value C. d (i) and the time-stamped count value C parsed from the physical layer receiver. m (i) Output the local time-stamped phase-locked count C through time-stamped phase-locked processing. sd To avoid excessive time-scale error between the inverter controller and the centralized controller, which would lead to a large phase-locked loop (PLL) error, when the local time-scale PLL is stable, the local time-scale PLL count value C at the same moment is... sd The time-scaled count value C of the centralized controller m The error needs to be less than the minimum phase control accuracy E. ph The requirement is that |C sd -C m | <N E =N m (j)×E ph / 2π.

[0061] The physical layer receiver of the inverter controller resolves the time stamp count value C corresponding to the locking instantaneous phase of the frame control section. m (j) Instantaneous voltage phase φ mL (j) and the number of clock points in the power frequency cycle N m (j) Simultaneously, the synchronization phase calculation part is input to perform synchronization phase calculation processing to obtain the corresponding local time-stamped phase-locked count C. sd Local synchronization instantaneous voltage phase φ sd .

[0062] The PWM pulse width modulation section in the inverter controller is based on the local synchronous instantaneous voltage phase φ sd The parameters provided by the inverter control section are used to generate a PWM pulse width modulation control signal output.

[0063] The synchronization phase calculation section of the inverter controller performs synchronization phase calculations in two different ways:

[0064] When C sd (j) <C sd ≤C sd (j)+N J hour,

[0065]

[0066]

[0067]

[0068] When C sd (j)+N J <C sd ≤C sd When (j+1),

[0069]

[0070] Among them, C sd (j) is the local time-stamped phase-locked count value corresponding to the lock signal output by the physical layer receiver after parsing the frame control part information, N. J The number of synchronization phase smoothing adjustment points is set to remove abrupt changes in the synchronization phase. j is the sequence number of the phase synchronization frame data prepared by the central controller each time, which is incremented by 1 each time data is prepared. Since the central controller performs phase locking once every time a phase synchronization frame is generated, j can also represent the number of phase locks performed by the central controller.

[0071] The process of synchronous phase calculation is the process of linear tracking adjustment within the time period corresponding to the number of synchronous phase smoothing adjustment points. In order to avoid the first few synchronous phase points from jumping due to untimely phase tracking during synchronous phase calculation, the linear tracking process is divided into two stages: first, fast tracking is performed when the local time scale phase-locked count value is small, i.e., the first processing case is adopted; then, normal phase tracking (synchronous phase) process is performed, i.e., the second processing case is adopted.

[0072] If the centralized controller and the inverter controller cannot communicate directly, for example, due to long distances or significant interference, the centralized controller can also transmit phase synchronization frame communication signals to an inverter controller participating in the phase synchronization group control operation at certain communication intervals through several repeaters. The structure of the repeaters is as follows: Figure 3 As shown, it mainly includes a physical layer receiver, a local counter, a time-stamped phase-locked loop (PLL) section, and a physical layer transmitter; the specific operation process of this repeater structure is as follows:

[0073] When the physical layer receiver of repeater (q) receives the phase synchronization frame communication signal from the central controller or the upstream repeater (p) and parses out the frame control information, it immediately generates a locking signal and sends it to the local counter. Here, p and q are different identifiers for the repeaters. The local counter of repeater (q) operates at frequency f. clk_r_q The counter increments by 1 under the control of the local clock, which in this embodiment has a nominal clock value of 25MHz; the local counter is locked to a local count value of C. r_q (i). The time-scaled phase-locked loop (PLL) of the repeater (q) is based on the local count value C. r_q (i) The time-stamp count value parsed from the physical layer receiver is processed by time-stamp phase-locked loop (PLL) to output the local time-stamp phase-locked loop (TPL) count C. sr_q .

[0074] If the phase synchronization frame communication signal (hereinafter referred to as the phase synchronization frame) received by the repeater (q) comes from the central controller, then the time stamp count value resolved by the physical layer receiver of the repeater (q) is C. m (i); If the phase synchronization frame received by repeater (q) comes from the previous repeater (p), then the time stamp count value resolved by the physical layer receiver of repeater (q) is C. r_p (i). Subsequently, the repeater (q) relays the phase synchronization frame via the physical layer transmitter of its communication section. This phase synchronization frame contains the time stamp count value C corresponding to the locked instantaneous phase received from the central controller. m (j) Instantaneous voltage phase φ mL (j) and the number of clock points in the power frequency cycle N m (j) and payload data, but its frame control portion contains the physical layer transmission time stamp count value C. sr_q (i) is the local time-stamped phase-locked count output value of the repeater (q) locked at the moment when the physical layer transmitter of the repeater (q) sends the phase synchronization frame.

[0075] Subsequently, the repeater relays a phase synchronization frame via the physical layer transmitter of its communication section. This phase synchronization frame includes at least the time stamp count value C corresponding to the locked instantaneous phase received from the central controller. m Instantaneous voltage phase φmL (j) and the number of clock points N in the power frequency cycle m (j) also includes a physical layer transmit time stamp count value, which refers to the local time stamp phase-locked loop (PLL) count output value C locked at the moment when the physical layer transmitter of the repeater transmits the phase synchronization frame. sr_q (i).

[0076] In the above process, the time stamp count value C contained in the synchronization phase frame m (i) or C sr_p (i) The phase synchronization frame is locked and placed into the frame control part of the phase synchronization frame to be sent at the instant when the physical layer transmitter of the central controller or repeater (p) sends the phase synchronization frame. When the physical layer receiver of the repeater (q) or inverter controller receives the frame control part of the phase synchronization frame, it immediately generates a lock signal and sends it to the local counter.

[0077] On the other hand, although the frequency of the communication time stamp count value in megahertz can meet the accuracy of marking the instantaneous voltage phase corresponding to the moment, the output of the local time stamp phase-locked loop (PLL) count of each repeater stage will experience synchronization fluctuations. These fluctuations, carried over to the local clock PLL input of the next repeater stage or inverter controller, will inevitably amplify the tracking fluctuations. Therefore, the more stages there are, the more important it is to maintain the synchronization accuracy with the time stamp count value C of the centralized controller. m The error will increase. If the instantaneous error of the local time-stamped phase-locked loop (PLL) counter is too large, phase synchronization control will also fail. Therefore, according to the system design parameters, each repeater needs to be set with a minimum phase control accuracy E. ph The performance requirements are set accordingly, and error limits are set based on these requirements. |C sd -C m | <N E =N m (j)×E ph / 2π; where C sd C is the local time-stamped phase-locked loop counter value of the inverter controller; m N m (j) is the time stamp count value and the number of clock points in the power frequency cycle corresponding to the instantaneous phase locked by the centralized controller; N E This is an intermediate variable with no practical meaning; j is the sequence number of the phase synchronization frame data prepared by the central controller each time, incremented by 1 each time data is prepared; E ph This represents the minimum accuracy requirement for phase control.

[0078] In this embodiment, the inverter controller and repeater perform the same processing when receiving the phase synchronization frame communication signal. Figure 1The right side shows the principle structure of the inverter controller, mainly including a local counter, a physical layer receiver, a time-stamped phase-locked loop (PLL) section, a synchronization phase calculation section, and a PWM modulation section. When the inverter controller's physical layer receiver receives the phase synchronization frame communication signal from the central controller or repeater and parses out the frame control information, it immediately generates a locking signal and sends it to the local counter. The local counter increments by 1 under the control of the ground clock. The local clock frequency of the inverter controller is f. clk_d Local counter count value C d The local count value of the physical layer receiver lock signal is C. d (i).

[0079] The time-scale phase-locked loop (PLL) processing section in the inverter controller relies on the local count value C. d (i), and the time-stamped count value C parsed from the physical layer receiver. m (i) Output the local time-stamped phase-locked count C through time-stamped phase-locked processing. sd When the local time-stamped phase-locked loop is stable, the local time-stamped phase-locked loop count value C at the same moment... sd The time-scaled count value C of the centralized controller m The error needs to be less than the minimum phase control accuracy E. ph The requirement is that |C sd -C m | <N E =N m (j)×E ph / 2π.

[0080] The physical layer receiver of the inverter controller resolves the time stamp count value C corresponding to the locking instantaneous phase of the frame control section. m (j) Instantaneous voltage phase φ mL (j) and the number of clock points in the power frequency cycle N m (j) is sent to the synchronization phase calculation section for processing to obtain the corresponding local time-stamped phase-locked count C. sd Local synchronization instantaneous voltage phase φ sd The PWM pulse width modulation section in the inverter controller is based on the local synchronous instantaneous voltage phase φ. sd The inverter control section generates a PWM pulse width modulation control signal output based on the operating parameters provided.

[0081] In this embodiment, the principle structure of the time-stamped phase-locked loop (PLL) processing for the repeater and inverter controller to receive phase synchronization frames is as follows: Figure 4 As shown, in Figure 4 Taking only the corresponding parameter labels of the phase synchronization frames received by the inverter controller from the centralized controller as an example, the processing flow of the time-stamped phase-locked loop is as follows:

[0082] ① The uncompensated local time-stamped phase-locked count value C' is locked based on the locking signal generated by the phase synchronization frame received by the inverter controller. sd Get C' sd (i) The local counter value C locked based on the lock signal. d (i) and the centralized controller physical layer transmit time stamp count value C contained in the current phase synchronization frame and the previous phase synchronization frame. m (i) and C m (i-1), the synchronization error d(i) is obtained by calculation according to the following formula:

[0083]

[0084] ② Using the synchronization error d(i) as input, perform proportional-integral control calculations to obtain the clock error e. S (i); Proportional clock error e in proportional-integral control P (i) Calculate according to the following formula:

[0085]

[0086] Among them, K P It is the proportional control coefficient, e Pmax and e Pmin These are the upper and lower threshold values ​​for the proportional clock error, set according to the clock requirements of the communication equipment. The calculation in the above formula starts from i=2, e P (i) The initial value is set to e P (0)=e P (1) = 0. The integral clock error e in proportional-integral control. I (i) Calculate according to the following formula:

[0087]

[0088] Among them, K I It is the proportional control coefficient, e Imax and e Imin These are the upper and lower threshold values ​​for the proportional clock error, set according to the clock requirements of the communication equipment. The calculation in the above formula starts from k=2, e I (i) The initial value is set to e I (0) = 0,

[0089]

[0090] Ultimately, the clock error e of the proportional-integral control output S (i) Calculate according to the following formula:

[0091] e S (i)=e P (i)+e I(i).

[0092] ③ Clock error e S (i) After adding 1, according to the clock f clk_d After counting and accumulating and rounding, the uncompensated local time-scaled phase-locked loop count C' is obtained. sd .

[0093] ④ If the delay between the instant the physical layer receiver generates the receive lock signal and the lock time of the physical layer transmitter transmitting the phase synchronization frame is fixed at N, then... d And set the average number of count errors to M. d Then the final output of the time-stamped phase-locked loop (PLL) processing is the local time-stamped PLL count value:

[0094]

[0095] The above time-scaled phase-locked loop processing steps constitute a feedback tracking system, the discrete form of which is:

[0096] C' sd (i)=C' sd (i-1)+(C m (i)-C m (i-1))·(1+e S (i-1));

[0097] In a preferred embodiment, e is set Imax =-e Imax =2e-5,e Pmax =-e Pmax =1e-5,K P =0.105, K I =0.005625, which is sufficient to achieve a clock error e S (i) fast stabilization and local time-scaled phase-locked loop counter C sd With the central controller time-stamped count value C m The consistency of |C sd -C m |The error is less than the phase synchronization operation control accuracy E ph Minimum required error N E =N m (j)×E ph / 2π.

[0098] After completing the time-stamped phase-locked loop (PLL) processing of the phase synchronization frame, the repeater obtains its local time-stamped PLL count C. sr Subsequently, the repeater relays the phase synchronization frame via the physical layer transmitter of its communication section. This phase synchronization frame contains the time stamp count value C corresponding to the locked instantaneous phase received from the central controller. m (j) Instantaneous voltage phase φmL (j) and the number of clock points in the power frequency cycle N m (j) and payload data. When the repeater forwards the phase synchronization frame, it replaces the physical layer transmission time stamp count value contained in the frame control part of the frame with the repeater's local time stamp phase-locked count output value C, which is locked at the time when the repeater's own physical layer transmitter transmits the phase synchronization frame. sr (i).

[0099] After the inverter controller and the central controller establish a synchronized local time-stamped phase-locked count, this embodiment further uses the time-stamped count value C corresponding to the locked instantaneous phase transmitted by the phase synchronization frame. m (j) Instantaneous voltage phase φ mL (j) and the number of clock points in the power frequency cycle N m (j) Constructing a local synchronous instantaneous voltage phase φ sd The synchronization phase is calculated and processed by the synchronization phase calculation section of the inverter controller, with the synchronization phase smoothing adjustment point N. J Linear tracking adjustment is performed within the corresponding time period to compensate for the discrete instantaneous voltage phase φ. mL (j) Phase jumps that occur when constructing continuous instantaneous phases.

[0100] The PWM pulse width modulation processing in the inverter controller is based on the local synchronous instantaneous voltage phase φ sd The inverter control section generates a PWM pulse width modulation control signal output based on the operating parameters provided.

[0101] This invention has the following characteristics:

[0102] The voltage phase at the power supply inlet is measured by a centralized controller installed at the regional power supply inlet. Based on the measurement results, multiple inverters are synchronized by phase-locking to obtain more accurate synchronization results.

[0103] The centralized controller establishes the correspondence between voltage phase and communication time stamp through a communication time stamp counter. It then sends phase synchronization frame data to the inverter controller via the communication network. The inverter controller, based on the processing of its communication physical layer receiver, achieves phase-locked synchronization using the communication time stamp. By combining this with the local phase-locked result, it recovers the local synchronization instantaneous voltage phase φ. sd The present invention provides a reliable and stable instantaneous synchronization phase for the group control operation of multiple AC inverters in a regional power distribution network system. The synchronization phase error of the inverter's PWM modulation control is small, and the continuous local synchronous instantaneous voltage phase data output facilitates instantaneous control through PWM modulation, thus avoiding oscillation faults in the operation of AC inverters within the region.

[0104] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A phase synchronization system of a regional distribution network inverter, characterized by, The centralized controller and the inverter controller are included, or the centralized controller, the inverter controller and the repeater are included. The centralized controller is arranged at a regional power supply inlet, and the position is relatively smaller in impedance of the power grid, and the voltage of the power grid is less affected by the load and the AC inverter; the centralized controller at least includes an AC voltage phase-locked part, a time scale counter and a physical layer transmitter; the AC voltage phase-locked part is used for phase locking the voltage phase measured at the regional power supply inlet, and obtaining an instantaneous voltage phase; the time scale counter is used for generating a time scale count value corresponding to the locked instantaneous phase and a physical layer transmission time scale count value of the centralized controller; and the physical layer transmitter is used for transmitting the locked instantaneous phase to the inverter controller according to a phase synchronization frame format directly or through the repeater according to a set communication interval. The phase synchronization frame communication signal at least includes a frame control part, and the frame control part includes the physical layer transmission time scale count value of the centralized controller, the time scale count value corresponding to the locked instantaneous phase, the instantaneous voltage phase and the clock point number of the power frequency cycle; The inverter controller at least includes a local counter, a physical layer receiver, a time scale phase-locked part, a synchronous phase calculation part and a PWM modulation part; the physical layer receiver is used for obtaining and analyzing the phase synchronization frame communication signal from the centralized controller or the repeater, and when the frame control part information is analyzed, a locking signal is immediately generated and sent to the local counter of the inverter controller; the local counter is used for obtaining the local count value locked by the local counter of the repeater, and setting the local count value; the time scale phase-locked part is used for calculating the local time scale phase-locked count of the inverter controller according to the local count value and the frame control part information analyzed by the physical layer receiver; the synchronous phase calculation part is used for calculating the local synchronous instantaneous voltage phase corresponding to the local time scale phase-locked count according to the frame control part information analyzed by the physical layer receiver; and the PWM modulation part is used for generating a PWM pulse width modulation control signal output according to the local synchronous instantaneous voltage phase.

2. The phase synchronization system of a zone networking inverter according to claim 1, wherein, The time scale phase-locked part is used for obtaining the local time scale phase-locked count of the inverter controller through time scale phase-locked processing according to the local count value and the time scale count value analyzed by the physical layer receiver.

3. The phase synchronization system of a zone networking inverter according to claim 1, wherein, The synchronous phase calculation part is used for obtaining the local synchronous instantaneous voltage phase corresponding to the local time scale phase-locked count of the inverter controller through synchronous phase calculation processing according to the time scale count value corresponding to the locked instantaneous phase of the frame control part, the instantaneous voltage phase and the clock point number of the power frequency cycle analyzed by the physical layer receiver of the inverter controller.

4. The phase synchronization system of a zone networking inverter according to claim 1, wherein, When the local time scale phase-locked count of the inverter controller is stable, the error between the local time scale phase-locked count value of the inverter controller and the time scale count value of the centralized controller at the same time needs to be less than the minimum accuracy requirement of the phase control, and the specific formula is as follows: |C sd -C m |<N E = N m (j)×E ph / 2π; Wherein, C sd is the local time scale phase-locked count value of the inverter controller; C m is the time scale count value of the centralized controller; N m (j) is the clock point number of the power frequency cycle; N E is an intermediate variable, which has no actual meaning; j is the serial number of each time the centralized controller prepares phase synchronization frame data, which is increased by 1 each time the data is prepared; E ph is the minimum accuracy requirement of phase control.

5. The phase synchronization system of a zone networking inverter according to claim 2, wherein, The time scale phase-locked processing of the time scale phase-locked part of the inverter controller is as follows: The synchronization error d(i) is calculated according to the following equation: ； where C sd (i) is the local count value locked by the lock signal generated by the phase synchronization frame received by the inverter controller, C d (i) is the local count value locked by the lock signal, C m (i) and C m (i-1) is the centralized controller physical layer transmission time stamp count value included in the current phase synchronization frame and the previous phase synchronization frame; The proportional-integral control calculation is performed on the synchronization error d(i) to obtain the clock error e S (i); the proportional clock error e P (i) is calculated according to the following formula: ； where K P is a proportional control coefficient, e Pmax and e Pmin are upper and lower threshold values of the proportional clock error set according to the clock requirements of the communication equipment, the above formula is calculated from i = 2, e P (i) is the initial value e P (0) = e P (1) = 0; the integral clock error e I (i) in the proportional integral control is calculated according to the following formula: ； where K I is a proportional control coefficient, e Imax and e Imin are upper and lower threshold values of the proportional clock error set according to the clock requirements of the communication equipment, the above formula is calculated from k = 2, e I (i) the initial value is e I (0) = 0, ; Finally, the clock error e of the proportional-integral control output S (i) is calculated according to the formula: ； Clock error e S (i) after adding 1, according to the clock f clk_d After counting accumulation and rounding, the uncompensated local time scale phase-locked count C' is obtained sd ; If the instant time of the physical layer receiver generating the receiving lock signal corresponds to the fixed delay N of the lock time of the physical layer transmitter sending the phase synchronization frame d And the average number of the count error is set as M d The local time scale phase lock count value of the time scale phase lock processing final output is: ； The above time scale phase-locked processing steps constitute a feedback tracking system, and the discrete form is as follows: 。 6. The phase synchronization system of a zone networking inverter according to claim 3, wherein, The synchronous phase calculation processing of the synchronous phase calculation part of the inverter controller is divided into the following two cases: When C sd (j) < C sd ≤ C sd (j) + N J then, ； ； ； When C sd (j) + N J < C sd ≤ C sd (j+1) ； Wherein, C sd is the local time scale phase-locked count value of the inverter controller; C sd (j), φ mL (j) and N m (j) are respectively the local time scale phase-locked count value, the instantaneous voltage phase and the power frequency cycle clock point corresponding to the locked instantaneous phase of the frame control part parsed by the physical layer receiver; C m is the time scale count value of the centralized controller; φ sd is the local synchronous instantaneous voltage phase corresponding to the local time scale phase-locked count of the inverter controller; j is the serial number of each time the centralized controller prepares phase synchronization frame data, which is increased by 1 each time the data is prepared; N J is the set number of synchronous phase smoothing adjustment points for removing sudden changes in the synchronous phase.

7. The phase synchronization system of a zone networking inverter according to claim 1, wherein, The relay device comprises a physical layer receiver, a local counter, a time scale phase-locked part and a physical layer transmitter; The physical layer receiver of the relay device is used to receive the phase synchronization frame communication signal from the centralized controller or the upper level relay device, analyze the frame control part information and immediately generate a locking signal to the local counter; The time scale phase-locked part of the relay device is used to obtain the local time scale phase-locked count of the relay device through time scale phase-locked processing according to the local count value and the time scale count value analyzed by the physical layer receiver of the upper level relay device; if the phase synchronization frame communication signal received by the relay device is from the centralized controller, the time scale count value used is the time scale count value analyzed by the physical layer receiver of the centralized controller; The physical layer transmitter of the relay device is used to relay the phase synchronization frame, which comprises at least the time scale count value corresponding to the locking instantaneous phase from the centralized controller, the instantaneous voltage phase and the power frequency cycle clock point number, and further comprises the physical layer transmission time scale count value, wherein the physical layer transmission time scale count value refers to the local time scale phase-locked count output value locked at the time when the physical layer transmitter of the relay device transmits the phase synchronization frame.

8. The phase synchronization system of a zone networking inverter according to claim 1, wherein, The frame control part of the phase synchronization frame communication signal has a fixed time length.

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