Test structure and manufacturing method and test method thereof

Abstract

The present invention provides a test structure and a manufacturing method and a test method thereof. The test structure includes a first sub-test module and a second sub-test module. The first sub-test module includes a first word line, a first active area, a first contact column and a first metal line. The first active area extends along a first direction, and the first active area is electrically connected in series along the first direction by the first metal line. The second sub-test module includes a second word line, a second active area, a second contact column and a second metal line. The second active area extends along a second direction, and the second active area is electrically connected in series along the second direction by the second metal line. In the present invention, the first sub-test module is used to simulate the connection status of the bit line of the storage device along the first direction, and the second sub-test module is used to simulate the connection status of the bit line of the storage device along the second direction, and the monitoring resistor is used to achieve the purpose of quickly and effectively monitoring the bit line of the storage device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a test structure and a manufacturing method and a testing method thereof. Background Art

[0002] In semiconductor integrated circuits, with the development of semiconductor technology, the market share of non-volatile flash memory is increasing. In order to meet the market demand for high density, high performance and low cost, the technology nodes are getting smaller and smaller. The monitoring of the electrical parameters of non-volatile flash memory requires more comprehensive and more accurate testing, which can better reflect the process status.

[0003] like Figure 1 As shown, the existing test structure for the bit line (ByteLine) is mainly a functional test structure, and its structure is similar to the structure of the memory cell in the device area. The functional test structure includes a word line 21' and an active area 22' arranged orthogonally, and the word line 21' and the active area 22' are both long strips. The contact column 23' (CT) is arranged on the active area 22' and is located on both sides of the word line 21'. The bit line (not shown, metal line) is located on the contact column 23' and electrically leads out of the active area 21' to complete the functional test. If an abnormal result is obtained through the test structure, it is not possible to judge whether it is a functional abnormality of the memory cell or an abnormality of the bit line itself (for example, an abnormality of the metal column 23', or an abnormal connection between the metal column 23' and the active area 21' or the metal line), which makes it difficult to quickly and effectively monitor the abnormality of the bit line. Summary of the invention

[0004] The object of the present invention is to provide a test structure and a manufacturing method and a test method thereof, so as to quickly and effectively monitor the abnormality of the bit line of a memory device.

[0005] To solve the above technical problems, the present invention provides a test structure, which is used to detect the bit line of a memory device in a WAT ​​test, comprising a substrate and a first sub-test module and a second sub-test module arranged on the substrate;

[0006] The first sub-test module includes at least two first word lines, at least six first active areas, a plurality of first contact pillars, and a plurality of first metal lines, wherein the first word lines are located on the substrate and extend along a first direction, the first active area is located on the substrate and extends along the first direction, at least six first active areas are arranged into at least three groups along a second direction, at least three groups of the first active areas and at least two first word lines are sequentially arranged at intervals along the second direction, two first contact pillars are arranged on each first active area, the first metal lines and the first contact pillars are used to connect the first active areas in series along the first direction as a main direction to form a first S-type test circuit, and the head end and tail end of the first S-type test circuit are used as the first bit line test end;

[0007] The second sub-test module includes at least three second word lines, at least eight second active areas, a plurality of second contact pillars and a plurality of second metal lines. The second active areas are arranged on the substrate and extend along the second direction. At least eight second active areas are arranged into at least two groups along the second direction. The second word lines extend along the first direction and are arranged along the second direction. Each group of second active areas has one second word line. The remaining second word lines are located on the substrate between two adjacent groups of second active areas. The second contact pillars are located on the second active areas on both sides of the second word lines. The second active areas are connected in series along the second direction as the main direction using second metal lines and the second contact pillars to form a second S-type test circuit. The head and tail ends of the second S-type test circuit are used as second bit line test ends. The first direction is orthogonal to the second direction.

[0008] Optionally, the memory device is a split-gate flash memory device, the memory device has a device area and a test area, the test structure is located in the test area, and the first contact column and the second contact column are formed under the same process conditions as the contact column in the device area.

[0009] Optionally, the first active area, the first contact column and the first metal line are used to simulate the connection condition of the bit line of the device area along the first direction, and the second active area, the second contact column and the second metal line are used to simulate the connection condition of the bit line of the device area along the second direction.

[0010] Optionally, the first active area and the first contact pillars in the first sub-test module are evenly and symmetrically distributed on both sides of the first word line, and the second contact pillars in the second sub-test module are evenly and symmetrically distributed on both sides of the second word line.

[0011] Optionally, in the first sub-test module, the number of the first bit lines is n, the number of groups of the first active regions arranged along the first direction is n+1, and n is greater than or equal to 2.

[0012] Optionally, in the second sub-test module, the number of groups of the second active regions arranged along the first direction is m, the number of the second bit lines is 2m-1, and m is greater than or equal to 2.

[0013] According to another aspect of the present invention, a method for manufacturing a test structure is also provided, wherein the test structure is used to detect a bit line of a memory device in a WAT ​​test, and the method for manufacturing the test structure comprises:

[0014] providing a substrate;

[0015] Forming at least six first active regions and at least eight second active regions on the substrate, wherein the at least six first active regions extend along a first direction and are arranged into at least three groups along a second direction, and the at least eight second active regions extend along the second direction and are arranged into at least two groups along the second direction;

[0016] forming at least two first word lines and at least three second word lines, wherein the first word lines and the second word lines both extend along the first direction and are arranged along the second direction, at least two of the first word lines are located on the substrate between at least three groups of the first active regions, one of the second word lines is located on each group of the second active regions, and the remaining second word lines are located on the substrate between two adjacent groups of the second active regions;

[0017] Forming first contact pillars and second contact pillars, wherein two first contact pillars are disposed on each of the first active regions and the first contact pillars are located on both sides of the first word line, and two second contact pillars are disposed on each of the second active regions and the second contact pillars are located on both sides of the second word line;

[0018] Forming a first metal line and a second metal line, connecting the first active area in series along the first direction as the main direction by using the first metal line and the first contact column to form a first S-type test circuit, and connecting the second active area in series along the second direction as the main direction by using the second metal line and the second contact column to form a second S-type test circuit;

[0019] A first bit line test end and a second bit line test end are formed, the first end and the tail end of the first S-type test line are used as the first bit line test end, and the first end and the tail end of the second S-type test line are used as the second bit line test end.

[0020] Optionally, both the first word line and the second word line are virtual word lines.

[0021] According to another aspect of the present invention, a test method of a test structure is provided, wherein the test structure is used to detect a bit line of a memory device in a WAT ​​test, and the test method of the test structure comprises:

[0022] Providing a test structure as described above, the test structure comprising a first sub-test module having a first preset resistance range and a second sub-test module having a second preset resistance range;

[0023] Obtaining a first resistance test value of the first sub-test module, and comparing whether the first resistance test value is within the first preset resistance range, so as to determine whether a connection condition of the bit line along the first direction is normal;

[0024] A second resistance test value of the second sub-test module is obtained, and the second resistance test value is compared to see whether it is within the second preset resistance range, so as to determine whether the connection status of the bit line along the second direction is normal.

[0025] Optionally, the first resistance test value is greater than the upper limit of the first preset resistance range to determine that the bit line has an open circuit along the first direction, and the first resistance test value is less than the lower limit of the first preset resistance range to determine that the bit line has a short circuit along the first direction; the second resistance test value is greater than the upper limit of the second preset resistance range to determine that the bit line has an open circuit along the second direction, and the second resistance test value is less than the lower limit of the second preset resistance range to determine that the bit line has a short circuit along the second direction.

[0026] In summary, the present invention sets a first sub-test module and a second sub-test module on a substrate, in the first sub-test module, the first active area extends along the first direction, and then the first metal line and the first contact column are used to electrically connect the first active area in series along the first direction, so as to simulate the connection condition of the bit line of the storage device along the first direction, in the second sub-test module, the second active area extends along the second direction, and then the second metal line and the second contact column are used to electrically connect the second active area in series along the second direction, so as to simulate the connection condition of the bit line of the storage device along the second direction, and then through the testing of the first sub-test module and the second sub-test module, direct monitoring of the connection condition of the bit line of the storage device along the first direction and the second direction is realized, thereby realizing rapid and effective monitoring of the bit line of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0028] Figure 1 is a schematic diagram of the existing test structure;

[0029] Figure 2is a schematic diagram of a test structure provided in Example 1 of the present application;

[0030] Figure 3a and Figure 3b A schematic diagram of the structure of other test structures provided in Example 1 of the present application;

[0031] Figure 4 A flow chart of a method for manufacturing a test structure provided in Embodiment 2 of the present application;

[0032] Figure 5a to Figure 5f This is a structural schematic diagram corresponding to the manufacturing method of the test structure provided in Example 2.

[0033] Figure 1 middle:

[0034] 10'-substrate; 21'-word line; 22'-active area; 23'-contact pillar;

[0035] Figure 2 to Figure 5f middle:

[0036] 10-substrate; D1-first direction; D2-second direction;

[0037] 20 - first sub-test module; 21 - first word line; 22 - first active area; 23 - first contact column; 24 - first metal line; 25 - first bit line test end;

[0038] 30 - a second sub-test module; 31 - a second word line; 32 - a second active region; 33 - a second contact column; 34 - a second metal line; 35 - a second bit line test terminal. DETAILED DESCRIPTION

[0039] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0040] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0041] Embodiment 1

[0042] Figure 2 It is a structural diagram of the test structure provided in Example 1.

[0043] Please refer to Figure 2 The test structure provided in this embodiment detects the bit line of the memory device in the WAT test by using the test structure. The test structure includes a substrate 10 and a first sub-test module 20 and a second sub-test module 30 disposed on the substrate 10.

[0044] The first sub-test module 20 includes at least two first word lines 21, at least six first active areas 22, a plurality of first contact pillars 23 and a plurality of first metal lines 24. The first word lines 21 are located on the substrate 10 and extend along the first direction D1. The first active areas 22 are located on the substrate 10 and extend along the first direction D1. The at least six first active areas 22 are arranged into at least three groups along the second direction D2. The at least three groups of first active areas 22 and the at least two first word lines 21 are arranged in sequence along the second direction D2. Two first contact pillars 23 are provided on each first active area 22. The first metal lines 24 and the first contact pillars 23 are used to connect the first active areas 22 in series along the first direction D1 as the main direction to form a first S-type test circuit, and the head end and the tail end of the first S-type test circuit are used as the first bit line test end 25.

[0045] The second sub-test module 30 includes at least three second word lines 31, at least eight second active areas 32, a plurality of second contact pillars 33 and a plurality of second metal lines 34. The second active areas 32 are arranged on the substrate 10 and extend along the second direction D2. The at least eight second active areas 32 are arranged into at least two groups along the second direction D2. The second word lines 31 extend along the first direction D1 and are arranged along the second direction D2. Each group of second active areas 32 has one second word line 31, and the remaining second word lines 31 are located on the substrate 10 between two adjacent groups of second active areas 32. The second contact pillars 33 are located on the second active areas 32 on both sides of the second word lines 31. The second metal lines and the second contact pillars 33 are used to connect the second active areas 32 in series along the second direction D2 as the main direction to form a second S-type test circuit, and the head end and the tail end of the first S-type test circuit are used as the second bit line test end 35. The first direction D1 is orthogonal to the second direction D2.

[0046] The substrate 10 may be any substrate 10 suitable for forming a memory device, such as a silicon-based semiconductor substrate 10 or a silicon-on-insulator (SOI) substrate 10. A device region and a test region are provided on the substrate 10. The device unit is formed on the device region. The device unit may be, for example, a storage unit and a logic unit. The test structure is formed on the test region. The test region is located between the device regions. The test region may be, for example, located on a cutting path of the substrate 10. In this embodiment, the memory device may be, for example, a split-gate flash memory device. The test structure includes a first sub-test module 20 and a second sub-test module 30 located in the test region. The first sub-test module 20 is used to simulate the connection status of the bit line of the device region along the first direction D1 to detect (monitor) the connection status of the bit line along the first direction D1. The second sub-test module 30 is used to simulate the connection status of the bit line of the device region along the second direction D2 to detect (monitor) the connection status of the bit line along the second direction D2. The first direction D1 is orthogonal to the second direction D2. The first direction D1 may be, for example, horizontal, and the second direction D2 may be, for example, vertical.

[0047] Please continue to refer to Figure 2In this embodiment, the first sub-test module 20 includes two first word lines 21, six first active areas 22, twelve first contact pillars 23 and first metal lines 24. The first active area 22 is located on the substrate 10, and its shape can be, for example, rectangular (long strip), the first active area 22 extends along the first direction D1 and the six first active areas 22 are arranged in three groups (three rows) along the second direction D2, each group (each row) includes two first active areas 22, that is, the six first active areas 22 are arranged in three rows and two columns. The first word line 21 is located on the substrate 10, and its shape can be, for example, rectangular, the first word line 21 extends along the first direction D1 and is arranged at intervals along the second direction D2, two first word lines 21 are arranged in two rows and the two first word lines 21 are located between the three rows of first active areas 22. Two first contact pillars 23 are provided at both ends of each first active area 22, and the first active area 22 is electrically led out from both ends of the first active area 22 by using the two first contact pillars 23. Preferably, the first active area 22 and the first contact pillars 23 are evenly and symmetrically distributed on both sides of the first word line 21. Multiple sections of first metal wires 24 are connected in series by serpentine (S-shaped) routing along the first direction D1 as the main direction, and the first metal wires 24 are used to electrically connect two adjacent first active areas 22 by using the first contact pillars 23 at the middle position of each group of first active areas 22, and the first metal wires 24 arranged along the second direction D2 are used to connect the first end or the tail end of each group of first active areas 22. Thus, a first S-type test circuit is formed by connecting all the first active regions 22, first contact pillars 23 and first metal wires 24 in series, and the head end and tail end of the first S-type test circuit are electrically led out to the pad metal layer (pad layer) to form two electrodes, and the two electrodes are used as the first bit line test terminal 25. The first active region 22, the first contact pillar 23 and the first metal wire 24 are used to simulate the connection status of the bit line of the device region along the first direction D1, so that the connection status of the bit line along the first direction D1 can be judged (evaluated) by testing the first bit line test terminal 25 during the WAT test.

[0048] Please continue to refer to Figure 2In this embodiment, the second sub-test module 30 includes three second word lines 31, eight second active areas 32, sixteen second contact pillars 33 and second metal lines 34. The second active area 32 is on the substrate 10 (in the substrate 10), and its shape is, for example, rectangular. The second active area 32 extends along the second direction D2. The eight second active areas 32 are arranged into two groups (two rows) along the second direction D2. Each group has four second active areas 32, that is, the eight second active areas 32 are arranged into two rows and four columns. The shape of the second word line 31 is, for example, rectangular. The second word line 31 extends along the first direction D1 and is arranged at intervals along the second direction D2. The three second word lines 31 are arranged into three rows. The second word lines 31 of the odd rows (the first row and the third row) are respectively located on a group of second active areas 32, and the second word lines 31 of the even rows (the second row) are respectively located on the substrate 10 between two adjacent rows of second active areas 32. A second contact column 33 is provided at both ends of each second active region 32, and the second active region 32 is electrically led out from both ends by using two second contact columns 33, so that the second contact columns 33 are provided on both sides of each second word line 31. Preferably, the second contact columns 33 are evenly and symmetrically distributed on both sides of the second word line 31. Multiple sections of second metal wires 34 connect the eight second active regions 32 in series by serpentine routing along the second direction D2 as the main direction, and the second metal wires 34 are used to electrically connect two adjacent second active regions 32 by using the second contact column 33 in the middle position of each column of the second active regions 32, and the second metal wires 34 provided along the first direction D1 are used to connect the first or tail ends of each column of the second active regions 32. Thus, a second S-type test circuit is formed by connecting all the second active regions 32, second contact pillars 33 and second metal wires 34 in series, and the head end and tail end of the second S-type test circuit are electrically led out to the pad metal layer (pad layer) to form two electrodes, and the two electrodes are used as the second bit line test terminal 35. The second active region 32, the second contact pillar 33 and the second metal wire 34 are used to simulate the connection status of the bit line of the device region along the second direction D2, so that the connection status of the bit line along the second direction D2 can be judged (evaluated) by testing the second bit line test terminal 35 during the WAT test.

[0049] In other embodiments, the test structure may include at least two first sub-test modules 20 and at least two second sub-test modules 30, each of which includes a first sub-test module 20 and a second sub-test module 30. Figure 2 More first word lines 21, first active regions 22, first contact pillars 23 and first metal lines 24, each second sub-test module 30 includes more first word lines 21, first active regions 22, first contact pillars 23 and first metal lines 24. Figure 2More second word lines 31, second active areas 32, second contact pillars 33 and second metal lines 34 are provided to improve the detection rate of bit line abnormalities. In the first sub-test module, the number of first bit lines is n, the number of groups of first active areas arranged along the first direction D1 is n+1, and n is greater than or equal to 2; in the second sub-test module, the number of groups of second active areas arranged along the first direction D1 is m, the number of second bit lines is 2m-1, and m is greater than or equal to 2.

[0050] In such Figure 3a In the embodiment of FIG. 1 , the first sub-test module 20 includes three first word lines 21, twelve first active regions 22, twenty-four first contact pillars 23 and a first metal line 24. Figure 3b In the embodiment of FIG. 1 , the second sub-test module 30 includes three second word lines 31, twelve second active regions 32, twenty-four second contact pillars 33 and a second metal line 34. Figure 3a and Figure 3b In the test structure setting principle and Figure 2 The setting principle of the test structure shown is similar and will not be repeated here.

[0051] Preferably, the process parameters of the first active area 22, the second active area 32, the first contact pillar 23, the second contact pillar 33, the first metal line 24 and the second metal line 34 are as close as possible to the process parameters of the active area, the contact pillar and the metal line of the device area, so as to facilitate monitoring the abnormality of the bit line of the device area. The first metal line 24 and the second metal line 34 can be a first metal layer (M1), and an interlayer dielectric layer is filled between the first metal line 24 and the second metal line 34 and the substrate 10, and the material of the interlayer dielectric layer is, for example, silicon oxide. It should be noted that the first word line 21 and the second word line 31 can also be virtual word lines instead of actual word lines of the device area, for example, composed of an isolation structure of the device area.

[0052] Embodiment 2

[0053] Figure 4 It is a flow chart of the manufacturing method of the test structure provided in the second embodiment.

[0054] like Figure 4 As shown, the manufacturing method of the test structure provided in this embodiment uses the test structure to detect the bit line of the split-gate flash memory device in the WAT test, and the manufacturing method includes:

[0055] S01: providing a substrate;

[0056] S02: forming at least six first active regions and at least eight second active regions on the substrate, wherein the at least six first active regions extend along a first direction and are arranged into at least three groups along a second direction, and the at least eight second active regions extend along the second direction and are arranged into at least two groups along the second direction;

[0057] S03: forming at least two first word lines and at least three second word lines, wherein the first word lines and the second word lines both extend along the first direction and are arranged along the second direction, at least two of the first word lines are located on the substrate between at least three groups of the first active regions, one of the second word lines is located on each group of the second active regions, and the remaining second word lines are located on the substrate between two adjacent groups of the second active regions;

[0058] S04: forming a first contact column and a second contact column, wherein two first contact columns are disposed on each of the first active regions and the first contact columns are located on both sides of the first word line, and two second contact columns are disposed on each of the second active regions and the second contact columns are located on both sides of the second word line;

[0059] S05: forming a first metal line and a second metal line, connecting the first active area in series along the first direction as the main direction using the first metal line and the first contact column to form a first S-type test circuit, and connecting the second active area in series along the second direction as the main direction using the second metal line and the second contact column to form a second S-type test circuit;

[0060] S06: forming a first bit line test end and a second bit line test end, using the first end and the tail end of the first S-type test line as the first bit line test end, and using the first end and the tail end of the second S-type test line as the second bit line test end.

[0061] Figure 5a to Figure 5f The structural schematic diagram corresponding to the corresponding steps of the manufacturing method of the test structure provided in this embodiment is as follows. Figure 5a to Figure 5f The manufacturing method of the test structure provided in this embodiment is described in detail.

[0062] Please refer to Figure 5a , perform step S01, provide a substrate 10, the substrate having a device area and a test area.

[0063] Please refer to Figure 5b , perform step S02, and form six first active areas 22 and eight second active areas 32 on the test area of ​​the substrate 10, the first active areas 33 extend along the first direction D1 and are arranged in three rows along the second direction D2, and the second active areas 32 extend along the second direction D2 and are arranged in two rows along the second direction D2.

[0064] Please refer to Figure 5c, step S03 is performed to form two first word lines 21 and three second word lines 31, wherein the first word lines 21 are located on the substrate 10, the first word lines 21 extend along the first direction D1 and are arranged along the second direction D2, the second word lines 31 extend along the first direction D1 and are arranged along the second direction D2, some of the second word lines 31 are located on the second active regions 32, and the remaining second word lines 31 are located on the substrate 10 between two rows of second active regions 32. The first word lines 21 and the second word lines 31 may be virtual word lines, i.e., they do not form actual floating gate structures and control structures, but are only filled with isolation structures.

[0065] Please refer to Figure 5d , execute step S04 to form first contact pillars 23 and second contact pillars 33, two first contact pillars 23 are provided on each first active area 22 and the first contact pillars 23 are located on both sides of the first word line 21, and two second contact pillars 33 are provided on each second active area 32 and the second contact pillars 33 are located on both sides of the second word line 31.

[0066] Please refer to Figure 5e , execute step S05 to form a first metal line 24 and a second metal line 34, use the first metal line and the first contact column 23 to connect the first active area 22 in series along the first direction D1 as the main direction to form a first S-type test circuit, and use the second metal line 34 and the second contact column 33 to connect the second active area 32 in series along the second direction D2 as the main direction to form a second S-type test circuit.

[0067] Please refer to Figure 5f , execute step S06 to form a first bit line test terminal 25 and a second bit line test terminal 35, with the head end and tail end of the first S-type test line as the first bit line test terminal 25, and the head end and tail end of the second S-type test line as the second bit line test terminal 35.

[0068] It should be understood that since the test structure in the test area and the device unit in the device area are formed simultaneously under the same process conditions as far as possible, similar structures in the two can be made to have the same process parameters as far as possible through appropriate adjustments.

[0069] Embodiment 3

[0070] Embodiment 3 provides a testing method for a testing structure.

[0071] The test method of the test structure provided in this embodiment uses the test structure to detect the bit line of the memory device in the WAT test. The test method includes:

[0072] Providing a test structure as described above, the test structure comprising a first sub-test module having a first preset resistance range and a second sub-test module having a second preset resistance range;

[0073] Obtaining a first resistance test value of the first sub-test module, and comparing whether the first resistance test value is within the first preset resistance range, so as to determine whether a connection condition of the bit line along the first direction is normal;

[0074] A second resistance test value of the second sub-test module is obtained, and the second resistance test value is compared to see whether it is within the second preset resistance range, so as to determine whether the connection status of the bit line along the second direction is normal.

[0075] Specifically, the first preset resistance range can be set according to the relevant parameters of the first active area, the first contact column and the first metal line of the first sub-test module, and the first resistance test value can be obtained by performing a resistance test on the first bit line test end in the WAT test. If the first resistance test value is greater than the upper limit of the first preset resistance range, it is determined that the bit line has an open circuit (or contact abnormality) along the first direction, and if the first resistance test value is less than the lower limit of the first preset resistance range, it is determined that the bit line has a short circuit along the first direction. Similarly, the first preset resistance range and the second resistance test value of the second sub-test module can be obtained. If the second resistance test value is greater than the upper limit of the second preset resistance range, it is determined that the bit line has an open circuit (or contact abnormality) along the second direction, and if the second resistance test value is less than the lower limit of the second preset resistance range, it is determined that the bit line has a short circuit along the second direction.

[0076] In summary, the present invention sets a first sub-test module and a second sub-test module on a substrate, in the first sub-test module, the first active area extends along the first direction, and then the first metal line and the first contact column are used to electrically connect the first active area in series along the first direction, so as to simulate the connection condition of the bit line of the storage device along the first direction, in the second sub-test module, the second active area extends along the second direction, and then the second metal line and the second contact column are used to electrically connect the second active area in series along the second direction, so as to simulate the connection condition of the bit line of the storage device along the second direction, and then through the testing of the first sub-test module and the second sub-test module, direct monitoring of the connection condition of the bit line of the storage device along the first direction and the second direction is realized, thereby realizing rapid and effective monitoring of the bit line of the storage device.

[0077] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A test structure, using the test structure to detect the bit line of a memory device in a WAT ​​test, characterized in that: It includes a substrate and a first sub-test module and a second sub-test module arranged on the substrate; The first sub-test module includes at least two first word lines, at least six first active areas, a plurality of first contact pillars, and a plurality of first metal lines, wherein the first word lines are located on the substrate and extend along a first direction, the first active area is located on the substrate and extends along the first direction, at least six first active areas are arranged into at least three groups along a second direction, at least three groups of the first active areas and at least two first word lines are sequentially arranged at intervals along the second direction, two first contact pillars are arranged on each first active area, the first metal lines and the first contact pillars are used to connect the first active areas in series along the first direction as a main direction to form a first S-type test circuit, and the head end and tail end of the first S-type test circuit are used as the first bit line test end; The second sub-test module includes at least three second word lines, at least eight second active areas, a plurality of second contact pillars and a plurality of second metal lines. The second active areas are arranged on the substrate and extend along the second direction. At least eight second active areas are arranged into at least two groups along the second direction. The second word lines extend along the first direction and are arranged along the second direction. Each group of second active areas has one second word line. The remaining second word lines are located on the substrate between two adjacent groups of second active areas. The second contact pillars are located on the second active areas on both sides of the second word lines. The second active areas are connected in series along the second direction as the main direction using second metal lines and the second contact pillars to form a second S-type test circuit. The head and tail ends of the second S-type test circuit are used as second bit line test ends. The first direction is orthogonal to the second direction.

2. The test structure according to claim 1, characterized in that: The memory device is a split-gate flash memory device having a device area and a test area. The test structure is located in the test area. The first contact column and the second contact column are formed under the same process conditions as the contact column in the device area.

3. The test structure according to claim 2, characterized in that: The first active area, the first contact column and the first metal line are used to simulate the connection status of the bit line of the device area along the first direction, and the second active area, the second contact column and the second metal line are used to simulate the connection status of the bit line of the device area along the second direction.

4. The test structure according to claim 1, characterized in that: The first active area and the first contact pillars in the first sub-test module are evenly and symmetrically distributed on both sides of the first word line, and the second contact pillars in the second sub-test module are evenly and symmetrically distributed on both sides of the second word line.

5. The test structure according to any one of claims 1 to 4, characterized in that: In the first sub-test module, the number of the first bit lines is n, the number of groups of the first active regions arranged along the first direction is n+1, and n is greater than or equal to 2.

6. The test structure according to any one of claims 1 to 4, characterized in that: In the second sub-test module, the number of groups of the second active regions arranged along the first direction is m, the number of the second bit lines is 2m-1, and m is greater than or equal to 2.

7. A method for manufacturing a test structure, using the test structure to detect the bit line of a memory device in a WAT ​​test, characterized in that: The manufacturing method of the test structure comprises: providing a substrate; Forming at least six first active regions and at least eight second active regions on the substrate, wherein the at least six first active regions extend along a first direction and are arranged into at least three groups along a second direction, and the at least eight second active regions extend along the second direction and are arranged into at least two groups along the second direction; forming at least two first word lines and at least three second word lines, wherein the first word lines and the second word lines both extend along the first direction and are arranged along the second direction, at least two of the first word lines are located on the substrate between at least three groups of the first active regions, one of the second word lines is located on each group of the second active regions, and the remaining second word lines are located on the substrate between two adjacent groups of the second active regions; Forming first contact pillars and second contact pillars, wherein two first contact pillars are disposed on each of the first active regions and the first contact pillars are located on both sides of the first word line, and two second contact pillars are disposed on each of the second active regions and the second contact pillars are located on both sides of the second word line; Forming a first metal line and a second metal line, connecting the first active area in series along the first direction as the main direction by using the first metal line and the first contact column to form a first S-type test circuit, and connecting the second active area in series along the second direction as the main direction by using the second metal line and the second contact column to form a second S-type test circuit; A first bit line test end and a second bit line test end are formed, the first end and the tail end of the first S-type test line are used as the first bit line test end, and the first end and the tail end of the second S-type test line are used as the second bit line test end.

8. The method for manufacturing a test structure according to claim 7, characterized in that: The first word line and the second word line are both virtual word lines.

9. A method for testing a test structure, using the test structure to detect a bit line of a memory device in a WAT ​​test, characterized in that: The testing method of the test structure comprises: There is provided a test structure according to any one of claims 1 to 6, the test structure comprising a first sub-test module having a first preset resistance range and a second sub-test module having a second preset resistance range; Obtaining a first resistance test value of the first sub-test module, and comparing whether the first resistance test value is within the first preset resistance range, so as to determine whether a connection condition of the bit line along the first direction is normal; A second resistance test value of the second sub-test module is obtained, and the second resistance test value is compared to see whether it is within the second preset resistance range, so as to determine whether the connection status of the bit line along the second direction is normal.

10. The test method of the test structure according to claim 9, characterized in that: The first resistance test value is greater than the upper limit of the first preset resistance range to determine that the bit line has an open circuit along the first direction, and the first resistance test value is less than the lower limit of the first preset resistance range to determine that the bit line has a short circuit along the first direction; The second resistance test value is greater than the upper limit of the second preset resistance range to determine that the bit line has an open circuit along the second direction, and the second resistance test value is less than the lower limit of the second preset resistance range to determine that the bit line has a short circuit along the second direction.

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