Real random number generator and real random number generation method

Abstract

This invention provides a true random number generator and a method for generating a true random number, used to generate a random variable. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal based on a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal based on the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal based on the clock signal to generate a third sampled signal. An arithmetic circuit generates a random variable based on the first, second, and third sampled signals and adjusts a count value. The arithmetic circuit adjusts the clock signal based on the count value. This invention enables random number generation with rules that are difficult to predict, improving the security of internal computer data.

Description

Technical Field

[0001] This invention relates to a random number generator, and more particularly to a true random number generator and a method for generating true random numbers. Background Technology

[0002] With the development of electronic devices, random numbers have been applied in fields such as computer security, especially in computer security. However, when the rules governing the generation of random numbers can be predicted, it can compromise the security of data within the computer. Summary of the Invention

[0003] An embodiment of the present invention provides a true random number generator for generating a random variable, and includes a first delay circuit, a second delay circuit, a first sampling circuit, a second sampling circuit, a third sampling circuit, and an arithmetic circuit. The first delay circuit delays an input signal to generate a first delayed signal. The second delay circuit delays the first delayed signal to generate a second delayed signal. The first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. The second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. The third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. The arithmetic circuit generates a random variable and adjusts a count value based on the first, second, and third sampled signals. The arithmetic circuit adjusts the clock signal based on the count value.

[0004] The present invention further provides a method for generating a true random number, for generating a random variable, comprising: delaying an input signal to generate a first delayed signal; delaying the first delayed signal to generate a second delayed signal; sampling the input signal according to a clock signal to generate a first sampled signal; sampling the first delayed signal according to the clock signal to generate a second sampled signal; sampling the second delayed signal according to the clock signal to generate a third sampled signal; generating a random variable according to the first sampled signal, the second sampled signal, and the third sampled signal, and adjusting a count value; and adjusting the clock signal according to the count value.

[0005] The true random number generation method of the present invention can be implemented by the true random number generator of the present invention, which is hardware or firmware capable of performing specific functions, or it can be implemented by including program code in a recording medium and combining it with specific hardware. When the program code is loaded and executed by an electronic device, processor, computer or machine, the electronic device, processor, computer or machine becomes the true random number generator used to implement the present invention. Attached Figure Description

[0006] Figure 1This is a schematic diagram of the real random number generator of the present invention;

[0007] Figure 2 This is a possible schematic diagram of the operational circuit of the present invention;

[0008] Figure 3 This is a schematic diagram of the sampling signal of the present invention;

[0009] Figure 4 This is a flowchart illustrating the true random number generation method of the present invention.

[0010] Icon labels:

[0011] 100: Real random number generator;

[0012] 110, 200: Operational circuits;

[0013] 120: Clock generation circuit;

[0014] RN: Random variable;

[0015] D1~DN, D1, D2: Delay circuit;

[0016] S1~SN, S1, S2, S3, S4: Sampling circuit;

[0017] X0: Input signal;

[0018] DS1~DS(N-1), DS1, DS2, DS3: Delayed signals;

[0019] X1~X N X1, X2, X3, X4, X1~X4: Sampling signals;

[0020] CT: Count value;

[0021] CLK: Clock signal;

[0022] AD1, AD2: Adjustment signals;

[0023] 210: Mutual exclusion or gate;

[0024] 220: Counter;

[0025] 230: Processor;

[0026] 300: a point in time;

[0027] S411, S412, S413, S414, S415, S416, S417: Steps. Detailed Implementation

[0028] To make the objectives, features, and advantages of this invention more apparent and understandable, embodiments are provided below, along with detailed descriptions in conjunction with the accompanying drawings. This specification provides different embodiments to illustrate the technical features of different implementations of the invention. The configuration of the elements in the embodiments is for illustrative purposes only and is not intended to limit the invention. Furthermore, the repetition of some reference numerals in the embodiments is for simplification and does not imply any correlation between different embodiments.

[0029] Figure 1 This is a schematic diagram of the real random number generator of the present invention. The real random number generator 100 is used to generate a random variable RN and includes delay circuits D1 to DN, sampling circuits S1 to SN, and an arithmetic circuit 110. Delay circuits D1 to DN are connected in series. Since delay circuits D1 to DN have the same characteristics, only delay circuits D1 and D2 will be described below. In this embodiment, delay circuit D1 delays an input signal X0 to generate a delayed signal DS1. Delay circuit D2 delays the delayed signal DS1 to generate a delayed signal DS2. In a possible embodiment, the input signal X0 is random data.

[0030] Sampling circuits S1 to S1 SN sample delayed signals DS1 to DS(N-1). Since sampling circuits S1 to S1 SN have the same characteristics, only sampling circuits S1, S2, and S3 will be described below. Sampling circuit S1 samples the input signal X0 based on a clock signal CLK to generate a sample signal X1. Sampling circuit S2 samples the delayed signal DS1 based on the clock signal CLK to generate a sample signal X2. Sampling circuit S3 samples the delayed signal DS2 based on the clock signal CLK to generate a sample signal X3. This invention does not limit the types of sampling circuits S1 to S1 SN. In one possible embodiment, sampling circuits S1 to S1 SN are flip-flops (such as D-type flip-flops), latches, or registers.

[0031] The operational circuit 110 operates based on the sampled signals X1 to X... N The random variable RN is generated and a count value CT is adjusted. In one possible embodiment, the arithmetic circuit 110 has a metastable state detection circuit (not shown). The metastable state detection circuit determines the stability of the sampled signals X1 to X2. N The level of the sampled signal X4 is used to determine whether a metastable state has occurred. Taking sampling circuit S4 as an example, when metastability does not occur, the level of the sampled signal X4 is the same as the level of the delayed signal DS3. However, when metastability occurs, the level of the sampled signal X4 is not equal to the level of the delayed signal DS3. In this case, the level of the sampled signal X4 is unpredictable and may be either high or low.

[0032] In one possible embodiment, when a metastability occurs, the arithmetic circuit 110 adjusts the count value CT. In this example, when the number of metastability occurrences is too low, the arithmetic circuit 110 adjusts (e.g., increases) the frequency of the clock signal CLK to increase the number of metastability occurrences. In another possible embodiment, when the number of metastability occurrences is too high, the arithmetic circuit 110 adjusts (e.g., decreases) the frequency of the clock signal CLK to reduce the number of metastability occurrences.

[0033] In other embodiments, the arithmetic circuit 110 calculates based on the sampled signals X1 to X2. N The level of the sampling signal determines whether the count value CT is adjusted. For example, when the sampling signal X1~X... N One of the levels is different from the sampled signals X1 to X2. N When the other level is reached, the operation circuit 110 adjusts the count value CT. When the sampling signal X1~X N When the levels are the same, the operation circuit 110 does not adjust the count value CT.

[0034] In some embodiments, the arithmetic circuit 110 determines the time it takes for the count value CT to reach a preset value. When the time it takes for the count value CT to reach the preset value is greater than a first preset time (e.g., 5 seconds), it indicates that the number of metastability events is too low. Therefore, the arithmetic circuit 110 increases the frequency of the clock signal CLK. However, when the time it takes for the count value CT to reach the preset value is less than a second preset time (e.g., 1 second), it indicates that the number of metastability events is too high. Therefore, the arithmetic circuit 110 decreases the frequency of the clock signal CLK.

[0035] In other embodiments, when the arithmetic circuit 110 receives the sampled signals X1 to X2... N Then, the arithmetic circuit 110 enables a timer (not shown). When the timer performs a timing operation for a third preset time (e.g., 10 seconds), the timer may issue an interrupt signal (not shown). In this example, after receiving the interrupt signal, the arithmetic circuit 110 determines whether the count value CT is equal to a preset value. When the count value CT is not equal to the preset value, the arithmetic circuit 110 increases the frequency of the clock signal CLK.

[0036] This invention does not limit how the arithmetic circuit 110 adjusts the clock signal CLK. In one possible embodiment, the arithmetic circuit 110 generates an adjustment signal AD1 in a clock generation circuit 120 based on the count value CT. The clock generation circuit 120 adjusts the frequency of the clock signal CLK based on the adjustment signal AD1. In some embodiments, the clock generation circuit 120 is a high-frequency oscillator. In this embodiment, the clock generation circuit 120 is integrated into the real random number generator 100. In other embodiments, the clock generation circuit 120 may be independent of the real random number generator 100 or integrated into the arithmetic circuit 110.

[0037] In some embodiments, the arithmetic circuit 110 adjusts the delay time of delay circuits D1 to DN based on a count value CT. In this example, the arithmetic circuit 110 generates an adjustment signal AD2 based on the count value CT. Delay circuits D1 to DN set a delay time based on different adjustment signals AD2, and then delay the input signal X0 and delay signals DS1 to DS(N-1) based on this delay time. In some embodiments, when the number of metastable events is too low, the arithmetic circuit 110 may increase the delay time of delay circuits D1 to DN by adjusting signal AD2. When the number of metastable events is too high, the arithmetic circuit 110 may decrease the delay time of delay circuits D1 to DN by adjusting signal AD2. In this embodiment, the arithmetic circuit 110 provides adjustment signal AD2 to delay circuits D1 to DN, but this is not intended to limit the invention. In other embodiments, the arithmetic circuit 110 may provide adjustment signal AD2 to some of the delay circuits. In some embodiments, the arithmetic circuit 110 may provide different adjustment signals to different delay circuits. Therefore, the delay time of one of the delay circuits D1 to DN is different from the delay time of the other of the delay circuits D1 to DN.

[0038] In other embodiments, when the arithmetic circuit 110 receives the sampled signals X1 to X2... N Subsequently, the arithmetic circuit 110 enables a timer (not shown). When the timer performs a timing operation for a third preset time, the timer may issue an interrupt signal (not shown). In this example, after receiving the interrupt signal, the arithmetic circuit 110 determines whether the count value CT is equal to a preset value. When the count value CT is not equal to the preset value, the arithmetic circuit 110 increases the delay time of the delay circuits D1 to DN.

[0039] This invention does not limit the order in which the arithmetic circuit 110 generates adjustment signals AD1 and AD2. In one possible embodiment, when the number of metastable phenomena occurring is too low, the arithmetic circuit 110 generates only adjustment signal AD1 and not adjustment signal AD2. In this example, when the frequency of the clock signal CLK reaches a maximum frequency, if the number of metastable phenomena occurring is still too low, the arithmetic circuit 110 generates adjustment signal AD2. In another possible embodiment, when the number of metastable phenomena occurring is too low, the arithmetic circuit 110 generates only adjustment signal AD2 and not adjustment signal AD1. In this example, when the delay time of the delay circuits D1 to DN reaches a maximum value, if the number of metastable phenomena occurring is still too low, the arithmetic circuit 110 begins to generate adjustment signal AD1.

[0040] Since the timing of metastability is unpredictable, and the level of the erroneous sampled signal caused by metastability is also unpredictable, the operational circuit 110, based on the sampled signals X1 to X... N When a random variable RN is generated, then the random variable RN becomes unpredictable. Therefore, the safety of the random variable RN is significantly improved. For example, when metastability does not occur, the sampled signals X1 to X... N All are at the correct level. However, when metastability occurs, the sampled signals X1 to X... N At least one of them is at an incorrect level. Since the incorrect level is unpredictable and may be high or low, if the operation circuit 110 uses a sampled signal with an incorrect level as a random variable RN, the predictability of the random variable RN can be greatly reduced.

[0041] Figure 2 This is a possible schematic diagram of the operational circuit of the present invention. For example... Figure 2 As shown, the operational circuit 200 includes a mutex gate (XOR) 210, a counter 220, and a processor 230. The mutex gate 210 receives sampled signals X1 to X2. N When the sampling signal X1~X N The level of one is different from that of the sampled signals X1 to X2. N At the other time, the mutex gate 210 outputs a first level. When the sampling signal X1~X N When the levels are the same, the mutex gate 210 outputs a second level. The second level is relative to the first level. In one possible embodiment, the first level is a high level and the second level is a low level.

[0042] Counter 220 is coupled to mutex gate 210 and adjusts the count value CT according to the output of mutex gate 210. In one possible embodiment, when mutex gate 210 outputs a first level, counter 220 adjusts (increases or decreases) the count value CT. When mutex gate 210 outputs a second level, counter 220 does not adjust the count value CT. In this embodiment, the count value CT is related to the number of times metastability occurs.

[0043] Processor 230 is coupled to mutex gate 210 and counter 220. In one possible embodiment, processor 230 generates a random variable RN based on the output of mutex gate 210. In this example, processor 230 directly uses the output of mutex gate 210 as the random variable RN. In another possible embodiment, processor 230 receives sampled signals X1 to X2. N The sampled signal with an error level is used as a random variable RN. In other embodiments, processor 230 is coupled to counter 220 to read the count value CT. In this example, processor 230 generates at least one adjustment signal AD1 and adjustment signal AD2 based on the count value CT.

[0044] Figure 3 This is a schematic diagram of the sampling signals X1 to X4 of the present invention. For ease of explanation, Figure 3 Only sampled signals X1 to X4 are displayed. At time 300, the clock signal CLK triggers sampling circuits S1, S2, S3, and S4. Therefore, sampling circuits S1, S2, S3, and S4 generate sampled signals X1 to X4. In this example, because the setup and hold times of sampling circuit S4 are not suitable, at time 300, the level of sampled signal X4 has not yet been stably maintained at a target value.

[0045] Figure 4 This invention provides a method for generating true random numbers. First, an input signal is received and delayed to generate a first delayed signal (step S411). In one possible embodiment, step S411 uses a first delay circuit. In this example, the first delay circuit delays the input signal according to a first delay time. In some embodiments, the input signal is random number data.

[0046] Next, the first delayed signal is delayed to generate a second delayed signal (step S412). In one possible embodiment, step S412 uses a second delay circuit. In this example, the second delay circuit delays the first delayed signal according to a second delay time. In this example, the second delay circuit is connected in series with the first delay circuit. The first delay time may be the same as or different from the second delay time.

[0047] Based on a clock signal, the input signal is sampled to generate a first sampled signal (step S413). In one possible embodiment, step S413 uses a first sampling circuit to sample the input signal. In some embodiments, the first sampling circuit may be a flip-flop, a latch, or a temporary register.

[0048] Based on the clock signal, a first delayed signal is sampled to generate a second sampled signal (step S414). In one possible embodiment, step S414 uses a second sampling circuit to sample the first delayed signal. In some embodiments, the second sampling circuit may be a trigger, a latch, or a temporary register.

[0049] Based on the clock signal, a second delayed signal is sampled to generate a third sampled signal (step S415). In one possible embodiment, step S415 uses a third sampling circuit to sample the second delayed signal. In some embodiments, the third sampling circuit may be a flip-flop, a latch, or a temporary register.

[0050] Based on the first, second, and third sampled signals, a random variable is generated and a count value is adjusted (step S416). In one possible embodiment, step S416 may perform a mutually exclusive OR operation on the first, second, and third sampled signals and use the result as a random variable. In another possible embodiment, step S416 may detect the levels of the first, second, and third sampled signals. Assume that the level of the first sampled signal is different from the levels of the second and third sampled signals. In this example, step S416 uses the first sampled signal as a random variable.

[0051] In other embodiments, step S416 determines whether a metastable state has occurred based on the first sampled signal, the second sampled signal, and the third sampled signal. When a metastable state occurs, step S416 adjusts a count value. However, when no metastable state occurs, step S416 does not adjust the count value. In some embodiments, when the level of one of the first, second, and third sampled signals is different from the other of the first, second, and third sampled signals, step S416 adjusts the count value. However, when the first, second, and third sampled signals have the same level, step S416 stops adjusting the count value.

[0052] Based on the count value, adjust the clock signal (step S417). In one possible embodiment, step S417 first detects the time it takes for the count value to reach a preset value. When the time it takes for the count value to reach the preset value is greater than a first preset time, step S417 increases the frequency of the clock signal. Conversely, when the time it takes for the count value to reach the preset value is less than a second preset time, step S417 decreases the frequency of the clock signal.

[0053] In other embodiments, step S417 determines whether the count value is equal to a preset value after a third preset time. When the count value is not equal to the preset value, step S417 increases the frequency of the clock signal. In some embodiments, step S417 adjusts a delay time between the first delay signal and the second delay signal. In this example, step S417 adjusts at least one of the first delay time and the second delay time.

[0054] The real random number generation method, or a specific form or part thereof, of the present invention can exist in the form of program code. The program code can be stored on physical media, such as floppy disks, optical discs, hard disks, or any other machine-readable (e.g., computer-readable) storage media, or not limited to external computer program products. When the program code is loaded and executed by a machine, such as a computer, this machine becomes a real random number generator for the present invention. The program code can also be transmitted via some transmission medium, such as wires or cables, optical fibers, or any transmission method. When the program code is received, loaded, and executed by a machine, such as a computer, this machine becomes a real random number generator for the present invention. When implemented in a general-purpose processing unit, the program code, in conjunction with the processing unit, provides a unique device that operates similarly to application-specific logic circuitry.

[0055] Unless otherwise defined, all terms herein (including technical and scientific terms) are as commonly understood by those skilled in the art. Furthermore, unless expressly stated otherwise, definitions of terms in general dictionaries should be interpreted as consistent with their meaning in the context of their respective technical fields, and not as idealized states or overly formal expressions. While terms such as "first," "second," etc., may be used to describe various components and preset values, these components and preset values ​​should not be limited by these terms. These terms are merely used to distinguish one component from another or one preset value from another.

[0056] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make modifications and refinements without departing from the spirit and scope of the invention. For example, the systems, apparatus, or methods described in the embodiments of the present invention can be implemented in physical embodiments of hardware, software, or a combination of hardware and software. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A true random number generator, characterized in that, Used to generate a random variable, and includes: A first delay circuit delays an input signal to generate a first delayed signal; A second delay circuit delays the first delay signal to generate a second delay signal; A first sampling circuit samples the input signal based on a clock signal to generate a first sampling signal; A second sampling circuit samples the first delayed signal based on the clock signal to generate a second sampling signal; A third sampling circuit, based on the clock signal, samples the second delayed signal to generate a third sampled signal; and An arithmetic circuit generates the random variable based on the first sampled signal, the second sampled signal, and the third sampled signal, and adjusts a count value. The arithmetic circuit determines the time it takes for the count value to reach a preset value. When the time it takes for the count value to reach the preset value is greater than a first preset time, the arithmetic circuit increases the frequency of the clock signal.

2. The true random number generator as described in claim 1, characterized in that, The arithmetic circuit adjusts the delay time of at least one of the first delay circuit and the second delay circuit according to the count value.

3. The true random number generator as described in claim 1, characterized in that, The arithmetic circuit determines whether a metastable phenomenon has occurred based on the first sampled signal, the second sampled signal, and the third sampled signal. When the metastable phenomenon occurs, the arithmetic circuit adjusts the count value.

4. The true random number generator as described in claim 1, characterized in that, When the level of one of the first sampling signal, the second sampling signal, and the third sampling signal is different from the other of the first sampling signal, the second sampling signal, and the third sampling signal, the arithmetic circuit adjusts the count value.

5. The true random number generator as described in claim 4, characterized in that, When the first sampling signal, the second sampling signal, and the third sampling signal have the same level, the arithmetic circuit does not adjust the count value.

6. The true random number generator as described in claim 5, characterized in that, The operational circuit includes: A mutex gate that receives the first sampled signal, the second sampled signal, and the third sampled signal. When the level of one of the first, second, and third sampling signals is different from the other of the first, second, and third sampling signals, the mutex or gate outputs a first level; when the first, second, and third sampling signals have the same level, the mutex or gate outputs a second level, which is relative to the first level.

7. The true random number generator as described in claim 6, characterized in that, The operational circuit further includes: A counter, coupled to the mutex or gate, When the mutex or gate outputs the first level, the counter adjusts the count value; when the mutex or gate outputs the second level, the counter does not adjust the count value.

8. The true random number generator as described in claim 1, characterized in that, When the time it takes for the count value to reach the preset value is less than a second preset time, the arithmetic circuit reduces the frequency of the clock signal.

9. The true random number generator as described in claim 1, characterized in that, After a third preset time, the arithmetic circuit determines whether the count value is equal to a preset value. If the count value is not equal to the preset value, the arithmetic circuit increases the frequency of the clock signal.

10. The true random number generator as described in claim 1, characterized in that, The input signal is a random number.

11. A method for generating true random numbers, characterized in that, Used to generate a random variable, and includes: An input signal is delayed to generate a first delayed signal; The first delayed signal is delayed in order to generate a second delayed signal; Based on a clock signal, the input signal is sampled to generate a first sampled signal; Based on the clock signal, the first delayed signal is sampled to generate a second sampled signal; Based on the clock signal, the second delayed signal is sampled to generate a third sampled signal; Based on the first sampled signal, the second sampled signal, and the third sampled signal, the random variable is generated, and a count value is adjusted; and Adjust the frequency of the clock signal based on the count value; The steps for adjusting the frequency of the clock signal based on the count value include: Determine the time it takes for the count value to reach a preset value; and When the time it takes for the count value to reach the preset value is greater than a first preset time, the frequency of the clock signal is increased.

12. The method for generating true random numbers as described in claim 11, characterized in that, Including: Based on the count value, the delay time between the first delay signal and the second delay signal is adjusted.

13. The method for generating true random numbers as described in claim 11, characterized in that, Including: Based on the first sampling signal, the second sampling signal, and the third sampling signal, determine whether a metastable phenomenon has occurred; When this metastable phenomenon occurs, adjust the count value; and Stop adjusting the count value when the metastable phenomenon does not occur.

14. The method for generating true random numbers as described in claim 11, characterized in that, The step of adjusting the count value based on the first sampling signal, the second sampling signal, and the third sampling signal includes: Detect the levels of the first sampled signal, the second sampled signal, and the third sampled signal; and When the level of one of the first, second, and third sampling signals is different from the other of the first, second, and third sampling signals, the count value is adjusted.

15. The method for generating true random numbers as described in claim 14, characterized in that, The step of adjusting the count value based on the first sampling signal, the second sampling signal, and the third sampling signal further includes: When the first sampling signal, the second sampling signal, and the third sampling signal have the same level, the adjustment of the count value stops.

16. The method for generating true random numbers as described in claim 11, characterized in that, The steps for adjusting the clock signal based on the count value further include: When the time it takes for the count value to reach the preset value is less than a second preset time, the frequency of the clock signal is reduced.

17. The method for generating true random numbers as described in claim 11, characterized in that, Including: After a third preset time, determine whether the count value is equal to a preset value; and When the count value is not equal to the preset value, the frequency of the clock signal is increased.

18. The method for generating true random numbers as described in claim 11, characterized in that, The input signal is a random number.

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