Data transmission circuit, method and storage device

Abstract

The present application relates to a data transmission circuit, method and storage device, wherein the data transmission circuit includes a controllable delay module and a mode register data processing unit, wherein the controllable delay module is used to generate a delayed read command in response to a mode register read command; the mode register data processing unit is used to read out a setting parameter from a mode register in response to the mode register read command, and is also used to output the setting parameter in response to the delayed read command; wherein the time difference between the output start time of the setting parameter and the time when the controllable delay module receives the mode register read command is a first preset threshold. The present application can control the time of reading out the setting parameter in response to the mode register read command, and match it with the time of reading out the array area data in response to the array area data read command, and can meet the working parameter requirements of different types of semiconductor storage devices, and avoid control errors in the data transmission path caused by the influence of the working environment.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a data transmission circuit, method and storage device. Background Art

[0002] A semiconductor memory device generally includes a memory array area and a peripheral circuit area, wherein the memory array area is provided with a memory cell array including a plurality of memory cells. The peripheral circuit area is provided with a control circuit for controlling reading and writing and a mode register for storing setting parameters. The setting parameters stored in the mode register can be read out by issuing a mode register read command. If a transmission path for reading out the setting parameters in response to the mode register read command can be set, and a data transmission channel is shared with a transmission path for reading out the array area data in response to the array area data read command, the data can be accurately output through the data terminal of the semiconductor memory device, which can effectively reduce the area occupied by the data transmission circuit.

[0003] However, different types of semiconductor memory devices respond to array area data read commands at different times to read array area data, and the working circuits of different types of semiconductor memory devices are affected by working parameters to different degrees, resulting in the control time of responding to mode register read commands to read out setting parameters and the time of responding to array area data read commands to read out array area data being extremely complicated to match, making it difficult to simultaneously meet the working parameter requirements of different types of semiconductor memory devices, and easily causing control errors in the data transmission path of the semiconductor memory device, resulting in mode register operation errors, which seriously affects the accuracy of data transmission and the working efficiency of the semiconductor memory device. Summary of the invention

[0004] Based on this, it is necessary to provide a data transmission circuit, method and storage device to address the technical problems in the above-mentioned background technology, which can control the time of reading out the setting parameters in response to the mode register read command, match the time of reading out the array area data in response to the array area data read command, and meet the working parameter requirements of different types of semiconductor storage devices, avoiding control errors in the data transmission path due to the influence of the working environment.

[0005] In order to achieve the above-mentioned purpose and other purposes, one aspect of the present application provides a data transmission circuit, including a controllable delay module and a mode register data processing unit, the controllable delay module is used to generate a delayed read command in response to a mode register read command; the mode register data processing unit is connected to the controllable delay module, and is used to read out setting parameters from a mode register in response to the mode register read command, and is also used to output the setting parameters in response to the delayed read command; wherein the time difference between the output start time of the setting parameters and the time when the controllable delay module receives the mode register read command is a first preset threshold.

[0006] In the data transmission circuit in the above embodiment, a controllable delay module is set to respond to a mode register read command to generate a delayed read command, so that the mode register data processing unit responds to the mode register read command to read the setting parameters from the mode register, and outputs the setting parameters in response to the delayed read command; since the time difference between the output start time of the setting parameters and the time when the controllable delay module receives the mode register read command is a first preset threshold, the time for reading the setting parameters in response to the mode register read command matches the time for reading the array area data in response to the array area data read command. Once the operation delay of the controllable delay module in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

[0007] In one embodiment, the controllable delay module includes a reference delay unit and an adjustable delay unit, the reference delay unit is used to generate an initial delay read command in response to the mode register read command; the adjustable delay unit is connected to the output end of the reference delay unit and the input end of the mode register data processing unit, and is used to generate the delay read command after delaying the preset delay time from the moment of receiving the initial delay read command; wherein the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold. By setting the operation delay of the adjustable delay unit to the preset delay time, and setting the sum of the operation delay of the reference delay unit and the preset delay time to be equal to the first preset threshold, the operation delay range of the adjustable delay unit is reduced, so as to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module to the first preset threshold.

[0008] In one embodiment, the adjustable delay unit includes at least two first delay units connected in series; at least one of the first delay units is connected in parallel with a first controllable switch unit; wherein, by controlling the on and off of each of the first controllable switch units, the number of first delay units in the adjustable delay unit connected in series between the reference delay unit and the mode register data processing unit is changed to adjust the operation delay of the adjustable delay unit, thereby achieving gradient control of the operation delay of the adjustable delay unit, so as to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module to a first preset threshold.

[0009] In one embodiment, the mode register data processing unit also includes a first-in-first-out pointer processing unit and a first-in-first-out data processing unit. The first-in-first-out pointer processing unit is connected to the output end of the controllable delay module, and is used to generate a first pointer signal in response to the mode register read command, and is also used to generate a second pointer signal in response to the delay read command; the first-in-first-out data processing unit is connected to both the first-in-first-out pointer processing unit and the mode register, and is used to read the setting parameters from the mode register in response to the first pointer signal, and is also used to output the setting parameters in response to the second pointer signal. The mode register data processing unit is set to include a first-in-first-out pointer processing unit and a first-in-first-out data processing unit, wherein the first-in-first-out pointer processing unit generates a first pointer signal for driving the first-in-first-out data processing unit to read out the setting parameters from the mode register according to the mode register read command, and generates a second pointer signal for driving the first-in-first-out data processing unit to output the setting parameters according to the delayed read command, thereby realizing control of the time for reading out the setting parameters from the mode register in response to the mode register read command, thereby being able to control the time for reading out the setting parameters in response to the mode register read command to match the time for reading out the array area data in response to the array area data read command.

[0010] In one embodiment, the driving clock frequencies of the first pointer signal and the second pointer signal are the same, so as to achieve precise control of the time difference between reading data and outputting data by the first-in-first-out data processing unit.

[0011] In one embodiment, the first-in-first-out data processing unit includes a storage unit, and the output ends of multiple storage units are connected to the same node; the storage unit includes a storage subunit and a driver, and the input end of the driver is connected to the output end of the storage subunit, the storage subunit receives the setting parameters under the drive of the first pointer signal, and the driver outputs the setting parameters under the drive of the second pointer signal, so that the first-in-first-out data processing unit cooperates with the first-in-first-out pointer processing unit to achieve precise control of the time for reading out the setting parameters from the mode register in response to the mode register read command, thereby being able to precisely control the time for reading out the setting parameters in response to the mode register read command, and matching the time for reading out the array area data in response to the array area data read command.

[0012] In one embodiment, the data input terminal of each storage sub-unit is connected to a mode register, so that each storage sub-unit reads out a setting parameter from the mode register in response to the first pointer signal.

[0013] In one embodiment, the data transmission circuit further includes a command decoding circuit and an array area data processing unit, the first output end of the command decoding circuit is connected to the input end of the controllable delay module and the input end of the mode register data processing unit, the command decoding circuit is used to receive a read command, decode the read command and determine whether the read command is the mode register read command, if so, output the mode register read command, otherwise, generate an array area data read command; the input end of the array area data processing unit is connected to the second output end of the command decoding circuit and the storage cell array, and is used to respond to the array area data read command to read out the array area data from the storage cell array. This embodiment realizes reading out the setting parameters and array area data via the data transmission circuit. Compared with using different data transmission circuits to read out the setting parameters and array area data, this embodiment can effectively reduce the area occupied by the data transmission circuit, so as to further improve the integration of the semiconductor storage device.

[0014] In one embodiment, the difference between the operation delay of the array area data processing unit and the first preset threshold is a second preset threshold to meet the working parameter requirements of a specific type of semiconductor storage device such as dynamic random access memory (DRAM).

[0015] In one embodiment, the second preset threshold is an integer multiple of a column refresh period to meet the operating parameter requirements of a specific type of semiconductor memory device such as LPDDR4.

[0016] In one embodiment, the data transmission circuit further includes a first selector and a first-in first-out memory, wherein the first selector is connected to the output end of the array area data processing unit and the output end of the mode register data processing unit; the first-in first-out memory is connected to the output end of the first selector and is used to store the setting parameters or the array area data. This embodiment implements a transmission path for reading out the setting parameters in response to a mode register read command, and shares a data transmission channel with a transmission path for reading out the array area data in response to an array area data read command, thereby realizing the reading out of the setting parameters and the array area data through the data transmission circuit provided by the present application, which can effectively reduce the area occupied by the data transmission circuit.

[0017] In one embodiment, the data transmission circuit also includes a parallel-serial conversion circuit and a data driving module, the parallel-serial conversion circuit is connected to the output end of the first-in-first-out memory; the data driving module is connected to the output end of the parallel-serial conversion circuit, and is used to output the setting parameters or the array area data to improve the efficiency of data transmission.

[0018] Another aspect of the present application provides a storage device, including a storage cell array, a mode register, and a data transmission circuit as described in any one of the embodiments of the present application.

[0019] In the storage device in the above-mentioned embodiment, since the data transmission circuit as described in any of the embodiments of the present application is used to transmit the array area data and setting parameters, it is convenient to control the time of reading the setting parameters in response to the mode register read command, and match the time of reading the array area data in response to the array area data read command. Once the operation delay of the controllable delay module in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

[0020] Another aspect of the present application provides a data transmission method, comprising:

[0021] Control the controllable delay module to respond to the mode register read command and generate a delay read command;

[0022] In response to the mode register read command, the mode register data processing unit reads out the setting parameters from the mode register; and

[0023] In response to the delayed read command, the setting parameter is output based on the mode register data processing unit, wherein the time difference between the output start time of the setting parameter and the time when the controllable delay module receives the mode register read command is a first preset threshold.

[0024] In the data transmission method in the above embodiment, a delayed read command is generated based on a controllable delay module responding to a mode register read command, so that the mode register data processing unit responds to the mode register read command to read out the setting parameters from the mode register, and outputs the setting parameters in response to the delayed read command; since the time difference between the output start time of the setting parameters and the time when the controllable delay module receives the mode register read command is a first preset threshold, the time for reading out the setting parameters in response to the mode register read command matches the time for reading out the array area data in response to the array area data read command. Once the operation delay of the controllable delay module in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

[0025] In one embodiment, the controlling the controllable delay module to respond to the mode register read command and generate a delay read command comprises:

[0026] Controlling the reference delay unit to generate an initial delay read command in response to the mode register read command;

[0027] The adjustable delay unit is controlled to generate the delayed read command after delaying for a preset delay time from the moment of receiving the initial delayed read command, so that the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold.

[0028] In the data transmission method in the above embodiment, the reference delay unit is controlled to generate an initial delay read command in response to the mode register read command, so that the adjustable delay unit generates the delay read command after delaying the preset delay time from the moment of receiving the initial delay read command, so that the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold. This embodiment can narrow the operation delay range of the adjustable delay unit and improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module to the first preset threshold.

[0029] In one embodiment, the controlling the controllable delay module to respond to the mode register read command and before generating the delay read command, further comprises:

[0030] Receive a read command;

[0031] Decoding the read command and determining whether the read command is the mode register read command;

[0032] If yes, output the mode register read command;

[0033] Otherwise, an array area data read command is generated;

[0034] In response to the array area data read command, array area data is read out from the memory cell array.

[0035] In the data transmission method in the above embodiment, the received read command is decoded and it is determined whether the read command is the mode register read command; if so, the mode register read command is output; otherwise, an array area data read command is generated; the array area data is read from the storage cell array in response to the array area data read command, the setting parameters are read from the mode register based on the mode register data processing unit in response to the mode register read command, and the setting parameters are output based on the mode register data processing unit in response to the delay read command, wherein the time difference between the output start time of the setting parameters and the time when the controllable delay module receives the mode register read command is the first preset threshold. This embodiment can control the setting parameters in the mode register and the array area data to be read out via the same data output path, thereby improving the data transmission efficiency and effectively reducing the area occupied by the data output path, so as to further improve the integration of the semiconductor storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 This is a structural block diagram of a data transmission circuit provided in the first embodiment of the present application;

[0038] Figure 2 This is a structural block diagram of a data transmission circuit provided in the second embodiment of the present application;

[0039] Figure 3 This is a structural block diagram of a data transmission circuit provided in the third embodiment of the present application;

[0040] Figure 4 This is a structural block diagram of a data transmission circuit provided in the fourth embodiment of the present application;

[0041] Figure 5 A structural block diagram of a first-in-first-out data processing unit in a data transmission circuit provided in one embodiment of the present application;

[0042] Figure 6 A structural block diagram of a first-in-first-out data processing unit in a data transmission circuit provided in another embodiment of the present application;

[0043] Figure 7 This is a structural block diagram of a data transmission circuit provided in the fifth embodiment of the present application;

[0044] Figure 8a A schematic diagram of a timing sequence of a data transmission circuit responding to a read command provided in an embodiment of the present application;

[0045] Figure 8b for Figure 7 The working timing diagram of the data transmission circuit shown;

[0046] Fig. 9 This is a structural block diagram of a data transmission circuit provided in the sixth embodiment of the present application;

[0047] Fig.10a This is a structural block diagram of a data transmission circuit provided in the seventh embodiment of the present application;

[0048] Fig.10b for Fig.10a A schematic diagram of an implementation method;

[0049] Fig.11a A block diagram of a delay circuit for responding to a mode register read command;

[0050] Fig.11b for Fig.11a Working timing diagram;

[0051] Fig.12 A structural block diagram of a storage device provided in an embodiment of the present application;

[0052] Fig.13 A flowchart of a data transmission method provided in an embodiment of the present application;

[0053] Fig.14 A schematic diagram of a data transmission method according to another embodiment of the present application;

[0054] Fig.15 A flowchart of a data transmission method provided in another embodiment of the present application is shown.

[0055] Description of reference numerals:

[0056] 100, data transmission circuit; 10, controllable delay module; 20, mode register data processing unit; 200, mode register; 11, reference delay unit; 12, adjustable delay unit; 121, first delay unit; 122, first controllable switch unit; 21, first-in-first-out pointer processing unit; 22, first-in-first-out data processing unit; 221, storage unit; 2211, storage subunit; 2212, driver; 30, command decoding circuit; 40, array area data processing unit; 300, storage unit array; 50, first selector; 60, first-in-first-out memory; 70, parallel-serial conversion circuit; 80, data driving module; 501, first trigger; 502, second trigger; 503, third trigger; 504, fourth trigger; 400, delay chain; 1000, storage device; 2000, delay circuit. DETAILED DESCRIPTION

[0057] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0059] In addition, certain terms used throughout the specification and the claims that follow refer to specific components. Those skilled in the art will understand that manufacturers may refer to components by different names. This document does not intend to distinguish between components that have different names but the same function. In the following description and embodiments, the terms "comprises" and "includes" are used in an open manner and should be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if one device is connected to another device, the connection can be completed through a direct electrical connection, or through an indirect electrical connection through other devices and connectors.

[0060] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0061] Please refer to Figure 1 In one embodiment of the present application, a data transmission circuit 100 is provided, including a controllable delay module 10 and a mode register data processing unit 20, wherein the controllable delay module 10 is used to generate a delayed read command MrrCmdD in response to a mode register read command MrrCmd; the mode register data processing unit 20 is connected to the controllable delay module 10, and is used to read out a setting parameter MrrData1 from a mode register 200 in response to the mode register read command MrrCmd, and is also used to output a setting parameter MrrData2 in response to the delayed read command MrrCmdD; wherein the time difference between the output start time of the setting parameter MrrData2 and the time when the controllable delay module 10 receives the mode register read command MrrCmd is a first preset threshold.

[0062] As an example, please refer to Figure 1 , by setting the controllable delay module 10 to respond to the mode register read command MrrCmd and generate the delayed read command MrrCmdD, the mode register data processing unit 20 responds to the mode register read command MrrCmd to read the setting parameter MrrData1 from the mode register 200, and responds to the delayed read command MrrCmdD to output the setting parameter MrrData2; since the time difference between the output start time of the setting parameter MrrData2 and the time when the controllable delay module 10 receives the mode register read command MrrCmd is the first preset threshold, the time when the setting parameter MrrData2 is read out in response to the mode register read command MrrCmd matches the time when the array area data is read out in response to the array area data read command ReadCmd. Once the operation delay of the controllable delay module 10 in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module 10 in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices. Here, MrrData1 and MrrData2 can be the same or match a preset algorithm.

[0063] For further information, please refer to Figure 2In one embodiment of the present application, the controllable delay module 10 includes a reference delay unit 11 and an adjustable delay unit 12. The reference delay unit 11 is used to generate an initial delay read command MrrCmdD in response to a mode register read command MrrCmd; the adjustable delay unit 12 is connected to the output end of the reference delay unit 11 and the input end of the mode register data processing unit 20, and is used to generate a delay read command MrrCmdD after delaying a preset delay time from the moment of receiving the initial delay read command MrrCmdD; wherein the sum of the operation delay of the reference delay unit 11 and the preset delay time is equal to a first preset threshold. By setting the operation delay of the adjustable delay unit 12 to the preset delay time, and setting the sum of the operation delay of the reference delay unit 11 and the preset delay time to be equal to the first preset threshold, the operation delay range of the adjustable delay unit 12 is reduced, so as to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module 10 to the first preset threshold.

[0064] Further, in one embodiment of the present application, the adjustable delay unit includes at least two first delay units connected in series; at least one of the first delay units is connected in parallel with a first controllable switch unit; wherein, by controlling the on and off of each of the first controllable switch units, the number of first delay units in the adjustable delay unit connected in series between the reference delay unit and the mode register data processing unit is changed to adjust the operational delay of the adjustable delay unit.

[0065] As an example, see Figure 3 In one embodiment of the present application, the adjustable delay unit 12 includes three first delay units 121 connected in series, wherein two first delay units 121 are respectively connected in parallel with a first controllable switch unit 122; by controlling the on and off of each first controllable switch unit 122, the number of first delay units 121 in the adjustable delay unit 12 connected in series between the reference delay unit 11 and the mode register data processing unit 20 is changed to adjust the operation delay of the adjustable delay unit 12, thereby realizing gradient control of the operation delay of the adjustable delay unit 12 and improving the efficiency and accuracy of adjusting the operation delay of the controllable delay module 10 to the first preset threshold.

[0066] For further information, please refer to Figure 4 In one embodiment of the present application, the mode register data processing unit 20 further includes a first-in first-out pointer processing unit 21 and a first-in first-out data processing unit 22. The first-in first-out pointer processing unit 21 is connected to the output end of the controllable delay module 10 and is used to generate a first pointer signal FifoIn in response to the mode register read command MrrCmd. <n:0>, and is also used to generate a second pointer signal FifoOut in response to a delayed read command MrrCmdD <n:0>FIFO data processing unit 22 is connected to the FIFO pointer processing unit 21 and the mode register 200, and is used to respond to the first pointer signal FifoIn <n:0>Read the setting parameter MrrData1 from the mode register 200, and also respond to the second pointer signal FifoOut <n:0>Output setting parameter MrrData2. By setting the mode register data processing unit 20 to include a first-in first-out pointer processing unit 21 and a first-in first-out data processing unit 22, wherein the first-in first-out pointer processing unit 21 generates a first pointer signal FifoIn for driving the first-in first-out data processing unit 22 to read the setting parameter MrrData1 from the mode register 200 according to the mode register read command MrrCmd. <n:0>, n can be equal to the bit width of the setting parameter MrrData1, and a second pointer signal FifoOut is generated according to the delayed read command MrrCmdD for driving the first-in first-out data processing unit 22 to output the setting parameter MrrData2 <n:0>, to control the time of reading the setting parameter MrrData1 from the mode register 200 in response to the mode register read command MrrCmd, so as to control the time of reading the setting parameter MrrData2 in response to the mode register read command MrrCmd, and to match the time of reading the array area data ArrayData in response to the array area data read command ReadCmd. In one embodiment of the present application, the first pointer signal FifoIn <n:0>The second pointer signal FifoOut <n:0>The driving clock frequency is the same, so as to achieve accurate control of the time difference between reading data and outputting data by the first-in-first-out data processing unit 22.

[0067] Furthermore, in one embodiment of the present application, the first-in-first-out data processing unit includes a storage unit, and output ends of multiple storage units are connected to the same node; the storage unit includes a storage subunit and a driver, and the input end of the driver is connected to the output end of the storage subunit, the storage subunit receives the setting parameters under the drive of the first pointer signal, and the driver outputs the setting parameters under the drive of the second pointer signal.

[0068] As an example, see Figure 5 In one embodiment of the present application, the first-in-first-out data processing unit 22 includes eight storage units 221, and the output ends of the eight storage units 221 are all connected to the node O; the storage unit 221 includes a storage subunit 2211 and a driver 2212, and the input end of the driver 2212 is connected to the output end of the storage subunit 2211, and the storage subunit 2211 is connected to the output end of the first pointer signal FifoIn <n:0>The driver receives the setting parameter MrrData1, n=8, and the driver 2212 ... <n:0>The driver outputs the setting parameter MrrData2, so that the first-in-first-out data processing unit 22 cooperates with the first-in-first-out pointer processing unit 21 to achieve precise control of the time for reading the setting parameter MrrData2 in response to the mode register read command MrrCmd, thereby being able to precisely control the time for reading the setting parameter MrrData2 in response to the mode register read command MrrCmd, and matching it with the time for reading the array area data in response to the array area data read command.

[0069] As an example, see Figure 6 In one embodiment of the present application, the data input terminal of each storage subunit 2211 is connected to the mode register 200, so that each storage subunit 2211 responds to the first pointer signal FifoIn <n:0>The setting parameter MrrData1 is read out from the mode register 200 .

[0070] For further information, please refer to Figure 7 In one embodiment of the present application, the data transmission circuit 100 further includes a command decoding circuit 30 and an array area data processing unit 40. The first output end of the command decoding circuit 30 is connected to the input end of the controllable delay module 10 and the input end of the mode register data processing unit 20. The command decoding circuit 30 is used to receive a read command Read, decode the read command Read and determine whether the read command Read is a mode register read command MrrCmd. If so, the command decoding circuit 30 outputs the mode register read command MrrCmd. Otherwise, the command decoding circuit 30 generates an array area data read command ReadCmd. The input end of the array area data processing unit 40 is connected to the second output end of the command decoding circuit 30 and the storage cell array 300, and is used to respond to the array area data read command ReadCmd and read the array area data ArrayData from the storage cell array 300. This embodiment realizes reading out the setting parameter MrrData2 and the array area data ArrayData via the data transmission circuit 100. Compared with using different data transmission circuits 100 to read out the setting parameter MrrData2 and the array area data ArrayData, this embodiment can effectively reduce the area occupied by the data transmission circuit 100, so as to further improve the integration of the semiconductor memory device.

[0071] For further information, please refer to Figure 7 In one embodiment of the present application, the difference between the operation delay of the array area data processing unit 40 and the first preset threshold is a second preset threshold to meet the working parameter requirements of a specific type of semiconductor storage device such as a dynamic random access memory (DRAM).

[0072] As an example, see Figure 8a and Figure 8b In one embodiment of the present application, the first pointer signal FifoIn may be set <n:0>The frequency is the same as the mode register read command MrrCmd, and the second pointer signal FifoOut is set <n:0>The same as the frequency of the delayed read command MrrCmdD, the time difference between the driving time of the delayed read command MrrCmdD and the driving time of the mode register read command MrrCmd is set to the first preset threshold Td, and the difference between the operation delay of the array area data processing unit 40 and the first preset threshold is set to the second preset threshold, so that the time for reading out the setting parameter MrrData2 in response to the mode register read command MrrCmd matches the time for reading out the array area data ArrayData in response to the array area data read command ReadCmd.

[0073] As an example, in one embodiment of the present application, the second preset threshold may be set to an integer multiple of the column refresh period to meet the requirements of operating parameters of a specific type of semiconductor memory device, such as LPDDR4.

[0074] For further information, please refer to Fig. 9 In one embodiment of the present application, the data transmission circuit 100 further includes a first selector 50 and a first-in first-out memory 60. The first selector 50 is connected to the output end of the array area data processing unit 40 and the output end of the mode register data processing unit 20. The first-in first-out memory 60 is connected to the output end of the first selector 50 and is used to store the setting parameter MrrData1 or the array area data ArrayData. This embodiment implements a transmission path for reading the setting parameter MrrData2 in response to the mode register read command MrrCmd, and shares a data transmission channel with a transmission path for reading the array area data ArrayData in response to the array area data read command ReadCmd, and outputs the data to the outside through the first-in first-out memory 60, thereby effectively reducing the area occupied by the data transmission circuit 100.

[0075] For further information, please refer to Fig.10a and Fig.10b In one embodiment of the present application, the data transmission circuit 100 further includes a parallel-serial conversion circuit 70 and a data driving module 80. The parallel-serial conversion circuit 70 is connected to the output end of the first-in-first-out memory 60; the data driving module 80 is connected to the output end of the parallel-serial conversion circuit 70, and is used to output the setting parameter MrrData2 or the array area data ArrayData. By setting the parallel-serial conversion circuit 70, the serial data provided by the first-in-first-out memory 60 is converted into serial data and then outputted via the data driving module 80, so as to improve the efficiency of data transmission.

[0076] As an example, please refer to Fig.10b , the reference delay unit 11 may be set to include a plurality of sub-delay units 111 connected in series, wherein the sub-delay unit 111 may be used to replicate the operation delay of the array area data processing unit 40 in response to the array area data read command and read out the functional unit with a fixed delay time in the array area data path, and the operation delay of the adjustable delay unit 12 is set to match the delay time of the functional unit with a variable delay time in response to the array area data processing unit 40 in response to the array area data read command and read out the array area data path, so as to realize the gradient control of the operation delay of the adjustable delay unit, so as to improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module to the first preset threshold. Reference Fig.10a and Fig.10b For ease of understanding, an example is given. Assume that the array area data processing unit 40 responds to the array area data read command ReadCmd, and the delay time from reading ArrayData1 from the storage cell array 300 to outputting ArrayData2 is 2.5 nanoseconds. Then the reference delay unit 11 can be set to 2 nanoseconds, and the adjustable delay unit 12 can be set to 0.5 nanoseconds. The delay time of the adjustable delay unit 12 can vary within a range, for example, the delay time can be from 0.1 nanoseconds to 0.9 nanoseconds.

[0077] In the present application, the controllable delay module 10 is set to respond to the mode register read command MrrCmd and generate the delayed read command MrrCmdD, so that the mode register data processing unit 20 responds to the mode register read command MrrCmd to read the setting parameter MrrData1 from the mode register 200, and responds to the delayed read command MrrCmdD to output the setting parameter MrrData2; since the time difference between the output start time of the setting parameter MrrData2 and the time when the controllable delay module 10 receives the mode register read command MrrCmd is the first preset threshold, the time when the setting parameter MrrData2 is read out in response to the mode register read command MrrCmd matches the time when the array area data is read out in response to the array area data read command ReadCmd. Once the operation delay of the controllable delay module 10 in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module 10 in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

[0078] Fig.11a A delay circuit 2000 is provided in a data transmission circuit for responding to a mode register read command MrrCmd to read out a setting parameter MrrData2. Fig.11b for Fig.11a The delay circuit 2000 includes a first trigger 501, a second trigger 502, a third trigger 503, a fourth trigger 504 and a delay chain 400, wherein the delay chain 400 is used to generate a first clock signal Clk1, a second clock signal Clk2, a third clock signal Clk3, a fourth clock signal Clk4 and a delayed read command MrrCmdD in response to a mode register read command MrrCmd, wherein the first trigger 501 is used to receive a setting parameter MrrData1 in response to the first clock signal Clk1, the second trigger 502 is used to receive data provided by the first trigger 501 in response to the second clock signal Clk2, the third trigger 503 is used to receive data provided by the second trigger 502 in response to the third clock signal Clk3, and the fourth trigger 504 is used to receive data provided by the third trigger 503 in response to the fourth clock signal Clk4 and output the setting parameter MrrData2. By controlling the driving time of the first clock signal Clk1, the second clock signal Clk2, the third clock signal Clk3, the fourth clock signal Clk4 and the delayed read command MrrCmdD generated by the delay chain 400, the time of responding to the mode register read command MrrCmd to read out the setting parameter MrrData2 is controlled to match the time of responding to the array area data read command ReadCmd to read out the array area data ArrayData.

[0079] Also refer to Fig.10b and Fig.11a , both of which realize the output of the setting parameter MrrData in the mode register 200. When the manufacturing process, temperature or voltage changes greatly, Fig.11a Each clock (Clk1, Clk2, Clk3, Clk4) needs to be adjusted to ensure the correct timing from MrrData1 to MrrData2. Fig.10b The technical solution is easier to deploy.

[0080] Please refer to Fig.12 In one embodiment of the present application, a storage device 1000 is provided, including a storage cell array 300, a mode register 200, and a data transmission circuit 100 as in any embodiment of the present application. Since the data transmission circuit 100 as in any embodiment of the present application is used to transmit the array area data ArrayData and the setting parameter MrrData2, it is convenient to control the time of reading the setting parameter MrrData2 in response to the mode register read command MrrCmd, and match the time of reading the array area data ArrayData in response to the array area data read command ReadCmd. Once the operation delay of the controllable delay module 10 in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module 10 in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices 1000.

[0081] Please refer to Fig.13 In one embodiment of the present application, a data transmission method is provided, comprising:

[0082] Step 502, controlling the controllable delay module to respond to the mode register read command and generate a delay read command;

[0083] Step 504, responding to the mode register read command, reading the setting parameters from the mode register based on the mode register data processing unit; and

[0084] Step 506, in response to the delayed read command, output the setting parameters based on the mode register data processing unit, wherein the time difference between the output start time of the setting parameters and the time when the controllable delay module receives the mode register read command is a first preset threshold.

[0085] For details, please continue to refer to Fig.13 and Figure 7 , based on the controllable delay module 10 responding to the mode register read command MrrCmd and generating the delayed read command MrrCmdD, the mode register data processing unit 20 responds to the mode register read command MrrCmd to read the setting parameter MrrData1 from the mode register 200, and responds to the delayed read command MrrCmdD to output the setting parameter MrrData2; since the time difference between the output start time of the setting parameter MrrData2 and the time when the controllable delay module 10 receives the mode register read command MrrCmd is the first preset threshold, the time of reading the setting parameter MrrData2 in response to the mode register read command MrrCmd matches the time of reading the array area data ArrayData in response to the array area data read command ReadCmd. Once the operation delay of the controllable delay module 10 in the present application is determined, it is little affected by changes in the working environment, and can effectively avoid control errors in the data transmission path caused by the influence of the working environment. In addition, the operation delay of the controllable delay module 10 in the present application can be controlled and adjusted to meet the working parameter requirements of different types of semiconductor storage devices.

[0086] For further information, please refer to Fig.14 In one embodiment of the present application, the controllable delay module responds to the mode register read command and generates a delay read command, including:

[0087] Step 5021, controlling the reference delay unit to generate an initial delay read command in response to the mode register read command;

[0088] Step 5022, controlling the adjustable delay unit to generate the delayed read command after delaying for a preset delay time from the moment of receiving the initial delayed read command, so that the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold.

[0089] For details, please continue to refer to Fig.14 and Figure 3 By controlling the reference delay unit 11 to respond to the mode register read command MrrCmd and generate the initial delay read command MrrCmdD, the adjustable delay unit 12 generates the delay read command MrrCmdD after delaying for a preset delay time from the moment of receiving the initial delay read command MrrCmdD, so that the sum of the operation delay of the reference delay unit 11 and the preset delay time is equal to the first preset threshold. This embodiment can narrow the operation delay range of the adjustable delay unit 12 and improve the efficiency and accuracy of adjusting the operation delay of the controllable delay module 10 to the first preset threshold.

[0090] For further information, please refer to Fig.15 In one embodiment of the present application, before the controllable delay module responds to the mode register read command and generates a delay read command, it also includes:

[0091] Step 5011, receiving a read command;

[0092] Step 5012, decoding the read command and determining whether the read command is the mode register read command;

[0093] Step 5013: If yes, output the mode register read command;

[0094] Step 5014: Otherwise, an array area data read command is generated;

[0095] Step 507: Read the array area data from the memory cell array in response to the array area data read command.

[0096] For details, please continue to refer to Fig.15 As shown in FIG10 , the received read command is decoded and judged whether the read command is a mode register read command MrrCmd; if so, the mode register read command MrrCmd is output; otherwise, the array area data read command ReadCmd is generated; the array area data ArrayData is read from the memory cell array 300 in response to the array area data read command ReadCmd, the setting parameter MrrData1 is read from the mode register 200 in response to the mode register read command MrrCmd and based on the mode register data processing unit 20, and the setting parameter MrrData2 is output based on the mode register data processing unit 20 in response to the delay read command MrrCmdD, wherein the time difference between the output start time of the setting parameter MrrData2 and the time when the controllable delay module 10 receives the mode register read command MrrCmd is the first preset threshold. This embodiment can control the setting parameter MrrData1 in the mode register 200 and the array area data ArrayData to be read out via the same data output path, thereby improving the data transmission efficiency and effectively reducing the area occupied by the data output path, so as to further improve the integration of the semiconductor memory device.

[0097] For the specific definition of the data transmission method in the above embodiment, please refer to the definition of the data transmission device above, which will not be repeated here.

[0098] It should be understood that although Figure 13-Figure 15 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 13-Figure 15 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0099] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0100] Please note that the above embodiments are for illustrative purposes only and are not meant to limit the present invention.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A data transmission circuit, characterized in that: include: A controllable delay module for generating a delayed read command in response to a mode register read command; a mode register data processing unit connected to the controllable delay module, configured to read out setting parameters from the mode register in response to the mode register read command, and further configured to output the setting parameters in response to the delay read command; Wherein, the time difference between the output start time of the setting parameter and the time when the controllable delay module receives the mode register read command is a first preset threshold; A command decoding circuit, whose first output terminal is connected to the input terminal of the controllable delay module and the input terminal of the mode register data processing unit, is used to receive a read command, decode the read command and determine whether the read command is the mode register read command, if so, output the mode register read command, otherwise, generate an array area data read command; an array area data processing unit, whose input end is connected to the second output end of the command decoding circuit and the storage cell array, and is used to respond to the array area data read command and read the array area data from the storage cell array; the difference between the operation delay of the array area data processing unit and the first preset threshold is a second preset threshold; A transmission path for reading the setting parameters in response to the mode register read command and a transmission path for reading the array area data in response to the array area data read command share a data transmission channel; The controllable delay module comprises: A reference delay unit, configured to generate an initial delay read command in response to the mode register read command; an adjustable delay unit connected to the output end of the reference delay unit and the input end of the mode register data processing unit, and configured to generate the delayed read command after delaying for a preset delay time from the moment of receiving the initial delayed read command; Wherein, the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold; The reference delay unit is used to replicate the operation delay of a functional unit with a fixed delay time in a path where the array area data processing unit responds to the array area data read command and reads out the array area data, and the operation delay of the adjustable delay unit matches the operation delay of a functional unit with a variable delay time in a path where the array area data processing unit responds to the array area data read command and reads out the array area data.

2. The data transmission circuit according to claim 1, characterized in that: The adjustable delay unit includes at least two first delay units connected in series; At least one of the first delay units is connected in parallel with a first controllable switch unit; By controlling the on and off of each of the first controllable switch units, the number of first delay units in the adjustable delay unit connected in series between the reference delay unit and the mode register data processing unit is changed to adjust the operation delay of the adjustable delay unit.

3. The data transmission circuit according to any one of claims 1 to 2, characterized in that: The mode register data processing unit also includes: a first-in-first-out pointer processing unit connected to the output end of the controllable delay module, for generating a first pointer signal in response to the mode register read command, and for generating a second pointer signal in response to the delay read command; A FIFO data processing unit is connected to the FIFO pointer processing unit and the mode register, and is used to read out setting parameters from the mode register in response to the first pointer signal, and is also used to output the setting parameters in response to the second pointer signal.

4. The data transmission circuit according to claim 3, characterized in that: The driving clock frequency of the first pointer signal and the second pointer signal is the same.

5. The data transmission circuit according to claim 3, characterized in that: The first-in-first-out data processing unit comprises: Storage units, wherein output ends of a plurality of the storage units are connected to the same node; The storage unit includes a storage subunit and a driver, the input end of the driver is connected to the output end of the storage subunit, the storage subunit receives the setting parameter under the drive of the first pointer signal, and the driver outputs the setting parameter under the drive of the second pointer signal.

6. The data transmission circuit according to claim 5, characterized in that: The data input terminal of each storage subunit is connected to the mode register.

7. The data transmission circuit according to claim 1, characterized in that: The second preset threshold is an integer multiple of a column refresh period.

8. The data transmission circuit according to claim 1, characterized in that: Also includes: A first selector connected to both the output end of the array area data processing unit and the output end of the mode register data processing unit; A first-in first-out memory is connected to the output end of the first selector and is used to store the setting parameters or the array area data.

9. The data transmission circuit according to claim 8, characterized in that: Also includes: A parallel-serial conversion circuit connected to the output end of the first-in-first-out memory; A data driving module is connected to the output end of the parallel-serial conversion circuit and is used for outputting the setting parameters or the array area data.

10. A storage device, characterized in that: include: A storage unit array, used for storing array area data; Mode register, used to store setting parameters; as well as The data transmission circuit according to any one of claims 1 to 9.

11. A data transmission method, characterized in that: include: Control the controllable delay module to respond to the mode register read command and generate a delay read command; In response to the mode register read command, the mode register data processing unit reads out the setting parameters from the mode register; as well as In response to the delayed read command, output the setting parameter based on the mode register data processing unit, wherein the time difference between the output start time of the setting parameter and the time when the controllable delay module receives the mode register read command is a first preset threshold; Based on receiving a read command from a command decoding circuit, decoding the read command and determining whether the read command is the mode register read command, if so, outputting the mode register read command, otherwise, generating an array area data read command, wherein a first output terminal of the command decoding circuit is connected to an input terminal of the delay module and an input terminal of the mode register data processing unit; Based on the array area data processing unit responding to the array area data read command, the input end of the array area data processing unit is connected to the second output end of the command decoding circuit and the storage unit array, the array area data is read from the storage unit array, and the difference between the operation delay of reading the array area data and the first preset threshold is the second preset threshold; A transmission path for reading the setting parameters in response to the mode register read command and a transmission path for reading the array area data in response to the array area data read command share a data transmission channel; The controlling the controllable delay module to respond to the mode register read command and generate a delay read command includes: Controlling the reference delay unit to generate an initial delay read command in response to the mode register read command; Controlling the adjustable delay unit to generate the delayed read command after delaying for a preset delay time from the moment of receiving the initial delayed read command, so that the sum of the operation delay of the reference delay unit and the preset delay time is equal to the first preset threshold; The reference delay unit is used to replicate the operation delay of a functional unit with a fixed delay time in a path where the array area data processing unit responds to the array area data read command and reads out the array area data, and the operation delay of the adjustable delay unit matches the operation delay of a functional unit with a variable delay time in a path where the array area data processing unit responds to the array area data read command and reads out the array area data.

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