Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes: a first bare chip, a pre-wiring substrate, a plastic packaging layer, a plurality of conductive plugs, a first conductive trace, a first conductive bump, a first dielectric layer and passive devices. The pre-wiring substrate can transfer the wiring layer that needs to be formed on the active surface of the bare chip to the pre-wiring substrate. The pre-wiring substrate includes complex multi-circuits. These complex multi-circuits are embedded in the semiconductor packaging structure by being electrically connected to the pads on the active surface of the bare chip, which can improve the performance of the entire semiconductor packaging structure and also realize the inclusion of passive devices into the semiconductor packaging structure. The pre-wiring substrate can be tested before packaging to avoid the use of known bad pre-wiring substrates. The pre-wiring substrate is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the packaging time of the entire packaging process.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] As electronic devices become smaller and lighter, semiconductor packaging structures with compact structures and small volumes are increasingly favored by the market.

[0003] As the integration of chips becomes higher and the functions they implement become more complex, the chip packaging has shown increasingly complex rewiring requirements in recent years, which has resulted in wiring difficulties due to the small surface area of ​​the chip. In addition, due to the overly dense wiring, it is easy for fine wiring to short-circuit, thus affecting the yield of the product. At the same time, the service life of the chip is also relatively low; especially when multiple wiring layers need to be formed, the process is difficult to control due to the complexity of the process. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor packaging structure and a manufacturing method thereof to solve the problems in the related art.

[0005] To achieve the above object, a first aspect of the present invention provides a semiconductor packaging structure, comprising:

[0006] A first die, the first die comprising a plurality of first pads, the first pads being located on an active surface of the first die;

[0007] A pre-wiring substrate, wherein a pre-wiring circuit is provided in the pre-wiring substrate, wherein the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, wherein the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the back side of the pre-wiring substrate faces the back side of the first bare chip;

[0008] A plastic encapsulation layer, covering the first bare chip and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the front side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the first bare chip;

[0009] A plurality of conductive plugs are located in the plastic encapsulation layer and on the side of the first die, the conductive plugs comprising a first end and a second end opposite to each other, the first end is connected to the back electrical connection point, and the second end is exposed to the front side of the plastic encapsulation layer;

[0010] A first conductive trace, located on the first pad, the second end of the conductive plug and the front side of the plastic layer, for electrically connecting the first die to the pre-wiring circuit;

[0011] a first conductive bump connected to the first conductive trace;

[0012] a first dielectric layer, embedding the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; and

[0013] A passive device is electrically connected to the front electrical connection point of the pre-wiring substrate.

[0014] Optionally, the active surface of the first bare chip is covered with a first protective layer, and the first protective layer exposes the first pad; the front side of the plastic layer exposes the first protective layer and the first pad; and the first conductive trace is also located on the first protective layer.

[0015] Optionally, it also includes: a second bare chip, the second bare chip includes a plurality of second solder pads, the second solder pads are located on the active surface of the second bare chip; the active surface of the second bare chip is covered with a second protective layer, the second protective layer exposes the second solder pads; the back side of the second bare chip and the back side of the pre-wiring substrate are facing each other; the plastic encapsulation layer also covers the second bare chip; the conductive plug is also located on the side of the second bare chip; the first conductive trace is also located on the second solder pad, for electrically connecting the first bare chip, the second bare chip and the pre-wiring circuit.

[0016] Optionally, it also includes: a third dielectric layer, located on the active surface of the first bare chip, the second end of the conductive plug and the front side of the plastic layer; the third dielectric layer exposes the first pad and the second end of the conductive plug; the first conductive trace is located on the first pad, the second end of the conductive plug and the third dielectric layer.

[0017] Optionally, it further includes: a second conductive trace located on the first conductive bump and the first dielectric layer;

[0018] a second conductive bump connected to the second conductive trace;

[0019] The second dielectric layer embeds the second conductive trace and the second conductive bump, and the second conductive bump is exposed outside the second dielectric layer.

[0020] A second aspect of the present invention provides a method for manufacturing a semiconductor packaging structure, comprising:

[0021] A plurality of groups of parts to be encapsulated are provided, each group of the parts to be encapsulated comprises: a first bare chip, the first bare chip comprises a plurality of first pads, the first pads are located on the active surface of the first bare chip; a pre-wiring substrate, the pre-wiring substrate is provided with a pre-wiring circuit, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front of the pre-wiring substrate, and the back electrical connection point is exposed on the back of the pre-wiring substrate; the back of the pre-wiring substrate faces the back of the first bare chip;

[0022] Forming a plastic encapsulation layer, wherein the plastic encapsulation layer covers the plurality of groups of components to be encapsulated, the back side of the plastic encapsulation layer exposes the front side of each of the pre-wiring substrates, and the front side of the plastic encapsulation layer exposes the active surface of each of the first bare chips;

[0023] A plurality of conductive plugs are formed in the plastic layer, the conductive plugs are located at the side of the first bare die, the conductive plugs include a first end and a second end opposite to each other, the first end is connected to the back electrical connection point, and the second end is exposed to the front side of the plastic layer; a first conductive trace is formed on the first pad, the second end of the conductive plug and the front side of the plastic layer to electrically connect the first bare die in the group with the pre-wiring circuit;

[0024] forming a first conductive bump on the first conductive trace and forming a first dielectric layer that buries the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer;

[0025] electrically connecting a passive device to the front electrical connection point of the pre-wiring substrate;

[0026] A plurality of semiconductor packaging structures are formed by cutting, each of which includes a group of the parts to be encapsulated.

[0027] Optionally, forming a plastic encapsulation intermediate includes:

[0028] A plurality of groups of components to be plastic-encapsulated are carried on a carrier, and an active surface of each of the first bare chips faces the carrier;

[0029] The forming of the plastic sealing layer comprises:

[0030] Forming a plastic sealing layer on the surface of the carrier board to embed each group of the components to be plastic sealed;

[0031] The carrier is removed to expose the active surface of each of the first bare chips and the front side of the plastic encapsulation layer; before removing the carrier or after forming the first dielectric layer, the plastic encapsulation layer is thinned until the front side of each of the pre-wiring substrates is exposed.

[0032] Optionally, the active surface of the first die is covered with a first protective layer, the first protective layer has a first opening exposing the first pad; the first opening serves as an alignment pattern feature to arrange the first die on the carrier according to a predetermined arrangement position.

[0033] Optionally, the back side of the first die has an alignment mark so that the pre-wiring substrate is applied to the back side of the first die.

[0034] Optionally, the plurality of groups of components to be encapsulated are carried on a carrier board, and the front side of each of the pre-wiring substrates faces the carrier board;

[0035] The forming of the plastic sealing layer comprises:

[0036] Forming a plastic encapsulation layer on the surface of the carrier board to embed each group of the components to be plastic encapsulated; thinning the plastic encapsulation layer until the active surface of each of the first bare chips is exposed;

[0037] The carrier board is removed to expose the front side of each pre-wiring substrate and the back side of the plastic encapsulation layer.

[0038] Optionally, the active surface of the first die is covered with a first protective layer; the plastic encapsulation layer is thinned until the first protective layer is exposed; before forming the first conductive trace, a first opening is formed in the first protective layer to expose the first pad; or

[0039] The active surface of the first bare chip is covered with a first protective layer, and the first protective layer has a first opening exposing the first pad; the plastic packaging layer is thinned until the first protective layer and the first pad are exposed.

[0040] Optionally, each group of the parts to be encapsulated further includes: a second bare chip, the second bare chip includes a plurality of second solder pads, the second solder pads are located on the active surface of the second bare chip; the active surface of the second bare chip is covered with a second protective layer; the back side of the second bare chip faces the back side of the pre-wiring substrate.

[0041] Optionally, the pre-wiring substrates of each group of the parts to be plastic-encapsulated are connected together and are cut apart in the step of cutting to form a plurality of semiconductor package structures.

[0042] Compared with the prior art, the present invention has the following beneficial effects:

[0043] First, the pre-wiring substrate can transfer the wiring layer that needs to be formed on the active surface of the die to the pre-wiring substrate. The pre-wiring substrate includes complex multi-circuits. These complex multi-circuits are embedded in the semiconductor packaging structure by being electrically connected to the pads on the active surface of the die, which can improve the performance of the entire semiconductor packaging structure and also realize the inclusion of passive devices into the semiconductor packaging structure. Second, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate, which reduces the probability of short circuits and increases the product yield. At the same time, the number of layers of conductive traces can be reduced and the complexity of the process can be reduced. Third, a pre-formed pre-wiring substrate is provided, and the pre-wiring substrate can be tested before packaging to avoid the use of known bad pre-wiring substrates. Fourth, the pre-wiring substrate is a prefabricated substrate, and its production process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0044] In addition, the semiconductor packaging structure has the advantages of small size and compact structure, and is suitable for small and lightweight electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor package structure according to a first embodiment of the present invention;

[0046] Figure 2 yes Figure 1 A flowchart of a method for manufacturing a semiconductor packaging structure;

[0047] Figures 3 to 11 yes Figure 2 Schematic diagram of the intermediate structure corresponding to the process in;

[0048] Fig.12 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention;

[0049] Fig.13 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention;

[0050] Fig.14 FIG. 4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the present invention.

[0051] To facilitate understanding of the present invention, all reference numerals appearing in the present invention are listed below:

[0052] Semiconductor package structure 1, 6, 7, 8 first bare chip 11

[0053] First protection layer 110 First pad 111

[0054] Active surface 11a of the first die Back surface 11b of the first die

[0055] Pre-wiring substrate 12 Pre-wiring circuit 120

[0056] Front electrical connection point 121 Back electrical connection point 122

[0057] Front surface 12a of pre-wiring substrate Back surface 12b of pre-wiring substrate

[0058] Plastic sealing layer 13 Front side 13a of plastic sealing layer

[0059] Back side of plastic sealing layer 13b Conductive plug 14

[0060] The first end 14a of the conductive plug The second end 14b of the conductive plug

[0061] First conductive trace 15 First conductive bump 16

[0062] First dielectric layer 17 Passive components 18

[0063] Second conductive trace 19 Second conductive bump 20

[0064] Second dielectric layer 21 Third dielectric layer 22

[0065] First opening 110a Second opening 230a

[0066] The third opening 22a and the second bare chip 23

[0067] Second pad 231 Second protective layer 230

[0068] Active surface 23a of the second die Back surface 23b of the second die

[0069] Metal pattern blocks 15a, 19a through holes 141

[0070] Parts to be plastic sealed 2 Carrier board 3

[0071] First support plate 4 Second support plate 5 DETAILED DESCRIPTION

[0072] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0073] Figure 1 FIG. 4 is a schematic cross-sectional view of a semiconductor package structure according to a first embodiment of the present invention.

[0074] Reference Figure 1 As shown, the semiconductor package structure 1 includes:

[0075] A first bare chip 11, the first bare chip 11 includes a plurality of first pads 111, and the first pads 111 are located on an active surface 11a of the first bare chip 11;

[0076] A pre-wiring substrate 12, wherein a pre-wiring circuit 120 is provided in the pre-wiring substrate 12, and the pre-wiring circuit 120 includes a front electrical connection point 121 and a back electrical connection point 122, wherein the front electrical connection point 121 is exposed on the front side 12a of the pre-wiring substrate 12, and the back electrical connection point 122 is exposed on the back side 12b of the pre-wiring substrate 12; the back side 12b of the pre-wiring substrate 12 faces the back side 11b of the first bare chip 11;

[0077] The plastic encapsulation layer 13 covers the first bare chip 11 and the pre-wiring substrate 12, the back side 13b of the plastic encapsulation layer 13 exposes the front side 12a of the pre-wiring substrate 12, and the front side 13a of the plastic encapsulation layer 13 exposes the active surface 11a of the first bare chip 11;

[0078] A plurality of conductive plugs 14 are located in the plastic encapsulation layer 13 and on the side of the first die 11. The conductive plugs 14 include a first end 14a and a second end 14b opposite to each other. The first end 14a is connected to the back electrical connection point 122, and the second end 14b is exposed to the front side 13a of the plastic encapsulation layer 13.

[0079] The first conductive trace 15 is located on the first pad 111, the second end 14b of the conductive plug 14 and the front surface 13a of the plastic layer 13, and is used to electrically connect the first bare chip 11 and the pre-wiring circuit 120;

[0080] A first conductive bump 16 connected to the first conductive trace 15;

[0081] A first dielectric layer 17 embeds the first conductive trace 15 and the first conductive bump 16 , and the first conductive bump 16 is exposed outside the first dielectric layer 17 ; and

[0082] The passive device 18 is electrically connected to the front electrical connection point 121 of the pre-wiring substrate 12 .

[0083] The first die 11 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE).

[0084] Reference Figure 1 As shown, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first pad 111 is exposed on the active surface 11a. The first die 11 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The first pad 111 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0085] It should be noted that, in the present invention, “ / ” means “or”.

[0086] In this embodiment, the active surface 11 a of the first die 11 is provided with a first protective layer 110 . In other embodiments, the active surface 11 a of the first die 11 may also omit the first protective layer 110 .

[0087] The first protective layer 110 is an insulating material, which can be an organic high molecular polymer insulating material, or an inorganic insulating material or a composite material. The organic high molecular polymer insulating material is, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. The inorganic insulating material is, for example, at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which can be an inorganic-organic polymer composite material, such as SiO2 / resin polymer composite material.

[0088] The pre-wiring substrate 12 includes a pre-wiring line 120 and an insulating material layer filled between the pre-wiring lines 120. The pre-wiring substrate 12 may include a front surface 12a and a back surface 12b opposite to each other, a front electrical connection point 121 exposed on the front surface 12a of the pre-wiring substrate 12, and a back electrical connection point 122 exposed on the back surface 12b of the pre-wiring substrate 12. There may be a plurality of front electrical connection points 121 exposed on the front surface 12a of the pre-wiring substrate, and there may also be a plurality of back electrical connection points 122 exposed on the back surface 12b of the pre-wiring substrate.

[0089] Continue to refer to Figure 1 As shown, in this embodiment, the first die 11 and the pre-wiring substrate 12 are arranged back to back and can be fixed by an adhesive layer. The area of ​​the first die 11 is smaller than that of the pre-wiring substrate 12 to expose the back electrical connection points 122.

[0090] The material of the plastic encapsulation layer 13 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyether sulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol, etc. The material of the plastic encapsulation layer 13 may also be various polymers or composite materials of resins and polymers.

[0091] The plastic layer 13 includes a front side 13a and a back side 13b opposite to each other. In this embodiment, the front side 13a of the plastic layer 13 exposes the first protection layer 110 and the first pad 111 , and the back side 13b of the plastic layer 13 exposes the back side 12b of the pre-wiring substrate 12 .

[0092] The conductive plug 14 may be made of a metal with good conductivity such as copper.

[0093] The number and position of the conductive plugs 14 may be determined according to a predetermined circuit layout.

[0094] Figure 1 In the illustrated embodiment, the first conductive trace 15 includes a plurality of metal pattern blocks 15a, which have a layer. A portion of the metal pattern blocks 15a selectively electrically connects the second end 14b of the conductive plug 14 with the first pad 111 to achieve electrical connection between the conductive plug 14 and the first die 11. In addition, a portion of the metal pattern blocks 15a selectively electrically connects a plurality of first pads 111 to achieve circuit layout or electrical conduction of the first pads 111.

[0095] The layout of the first conductive traces 15 may be determined according to a predetermined circuit layout.

[0096] Reference Figure 1 As shown, in this embodiment, the first conductive bumps 16 on the first conductive traces 15 serve as external connection terminals of the semiconductor package structure 1 .

[0097] In other embodiments, an anti-oxidation layer may be further provided on the first conductive bump 16 .

[0098] The anti-oxidation layer may include: b1) a tin layer, or b2) a nickel layer and a gold layer stacked from bottom to top, or b3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer may prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation.

[0099] The material of the first dielectric layer 17 can be an organic high molecular polymer insulating material or an inorganic insulating material or a composite material. Examples of organic high molecular polymer insulating materials include polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), organic polymer film or other organic materials with similar insulating properties. Examples of inorganic insulating materials include at least one of silicon dioxide and silicon nitride. The composite material is an inorganic-organic composite material, which can be an inorganic-organic polymer composite material, such as a SiO2 / resin polymer composite material. Compared with inorganic insulating materials, the tensile stress of organic high molecular polymer insulating materials and composite materials is smaller, which can prevent the surface of the semiconductor packaging structure 1 from warping.

[0100] Compared with the solution of making a rewiring layer on the plastic package of the first bare chip 11, the advantages of using a pre-wiring substrate 12 in this solution are: first, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate 12, which reduces the probability of short circuit and increases the product yield. At the same time, the number of layers of conductive traces can be reduced and the complexity of the process can be reduced. Second, a pre-formed pre-wiring substrate 12 is provided, and the pre-wiring substrate 12 can be tested before packaging to avoid the use of known bad pre-wiring substrates 12. Third, the pre-wiring substrate 12 is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0101] In addition, the wiring layer to be formed on the active surface 11a of the die is transferred to the pre-wiring substrate 12, which includes complex multi-circuits, which are electrically connected to the first conductive trace 15 and the pad 111 on the active surface 11a of the die through the conductive plug 14 and embedded in the semiconductor package structure 1, which can improve the performance of the entire semiconductor package structure 1. Through the pre-wiring substrate 12, not only the passive device 18 is incorporated into the semiconductor package structure 1, enriching the function of the semiconductor package structure 1, but also because the pre-wiring substrate 12 includes complex multi-circuits, complex wiring between the passive device 18 and the first die 11 can be realized.

[0102] The passive device 18 may include resistors, inductors and capacitors, and their common feature is that they can work when there is a signal without adding power to the circuit. The passive device 18 includes an electrical connection point, which is connected to the front electrical connection point 121 of the pre-wiring substrate 12 to achieve the electrical signal input / output of the passive device 18.

[0103] This embodiment does not limit the number and types of the first bare chips 11 and the passive components 18 .

[0104] One embodiment of the present invention provides Figure 1 A method for manufacturing a semiconductor packaging structure 1. Figure 2 It is a flowchart of the production method. Figures 3 to 11 yes Figure 2 Schematic diagram of the intermediate structure corresponding to the process in .

[0105] First, refer to Figure 2 Step S1 in Figure 3 and Figure 4As shown, multiple groups of parts to be encapsulated 2 are provided, and each group of parts to be encapsulated 2 includes: a first bare chip 11, the first bare chip 11 includes a plurality of first solder pads 111, and the first solder pads 111 are located on the active surface 11a of the first bare chip 11; a pre-wiring substrate 12, and a pre-wiring circuit 120 is provided in the pre-wiring substrate 12, and the pre-wiring circuit 120 includes a front electrical connection point 121 and a back electrical connection point 122, the front electrical connection point 121 is exposed on the front side 12a of the pre-wiring substrate 12, and the back electrical connection point 122 is exposed on the back side 12b of the pre-wiring substrate 12; the back side 12b of the pre-wiring substrate 12 faces the back side 11b of the first bare chip 11. Among them, Figure 3 It is a top view of the carrier board and multiple groups of parts to be plastic-sealed; Figure 4 It is along Figure 3 Sectional view along line AA.

[0106] Specifically: refer to Figure 3 and Figure 4 As shown, a carrier board 3 and a plurality of groups of parts 2 to be encapsulated carried on the carrier board 3 are provided, each group of parts 2 to be encapsulated includes: a first bare chip 11, the first bare chip 11 includes a plurality of first solder pads 111, the first solder pads 111 are located on the active surface 11a of the first bare chip 11; a pre-wiring substrate 12, a pre-wiring circuit 120 is provided in the pre-wiring substrate 12, the pre-wiring circuit 120 includes a front electrical connection point 121 and a back electrical connection point 122, the front electrical connection point 121 is exposed on the front side 12a of the pre-wiring substrate 12, and the back electrical connection point 122 is exposed on the back side 12b of the pre-wiring substrate 12; the back side 12b of the pre-wiring substrate 12 and the back side 11b of the first bare chip 11 are facing each other; the active surface 11a of each first bare chip 11 faces the carrier board 3.

[0107] The first die 11 may be a power die (POWER DIE), a memory die (MEMORY DIE), a sensor die (SENSOR DIE), or a radio frequency die (RADIO FREQUENCE DIE).

[0108] Reference Figure 4 As shown, the first die 11 includes an active surface 11a and a back surface 11b opposite to each other. The first die 11 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. A first pad 111 exposed to the active surface 11a of the first die 11 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0109] In this embodiment, the active surface 11a of the first die 11 is provided with a first protective layer 110 to buffer stress on the first pad 111 when the plastic layer 13 is thinned. In other embodiments, the active surface 11a of the first die 11 may also omit the first protective layer 110.

[0110] The first die 11 is formed by dividing the wafer. The wafer includes an active surface of the wafer and a back surface of the wafer, and the active surface of the wafer exposes the first pad 111 and an insulating layer (not shown) protecting the first pad 111. After the wafer is cut, the first die 11 is formed. Accordingly, the first die 11 includes an active surface 11a and a back surface 11b, and the first pad 111 and the insulating layer electrically insulating the adjacent first pad 111 are exposed on the active surface 11a of the die.

[0111] A first protective layer 110 is applied on the active surface 11a of the first bare chip 11. The application process of the first protective layer 110 can be: applying the first protective layer 110 on the active surface of the wafer before the wafer is cut into the first bare chip 11, and cutting the wafer with the first protective layer 110 to form the first bare chip 11 with the first protective layer 110. It can also be: after the wafer is cut into the first bare chip 11, applying the first protective layer 110 on the active surface 11a of the first bare chip 11.

[0112] The first protective layer 110 is an insulating material, which may be an organic high molecular polymer insulating material, or an inorganic insulating material or a composite material. The organic high molecular polymer insulating material may be, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), an organic polymer film or other organic materials with similar insulating properties. The composite material may be an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as a SiO2 / resin polymer composite material.

[0113] The organic high molecular polymer insulating material can be pressed onto the insulating layer between the first pad 111 and the adjacent first pad 111 by a) lamination process, or b) first coated or printed on the insulating layer between the first pad 111 and the adjacent first pad 111 and then cured, or c) cured on the insulating layer between the first pad 111 and the adjacent first pad 111 by an injection molding process.

[0114] When the material of the first protection layer 110 is an inorganic material such as silicon dioxide or silicon nitride, it can be formed on the first pads 111 and the insulating layer between adjacent first pads 111 through a deposition process.

[0115] The first protective layer 110 may include one or more layers.

[0116] In this embodiment, refer to Figure 4 As shown, a first opening 110a is further opened in the first protection layer 110 to expose the first pad 111. The first opening 110a can be realized by dry etching or wet etching.

[0117] The wafer may be thinned from the back side before dicing to reduce the thickness of the first die 11 .

[0118] The pre-wiring substrate 12 includes a pre-wiring line 120 and an insulating material layer filled between the pre-wiring lines 120. The pre-wiring substrate 12 may include a front surface 12a and a back surface 12b opposite to each other, a front electrical connection point 121 exposed on the front surface 12a of the pre-wiring substrate 12, and a back electrical connection point 122 exposed on the back surface 12b of the pre-wiring substrate 12. There may be a plurality of front electrical connection points 121 exposed on the front surface 12a of the pre-wiring substrate, and there may also be a plurality of back electrical connection points 122 exposed on the back surface 12b of the pre-wiring substrate.

[0119] The pre-wiring substrates 12 of each group of components 2 to be encapsulated can be connected together or separated from each other.

[0120] Continue to refer to Figure 4 As shown, in this embodiment, the first die 11 and the pre-wiring substrate 12 are arranged back to back and can be fixed by an adhesive layer. The area of ​​the first die 11 is smaller than that of the pre-wiring substrate 12 to expose the back electrical connection points 122.

[0121] The carrier plate 3 is a hard plate, which may include a plastic plate, a glass plate, a ceramic plate or a metal plate.

[0122] When multiple groups of components 2 to be plastic-encapsulated are arranged on the surface of the carrier 3, the following may be included:

[0123] a) The first protective layer 110 faces the carrier 3, and the plurality of first bare chips 11 are arranged on the carrier 3. Specifically, the surface of the carrier 3 is provided with a plurality of mounting areas, each of which is provided with an alignment mark, and the first opening 110a can be used as an alignment pattern feature to arrange the first bare chips 11 on the carrier 3 according to a predetermined arrangement position. The surface of the carrier 3 can be coated with a whole adhesive layer to fix the plurality of first bare chips 11;

[0124] The adhesive layer may be made of an easily peelable material so as to peel the plurality of first bare chips 11 from the carrier 3, for example, a thermal separation material that can lose its stickiness by heating or a UV separation material that can lose its stickiness by ultraviolet irradiation may be used;

[0125] b) Next, each pre-wiring substrate 12 is applied to the back side 11b of the corresponding first die 11. The back side 11b of the first die 11 may have an alignment mark to achieve alignment between the pre-wiring substrate 12 and the first die 11 during the application process.

[0126] A group of plastic-encapsulated parts 2 are located in an area on the surface of the carrier 3, which is convenient for subsequent cutting. Multiple groups of plastic-encapsulated parts 2 are fixed on the surface of the carrier 3 to simultaneously manufacture multiple semiconductor packaging structures 1, which is conducive to mass production and cost reduction.

[0127] Next, refer to Figure 2 Step S2 in Figures 5 to 7 As shown, a plastic encapsulation layer 13 is formed, which covers multiple groups of components 2 to be encapsulated. The back side 13b of the plastic encapsulation layer 13 exposes the front side 12a of each pre-wiring substrate 12, and the front side 13a of the plastic encapsulation layer 13 exposes the active surface 11a of each first bare chip 11.

[0128] In this embodiment, step S2 specifically includes steps S21 to S22.

[0129] Step S21: Refer to Figure 5 As shown, a plastic sealing layer 13 is formed on the surface of the carrier board 3 to embed each group of plastic sealing parts 2; Figure 6 As shown, the plastic encapsulation layer 13 is thinned until the front side 12a of each pre-wiring substrate 12 is exposed.

[0130] The material of the plastic encapsulation layer 13 can be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer or polyvinyl alcohol. The material of the plastic encapsulation layer 13 can also be various polymers or composite materials of resin and polymer. Correspondingly, the encapsulation can be performed by filling liquid plastic encapsulation material between the stacking structure of each first bare chip 11 and the pre-wiring substrate 12, and then curing it at high temperature through the plastic encapsulation mold. In some embodiments, the plastic encapsulation layer 13 can also be formed by plastic material molding methods such as hot pressing molding and transfer molding.

[0131] The plastic packaging layer 13 may include a front surface 13 a and a back surface 13 b opposite to each other.

[0132] Reference Figure 6 As shown, the plastic encapsulation layer 13 is thinned from the back side 13 b by mechanical grinding, such as grinding with a grinding wheel, to expose the back side 12 b of the pre-wiring substrate 12 .

[0133] During the process of forming the plastic encapsulation layer 13 and grinding the plastic encapsulation layer 13 , the first protection layer 110 can buffer the stress of the first pad 111 .

[0134] Step S22: Refer to Figure 7 As shown, the carrier board 3 is removed to expose the first protection layer 110 , the first pad 111 and the front side 13 a of the plastic packaging layer 13 .

[0135] The carrier board 3 may be removed by conventional removal methods such as laser stripping and UV irradiation.

[0136] After removing the carrier 3, a first support plate 4 may be further provided on the front surface 12a of the pre-wiring substrate 12 and the back surface 13b of the plastic encapsulation layer 13. The first support plate 4 is a hard plate member, and may include a glass plate, a ceramic plate, a metal plate, etc. The first support plate 4 may play a supporting role in the subsequent steps of forming the first conductive trace 15, and / or forming the first conductive bump 16, and / or forming the first dielectric layer 17.

[0137] In other embodiments, steps S1', S21' to S22' may also be included.

[0138] Step S1 ′ is substantially the same as step S1 , with the only difference being that in each group of components 2 to be encapsulated, the front surface 12 a of each pre-wiring substrate 12 faces the carrier 3 .

[0139] Step S21′ is substantially the same as step S21, except that the plastic encapsulation layer 13 is thinned until the active surface 11a of each first die 11 is exposed. When the active surface 11a has a first protective layer 110, the first protective layer 110 is exposed. The first protective layer 110 protects the first pad 111 when the plastic encapsulation layer 13 is thinned.

[0140] Step S22 ′ is substantially the same as step S22 , except that after the carrier 3 is removed, the front surface 12 a of each pre-wiring substrate 12 and the back surface 13 b of the plastic packaging layer 13 are exposed.

[0141] Next, refer to Figure 2 Step S3 in Figure 8 and Fig. 9 As shown, a plurality of conductive plugs 14 are formed in the plastic encapsulation layer 13. The conductive plugs 14 are located on the side of the first bare chip 11. The conductive plugs 14 include a first end 14a and a second end 14b opposite to each other. The first end 14a is connected to the back electrical connection point 122, and the second end 14b is exposed to the front side 13a of the plastic encapsulation layer 13. A first conductive trace 15 is formed on the first pad 111, the second end 14b of the conductive plug 14, and the front side 13a of the plastic encapsulation layer 13 to electrically connect the first bare chip 11 in the group with the pre-wiring circuit 120.

[0142] In this embodiment, refer to Figure 8 As shown, a plurality of through holes 141 may be formed in the plastic encapsulation layer 13 , and the bottoms of the through holes 141 expose the back electrical connection points 122 .

[0143] The through hole 141 may be formed by dry etching, wet etching or laser drilling.

[0144] In other embodiments, in the first die 11 , if the first pad 111 is covered with the first protection layer 110 , before the first conductive trace 15 is fabricated, a first opening 110 a is formed in the first protection layer 110 to expose the first pad 111 .

[0145] If the material of the first protective layer 110 is a laser-reactive material, such as epoxy resin, etc., the first opening 110a can be formed by modifying it by laser irradiation. If the material of the first protective layer 110 is a photosensitive material, such as polyimide, etc., the first opening 110a can be formed by first exposing and then developing. If the material of the first protective layer 110 is a material that can be dry-etched or wet-etched, such as silicon dioxide, silicon nitride, etc., the first opening 110a can be formed by dry-etching or wet-etching.

[0146] In this embodiment, forming the first conductive trace 15 includes the following steps S311 - S314 .

[0147] Step S311 : forming a photoresist layer on the first protection layer 110 of each first bare chip 11 , the first pad 111 exposed by the first protection layer 110 , the front surface 13 a of the plastic layer 13 , and in each through hole 141 .

[0148] In this step S311, in an optional solution, the photoresist layer formed may be a photosensitive film. The photosensitive film may be torn off from the tape and applied to the first protective layer 110 of each first bare chip 11, each first pad 111, the front surface 13a of the plastic layer 13, and the opening of each through hole 141. In other optional solutions, the photoresist layer may also be formed by first applying a liquid photoresist and then heating and curing it.

[0149] Step S312: exposing and developing the photoresist layer, and retaining the photoresist layer in a first predetermined area, the first predetermined area being complementary to the area where the metal pattern block 15a of the first conductive trace 15 to be formed is located.

[0150] Step S313 : filling a metal layer in a complementary region of the first predetermined region to form a conductive plug 14 and a metal pattern block 15 a of the first conductive trace 15 .

[0151] In other embodiments, a metal layer may be first filled into the through hole 141 to form the conductive plug 14 , and then the first conductive trace 15 may be manufactured.

[0152] A portion of the metal pattern blocks 15a selectively electrically connects the second end 14b of the conductive plug 14 with the first pad 111 to achieve electrical connection between the pre-wiring circuit 120 and the first die 11. In addition, a portion of the metal pattern blocks 15a selectively electrically connects a plurality of first pads 111 to achieve circuit layout or electrical conduction of the first pads 111.

[0153] This step S313 can be completed by using an electroplating process. The electroplating process of copper or aluminum is relatively mature.

[0154] Specifically, before forming the photoresist layer in step S311, a seed layer (Seed Layer) can be formed by physical vapor deposition or chemical vapor deposition on the first protective layer 110 of each first bare chip 11, the first pad 111 exposed by the first protective layer 110, the front surface 13a of the plastic layer 13, and each through hole 141. The seed layer can be used as a power supply layer for electroplating copper or aluminum.

[0155] Electroplating may include electrolytic plating or electrodeless plating. Electrolytic plating is to use the workpiece to be plated as a cathode to electrolyze the electrolyte to form a layer of metal on the workpiece to be plated. Electroless plating is a method of reducing and precipitating metal ions in the solution to form a metal layer on the workpiece to be plated. In some embodiments, the conductive plug 14 and the metal pattern block 15a may also be formed by sputtering first and then etching.

[0156] Step S314: removing the remaining photoresist layer in the first predetermined area by ashing.

[0157] After ashing, the seed layer in the first predetermined area is removed by dry etching or wet etching.

[0158] The metal pattern block 15 a of the first conductive trace 15 may be polished, for example, by chemical mechanical polishing to achieve a smooth upper surface.

[0159] It should be noted that the metal pattern blocks 15a of the first conductive traces 15 in step S3 are arranged according to design requirements, and the distribution of the first conductive traces 15 on different groups of parts 2 to be encapsulated may be the same or different.

[0160] Afterwards, refer to Figure 2 Step S4 in Fig. 9 As shown, a first conductive bump 16 is formed on the first conductive trace 15 , and a first dielectric layer 17 is formed to embed the first conductive trace 15 and the first conductive bump 16 . The first conductive bump 16 is exposed outside the first dielectric layer 17 .

[0161] Forming the first conductive bump 16 and the first dielectric layer 17 may include steps S411 - S415 .

[0162] Step S411 : forming a photoresist layer on the metal pattern block 15 a , the first protection layer 110 exposed by the metal pattern block 15 a , and the front surface 13 a of the plastic layer 13 .

[0163] In this step S411, in an optional solution, the photoresist layer formed can be a photosensitive film. The photosensitive film can be torn off from the tape and applied to the metal pattern block 15a, the first protective layer 110 exposed by the metal pattern block 15a, and the front side 13a of the plastic layer 13. In other optional solutions, the photoresist layer can also be formed by first applying a liquid photoresist and then heating and curing.

[0164] Step S412: exposing and developing the photoresist layer to retain the photoresist in the second predetermined area. The second predetermined area is complementary to the area where the first conductive bump 16 is to be formed.

[0165] In this step S412, the photoresist layer is patterned. In other optional solutions, other easily removable sacrificial materials can also be used to replace the photoresist layer.

[0166] Step S413 : filling a metal layer in a complementary region of the second predetermined region to form a first conductive bump 16 .

[0167] This step S413 can be completed by electroplating. The process of electroplating copper or aluminum is relatively mature. Before electroplating copper or aluminum, a seed layer (Seed Layer) can be firstly physically vapor deposited or chemically vapor deposited as a power supply layer.

[0168] Step S414: removing the remaining photoresist layer in the second predetermined area by ashing.

[0169] The first conductive bump 16 can be smoothed on its upper surface by a polishing process, such as chemical mechanical polishing.

[0170] Step S415: Refer to Fig. 9 As shown, a first dielectric layer 17 is formed on the first conductive bump 16, the metal pattern block 15a, the first protection layer 110 exposed by the metal pattern block 15a, and the front surface 13a of the plastic layer 13; the first dielectric layer 17 is thinned until the first conductive bump 16 is exposed.

[0171] The first dielectric layer 17 is an insulating material, which may be an organic high molecular polymer insulating material, or an inorganic insulating material or a composite material. The organic high molecular polymer insulating material may be, for example, polyimide, epoxy resin, ABF (Ajinomoto buildup film), PBO (Polybenzoxazole), an organic polymer film or other organic materials with similar insulating properties. The composite material may be an inorganic-organic composite material, which may be an inorganic-organic polymer composite material, such as a SiO2 / resin polymer composite material.

[0172] The organic high molecular polymer insulating material can be pressed onto the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front side 13a of the plastic encapsulation layer 13 by a) a lamination process, or b) first coated on the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front side 13a of the plastic encapsulation layer 13 and then cured, or c) cured on the first conductive trace 15, the first conductive bump 16, the first protective layer 110 not covering the first conductive trace 15, and the front side 13a of the plastic encapsulation layer 13 by an injection molding process.

[0173] When the first dielectric layer 17 is made of inorganic insulating materials such as silicon dioxide or silicon nitride, it can be formed on the first conductive traces 15 , the first conductive bumps 16 , the first protection layer 110 not covering the first conductive traces 15 , and the front surface 13 a of the plastic layer 13 by a deposition process.

[0174] Compared with inorganic insulating materials, organic high molecular polymer insulating materials and composite materials have smaller tensile stress, which can prevent the plastic package from warping when the first dielectric layer 17 is formed over a large area.

[0175] The first dielectric layer 17 may include one or more layers.

[0176] When the first dielectric layer 17 covers the first conductive bump 16 , the first dielectric layer 17 is polished until the first conductive bump 16 is exposed.

[0177] After the first conductive bump 16 is exposed, in the optional solution a), refer to Fig. 9 As shown, the first conductive bump 16 serves as an external connection terminal of the semiconductor package structure 1 .

[0178] b) In an optional solution, after the first conductive bump 16 is exposed, an anti-oxidation layer is further formed on the first conductive bump 16 .

[0179] The anti-oxidation layer may include: b1) a tin layer, or b2) a nickel layer and a gold layer stacked from bottom to top, or b3) a nickel layer, a palladium layer and a gold layer stacked from bottom to top. The anti-oxidation layer may be formed by an electroplating process. The material of the first conductive bump 16 may be copper, and the anti-oxidation layer may prevent copper oxidation, thereby preventing the electrical connection performance from being deteriorated due to copper oxidation.

[0180] After the first conductive bump 16 is exposed, refer to Fig.10 As shown, the first support plate 4 is removed.

[0181] The first support plate 4 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0182] After removing the first support plate 4 , a second support plate 5 may be disposed on the first conductive bump 16 and the first dielectric layer 17 .

[0183] The second support plate 5 is a hard plate, which may include a glass plate, a ceramic plate, a metal plate, etc. The second support plate 5 may play a supporting role in the subsequent process of setting the passive device 18 .

[0184] Next, refer to Figure 2 Step S5 in Fig.10 As shown, each passive device 18 is electrically connected to the corresponding front electrical connection point 121 of the pre-wiring substrate 12 .

[0185] The passive device 18 may include resistors, inductors, and capacitors, and their common feature is that they can work when there is a signal without adding power to the circuit. The passive device 18 includes an electrical connection point, which is connected to the front electrical connection point 121 of the pre-wiring substrate 12 to achieve the electrical signal input / output of the passive device 18. The electrical connection point of the passive device 18 and the front electrical connection point 121 of the pre-wiring substrate 12 can be connected together by soldering.

[0186] In some embodiments, the plastic encapsulation layer 13 is thinned until the front surface 12 a of the pre-wiring substrate 12 is exposed. This may also be performed after step S4 is completed and before step S5 is started.

[0187] After the passive device 18 is set, refer to Fig.11 As shown, the second support plate 5 is removed.

[0188] The second support plate 5 can be removed by conventional removal methods such as laser stripping and UV irradiation.

[0189] Afterwards, refer to Figure 2 Step S6 in Fig.11 and Figure 1 As shown, a plurality of semiconductor package structures 1 are formed by cutting, and each semiconductor package structure 1 includes a group of parts 2 to be encapsulated.

[0190] For the embodiment in which the pre-wiring substrates 12 of each group of the components 2 to be encapsulated are connected together, the pre-wiring substrates 12 are cut apart during the cutting process in step S6 .

[0191] The advantages of using a pre-wiring substrate 12 in the semiconductor packaging structure 1 formed through the above steps are: first, the fine wiring in the rewiring layer is transferred to the pre-wiring substrate 12, which reduces the probability of short circuit and increases the product yield. At the same time, the number of layers of the first conductive trace 15 can be reduced, and the complexity of the process can be reduced. Second, a pre-formed pre-wiring substrate 12 is provided, and the pre-wiring substrate 12 can be tested before packaging to avoid using a known bad pre-wiring substrate 12. Third, the pre-wiring substrate 12 is a prefabricated substrate, and its manufacturing process is independent of the packaging process, which can save the packaging time of the entire packaging process.

[0192] In addition, the wiring layer to be formed on the active surface 11a of the die is transferred to the pre-wiring substrate 12. The pre-wiring substrate 12 includes complex multi-circuits, which are embedded in the semiconductor package structure 1 by being electrically connected to the pads 111 on the active surface 11a of the die, thereby improving the performance of the entire semiconductor package structure 1. Through the pre-wiring substrate 12, the passive device 18 is also incorporated into the semiconductor package structure 1, enriching the function of the semiconductor package structure 1.

[0193] Fig.12 FIG. 2 is a schematic cross-sectional view of a semiconductor package structure according to a second embodiment of the present invention. Fig.12 As shown, the semiconductor package structure 6 in this embodiment is substantially the same as the semiconductor package structure 1 in the above-mentioned embodiment, except that:

[0194] The second conductive trace 19 is located on the first conductive bump 16 and the first dielectric layer 17;

[0195] A second conductive bump 20 connected to the second conductive trace 19;

[0196] The second dielectric layer 21 embeds the second conductive trace 19 and the second conductive bump 20 , and the second conductive bump 20 is exposed outside the second dielectric layer 21 .

[0197] In other words, in this embodiment, the second conductive bumps 20 on the second conductive traces 19 serve as external connection terminals of the semiconductor package structure 6 .

[0198] Fig.12 In the illustrated embodiment, the second conductive trace 19 includes a plurality of metal pattern blocks 19 a having one layer. The second conductive trace 19 can realize a re-circuit layout of the first conductive trace 15 and the first conductive bump 16 .

[0199] Accordingly, the manufacturing method is different from the above-mentioned embodiment in that after step S4 and before step S5, the following steps are further performed:

[0200] forming a second conductive trace 19 on the first conductive bump 16 and the first dielectric layer 17;

[0201] A second conductive bump 20 is formed on the second conductive trace 19 , and a second dielectric layer 21 is formed to embed the second conductive trace 19 and the second conductive bump 20 . The second conductive bump 20 is exposed outside the second dielectric layer 21 .

[0202] The material and the forming process of the second conductive trace 19 may refer to the material and the forming process of the first conductive trace 15 .

[0203] The material and the forming process of the second conductive bump 20 may refer to the material and the forming process of the first conductive bump 16 .

[0204] The material and formation process of the second dielectric layer 21 may refer to the material and formation process of the first dielectric layer 17 .

[0205] In other embodiments, one or more layers of conductive trace layout may be provided between the second conductive trace 19 and the first conductive bump 16 .

[0206] Fig.13 FIG. 1 is a schematic cross-sectional view of a semiconductor package structure according to a third embodiment of the present invention. Fig.13 As shown, the semiconductor package structure 7 in this embodiment is substantially the same as the semiconductor package structures 1 and 6 in the aforementioned embodiments, with the only difference being that: the first protective layer 110 is omitted, and the active surface 11a of the first bare chip 11, the second end 14b of the conductive plug 14 and the front surface 13a of the plastic layer 13 are provided with a third dielectric layer 22; the third dielectric layer 22 has a third opening 22a exposing the first pad 111 and the second end 14b of the conductive plug 14; and the first conductive trace 15 is located on the first pad 111, the second end 14b of the conductive plug 14 and the third dielectric layer 22.

[0207] Accordingly, the manufacturing method is different from the aforementioned embodiment in that: in step S3, before forming the first conductive trace 15, a third dielectric layer 22 is formed on the exposed active surface 11a of the first bare chip 11, the second end 14b of the conductive plug 14, and the front surface 13a of the plastic layer 13; a plurality of third openings 22a are formed in the third dielectric layer 22, and the third openings 22a expose the first pad 111 and the second end 14b of the conductive plug 14; and then the first conductive trace 15 is formed on the first pad 111, the second end 14b of the conductive plug 14, and the third dielectric layer 22.

[0208] The material of the third dielectric layer 22 refers to the material of the first dielectric layer 17 .

[0209] If the material of the third dielectric layer 22 is a laser-reactive material, such as epoxy resin, etc., the third opening 22a can be formed by modifying it by laser irradiation. If the material of the third dielectric layer 22 is a photosensitive material, such as polyimide, etc., the third opening 22a can be formed by first exposing and then developing. If the material of the third dielectric layer 22 is a dry-etchable or wet-etchable material, such as silicon dioxide, silicon nitride, etc., the third opening 22a can be formed by dry-etching or wet-etching.

[0210] Fig.14 FIG. 4 is a schematic cross-sectional view of a semiconductor package structure according to a fourth embodiment of the present invention. Fig.14 As shown, the semiconductor packaging structure 8 in this embodiment is substantially the same as the semiconductor packaging structures 1 and 6 in the aforementioned embodiments, with the only difference being that: it also includes: a second die 23, the second die 23 includes a plurality of second solder pads 231, and the second solder pads 231 are located on the active surface 23a of the second die 23; the active surface 23a of the second die 23 is covered with a second protective layer 230, and the second protective layer 230 exposes the second solder pads 231; the back side 23b of the second die 23 and the back side 12b of the pre-wiring substrate 12 are facing each other; the plastic encapsulation layer 13 also covers the second die 23; the conductive plug 14 is also located on the side of the second die 23; the first conductive trace 15 is also located on the second solder pad 231, and is used to electrically connect the first die 11, the second die 23 and the pre-wiring circuit 120.

[0211] The second die 23 includes an active surface 23a and a back surface 23b opposite to each other. A second pad 231 is exposed on the active surface 23a. The second die 23 may include a variety of devices formed on a semiconductor substrate, and an electrical interconnection structure electrically connected to each device. The second pad 231 is connected to the electrical interconnection structure for inputting / outputting electrical signals of each device.

[0212] The material and the forming method of the second protection layer 230 may refer to the material and the forming method of the first protection layer 110 .

[0213] Accordingly, the manufacturing method of the semiconductor packaging structure 8 is different from the above-mentioned embodiment in that in step S1 , each group of components 2 to be encapsulated further includes a second die 23 , and the active surface 23 a of the second die 23 also faces the carrier 3 .

[0214] For the method of forming the plastic encapsulation layer 13 in step S2 , the first die 11 and the second die 23 need to have the same thickness. The thickness of the first die 11 and the second die 23 can be controlled by controlling the thickness of the first protective layer 110 and the second protective layer 230 to achieve the same thickness.

[0215] Regarding the method for forming the plastic encapsulation layer 13 in step S2 ′, the thickness of the first die 11 and the second die 23 can be made the same during the process of thinning the plastic encapsulation layer 13 .

[0216] Before the molding, the second protective layer 230 may have a second opening 230a for exposing the second pad 231. Alternatively, before the molding, the second protective layer 230 may also cover the second pad 231, and the second opening 230a is made before forming the first conductive trace 15.

[0217] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first die, the first die comprising a plurality of first pads, the first pads being located on an active surface of the first die; A pre-wiring substrate, wherein a pre-wiring circuit is provided in the pre-wiring substrate, wherein the pre-wiring circuit includes a front electrical connection point and a back electrical connection point, wherein the front electrical connection point is exposed on the front side of the pre-wiring substrate, and the back electrical connection point is exposed on the back side of the pre-wiring substrate; the back side of the pre-wiring substrate faces the back side of the first bare chip; A plastic encapsulation layer, covering the first bare chip and the pre-wiring substrate, wherein the back side of the plastic encapsulation layer exposes the front side of the pre-wiring substrate, and the front side of the plastic encapsulation layer exposes the active surface of the first bare chip; A plurality of conductive plugs are located in the plastic encapsulation layer and on the side of the first die, the conductive plugs comprising a first end and a second end opposite to each other, the first end is connected to the back electrical connection point, and the second end is exposed to the front side of the plastic encapsulation layer; A first conductive trace, located on the first pad, the second end of the conductive plug and the front side of the plastic layer, for electrically connecting the first die to the pre-wiring circuit; a first conductive bump connected to the first conductive trace; a first dielectric layer, embedding the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; as well as A passive device is electrically connected to the front electrical connection point of the pre-wiring substrate.

2. The semiconductor package structure according to claim 1, wherein: The active surface of the first bare chip is covered with a first protective layer, and the first protective layer exposes the first pad; the front side of the plastic layer exposes the first protective layer and the first pad; and the first conductive trace is also located on the first protective layer.

3. The semiconductor package structure according to claim 2, characterized in that: Also includes: A second die, the second die comprises a plurality of second pads, the second pads are located on the active surface of the second die; the active surface of the second die is covered with a second protective layer, the second protective layer exposes the second pads; the back surface of the second die faces the back surface of the pre-wiring substrate; the plastic encapsulation layer also covers the second die; the conductive plug is also located on the side of the second die; the first conductive trace is also located on the second pad, for electrically connecting the first die, the second die and the pre-wiring circuit.

4. The semiconductor package structure according to claim 1, wherein: Also includes: A third dielectric layer is located on the active surface of the first die, the second end of the conductive plug and the front surface of the plastic packaging layer; The third dielectric layer exposes the first pad and the second end of the conductive plug; the first conductive trace is located on the first pad, the second end of the conductive plug and the third dielectric layer.

5. The semiconductor package structure according to claim 1, wherein: Also includes: a second conductive trace located on the first conductive bump and the first dielectric layer; a second conductive bump connected to the second conductive trace; The second dielectric layer embeds the second conductive trace and the second conductive bump, and the second conductive bump is exposed outside the second dielectric layer.

6. A method for manufacturing a semiconductor packaging structure, characterized in that: include: A plurality of groups of parts to be encapsulated are provided, each group of the parts to be encapsulated comprises: a first bare chip, the first bare chip comprises a plurality of first pads, the first pads are located on the active surface of the first bare chip; a pre-wiring substrate, the pre-wiring substrate is provided with a pre-wiring circuit, the pre-wiring circuit comprises a front electrical connection point and a back electrical connection point, the front electrical connection point is exposed on the front of the pre-wiring substrate, and the back electrical connection point is exposed on the back of the pre-wiring substrate; the back of the pre-wiring substrate faces the back of the first bare chip; Forming a plastic encapsulation layer, wherein the plastic encapsulation layer covers the plurality of groups of components to be encapsulated, the back side of the plastic encapsulation layer exposes the front side of each of the pre-wiring substrates, and the front side of the plastic encapsulation layer exposes the active surface of each of the first bare chips; A plurality of conductive plugs are formed in the plastic layer, the conductive plugs are located at the side of the first bare die, the conductive plugs include a first end and a second end opposite to each other, the first end is connected to the back electrical connection point, and the second end is exposed to the front side of the plastic layer; a first conductive trace is formed on the first pad, the second end of the conductive plug and the front side of the plastic layer to electrically connect the first bare die in the group with the pre-wiring circuit; forming a first conductive bump on the first conductive trace and forming a first dielectric layer that buries the first conductive trace and the first conductive bump, wherein the first conductive bump is exposed outside the first dielectric layer; electrically connecting each passive device to the corresponding front electrical connection point of the pre-wiring substrate; A plurality of semiconductor packaging structures are formed by cutting, each of which includes a group of the parts to be encapsulated.

7. The method for manufacturing a semiconductor package structure according to claim 6, wherein: The plurality of groups of components to be encapsulated are carried on a carrier, and the active surface of each of the first bare chips faces the carrier; The forming of the plastic sealing layer comprises: Forming a plastic sealing layer on the surface of the carrier board to embed each group of the components to be plastic sealed; The carrier is removed to expose the active surface of each of the first bare chips and the front side of the plastic encapsulation layer; before removing the carrier or after forming the first dielectric layer, the plastic encapsulation layer is thinned until the front side of each of the pre-wiring substrates is exposed.

8. The method for manufacturing a semiconductor package structure according to claim 7, characterized in that: The active surface of the first die is covered with a first protection layer, and the first protection layer has a first opening exposing the first pad; the first opening is used as an alignment pattern feature to arrange the first die on the carrier according to a predetermined arrangement position.

9. The method for manufacturing a semiconductor package structure according to claim 7, wherein: The back side of the first die has an alignment mark to apply the pre-wiring substrate to the back side of the first die.

10. The method for manufacturing a semiconductor package structure according to claim 6, wherein: The plurality of groups of components to be encapsulated are carried on a carrier, and the front side of each pre-wiring substrate faces the carrier; The forming of the plastic sealing layer comprises: Forming a plastic encapsulation layer on the surface of the carrier board to embed each group of the components to be plastic encapsulated; thinning the plastic encapsulation layer until the active surface of each of the first bare chips is exposed; The carrier board is removed to expose the front side of each pre-wiring substrate and the back side of the plastic encapsulation layer.

11. The method for manufacturing a semiconductor package structure according to claim 10, wherein: The active surface of the first die is covered with a first protective layer; the plastic encapsulation layer is thinned until the first protective layer is exposed; before forming the first conductive trace, a first opening is formed in the first protective layer to expose the first pad; or The active surface of the first die is covered with a first protection layer, and the first protection layer has a first opening exposing the first pad; The plastic packaging layer is thinned until the first protection layer and the first pad are exposed.

12. The method for manufacturing a semiconductor package structure according to claim 11, characterized in that: Each group of the parts to be encapsulated also includes: a second bare chip, the second bare chip includes a plurality of second pads, the second pads are located on the active surface of the second bare chip; the active surface of the second bare chip is covered with a second protective layer; the back surface of the second bare chip faces the back surface of the pre-wiring substrate.

13. The method for manufacturing a semiconductor package structure according to any one of claims 6 to 12, characterized in that: The pre-wiring substrates of each group of the parts to be plastic-encapsulated are connected together and are cut apart in the step of cutting to form a plurality of semiconductor packaging structures.

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