Semiconductor structure preparation method and semiconductor structure

Abstract

The present invention provides a method for preparing a semiconductor structure and a semiconductor structure; the method for preparing a semiconductor structure comprises the following steps: providing a substrate; forming a bottom contact structure in the substrate; forming a storage unit on the bottom contact structure; forming a shielding structure covering the storage unit, wherein the shielding structure comprises a plurality of dielectric layers and shielding layers arranged alternately. The present invention enables the semiconductor structure to realize multiple reflections and absorption of electromagnetic fields by using the shielding layers and dielectric layers, so as to achieve a better shielding effect on the electromagnetic field.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] The information storage function of magnetic random access memory (MRAM) is realized by the magnetic polarization of the magnetic tunnel junction (MTJ) in the memory structure. However, the magnetic polarization of the magnetic tunnel junction may be affected by the external electromagnetic field. For example, the external electromagnetic field will distort or change the spin direction of the magnetic tunnel junction, which may interfere with the stored information. The existing magnetic random access memory adopts a chip-level shielding structure and cannot provide a strong anti-interference function against the external electromagnetic field. Summary of the invention

[0003] The invention provides a method for preparing a semiconductor structure having a better shielding effect against an external electromagnetic field.

[0004] To achieve the above object, the present invention adopts the following technical solution:

[0005] According to one aspect of the present invention, a method for preparing a semiconductor structure is provided, wherein the method comprises the following steps: providing a substrate; forming a bottom contact structure in the substrate; forming a storage unit on the bottom contact structure; forming a shielding structure covering the storage unit, wherein the shielding structure comprises a plurality of alternatingly arranged dielectric layers and shielding layers.

[0006] Optionally, the shielding structure includes a first dielectric layer, a first shielding layer, a second dielectric layer and a second shielding layer sequentially coated on the storage unit.

[0007] Optionally, the method for forming a bottom contact structure in the substrate includes: forming a third shielding material layer, a third dielectric material layer, a fourth shielding material layer and a fourth dielectric material layer in sequence on the substrate; forming a plurality of bottom contact holes in the substrate, the bottom contact holes penetrating the third shielding material layer, the third dielectric material layer, the fourth shielding material layer and the fourth dielectric material layer; and filling the bottom contact holes with conductive material.

[0008] Optionally, the method for forming a storage unit on the bottom contact structure includes: sequentially forming a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer and a top electrode material layer on the fourth dielectric material layer; forming a mask layer having an opening pattern on the top electrode material layer; and etching the bottom electrode material layer, the free material layer, the tunneling barrier material layer, the fixed material layer and the top electrode material layer using the mask layer to form a plurality of discrete storage units on the fourth dielectric material layer, wherein the storage units are connected to the bottom contact structure one-to-one.

[0009] Optionally, the method for forming a shielding structure covering the storage unit includes: forming a fifth dielectric material layer on the surface of the storage unit; partially removing the fourth dielectric material layer between the storage units; forming a fifth shielding material layer on the surface of the fifth dielectric material layer; partially removing the fourth shielding material layer between the storage units; partially removing the third dielectric material layer between the storage units; forming a sixth dielectric material layer on the surface of the fifth shielding material layer; forming a sixth shielding material layer on the surface of the sixth dielectric material layer; and partially removing the third shielding material layer between the storage units.

[0010] Optionally, in the step of partially removing the fourth dielectric material layer between the storage cells, the fourth dielectric material layer is retained below the fifth dielectric material layer on the side wall of the storage cell; in the step of partially removing the fourth shielding material layer between the storage cells, the fourth shielding material layer is retained below the fifth shielding material layer on the side wall of the storage cell; in the step of partially removing the third dielectric material layer between the storage cells, the third dielectric material layer is retained below the fifth shielding material layer on the side wall of the storage cell; in the step of partially removing the third shielding material layer between the storage cells, the third shielding material layer is retained below the sixth shielding material layer on the side wall of the storage cell.

[0011] Optionally, the first dielectric layer includes the fifth dielectric material layer and the fourth dielectric material layer connected as one; the first shielding layer includes the fifth shielding material layer and the fourth shielding material layer connected as one; the second dielectric layer includes the third dielectric material layer and the sixth dielectric material layer connected as one; the second shielding layer includes the third shielding material layer and the sixth shielding material layer connected as one.

[0012] Optionally, the method further includes: forming a top contact structure on the storage unit, wherein the top contact structure passes through the shielding layer and is connected to the top electrode material layer.

[0013] The present invention also provides a semiconductor structure, characterized in that it includes: a substrate; a bottom contact structure and a storage unit located on the substrate, the bottom contact structure is connected to the bottom of the storage unit; a shielding structure, the shielding structure is coated on the periphery of the storage unit, wherein the shielding structure includes a plurality of alternatingly arranged dielectric layers and shielding layers.

[0014] Optionally, the shielding structure includes a first dielectric layer, a first shielding layer, a second dielectric layer and a second shielding layer sequentially coated on the storage unit.

[0015] Optionally, the dielectric layer and the shielding layer are also located below the storage unit.

[0016] Optionally, the storage unit includes a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer and a top electrode layer, wherein the bottom contact structure is connected to the bottom electrode material layer; and also includes: a top contact structure, wherein the top contact structure is connected to the top electrode material layer.

[0017] Optionally, the top electrode material layer has a curved top.

[0018] Optionally, the shielding structure has a flush top surface.

[0019] Optionally, the top electrode material layer and the shielding structure have flush top surfaces.

[0020] The semiconductor structure preparation method and semiconductor structure proposed by the present invention adopt a method of forming multiple dielectric layers and multiple shielding layers outside the storage unit, and the dielectric layers and the shielding layers are arranged alternately. The semiconductor structure can use the shielding layers and dielectric layers to achieve multiple reflections and absorption of electromagnetic fields, and can achieve better shielding effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Various objects, features and advantages of the present invention will become more apparent by considering the following detailed description of preferred embodiments of the present invention in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present invention and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0022] Figures 1 to 19 They are schematic structural diagrams of a semiconductor structure at multiple steps of a method for preparing a semiconductor structure according to an exemplary embodiment;

[0023] Fig. 20 yes Fig.19 A cross-sectional view of the semiconductor structure along line XX according to the method shown;

[0024] Fig.21 yes Fig.19 A schematic diagram of the external electromagnetic field shielding principle of a semiconductor structure according to the method shown;

[0025] Fig. 22 is a schematic structural diagram of a semiconductor structure according to another exemplary embodiment;

[0026] Fig.23 yes Figure 5 A magnified image of the storage material layer. DETAILED DESCRIPTION

[0027] Typical embodiments that embody the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various changes in different embodiments without departing from the scope of the present invention, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present invention.

[0028] In the following description of different exemplary embodiments of the present invention, reference is made to the accompanying drawings, which form a part of the present invention and in which different exemplary structures, systems and steps that can implement multiple aspects of the present invention are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present invention. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present invention, these terms are used herein only for convenience, such as according to the direction of the examples described in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present invention.

[0029] See also Figures 1 to 20 As described above, it is representatively shown as a schematic diagram of the structure of the semiconductor structure under multiple steps of the method for preparing the semiconductor structure proposed by the present invention. In this exemplary embodiment, the method for preparing the semiconductor structure proposed by the present invention is described by taking the application to magnetic random access memory as an example. It is easy for those skilled in the art to understand that in order to apply the relevant design of the present invention to other types of semiconductor devices (such as phase change memory, resistance memory, ferroelectric memory, etc.) or other methods, various modifications, additions, substitutions, deletions or other changes are made to the specific embodiments described below, and these changes are still within the scope of the principle of the method for preparing the semiconductor structure proposed by the present invention.

[0030] like Figures 1 to 19 As shown, in this embodiment, the method for preparing a semiconductor structure provided by the present invention comprises at least the following steps:

[0031] Providing a substrate 110;

[0032] forming a bottom contact structure 130 in the substrate 110;

[0033] forming a memory cell 610 on the bottom contact structure 130;

[0034] A shielding structure covering the storage unit 610 is formed, wherein the shielding structure includes a plurality of alternately arranged dielectric layers and shielding layers.

[0035] The present invention forms multiple dielectric layers and multiple shielding layers outside the storage unit 610, and the dielectric layers and the shielding layers are arranged alternately, which can enhance the reflection and absorption of external electromagnetic fields and achieve better shielding effect.

[0036] For example, in this embodiment, the shielding structure may include a first dielectric layer 500, a first shielding layer 300, a second dielectric layer 400, and a second shielding layer 200 sequentially coated on the storage unit 610. In other embodiments, the preparation method proposed in the present invention may also form more than two shielding layers and dielectric layers alternately arranged with these shielding layers outside the storage unit 610, for example, Fig. 22 FIG. 1 is a schematic structural diagram of another embodiment of the semiconductor structure provided by the present invention.

[0037] For example, Figures 1 to 14 As shown, the method of forming the bottom contact structure 130 in the substrate 110 may include the following steps:

[0038] like Figures 1 to 3 As shown, a third shielding material layer 210 , a third dielectric material layer 410 , a fourth shielding material layer 310 and a fourth dielectric material layer 510 are sequentially formed on the substrate 110 .

[0039] Optionally, the substrate 110 may be silicon oxide, silicon nitride, etc.; it may also be a semiconductor substrate such as silicon, germanium, gallium carbide, gallium arsenide, etc.

[0040] Optionally, in this embodiment, the material of the third shielding material layer 210 and the fourth shielding material layer 310 may include an alloy of iron (Fe), cobalt (Co) and nickel (Ni), such as cobalt iron, nickel iron and nickel cobalt iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys, etc. In addition, the material of each shielding material layer may be, but is not limited to, the same. The third shielding material layer 210 and the fourth shielding material layer 310 may be formed by PVD or CVD.

[0041] Optionally, in this embodiment, the materials of the third dielectric material layer 410 and the fourth dielectric material layer 510 include SiN, SiO2, NDC, BD (Black Diamond), etc. The materials of each dielectric material layer can be, but are not limited to, the same. The third dielectric material layer 410 and the fourth dielectric material layer 510 can be formed by PVD or CVD.

[0042] like Figure 4 As shown, a plurality of bottom contact holes 120 are formed in the substrate 110, and the bottom contact holes 120 penetrate the third shielding material layer 210, the third dielectric material layer 410, the fourth shielding material layer 310, and the fourth dielectric material layer 510. Specifically, a mask layer may be formed on the fourth dielectric material layer 510, and a photolithography pattern layer, such as a photoresist layer with an opening pattern, may be formed on the mask layer. The third shielding material layer 210, the third dielectric material layer 410, the fourth shielding material layer 310, the fourth dielectric material layer 510, and the substrate 130 may be etched using the photolithography pattern layer and the mask layer to form the bottom contact holes 120 penetrating the third shielding material layer 210, the third dielectric material layer 410, the fourth shielding material layer 310, and the fourth dielectric material layer 510, and the bottom of the bottom contact holes 120 is located in the substrate 110. The mask layer may be a multi-layer film structure or a single-layer film structure, such as any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a carbon layer, or any combination thereof.

[0043] like Figure 5 As shown, a conductive material is filled in the bottom contact hole 120 to form a bottom contact structure 130. Specifically, the conductive material may include a semiconductor conductive material, such as polysilicon, etc., or may include a metal conductive material, such as tungsten, cobalt, etc. A conductive material layer may be formed on the surface of the bottom contact hole 120 and the fourth dielectric material layer 510 by PVD, CVD, ALD, etc., and the conductive material layer on the fourth dielectric material layer 510 may be removed by etching back or CMP process, and the conductive material layer retained in the bottom contact hole 120 forms the bottom contact structure 130, and the upper surface of the bottom contact structure 130 is exposed to the upper surface of the fourth dielectric material layer 510.

[0044] As an example, a method of forming a memory cell 610 on a bottom contact structure 130 includes:

[0045] like Figure 5 As shown, a storage material layer 600 is formed on the fourth dielectric material layer 510 and the bottom contact structure 130 .

[0046] Optional, such as Fig.23 As shown, Fig.23 yes Figure 5600. The storage material layer 600 includes a bottom electrode material layer 601, a free material layer 602, a tunneling barrier material layer 603, a fixed material layer 604, and a top electrode material layer 605 stacked in sequence. For example, the materials of the bottom electrode material layer 601 and the top electrode material layer 605 include but are not limited to W, TiN, Ta, TaN, etc.; the materials of the free material layer 602 and the fixed material layer 604 include but are not limited to CoBTa, CoFeB or CoFeBTa, etc.; the materials of the tunneling barrier material layer 603 include but are not limited to MgO, etc. Specifically, the above-mentioned material layers can be formed by processes such as PVD or CVD.

[0047] A mask layer having an opening pattern is formed on the storage material layer 600. Specifically, a mask layer may be formed on the top electrode material layer 605, and a photolithography pattern layer, such as a photoresist layer having an opening pattern, may be formed on the mask layer. The mask layer may be etched using the photolithography pattern layer to form an opening pattern on the mask layer. The mask layer may be a multi-layer film structure or a single-layer film structure, such as any one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer or a carbon layer or any combination thereof. The bottom electrode material layer 601, the free material layer 602, the tunneling barrier material layer 603, the fixed material layer 604 and the top electrode material layer 605 may be etched using the mask layer to form a plurality of discrete storage cells 610 on the fourth dielectric material layer 510, such as Figure 6 As shown, the storage cells 610 are connected to the bottom contact structures 130 in a one-to-one correspondence.

[0048] Optionally, the top of the storage unit 610 is arc-shaped. Specifically, the top electrode material layer 605 after etching has an arc-shaped top. The arc-shaped top can increase the distance between the tops of different storage units 610 and reduce the risk of short circuits of adjacent storage units 610. At the same time, the arc-shaped top is conducive to the filling of the dielectric layer between the subsequent storage units 610.

[0049] Illustratively, a method of forming a shielding structure encapsulating a storage unit 610 includes:

[0050] like Figure 7As shown, a fifth dielectric material layer 520 is formed on the surface of the storage unit 610. Specifically, the fifth dielectric material layer 520 is formed on the top surface of the storage unit 610 and the two side surfaces and the fourth dielectric material layer 510 between the storage units 610 using a deposition process such as CVD. The material of the fifth dielectric material layer 520 includes SiN, SiO2, NDC, BD (Black Diamond), etc. Specifically, a mask pattern layer can be formed on the fifth dielectric material layer 520, and the mask pattern layer exposes the fifth dielectric material layer 520 on the fourth dielectric material layer 510 between the storage units 610. The mask pattern layer can be a photoresist layer. The fifth dielectric material layer 520 on the fourth dielectric material layer 510 between the storage units 610 is etched and removed using the mask pattern layer, and the fifth dielectric material layer 520 on the top surface and the two side surfaces of the storage unit 610 is retained.

[0051] like Figure 8 As shown, the fourth dielectric material layer 510 between the storage units 610 is partially removed. Specifically, the portion between the storage units 610 that is not covered by the fifth dielectric material layer 520 on the sidewall of the storage unit 610 can be removed by etching, and the fourth dielectric material layer 510 below the fifth dielectric material layer 520 on the sidewall of the storage unit 610 is retained. The fifth dielectric material layer 520 and the fourth dielectric material layer 510 remaining after the partial removal together form a first dielectric layer 500 that is connected and surrounds the storage unit 610. The material of the fifth dielectric material layer 520 and the fourth dielectric material layer 510 can be the same or different.

[0052] like Fig. 9 As shown, a fifth shielding material layer 320 is formed on the surface of the fifth dielectric material layer. Specifically, the fifth shielding material layer 320 is formed on the top surface of the fifth dielectric material layer and the two side surfaces and the fourth shielding material layer 310 between the storage units 610 by using a deposition process such as CVD or PVD. The material of the fifth shielding material layer 320 may include an alloy of iron (Fe), cobalt (Co) and nickel (Ni), such as cobalt iron, nickel iron and nickel cobalt iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys, etc. Specifically, a mask pattern layer may be formed on the fifth shielding material layer 320, the mask pattern layer exposing the fifth shielding material layer 320 on the fourth shielding material layer 310 between the storage units 610, and the mask pattern layer may be a photoresist layer. The fifth shielding material layer 320 on the fourth shielding material layer 310 between the storage units 610 is etched and removed by using the mask pattern layer, and the fourth shielding material layer 310 on the top surface and the two side surfaces of the fifth dielectric material layer is retained.

[0053] Optionally, the fifth shielding material layer 320 is also formed on the sidewall of the fourth dielectric material layer 510 below the fifth dielectric material layer on the sidewall of the storage unit 610. The fifth shielding material layer 320 on the sidewall of the fourth dielectric material layer 510 is in direct contact with the fourth shielding material layer 310.

[0054] like Fig.10 As shown, the fourth shielding material layer 310 between the storage units 610 is partially removed. Specifically, the portion between the storage units 610 that is not covered by the fifth shielding material layer 320 can be removed by etching, and the fourth shielding material layer 310 below the first dielectric layer 500 and the fifth shielding material layer 320 is retained. The fifth shielding material layer 320 and the remaining fourth shielding material layer 310 after the partial removal together form a first shielding layer 300 that is connected and surrounds the storage unit 610. The material of the fifth shielding material layer 320 and the fourth shielding material layer 310 can be the same or different.

[0055] like Fig.11 As shown, the third dielectric material layer 410 between the storage units 610 is partially removed. Specifically, a mask pattern layer can be formed on the fifth shielding material layer 320, and the mask pattern layer exposes the third dielectric material layer 410 on the third shielding material layer 210 between the storage units 610. The mask pattern layer can be a photoresist layer. The third dielectric material layer 410 on the third shielding material layer 210 between the storage units 610 is etched and removed using the mask pattern layer, and the third dielectric material layer 410 below the fifth shielding material layer 320 is retained. For example, the third dielectric material layer 410 below the first shielding layer 300 can all be retained.

[0056] like Fig.12 As described above, a sixth dielectric material layer 420 is formed on the surface of the fifth shielding material layer. Specifically, the sixth dielectric material layer 420 can be formed on the top surface of the fifth shielding material layer 320 and the two side surfaces and the third shielding material layer 210 between the storage unit 610 by using a deposition process such as CVD. The material of the sixth dielectric material layer 420 includes SiN, SiO2, NDC, BD (Black Diamond), etc. The sixth dielectric material layer 420 between the storage units 610 is removed by etching, and the sixth dielectric material layer 420 on the sidewalls of the storage unit 610 is retained. Fig.13As shown, the sixth dielectric material layer 420 and the third dielectric material layer 410 together form a second dielectric layer 400 that is connected to and surrounds the storage unit 610. The materials of the sixth dielectric material layer 420 and the third dielectric material layer 410 may be the same or different. Specifically, the third dielectric material layer 410 between the storage units 610 may be partially removed first, the third dielectric material layer 410 below the first shielding layer 300 may be retained, and then the sixth dielectric material layer 420 may be formed on the surface of the first shielding layer 300 and the sidewall of the remaining third dielectric material layer 410. This may prevent the sixth dielectric material layer 420 on the surface of the first shielding layer 300 from being damaged during the process of partially removing the third dielectric material layer 410 between the storage units 610.

[0057] like Fig.13 As shown, a sixth shielding material layer 220 is formed on the surface of the sixth dielectric material layer 420. Specifically, the sixth shielding material layer 220 is formed on the top surface of the sixth dielectric material layer 420 and the two side surfaces and the third shielding material layer 210 between the storage units 610 by using a deposition process such as CVD or PVD. The material of the sixth shielding material layer 220 may include an alloy of iron (Fe), cobalt (Co) and nickel (Ni), such as cobalt iron, nickel iron and nickel cobalt iron, various combinations of NiFe and Co and other alloys with higher magnetic permeability, doped amorphous ferromagnetic alloys, etc. Specifically, a mask pattern layer may be formed on the sixth shielding material layer 220, the mask pattern layer exposing the sixth shielding material layer 220 on the third shielding material layer 210 between the storage units 610, and the mask pattern layer may be a photoresist layer. The third shielding material layer 210 and the sixth shielding material layer 220 between the storage units 610 are etched away using the mask pattern layer, and the sixth shielding material layer 220 on the top surface and both side surfaces of the sixth dielectric material layer 420 and the third shielding material layer 210 below the sixth shielding material layer 220 are retained. Fig.14 As shown, the sixth shielding material layer 220 and the third shielding material layer 210 together form an integrated second shielding layer 200 surrounding the storage unit 610. The sixth shielding material layer 220 and the third shielding material layer 210 may be made of the same or different materials.

[0058] As an example, the method further includes: forming a top contact structure 740 on the memory cell 610 , wherein the top contact structure 740 passes through the shielding layer and is connected to the top electrode material layer.

[0059] Specifically, Figures 15 to 17As shown, a seventh dielectric material layer 710 covering the storage unit 610 is formed; the seventh dielectric material layer 710 and the tops of the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400 and the second shielding layer 200 are partially removed by a CMP process, so that the tops of the remaining portions of the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400 and the second shielding layer 200 are exposed to the remaining surface of the seventh dielectric material layer 710; Fig.16 As shown, the shield structure has a flush top surface.

[0060] Optionally, the seventh dielectric material layer 710 and the tops of the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400, and the second shielding layer 200 are partially removed by a CMP process, so that the tops of the remaining portions of the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400, and the second shielding layer 200 are exposed to the remaining surface of the seventh dielectric material layer 710, and the tops of the memory cells 610 are exposed to the remaining surface of the seventh dielectric material layer 710. Specifically, the top electrode material layer of the memory cell 610 is exposed to the remaining surface of the seventh dielectric material layer 710, and the top electrode material layer has a flush top surface with the shielding structure. For example, the top electrode material layer has a flush top surface with the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400, and the second shielding layer 200. Specifically, the top electrode material layer has an arc-shaped top surface, and the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400 and the second shielding layer 200 sequentially formed on the top surface of the top electrode material layer also have an arc-shaped top surface. The top electrode material layer is polished using a CMP process to expose the top electrode material layer, so as to form a top contact structure 740 connected to the top electrode material layer in a subsequent process, thereby avoiding alignment problems caused by photolithography and etching processes and difficult etching problems of multiple shielding layers and dielectric layers.

[0061] An eighth dielectric material layer 720 is formed on the surface of the remaining seventh dielectric material layer 710, so that the eighth dielectric material layer 720 and the remaining seventh dielectric material layer 710 form an interlayer dielectric layer 700. Fig.17 , which representatively shows a schematic diagram of the structure of the semiconductor structure in the step of “forming the eighth dielectric material layer 720” (i.e., the step of “forming the interlayer dielectric layer 700”). Specifically, under the above steps, the semiconductor structure includes a substrate 110, a bottom contact electrode 130, a storage unit 610 (surrounded by the first dielectric layer 500, the first shielding layer 300, the second dielectric layer 400, and the second shielding layer 200 in sequence), and the seventh dielectric material layer 710 and the eighth dielectric material layer 720 remaining after partial removal. The eighth dielectric material layer 720 is formed on the surface of the remaining seventh dielectric material layer 710, and covers the exposed portions of each dielectric layer and each shielding layer. Fig.18 As shown, the eighth dielectric material layer 720 and the seventh dielectric material layer 710 remaining after partial removal form an interlayer dielectric layer 700 .

[0062] Alternatively, if Fig.18 and Fig.19 As shown, in this embodiment, the formation of the top contact structure 740 includes the following steps:

[0063] A top contact hole 730 is formed in the interlayer dielectric layer 700 , and the top contact hole 730 penetrates each shielding layer and each dielectric layer, so that the top of the memory cell 610 is exposed to the bottom end of the top contact hole 730 ;

[0064] A top contact structure 740 is formed in the top contact hole 730, and the bottom end of the top contact structure 740 contacts the memory cell 610. The top contact structure 740 may be formed by a metal conductive material filled in the top contact hole 730. Except for the portion in contact with the bottom contact structure 130 and the top contact structure 740, the rest of the memory cell 610 is surrounded by a shielding structure having multiple (e.g., two) shielding layers and a dielectric layer.

[0065] See also Fig. 20 , Fig. 20 Representatively shown Fig.19 A cross-sectional view of the semiconductor structure along line XX is shown in the illustrated method.

[0066] like Fig. 20 As shown, under this viewing angle, the morphology of the multiple shielding layers and the multiple dielectric layers around the storage unit 610 can be observed, and the shielding layers and the dielectric layers are roughly in an annular shielding structure that alternately surrounds the outside of the storage unit 610. Taking the above-mentioned embodiment in which the outside of the storage unit 610 is surrounded by two shielding layers and two dielectric layers as an example, in the direction from the inside to the outside of the outside of the storage unit 610, the annular morphology of the first dielectric layer 500, the annular morphology of the first shielding layer 300, the annular morphology of the second dielectric layer 400, and the annular morphology of the second shielding layer 200 are in turn.

[0067] It should be noted that the methods for preparing semiconductor structures shown in the drawings and described in this specification are only a few examples of many methods for preparing semiconductor structures that can employ the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any steps of the methods for preparing semiconductor structures shown in the drawings or described in this specification.

[0068] In summary, the method for preparing the semiconductor structure proposed in the present invention adopts a method design in which multiple dielectric layers and multiple shielding layers are formed outside the storage unit 610, and the dielectric layers and the shielding layers are arranged alternately. The semiconductor structure can use the shielding layers and dielectric layers to achieve multiple reflections and absorptions of the electromagnetic field, so as to achieve a better shielding effect.

[0069] Based on the above detailed description of an exemplary embodiment of the semiconductor structure proposed by the present invention, the following will be combined with Fig. 22 , another exemplary embodiment of the semiconductor structure proposed by the present invention is described.

[0070] like Fig. 22 As shown, in this embodiment, the storage unit 610 of the semiconductor structure proposed by the present invention is surrounded by three dielectric layers and three shielding layers, and the dielectric layers and the shielding layers are arranged alternately. Specifically, based on the description of the first embodiment of the semiconductor structure, in this embodiment, the second shielding layer 200 is further surrounded by a third dielectric layer 900, and the third dielectric layer 900 is further surrounded by a third shielding layer 800.

[0071] See also Fig.21 , Fig.21 Representatively shown Fig.19 A schematic diagram of the external electromagnetic field shielding principle of a semiconductor structure under the method shown.

[0072] like Fig.21 As shown, the preparation method of the semiconductor structure proposed in the present invention can surround a multi-layer shielding structure outside the storage unit 610. Taking a part of them, such as the first shielding layer 300, the second shielding layer 200 and the second dielectric layer 400 therebetween as an example, it can be observed that when the external incident electromagnetic field reaches the second shielding layer 200, a part is directly reflected by the second shielding layer 200, and the electromagnetic field that is not reflected by the surface of the second shielding layer 200 and enters the second shielding layer 200 is attenuated by the second shielding layer 200 during the process of propagating forward in the second shielding layer 200, that is, the second shielding layer 200 will absorb the electromagnetic field, and the remaining part after absorption will be reflected again by the first shielding layer 300 and return to the first shielding layer 300, and similarly produce absorption and attenuation. This reflection may occur multiple times between the interfaces of the two shielding layers, and the shielding purpose is finally achieved through multiple reflections, absorption and attenuation.

[0073] Accordingly, the semiconductor structure made by the semiconductor structure preparation method proposed in the present invention has multiple anti-interference layers for external electric fields (shielding structure with multiple shielding layers), and therefore can achieve effective shielding of external electromagnetic fields through multiple reflections and absorption of electromagnetic fields.

[0074] Based on the above detailed description of several exemplary embodiments of the method for preparing a semiconductor structure according to the present invention, the following will be combined with Fig.19 , an exemplary implementation of the semiconductor structure proposed by the present invention is described.

[0075] like Fig.19 As shown, in this embodiment, the semiconductor structure proposed by the present invention includes:

[0076] Substrate 110;

[0077] A bottom contact structure 130 and a memory cell 610 are located on the substrate 110 , wherein the bottom contact structure 130 is connected to the bottom of the memory cell 610 ;

[0078] The shielding structure is coated on the periphery of the storage unit 610 , wherein the shielding structure includes a plurality of alternately arranged dielectric layers and shielding layers.

[0079] Optionally, the shielding structure includes a first dielectric layer 500 , a first shielding layer 300 , a second dielectric layer 400 and a second shielding layer 200 which are sequentially coated on the storage unit 610 .

[0080] Optionally, the dielectric layer and the shielding layer are also located below the storage unit 610 .

[0081] Optionally, the memory cell 610 includes a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer and a top electrode material layer, wherein the bottom contact structure 130 is connected to the bottom electrode material layer;

[0082] It also includes: a top contact structure 740, and the top contact structure 740 is connected to the top electrode material layer.

[0083] Optionally, the top electrode material layer has a curved top.

[0084] Optionally, the shielding structure has a flush top surface.

[0085] Optionally, the top electrode material layer and the shielding structure have flush top surfaces.

[0086] Based on the above detailed description of an exemplary embodiment of the semiconductor structure proposed by the present invention, the following will be combined with Fig. 22 , another exemplary embodiment of the semiconductor structure proposed by the present invention is described.

[0087] like Fig. 22As shown, in this embodiment, the storage unit 610 of the semiconductor structure proposed by the present invention is surrounded by three dielectric layers and three shielding layers, and the dielectric layers and the shielding layers are arranged alternately. Specifically, based on the description of the first embodiment of the semiconductor structure, in this embodiment, the second shielding layer 200 is further surrounded by a third dielectric layer 900, and the third dielectric layer 900 is further surrounded by a third shielding layer 800.

[0088] Based on this, it is easy to understand that in various possible implementations consistent with the design concept of the semiconductor structure proposed in the present invention, the semiconductor structure includes a storage unit 610, which is surrounded by multiple dielectric layers and multiple shielding layers on the outside, and the dielectric layers and shielding layers are arranged alternately.

[0089] It should be noted that the semiconductor structures shown in the drawings and described in this specification are only a few examples of the many types of semiconductor structures that can employ the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any details or any structures of the semiconductor structures shown in the drawings or described in this specification.

[0090] In summary, the semiconductor structure proposed in the present invention adopts a structural design in which multiple dielectric layers and multiple shielding layers are formed outside the storage unit, and the dielectric layers and the shielding layers are arranged alternately. Accordingly, the shielding layers and the dielectric layers can be used to reflect and absorb the electromagnetic field, so that the interference of the external electromagnetic field is minimized.

[0091] The above describes and / or illustrates in detail the method for preparing the semiconductor structure proposed by the present invention and the exemplary embodiment of the semiconductor structure. However, the embodiments of the present invention are not limited to the specific embodiments described herein. On the contrary, the components and / or steps of each embodiment can be used independently and separately from other components and / or steps described herein. Each component and / or each step of an embodiment can also be used in combination with other components and / or steps of other embodiments. When introducing the elements / components / etc. described and / or illustrated herein, the terms "one", "one" and "above" are used to indicate the presence of one or more elements / components / etc. The terms "include", "include" and "have" are used to indicate the meaning of open inclusion and mean that in addition to the listed elements / components / etc., there may be other elements / components / etc. In addition, the terms "first" and "second" in the claims and the specification are used only as marks and are not numerical restrictions on their objects.

[0092] Although the method for preparing the semiconductor structure and the semiconductor structure proposed by the present invention have been described according to different specific embodiments, those skilled in the art will recognize that the implementation of the present invention can be modified within the spirit and scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a bottom contact structure in the substrate; forming a memory cell on the bottom contact structure; forming a shielding structure covering the storage unit, wherein the shielding structure comprises a plurality of dielectric layers and shielding layers arranged alternately; The shielding structure comprises a first dielectric layer, a first shielding layer, a second dielectric layer and a second shielding layer sequentially coated on the storage unit; The method for forming a bottom contact structure in the substrate comprises: forming a third shielding material layer, a third dielectric material layer, a fourth shielding material layer and a fourth dielectric material layer in sequence on the substrate; forming a plurality of bottom contact holes in the substrate, wherein the bottom contact holes penetrate the third shielding material layer, the third dielectric material layer, the fourth shielding material layer and the fourth dielectric material layer; A conductive material is filled in the bottom contact hole.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The method for forming a memory cell on the bottom contact structure comprises: On the fourth dielectric material layer, a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer and a top electrode material layer are sequentially formed; forming a mask layer having an opening pattern on the top electrode material layer; The bottom electrode material layer, the free material layer, the tunneling barrier material layer, the fixed material layer and the top electrode material layer are etched using the mask layer to form a plurality of discrete storage cells on the fourth dielectric material layer, wherein the storage cells are connected to the bottom contact structure one by one.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The method for forming a shielding structure covering the storage unit comprises: forming a fifth dielectric material layer on the surface of the storage unit; Partially removing the fourth dielectric material layer between the storage units; forming a fifth shielding material layer on the surface of the fifth dielectric material layer; Partially removing the fourth shielding material layer between the storage units; Partially removing the third dielectric material layer between the storage units; forming a sixth dielectric material layer on the surface of the fifth shielding material layer; forming a sixth shielding material layer on the surface of the sixth dielectric material layer; The third shielding material layer between the storage units is partially removed.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: In the step of partially removing the fourth dielectric material layer between the storage units, the fourth dielectric material layer below the fifth dielectric material layer on the side wall of the storage unit is retained; In the step of partially removing the fourth shielding material layer between the storage units, the fourth shielding material layer below the fifth shielding material layer on the side wall of the storage unit is retained; In the step of partially removing the third dielectric material layer between the storage units, the third dielectric material layer below the fifth shielding material layer on the side wall of the storage unit is retained; In the step of partially removing the third shielding material layer between the storage cells, the third shielding material layer below the sixth shielding material layer on the side walls of the storage cells is retained.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: The first dielectric layer includes the fifth dielectric material layer and the fourth dielectric material layer connected as one; The first shielding layer comprises the fifth shielding material layer and the fourth shielding material layer connected as one; The second dielectric layer includes the third dielectric material layer and the sixth dielectric material layer connected as one; The second shielding layer includes the third shielding material layer and the sixth shielding material layer which are connected as one.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: Also includes: A top contact structure is formed on the memory cell, wherein the top contact structure passes through the shielding layer and is connected to the top electrode material layer.

7. A semiconductor structure, characterized in that: include: substrate; A bottom contact structure and a memory cell located on the substrate, wherein the bottom contact structure is connected to the bottom of the memory cell; A shielding structure, the shielding structure is coated on the periphery of the storage unit, wherein the shielding structure comprises a plurality of dielectric layers and shielding layers arranged alternately; The shielding structure comprises a first dielectric layer, a first shielding layer, a second dielectric layer and a second shielding layer sequentially coated on the storage unit; The dielectric layer and the shielding layer are also located below the storage unit.

8. The semiconductor structure according to claim 7, characterized in that: The memory cell comprises a bottom electrode material layer, a free material layer, a tunneling barrier material layer, a fixed material layer and a top electrode layer, wherein the bottom contact structure is connected to the bottom electrode material layer; It also includes: a top contact structure, wherein the top contact structure is connected to the top electrode material layer.

9. The semiconductor structure according to claim 8, characterized in that: The top electrode material layer has a curved top.

10. The semiconductor structure according to claim 9, characterized in that: The shielding structure has a flush top surface.

11. The semiconductor structure according to claim 10, characterized in that: The top electrode material layer and the shielding structure have flush top surfaces.

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