A clock synchronization circuit with half-cycle delay stepping
Through the half-period delay stepping clock synchronization circuit, the challenge of phase noise and synchronous output on broadband is solved, and the clock synchronization and frequency division functions under the CMOS process are realized, ensuring 50% duty cycle and synchronization effect of the output clock signal.
Patent Information
- Application Number
- CN202210575288.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-05-25
- Publication Date
- 2025-08-01
- Estimated Expiration
- 2042-05-25
AI Technical Summary
Existing phase-locked loop systems are difficult to achieve extremely low phase noise on broadband, and the synchronous output design of multiple clock frequency resources in large-scale circuit systems has the challenge of fixed delay and synchronous output, especially the synchronous clock circuit with a 50% duty cycle output cannot be effectively implemented in high-speed, high-precision ADC and clock synchronization network.
The clock synchronization circuit with half-period delay step is adopted, including a 1-1024 frequency division circuit and a half-period delay step output circuit, combined with a delay period pulse cancellation circuit and a duty cycle correction clock output circuit, realizes a delay step of 0.5 cycles and an integer frequency division, and is synchronized with the rising edge of the input signal clock.
It realizes a simple circuit structure, suitable for CMOS process, has delay pulse cancellation capability, ensures 50% duty cycle of the output clock signal, and reduces the operating frequency of the counter, realizing clock source synchronization and frequency division functions.
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Figure CN115149946B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of clock circuits, and particularly relates to the field of large-scale digital clock synchronization. Specifically, it refers to a clock synchronization circuit with a half-cycle delay step. Background Art
[0002] Driven by factors such as cost, integration, and power consumption, CMOS process technology has advanced by leaps and bounds. In fields such as high-speed and high-precision ADC, clock synchronization networks, and radio frequency transceivers, increasingly high requirements are put forward for the frequency synthesis field. The frequency synthesizer has gradually become a key module determining the performance of electronic systems and plays an irreplaceable role in fields such as communication and radar.
[0003] The phase-locked loop (PLL) technology is the most important means in current frequency synthesis technology. A typical PLL system includes modules such as a frequency discriminator and phase detector, a charge pump, a filter, a voltage-controlled oscillator, and a programmable frequency divider. The bandwidth of the PLL usually makes a design compromise in suppressing low-frequency noise and high-frequency noise. It is difficult for a single-stage CMOS PLL to achieve extremely low phase noise over a wide bandwidth. At the same time, designers of large-scale circuit systems hope that multiple clock frequency resources have measurable fixed delays and are synchronously output to ensure the correctness of the timing of large systems. Therefore, clock synchronization technology, especially a synchronous clock circuit with a 50% duty cycle output, is particularly important. Summary of the Invention
[0004] In view of this, the present invention provides a circuit applicable to the CMOS process, which can achieve a delay step of 0.5 cycle, can perform integer frequency division, and is synchronized with the rising edge of the input signal clock.
[0005] To achieve the above object, the present invention adopts the following technical solutions:
[0006] A clock synchronization circuit with a half-cycle delay step includes a 1-1024 frequency division circuit 100 and a half-cycle delay step output circuit 200;
[0007] The externally input clock signal is connected to the signal input port of the 1-1024 frequency division circuit 100. The output port of the 1-1024 frequency division circuit 100 is connected to the frequency division input port of the half-cycle delay step output circuit 200. The externally input clock signal is also connected to the clock input port of the half-cycle delay step output circuit 200;
[0008] The synchronization input port of the half-cycle delay step output circuit 200 is used to receive a synchronization signal, the step mode selection signal input port of the half-cycle delay step output circuit 200 is used to receive a selection signal, and the delay cycle control signal input port of the half-cycle delay step output circuit 200 is used to receive a total delay cycle control signal; the reset signal output port of the half-cycle delay step output circuit 200 is connected to the input reset port of the 1-1024 frequency division circuit 100; the clock output port of the half-cycle delay step output circuit 200 is used to output a frequency-divided signal after delay;
[0009] The 1-1024 frequency division circuit 100 further has a frequency division configuration port. By configuring the binary bit of this port, the 1-1024 frequency division circuit 100 realizes the corresponding decimal frequency division ratio;
[0010] When the input reset port of the 1-1024 frequency division circuit 100 inputs logic "1", the output port of the 1-1024 frequency division circuit 100 outputs logic "0". When the input reset port of the 1-1024 frequency division circuit 100 inputs logic "0", the output port of the 1-1024 frequency division circuit 100 outputs a normal frequency-divided signal.
[0011] Further, the half-cycle delay step output circuit 200 includes a delay cycle pulse elimination circuit and a duty cycle correction clock output circuit;
[0012] The delay cycle pulse elimination circuit includes a 6-bit subtraction counter 201, first to sixth inverters 202 to 207, a six-input AND gate 208, a first D flip-flop 209 with an asynchronous clear port, a second D flip-flop 210 with an asynchronous clear port, a 2-to-1 data selector 211, and a seventh inverter 212;
[0013] The clock input port of the half-cycle delay step output circuit 200 is the clock input port of the 6-bit subtraction counter 201, the synchronous input port of the half-cycle delay step output circuit 200 is the synchronous input port of the 6-bit subtraction counter 201, and the delay cycle control signal input port of the half-cycle delay step output circuit 200 is the delay cycle control signal input port of the 6-bit subtraction counter 201; the data output ports of the 6-bit subtraction counter 201 are respectively connected to the signal input ports of the first to sixth inverters from high to low; the signal output ports of the first to sixth inverters are respectively connected to the six signal input ports of the six-input AND gate 208, and the signal output port of the six-input AND gate 208 is simultaneously connected to the asynchronous logic reset ports of the first and second D flip-flops with asynchronous reset ports; the externally input clock signal is also simultaneously connected to the clock input port of the first D flip-flop with asynchronous reset port 209, the data input port of the 2-to-1 data selector 211, and the signal input port of the seventh inverter 212; the signal output port of the seventh inverter 212 is connected to the other data input port of the 2-to-1 data selector 211; the output port of the 2-to-1 data selector 211 is connected to the clock input port of the second D flip-flop with asynchronous reset port 210; the frequency division input port of the half-cycle delay step output circuit 200 is connected to the data port of the first D flip-flop with asynchronous reset port 209, and the data output port of the first D flip-flop with asynchronous reset port 209 is connected to the data input port of the second D flip-flop with asynchronous reset port 210; the signal output port of the six-input AND gate 208 is the reset signal output port of the half-cycle delay step output circuit 200;
[0014] The duty cycle correction clock output circuit is composed of a rising-edge D flip-flop 213, a falling-edge D flip-flop 214, and an OR gate 215; the data output port of the second D flip-flop with asynchronous reset port 210 is simultaneously connected to the data ports of the rising-edge D flip-flop 213 and the falling-edge D flip-flop 214; the output port of the 2-to-1 data selector 211 is simultaneously connected to the clock ports of the rising-edge D flip-flop 213 and the falling-edge D flip-flop 214; the data output ports of the rising-edge D flip-flop 213 and the falling-edge D flip-flop 214 are respectively connected to one signal input port of the OR gate 215, and the signal output port of the OR gate 215 is the clock output port of the half-cycle delay step output circuit 200.
[0015] The beneficial effects of the present invention are as follows:
[0016] 1. The circuit structure of the present invention is simple and suitable for implementation in CMOS process.
[0017] 2. The present invention has a delay pulse elimination technology, which can ensure that the output remains low during the delay time.
[0018] 3. The present invention has a clock duty cycle correction technology, which can ensure that the output clock signal has a 50% duty cycle.
[0019] 4. The present invention adopts a clock phase inversion function, which can effectively reduce the operating frequency of the counter.
[0020] 5. The present invention has the characteristics of clock source synchronization, frequency division, and output with a 0.5-cycle delay step. It can implement a circuit with a 0.5-cycle delay step, integer frequency division, and synchronization with the rising edge of the input signal clock. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is the circuit schematic diagram of the clock synchronization circuit with a half-cycle delay step in the embodiment of the present invention;
[0022] Figure 2 is Figure 1 the internal circuit schematic diagram of the half-cycle delay step output circuit in
[0023] Figure 3 is Figure 2 the signal waveform diagram of the OUT3 port in DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] In order to further illustrate the technical solutions disclosed in the present invention, the following will be described in detail in combination with the specification drawings and specific embodiments. Those skilled in the art should know that the optimized designs and improvement methods made without departing from the spirit of the invention fall within the protection scope of the present invention, and the conventional technologies in this field will not be described in detail in this specific embodiment.
[0025] As Figure 1 shown, a clock synchronization circuit with a half-cycle delay step includes a 1-1024 frequency division circuit 100 and a half-cycle delay step output circuit 200;
[0026] The externally input clock signal enters from the signal input port of the 1-1024 frequency division circuit 100. After being frequency divided by the 1-1024 frequency division circuit 100, it is input from the output port of the 1-1024 frequency division circuit 100 to the frequency division input port of the half-cycle delay step output circuit 200. At the same time, the externally input clock signal is also sent to the clock input port of the half-cycle delay step output circuit 200;
[0027] The synchronous input port of the half-cycle delay step output circuit 200 receives a synchronous signal, the step mode selection signal input port of the half-cycle delay step output circuit 200 receives a selection signal, and the delay cycle control signal input port of the half-cycle delay step output circuit 200 receives a total delay cycle control signal; the reset signal output port of the half-cycle delay step output circuit 200 outputs a reset signal to the input reset port of the 1-1024 frequency division circuit 100; the clock output port of the half-cycle delay step output circuit 200 outputs a frequency division signal after delay;
[0028] The 1-1024 frequency division circuit 100 also has a frequency division configuration port. By configuring the binary bit of this port, the 1-1024 frequency division circuit 100 realizes the corresponding decimal frequency division ratio;
[0029] When the input reset port of the 1-1024 frequency division circuit 100 inputs logic "1", the output port of the 1-1024 frequency division circuit 100 outputs logic "0". When the input reset port of the 1-1024 frequency division circuit 100 inputs logic "0", the output port of the 1-1024 frequency division circuit 100 outputs a normal frequency division signal.
[0030] As Figure 2 shown, the half-cycle delay step output circuit 200 includes a delay cycle pulse elimination circuit and a duty cycle correction clock output circuit;
[0031] The delay cycle pulse elimination circuit includes a 6-bit subtraction counter 201, first to sixth inverters 202 to 207, a six-input AND gate 208, a first D flip-flop 209 with an asynchronous clear port, a second D flip-flop 210 with an asynchronous clear port, a 2-to-1 data selector 211, and a seventh inverter 212;
[0032] The clock input port of the half - period delay step - output circuit 200 is the same as the clock input port of the 6 - bit subtraction counter 201. The synchronous input port of the half - period delay step - output circuit 200 is the same as the synchronous input port of the 6 - bit subtraction counter 201. The delay - period control signal input port of the half - period delay step - output circuit 200 is the same as the delay - period control signal input port of the 6 - bit subtraction counter 201. The data output port of the 6 - bit subtraction counter 201 is connected to the signal input ports of the first to sixth inverters from the high - order bit to the low - order bit. The signal output ports of the first to sixth inverters are respectively connected to the six signal input ports of the six - input AND gate 208. The signal output port of the six - input AND gate 208 is simultaneously connected to the asynchronous logic reset ports of the first and second D - flip - flops with asynchronous clear ports. The externally input clock signal is also simultaneously sent to the clock input port of the first D - flip - flop with asynchronous clear port 209, the data input port of the 2 - to - 1 data selector 211, and the signal input port of the seventh inverter 212. The signal output port of the seventh inverter 212 is connected to the other data input port of the 2 - to - 1 data selector 211. The output port of the 2 - to - 1 data selector 211 is connected to the clock input port of the second D - flip - flop with asynchronous clear port 210. The frequency - division input port of the half - period delay step - output circuit 200 is connected to the data port of the first D - flip - flop with asynchronous clear port 209. The data output port of the first D - flip - flop with asynchronous clear port 209 is connected to the data input port of the second D - flip - flop with asynchronous clear port 210. The signal output port of the six - input AND gate 208 is the reset signal output port of the half - period delay step - output circuit 200.
[0033] The duty - cycle correction clock output circuit is composed of a rising - edge D - flip - flop 213, a falling - edge D - flip - flop 214, and an OR gate 215. The data output port of the second D - flip - flop with asynchronous clear port 210 is simultaneously connected to the data ports of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214. The output port of the 2 - to - 1 data selector 211 is simultaneously connected to the clock ports of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214. The data output ports of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214 are respectively connected to one signal input port of the OR gate 215. The signal output port of the OR gate 215 is the clock output port of the half - period delay step - output circuit 200.
[0034] The following is a more specific example:
[0035] A clock synchronization circuit with half - period delay step, the structure of which is as Figure 1 shown, including two parts: a 1 - to - 1024 frequency - division circuit 100 and a half - period delay step - output circuit 200.
[0036] Among them, some ports of the 1 - to - 1024 frequency - division circuit are as follows:
[0037] Signal input terminal, from which the clock signal enters;
[0038] Frequency division configuration port <9:0>, by configuring the binary bit of this port, the 1 - 1024 frequency division circuit 100 realizes the corresponding decimal frequency division ratio;
[0039] Input reset terminal, when the logic "1" is input to this port, the output terminal OUT1 of the 1 - 1024 frequency division circuit 100 outputs the logic "0", when the logic "0" is input to this port, the output terminal OUT1 of the 1 - 1024 frequency division circuit 100 outputs the normal frequency division signal.
[0040] The 2Ghz signal is input to the signal input terminal, and the binary number corresponding to the decimal number 10 is input to the frequency division configuration port <9:0>. When the input reset signal is 0, the output terminal OUT1 of the 1 - 1024 frequency division circuit 100 outputs a periodic signal of 200Mhz; when the input reset signal is 1, the output terminal OUT1 of the 1 - 1024 frequency division circuit 100 outputs the logic "0" constantly.
[0041] The connection relationship between the 1 - 1024 frequency division circuit 100 and the half - period delay step - by - step output circuit 200 is as follows:
[0042] The signal input terminal of the 1 - 1024 frequency division circuit 100 is connected to the clock input port CLK_INOUT of the half - period delay step - by - step output circuit 200, the output terminal OUT1 of the 1 - 1024 frequency division circuit 100 is connected to the frequency division input port CLK_DIV of the half - period delay step - by - step output circuit 200, the synchronization signal SYNC is connected to the synchronization input port of the half - period delay step - by - step output circuit 200, the selection signal SEL is connected to the step - by - step mode selection signal input port of the half - period delay step - by - step output circuit 200, and the total delay period control signal is connected to the delay period control signal input terminal DELAY<5:0> of the half - period delay step - by - step output circuit 200. The reset signal output port RESET_DIV of the half - period delay step - by - step output circuit 200 is connected to the input reset terminal of the 1 - 1024 frequency division circuit 100. The clock output port OUT2 of the half - period delay step - by - step output circuit 200 outputs the delayed frequency division signal.
[0043] The structure of the half - period delay step - by - step output circuit 200 is as Figure 2As shown. After the input clock signal is divided by the 1-1024 frequency divider circuit 100, it is input from OUT1 to the CLK_DIV port of the half-cycle delay step output circuit 200. At the same time, the signal input of the 1-1024 frequency divider circuit 100 is output to the CLK_INPUT port of the half-cycle delay step output circuit 200. The signal at the CLK_INPUT port is an integer multiple of the signal at the CLK_DIV port. At the same time, the signal at the CLK_INPUT port samples the signal at the CLK_DIV port. When a low-frequency signal is sampled by a high-frequency signal that is an integer multiple of it, the signal at the CLK_DIV port is synchronized by the clock edge of the signal at the CLK_INPUT port.
[0044] The half - period delay step - output circuit 200 consists of a delay - period pulse elimination circuit and a duty - cycle correction clock output circuit. Among them, the delay - period pulse elimination circuit is composed of a 6 - bit subtraction counter 201, the first to sixth inverters 202 - 207, a six - input AND gate 208, a first D - flip - flop with an asynchronous clear port 209, a second D - flip - flop with an asynchronous clear port 210, a 2 - to - 1 data selector 211, and a seventh inverter 212. The signal CLK_INPUT is connected to the CLK_INPUT port of the 6 - bit subtraction counter 201, the synchronization signal SYNC is connected to the SYNC port of the 6 - bit subtraction counter 201, and the total delay - period control signal is connected to the DELAY<5:0> port of the 6 - bit subtraction counter 201. The data output ports bit<5:0> of the 6 - bit subtraction counter 201 are sequentially connected to the signal input terminals of the first to sixth inverters 202 - 207 from the high - bit to the low - bit. The signal input terminals of the first to sixth inverters are respectively connected to the signal input terminals of the six - input AND gate 208. The signal output terminal CDN of the six - input AND gate 208 is simultaneously connected to the asynchronous logic clear port CDN of the first D - flip - flop with an asynchronous clear port 209 and the asynchronous logic clear port CDN of the second D - flip - flop with an asynchronous clear port 210. The clock input signal CLK_INPUT is simultaneously connected to the clock input port CLK of the first D - flip - flop with an asynchronous clear port 209, the data input port of the 2 - to - 1 data selector 211, and the signal input terminal of the seventh inverter 212. The signal output terminal of the seventh inverter 212 is connected to the other data input port of the 2 - to - 1 data selector 211. The output port of the 2 - to - 1 data selector 211 is connected to the clock port CLK of the second D - flip - flop with an asynchronous clear port 210. The clock - divided signal CLK_DIV is connected to the data port D of the first D - flip - flop with an asynchronous clear port 209. The data output port Q of the first D - flip - flop with an asynchronous clear port 209 is connected to the data input port D of the second D - flip - flop with an asynchronous clear port 210. The data output port Q of the second D - flip - flop with an asynchronous clear port 210 is connected to OUT3. The signal output terminal of the six - input AND gate 208 is connected to RESET_DIV.
[0045] The duty - cycle correction clock output circuit of the half - period delay step - output circuit 200 is composed of a rising - edge D - flip - flop 213, a falling - edge D - flip - flop 214, and an OR gate 215. OUT3 is simultaneously connected to the data ports D of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214. The output port of the 2 - to - 1 data selector 211 is simultaneously connected to the clock ports CLK of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214. The data output ports Q of the rising - edge D - flip - flop 213 and the falling - edge D - flip - flop 214 are respectively connected to the signal input terminals of the OR gate 215. The signal output terminal of the OR gate 215 is connected to OUT2.
[0046] In this embodiment, a 200Mhz signal is input through the CLK_INPUT port. After 10 - division, the delay word configured for the first time is 3 (with a delay of 1.5 cycles relative to the configuration word 0). As Figure 3 shown, the waveform of the output OUT3 signal is as shown in DELAY_3; the delay word configured for the second time is 6 (with a delay of 3 cycles relative to the configuration word 0), and the waveform of the output OUT3 signal is as shown in DELAY_6. The rising edges of the clocks of DELAY_3 and DELAY_6 are aligned with the CLK_INPUT signal, and DELAY_6 outputs with a 1.5 - cycle delay compared to DELAY_3. This circuit simultaneously realizes the functions of frequency division, delay output with a 0.5 - cycle step, and clock edge synchronization with the main clock.
Claims
1. A clock synchronization circuit with half-period delay stepping, characterized in that It includes a 1 - 1024 frequency - division circuit (100) and a half - cycle delay step - by - step output circuit (200); The externally input clock signal is connected to the signal input port of the 1 - 1024 frequency - division circuit (100). The output port of the 1 - 1024 frequency - division circuit (100) is connected to the frequency - division input port of the half - cycle delay step - by - step output circuit (200). The externally input clock signal is also connected to the clock input port of the half - cycle delay step - by - step output circuit (200); The synchronous input port of the half - cycle delay step - by - step output circuit (200) is used to receive a synchronous signal. The step - by - step mode selection signal input port of the half - cycle delay step - by - step output circuit (200) is used to receive a selection signal. The delay - period control signal input port of the half - cycle delay step - by - step output circuit (200) is used to receive a total delay - period control signal. The reset signal output port of the half - cycle delay step - by - step output circuit (200) is connected to the input reset port of the 1 - 1024 frequency - division circuit (100). The clock output port of the half - cycle delay step - by - step output circuit (200) is used to output the delayed frequency - divided signal; The 1 - 1024 frequency - division circuit (100) also has a frequency - division configuration port. By configuring the binary bit of this port, the 1 - 1024 frequency - division circuit (100) realizes the corresponding decimal - number frequency - division ratio; When the input reset port of the 1 - 1024 frequency - division circuit (100) inputs logic "1", the output port of the 1 - 1024 frequency - division circuit (100) outputs logic "0". When the input reset port of the 1 - 1024 frequency - division circuit (100) inputs logic "0", the output port of the 1 - 1024 frequency - division circuit (100) outputs the normal frequency - divided signal; The half - cycle delay step - by - step output circuit (200) includes a delay - period pulse elimination circuit and a duty - cycle correction clock output circuit; The delay - period pulse elimination circuit includes a 6 - bit subtraction counter (201), the first to sixth inverters (202~207), a six - input AND gate (208), a first D - flip - flop with an asynchronous clear port (209), a second D - flip - flop with an asynchronous clear port (210), a 2 - to - 1 data selector (211), and a seventh inverter (212); The duty - cycle correction clock output circuit is composed of a rising - edge D - flip - flop (213), a falling - edge D - flip - flop (214), and an OR gate (215). The data output port of the second D - flip - flop with an asynchronous clear port (210) is connected to the data ports of both the rising - edge D - flip - flop (213) and the falling - edge D - flip - flop (214). The output port of the 2 - to - 1 data selector (211) is connected to the clock ports of both the rising - edge D - flip - flop (213) and the falling - edge D - flip - flop (214). The data output ports of the rising - edge D - flip - flop (213) and the falling - edge D - flip - flop (214) are respectively connected to one signal input port of the OR gate (215). The signal output port of the OR gate (215) is the clock output port of the half - cycle delay step - by - step output circuit (200).
2. The clock synchronization circuit with half-cycle delay stepping according to claim 1, wherein The clock input port of the half-cycle delay step output circuit (200) is the clock input port of the 6-bit subtraction counter (201), the synchronous input port of the half-cycle delay step output circuit (200) is the synchronous input port of the 6-bit subtraction counter (201), and the delay cycle control signal input port of the half-cycle delay step output circuit (200) is the delay cycle control signal input port of the 6-bit subtraction counter (201); the data output ports of the 6-bit subtraction counter (201) are respectively connected to the signal input ports of the first to sixth inverters from the high bit to the low bit; the signal output ports of the first to sixth inverters are respectively connected to the six signal input ports of the six-input AND gate (208), and the signal output port of the six-input AND gate (208) is simultaneously connected to the asynchronous logic reset ports of the first and second D flip-flops with asynchronous reset ports; the externally input clock signal is also simultaneously connected to the clock input port of the first D flip-flop with asynchronous reset port (209), the data input port of the 2-to-1 data selector (211), and the signal input port of the seventh inverter (212). The signal output port of the seventh inverter (212) is connected to the other data input port of the 2-to-1 data selector (211). The output port of the 2-to-1 data selector (211) is connected to the clock input port of the second D flip-flop with asynchronous reset port (210); the frequency division input port of the half-cycle delay step output circuit (200) is connected to the data port of the first D flip-flop with asynchronous reset port (209), and the data output port of the first D flip-flop with asynchronous reset port (209) is connected to the data input port of the second D flip-flop with asynchronous reset port (210); the signal output port of the six-input AND gate (208) is the reset signal output port of the half-cycle delay step output circuit (200).
Citation Information
Patent Citations
Delay locked loop
CN104753524A
Programmable frequency divider and computer storage medium
WO2018094924A1