Wiring substrate, array substrate and light emitting module

Abstract

The present disclosure provides a wiring substrate, an array substrate and a light-emitting module, which belong to the field of display technology. The wiring substrate comprises a base substrate, a first metal wiring layer and an insulating material layer stacked in sequence, the first metal wiring layer is provided with a plurality of driving leads extending along a first direction, and the insulating material layer is provided with a plurality of vias exposing the driving leads. By adjusting the positions of the driving leads and the vias, the wiring substrate can be applied to different microchips, and can be used to prepare different array substrates.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a wiring substrate, an array substrate and a light-emitting module. Background Art

[0002] The Mini LED (mini light-emitting diode) backlight substrate adopts a direct-down design and achieves regional dimming in a smaller range by arranging a large number of Mini LEDs. Compared with traditional backlight designs, it has better optical performance and can achieve better brightness uniformity and higher color contrast within a smaller mixing distance.

[0003] Currently, there are many different microchips suitable for Mini LED backlight substrates, but different microchips have different requirements for the routing distribution of Mini LED backlight substrates, which leads to the need to develop backlight substrates corresponding to different microchips in a targeted manner, and the masks and intermediate substrates of different backlight substrates cannot be shared. This not only increases the development cycle and cost of different backlight substrates, but also is not conducive to simplifying the process.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art, provide a wiring substrate, an array substrate and a light-emitting module, and reduce the cost of the light-emitting module.

[0006] According to one aspect of the present disclosure, there is provided a wiring substrate, comprising a plurality of control regions distributed in an array, wherein the plurality of control regions are arranged into a plurality of control region rows and a plurality of control region columns; any one of the control region columns comprises at least two control regions arranged along a first direction, and any one of the control region rows comprises at least two control regions arranged along a second direction; the second direction is parallel to a plane where the wiring substrate is located and intersects with the first direction;

[0007] Any one of the control regions comprises four device areas distributed in an array, and the device areas are used to set functional devices electrically connected to each other; the four device areas in any one of the control regions are respectively a first device area, a second device area, a third device area and a fourth device area; wherein the first device area is the device area located in the first row in the first direction and in the first column in the second direction in the control region; the second device area is the device area located in the first row in the first direction and in the second column in the second direction in the control region; the third device area is the device area located in the second row in the first direction and in the first column in the second direction in the control region; the fourth device area is the device area located in the second row in the first direction and in the second column in the second direction in the control region;

[0008] The wiring substrate comprises a base substrate, a first metal wiring layer and an insulating material layer which are stacked in sequence; the first metal wiring layer is provided with a driving lead extending along the first direction; in any one of the control area columns, the driving lead at least comprises a first power supply voltage lead, a first input lead, a reference voltage lead, a second input lead and a second power supply voltage lead which are arranged in sequence along the second direction; the wiring substrate also has at least one signal channel extending along the first direction, and any one of the signal channels comprises at least one of the control area columns; in any one of the signal channels, the driving lead further comprises at least one address lead;

[0009] The control region includes a first control region; in one of the first control regions, the insulating material layer is provided with a first power via to a sixth power via, a first input via to a fourth input via, a first reference via and a second reference via;

[0010] The first power via to the third power via are arranged in sequence along the first direction and expose a portion of the first power voltage lead respectively; the first power via is located on a side of the device area A(1,1) away from the device area A(2,1) or between the device area A(1,1) and the device area A(2,1); the second power via is located between the device area A(1,1) and the device area A(2,1); the third power via is located on a side of the device area A(2,1) away from the device area A(1,1);

[0011] The fourth power via to the sixth power via are arranged in sequence along the first direction and expose a portion of the second power voltage lead respectively; the fourth power via is located at a side of the second device area away from the fourth device area or between the second device area and the fourth device area; the fifth power via is located between the second device area and the fourth device area; the sixth power via is located at a side of the fourth device area away from the second device area;

[0012] The first input via and the second input via respectively expose a portion of the first input lead; the first input via is located between an edge of the first device region away from the third device region and an edge of the third device region close to the first device region; the second input via is located on a side of the third device region away from the first device region;

[0013] The third input via and the fourth input via respectively expose a portion of the second input lead; the third input via is located between an edge of the second device region away from the fourth device region and an edge of the fourth device region close to the second device region; the fourth input via is located on a side of the fourth device region away from the second device region;

[0014] The first reference via and the second reference via both expose a portion of the reference voltage lead; along the first direction, the first reference via is located between the first device region and the third device region, and the second reference via is located on a side of the third device region away from the first device region;

[0015] In any one of the signal channels, the insulating material layer is further provided with at least one address via hole exposing a partial area of ​​the at least one address lead.

[0016] In an exemplary embodiment of the present disclosure, in one of the control area columns, the first power via and the fourth power via are symmetrical about a first symmetry axis, the second power via and the fifth power via are symmetrical about a second symmetry axis, and the third power via and the sixth power via are symmetrical about a third symmetry axis; the first symmetry axis, the second symmetry axis and the third symmetry axis extend along the first direction and overlap with each other.

[0017] In an exemplary embodiment of the present disclosure, in one of the control area columns, the first input via and the third input via are symmetrical about a fourth axis of symmetry, and the second input via and the fifth input via are symmetrical about a sixth axis of symmetry; the fourth axis of symmetry and the fifth axis of symmetry extend along the first direction and overlap with each other.

[0018] In an exemplary embodiment of the present disclosure, in one of the first control regions, along the first direction, the first power via and the fourth power via are located between the first device area and the first reference via, the second power via and the fifth power via are located between the third device area and the first reference via; the third power via and the sixth power via are located between the third device area and the second reference via.

[0019] In an exemplary embodiment of the present disclosure, in one of the first control areas, the insulating material layer is further provided with a third reference via and a fourth reference via exposing a partial area of ​​the reference voltage lead; the third reference via is symmetrical with the first reference via about the sixth symmetry axis, and the fourth reference via is symmetrical with the second reference via about the seventh symmetry axis; the sixth symmetry axis and the seventh symmetry axis extend along the first direction and overlap with each other.

[0020] In an exemplary embodiment of the present disclosure, in one of the first control regions, in the second direction, the third reference via and the fourth reference via are located on a side of the first reference via and the second reference via away from the first power supply voltage lead;

[0021] In one of the first control regions, the first power via, the first input via, the first reference via, the fourth power via, the third input via and the third reference via form a first via group; the third power via, the second input via and the second reference via, the sixth power via, the fourth input via and the fourth reference via form a second via group;

[0022] The relative positions between the via holes in the first via hole group are the same as the relative positions between the via holes in the second via hole group.

[0023] In an exemplary embodiment of the present disclosure, in one of the first control regions, the insulating material layer is further provided with a fifth reference via hole exposing a portion of the reference voltage lead, and the fifth reference via hole is located between the four device regions.

[0024] In an exemplary embodiment of the present disclosure, in one of the first control regions, the insulating material layer is further provided with a fifth input via exposing a partial area of ​​the first input lead; along the first direction, the fifth input via is located between the first reference via and the third device region; the insulating material layer may also be provided with a sixth input via exposing a partial area of ​​the second input lead; the sixth input via is symmetrical to the fifth input via about an eighth symmetry axis, and the eighth symmetry axis extends along the first direction.

[0025] In an exemplary embodiment of the present disclosure, the control area further includes a second control area; in any one of the control area columns, the second control area is located on one side of the first direction of each of the first control areas;

[0026] In one of the second control regions, the insulating material layer is provided with a seventh power via to a tenth power via, a seventh input via to a tenth input via, and a sixth reference via to a tenth reference via;

[0027] The seventh power via and the eighth power via both expose at least a portion of the first power voltage lead, and the ninth power via and the tenth power via both expose at least a portion of the second power voltage lead; the eighth power via is located on one side of the first direction of the seventh power via and between the first device area and the third device area; the tenth power via is located on one side of the first direction of the ninth power via and between the second device area and the fourth device area;

[0028] The seventh input via and the eighth input via both expose a portion of the first input lead; the seventh input via is located on a side of the first device region away from the third device region; the eighth input via is located between the first device region and the third device region; the ninth input via and the tenth input via both expose a portion of the second input lead; the ninth input via is located on a side of the second device region away from the fourth device region; the tenth input via is located between the second device region and the fourth device region;

[0029] The sixth reference via to the tenth reference via all expose a partial area of ​​the reference voltage lead; wherein the sixth reference via and the seventh reference via are arranged along the second direction and are located between the first device area and the third device area; the eighth reference via is located between the first device area and the third device area, the ninth reference via is located between the second device area and the fourth device area, and the tenth reference via is located between the four device areas of the second control area.

[0030] In an exemplary embodiment of the present disclosure, the wiring substrate includes a fan-out area, and the first metal wiring layer is provided with fan-out leads connected to each of the driving leads in the fan-out area; wherein the driving leads are connected to the corresponding fan-out leads in the second control area.

[0031] In an exemplary embodiment of the present disclosure, the number of the address leads is not less than the number of the control region rows;

[0032] The address vias include a first address via and a second address via; the first address via is arranged near one end of the address leads, and at least one of the first address vias is arranged in any one of the signal channels; the second address via corresponding to the control area row is arranged in any one of the control area rows, and the second address vias corresponding to each of the control area rows respectively expose partial areas of different address leads.

[0033] In an exemplary embodiment of the present disclosure, the address via also includes a third address via; along the first direction, the first address via and the third address via are respectively distributed at both ends of the wiring substrate; within one of the signal channels, the number of the address leads is at least two, the number of the third address via is at least 1, and at least one of the first address via and at least one of the third address vias respectively expose different address leads.

[0034] In an exemplary embodiment of the present disclosure, two address leads are arranged in one control area column, and one first address via and one third address via are arranged; the first address via exposes one of the address leads, and the third address via exposes the other address lead.

[0035] In an exemplary embodiment of the present disclosure, two ends of any one of the address leads are exposed by the first address via and the third address via, respectively.

[0036] In an exemplary embodiment of the present disclosure, the number of the second address vias is the same as the number of the control area rows, and each of the second address vias is arranged in a one-to-one correspondence with each of the control area rows; each of the second address vias respectively exposes a different address lead, and any second address via is located in the corresponding control area row.

[0037] In an exemplary embodiment of the present disclosure, within any one of the control region rows, the number of the second address vias is the same as the number of the address leads and are arranged in a one-to-one correspondence, and any one of the second address vias exposes the corresponding address lead.

[0038] In an exemplary embodiment of the present disclosure, the first metal wiring layer also has a first voltage distribution line extending along the second direction, and each of the driving leads is located on one side of the first direction of the first voltage distribution line; the first power supply voltage lead and the second power supply voltage lead extend in the opposite direction of the first direction to connect with the first voltage distribution line, or the reference voltage lead extends in the opposite direction of the first direction to connect with the first voltage distribution line.

[0039] In an exemplary embodiment of the present disclosure, the first metal wiring layer further includes a second voltage distribution line extending along the second direction; wherein the first voltage distribution line is located between the second voltage distribution line and each of the driving leads.

[0040] According to another aspect of the present disclosure, an array substrate is provided, comprising the above wiring substrate.

[0041] In an exemplary embodiment of the present disclosure, the array substrate further comprises a second metal wiring layer and an insulating protection layer sequentially stacked on the insulating material layer of the wiring substrate away from the side of the base substrate, and comprises a plurality of functional devices and a plurality of microchips;

[0042] Among them, the second metal wiring layer includes multiple connecting leads, multiple device pad groups and multiple chip pad groups, the functional device is bound and connected to the device pad group, and the microchip is bound and connected to the chip pad group; the device pad group and the chip pad group are connected to the connecting leads; at least part of the connecting leads are connected to the first metal wiring layer through at least part of the vias provided on the insulating material layer.

[0043] In an exemplary embodiment of the present disclosure, a device control circuit is provided in any one of the device regions, and the device control circuit includes one of the functional devices or a plurality of electrically connected functional devices;

[0044] In the first control region, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the first power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the second power via or the third power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the fourth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the fifth power via or the sixth power via.

[0045] In an exemplary embodiment of the present disclosure, in one of the control regions, the array substrate is provided with four chip pad groups corresponding to the four device regions one by one; any one of the chip pad groups includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad, and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to the output sub-pad of the chip pad group corresponding to the device region through the connecting lead;

[0046] In one of the signal channels, the device areas are numbered in sequence, and the device area numbered 1 is located at one end of the signal channel in the first direction; the chip pad groups corresponding to the device areas are cascaded in sequence according to the numbering order of the device areas; the second input sub-pad of the chip pad group corresponding to the device area numbered 1 is connected to one of the address leads through the connecting lead overlapping the address via; the output sub-pad of the chip pad group corresponding to the device area numbered (n-1) is connected to the second input sub-pad of the chip pad group corresponding to the device area numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels;

[0047] In any one of the first control regions, the reference voltage sub-pad of the chip pad group corresponding to the first device area and the reference voltage sub-pad of the chip pad group corresponding to the second device area are connected to the reference voltage lead through the connecting lead overlapping the first reference via hole; the reference voltage sub-pad of the chip pad group corresponding to the third device area and the reference voltage sub-pad of the chip pad group corresponding to the fourth device area are connected to the reference voltage lead through the connecting lead overlapping the second reference via hole; the first input sub-pad of the chip pad group corresponding to the first device area is connected to the reference voltage lead through the connecting lead overlapping the second reference via hole. The pad is connected to the first input lead through the connecting lead overlapping the first input via; the first input sub-pad of the chip pad group corresponding to the third device area and the first input lead are connected through the connecting lead overlapping the second input via; the first input sub-pad of the chip pad group corresponding to the second device area and the second input lead are connected through the connecting lead overlapping the third input via; the first input sub-pad of the chip pad group corresponding to the fourth device area and the second input lead are connected through the connecting lead overlapping the fourth input via.

[0048] In an exemplary embodiment of the present disclosure, in one of the control regions, the array substrate is provided with four chip pad groups corresponding to the four device regions one by one; any one of the chip pad groups includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad, and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to the output sub-pad of the chip pad group corresponding to the device region through the connecting lead;

[0049] In one of the signal channels, the device areas are numbered in sequence, and the device area numbered 1 is located at one end of the signal channel in the first direction; the chip pad groups corresponding to the device areas are cascaded in sequence according to the numbering order of the device areas; the second input sub-pad of the chip pad group corresponding to the device area numbered 1 is connected to one of the address leads through the connecting lead overlapping the address via; the output sub-pad of the chip pad group corresponding to the device area numbered (n-1) is connected to the second input sub-pad of the chip pad group corresponding to the device area numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels;

[0050] In any one of the first control regions, the first input sub-pad of the chip pad group corresponding to the first device region is connected to the first input lead via the connecting lead overlapping the first input via; the first input sub-pad of the chip pad group corresponding to the third device region is connected to the first input lead via the connecting lead overlapping the second input via; the first input sub-pad of the chip pad group corresponding to the second device region is connected to the second input lead via the connecting lead overlapping the third input via; the first input sub-pad of the chip pad group corresponding to the fourth device region is connected to the second input lead via the connecting lead overlapping the fourth input via;

[0051] When the wiring substrate is provided with the third reference via and the fourth reference via, in any one of the first control areas, the reference voltage sub-pad of the chip pad group corresponding to the first device area and the reference voltage lead are connected through the connecting lead overlapping with the first reference via; the reference voltage sub-pad of the chip pad group corresponding to the third device area and the reference voltage lead are connected through the connecting lead overlapping with the second reference via; the reference voltage sub-pad of the chip pad group corresponding to the second device area and the reference voltage lead are connected through the connecting lead overlapping with the third reference via; the reference voltage sub-pad of the chip pad group corresponding to the fourth device area and the reference voltage lead are connected through the connecting lead overlapping with the fourth reference via.

[0052] In an exemplary embodiment of the present disclosure, when the wiring substrate includes the second control area, in any one of the second control areas, the chip pad group corresponding to the first device area and the chip pad group corresponding to the second device area are located between the first device area and the second device area; and the chip pad group corresponding to the first device area is arranged close to the first device area, and the chip pad group corresponding to the second device area is arranged close to the second device area; in the first direction, the chip pad group corresponding to the third device area is between the first device area and the third device area, and the chip pad group corresponding to the fourth device area is between the second device area and the fourth device area;

[0053] In any one of the chip pad groups corresponding to the first device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the sixth reference via, and the first input sub-pad is connected to the first input lead through the connection lead overlapping the seventh input via;

[0054] In the chip pad group corresponding to the second device area in any one of the second control regions, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the seventh reference via, and the first input sub-pad is connected to the second input lead through the connection lead overlapping the ninth input via;

[0055] In any one of the chip pad groups corresponding to the third device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the eighth reference via, and the first input sub-pad is connected to the first input lead through the connection lead overlapping the eighth input via;

[0056] In any one of the chip pad groups corresponding to the fourth device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the ninth reference via, and the first input sub-pad is connected to the second input lead through the connection lead overlapping the tenth input via;

[0057] In any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via.

[0058] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; the reference voltage sub-pad is located on one side of the first direction of the address sub-pad;

[0059] In any one of the first control areas, the reference voltage sub-pad is located on one side of the first direction of the address sub-pad; the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the second reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

[0060] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0061] When the wiring substrate is provided with the fifth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

[0062] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0063] When the wiring substrate is provided with the fifth input via and the sixth input via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping with the fifth input via, and the other is connected to the second input lead through the connecting lead overlapping with the sixth input via; the address sub-pad is connected to the address lead through the connecting lead overlapping with the address via.

[0064] In an exemplary embodiment of the present disclosure, when the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence;

[0065] The reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the eighth input via, and the other is connected to the second input lead through the connecting lead overlapping the tenth input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

[0066] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0067] In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels;

[0068] In any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the second reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

[0069] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0070] In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering sequence of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead;

[0071] When the wiring substrate includes the fifth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

[0072] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0073] In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels;

[0074] When the wiring substrate includes the fifth reference via and the sixth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the fifth input via, and the other is connected to the second input lead through the connecting lead overlapping the sixth input via.

[0075] In an exemplary embodiment of the present disclosure, when the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence;

[0076] The reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the eighth input via, and the other is connected to the second input lead through the connecting lead overlapping the tenth input via.

[0077] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes two reference voltage sub-pads, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0078] In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels;

[0079] In any one of the first control areas, in the second direction, the reference voltage sub-pad is located between the selection signal sub-pad and the first reference via; one of the reference voltage sub-pads is connected to the reference voltage lead through the connecting lead overlapping the first reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

[0080] In an exemplary embodiment of the present disclosure, in any one of the control regions, the array substrate is provided with one chip pad group, and the chip pad group is located between the four device regions of the control region; the chip pad group includes two reference voltage sub-pads, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device regions are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads;

[0081] In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering sequence of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead;

[0082] When the wiring substrate includes the fifth reference via, in any one of the first control areas, in the second direction, the reference voltage sub-pad is located between the selection signal sub-pad and the first reference via; the chip pad group is located on the second direction side of the fifth reference via; one of the reference voltage sub-pads is connected to the reference voltage lead through the connecting lead overlapping the first reference via; the other reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

[0083] In an exemplary embodiment of the present disclosure, when the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence;

[0084] One of the reference voltage sub-pads is connected to the reference voltage lead via the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead via the connecting lead overlapping the eighth input via, and the other is connected to the second input lead via the connecting lead overlapping the tenth input via.

[0085] According to another aspect of the present disclosure, a light-emitting module is provided, comprising the above-mentioned array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0086] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0087] Figure 1 This is a schematic diagram of the positions of the pins of the first chip in the present disclosure.

[0088] Figure 2 Schematic diagram of the positions of the sub-pads of the first pad group in the present disclosure.

[0089] Figure 3 Schematic diagram of the positions of the pins of the second chip in the present disclosure.

[0090] Figure 4 Schematic diagram of the positions of the sub-pads of the second pad group in the present disclosure.

[0091] Figure 5 Schematic diagram of the positions of the pins of the third chip in the present disclosure.

[0092] Figure 6 FIG. 4 is a schematic diagram of the positions of the sub-pads of the third pad group in the present disclosure.

[0093] Figure 7 Schematic diagram of the positions of the pins of the fourth chip in the present disclosure.

[0094] Figure 8 Schematic diagram of the positions of the sub-pads of the fourth pad group in the present disclosure.

[0095] Fig. 9 Schematic diagram of a partial structure of a wiring substrate in one embodiment of the present disclosure, wherein: Fig. 9 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0096] Fig.10for Fig. 9 The schematic diagram of a partial enlargement of a wiring substrate in a first control area is shown, wherein: Fig.10 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0097] Fig.11 This is a schematic diagram of the structure of a first array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.11 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the first pad group for binding the first chip, and the functional devices in each device area are illustrated.

[0098] Fig.12 This is a schematic diagram of the structure of a second array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.12 Only the driving leads, the relative positions of at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the second pad group for binding the second chip, and the functional devices in each device area are illustrated.

[0099] Fig.13 This is a schematic diagram of the structure of a third array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.13 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the third pad group for binding the third chip, and the functional devices in each device area are illustrated.

[0100] Fig.14 This is a schematic diagram of the structure of a fourth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.14 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the fourth pad group for binding the fourth chip, and the functional devices in each device area are illustrated.

[0101] Fig.15 Schematic diagram of a partial structure of a wiring substrate in one embodiment of the present disclosure, wherein: Fig.15 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0102] Fig.16 for Fig.15 The schematic diagram of a partial enlargement of a wiring substrate in a first control area is shown, wherein: Fig.16 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0103] Fig.17This is a schematic diagram of the structure of a fifth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.17 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the first pad group for binding the first chip, and the functional devices in each device area are illustrated.

[0104] Fig.18 This is a schematic diagram of the structure of a sixth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.18 Only the driving leads, the relative positions of at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the second pad group for binding the second chip, and the functional devices in each device area are illustrated.

[0105] Fig.19 This is a schematic diagram of the structure of a seventh array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.19 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the third pad group for binding the third chip, and the functional devices in each device area are illustrated.

[0106] Fig. 20 This is a schematic diagram of the structure of an eighth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig. 20 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the fourth pad group for binding the fourth chip, and the functional devices in each device area are illustrated.

[0107] Fig.21 Schematic diagram of a partial structure of a wiring substrate in one embodiment of the present disclosure, wherein: Fig.21 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0108] Fig. 22 for Fig.21 The schematic diagram of a partial enlargement of a wiring substrate in a first control area is shown, wherein: Fig. 22 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0109] Fig.23 This is a schematic diagram of the structure of a ninth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.23 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the first pad group for binding the first chip, and the functional devices in each device area are illustrated.

[0110] Fig.24 This is a schematic diagram of the structure of the tenth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.24 Only the driving leads, the relative positions of at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the second pad group for binding the second chip, and the functional devices in each device area are illustrated.

[0111] Fig.25 This is a schematic structural diagram of an eleventh array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.25 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the third pad group for binding the third chip, and the functional devices in each device area are illustrated.

[0112] Fig.26 This is a schematic structural diagram of a twelfth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.26 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the fourth pad group for binding the fourth chip, and the functional devices in each device area are illustrated.

[0113] Fig. 27 Schematic diagram of a partial structure of a wiring substrate in one embodiment of the present disclosure, wherein: Fig. 27 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0114] Fig.28 for Fig. 27 The schematic diagram of a partial enlargement of a wiring substrate in a first control area is shown, wherein: Fig.28 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0115] Fig.29 This is a schematic structural diagram of a thirteenth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.29 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the first pad group for binding the first chip, and the functional devices in each device area are illustrated.

[0116] Fig.30 This is a schematic structural diagram of a fourteenth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.30Only the driving leads, the relative positions of at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the second pad group for binding the second chip, and the functional devices in each device area are illustrated.

[0117] Fig.31 This is a schematic structural diagram of a fifteenth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.31 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the third pad group for binding the third chip, and the functional devices in each device area are illustrated.

[0118] Fig.32 This is a schematic diagram of the structure of a sixteenth array substrate in a first control area in an embodiment of the present disclosure; wherein: Fig.32 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the fourth pad group for binding the fourth chip, and the functional devices in each device area are illustrated.

[0119] Fig.33 Schematic diagram of a partial structure of a wiring substrate in one embodiment of the present disclosure, wherein: Fig.33 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0120] Fig.34 for Fig.33 The schematic diagram of a partial enlargement of a second control area of ​​a wiring substrate shown in FIG. Fig.34 Only the relative positions of at least part of the vias provided in the first metal wiring layer and the insulating material layer are illustrated.

[0121] Fig.35 This is a schematic diagram of the structure of a seventeenth array substrate in a second control area in an embodiment of the present disclosure; wherein: Fig.35 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the first pad group for binding the first chip, and the functional devices in each device area are illustrated.

[0122] Fig.36 This is a schematic diagram of the structure of an eighteenth array substrate in a second control area in an embodiment of the present disclosure; wherein: Fig.36 Only the driving leads, the relative positions of at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the second pad group for binding the second chip, and the functional devices in each device area are illustrated.

[0123] Fig.37This is a schematic diagram of the structure of a nineteenth array substrate in a second control area in an embodiment of the present disclosure; wherein: Fig.37 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the third pad group for binding the third chip, and the functional devices in each device area are illustrated.

[0124] Fig.38 This is a schematic diagram of the structure of the twentieth array substrate in a second control area in an embodiment of the present disclosure; wherein: Fig.38 Only the relative positions of the driving leads, at least part of the vias provided in the insulating material layer, the connecting leads (indicated by thick lines), the fourth pad group for binding the fourth chip, and the functional devices in each device area are illustrated.

[0125] Fig.39 It is a schematic diagram of the partial structure of input leads and reference voltage leads in a wiring substrate according to an embodiment of the present disclosure.

[0126] Fig.40 The present invention is a schematic diagram of the relative positions of address vias and address leads in a wiring substrate according to an embodiment of the present invention.

[0127] Fig.41 The present invention is a schematic structural diagram of an array substrate in which a microchip is electrically connected to an address lead in an embodiment of the present invention.

[0128] Fig.42 The present invention is a schematic structural diagram of an array substrate in which a microchip is electrically connected to an address lead in an embodiment of the present invention.

[0129] Fig.43 The present invention is a schematic diagram of the relative positions of address vias and address leads in a wiring substrate according to an embodiment of the present invention.

[0130] Fig.44 The present invention is a schematic structural diagram of an array substrate in which a microchip is electrically connected to an address lead in an embodiment of the present invention.

[0131] Fig.45 The present invention is a schematic structural diagram of an array substrate in which a microchip is electrically connected to an address lead in an embodiment of the present invention.

[0132] Fig.46 This is a schematic diagram of the local structure of an array substrate according to an embodiment of the present disclosure, at one end away from the binding area.

[0133] Fig.47 FIG. 1 is a schematic diagram of a partial structure of an array substrate according to an embodiment of the present disclosure, wherein: Fig.47 Functional devices bonded to the device pad groups are not shown.

[0134] Fig.48 In one embodiment of the present disclosure, the wiring substrate is Fig.47 Schematic diagram of the cross-sectional structure of the MN position.

[0135] Fig.49 In one embodiment of the present disclosure, the array substrate is Fig.47 Schematic diagram of the cross-sectional structure of the MN position, where: Fig.49 Functional devices bonded to the device pad groups are not shown.

[0136] Fig.50 This is a schematic structural diagram of a first metal wiring layer at one end close to a binding area in one embodiment of the present disclosure.

[0137] Description of reference numerals:

[0138] 101, substrate; 102, first metal wiring layer; 1021, copper seed layer; 1022, copper growth layer; 103, insulating material layer; 1031, first passivation layer; 1032, planarization organic material layer; 104, second metal wiring layer; 105, insulating protection layer; 1051, second passivation layer; 1052, organic protection layer; 106, microchip; 107, functional device; 108, buffer layer; 201, control area; 210, control area row; 220, control area column; 2011, first control area; 2012, second control area; 300, driving lead; 301, protrusion; 302, accommodation gap; 303, first support metal part; 304, second support metal part ; 305, third supporting metal part; 306, fourth supporting metal part; 310, first power supply voltage lead; 320, first input lead; 330, reference voltage lead; 340, second input lead; 350, second power supply voltage lead; 360, address lead; 361, first address lead; 362, second address lead; 371, first voltage distribution line; 372, second voltage distribution line; 373, jumper lead; 374, conductive connection part; 400, fan-out lead; 500, connecting lead; 010, first chip; 011, reference voltage pin; 012, output pin; 013, first input pin; 014, second input pin; P10, first pad group; P11, reference voltage sub-pad ; P12, output sub-pad; P13, first input sub-pad; P14, second input sub-pad; 020, second chip; 021, reference voltage pin; 0221, first output pin; 0222, second output pin; 0223, third output pin; 0224, fourth output pin; 023, chip power pin; 024, drive data pin; 025, address pin; P20, second pad group; P21, reference voltage sub-pad; P221, first output sub-pad; P222, second output sub-pad; P223, third output sub-pad; P224, fourth output sub-pad; P23, chip power sub-pad; P24, drive data sub-pad; P25, address sub-pad; 030, third Chip; 031, reference voltage pin; 0321, first output pin; 0322, second output pin; 0323, third output pin; 0324, fourth output pin; 033, chip power pin; 034, drive data pin; 035, strobe signal pin; 036, relay signal pin; P30, third pad group; P31, reference voltage sub-pad; P321, first output sub-pad; P322, second output sub-pad; P323, third output sub-pad; P324, fourth output sub-pad; P33, chip power sub-pad; P34, drive data sub-pad; P35, strobe signal sub-pad; P36, relay signal sub-pad; 040, fourth chip; 041, reference voltage pin;0421, first output pin; 0422, second output pin; 0423, third output pin; 0424, fourth output pin; 043, chip power pin; 044, drive data pin; 045, strobe signal pin; 046, relay signal pin; P40, fourth pad group; P41, reference voltage sub-pad; P421, first output sub-pad; P422, second output sub-pad; P423, third output sub-pad; P424, fourth Output sub-pad; P43, chip power sub-pad; P44, drive data sub-pad; P45, strobe signal sub-pad; P46, relay signal sub-pad; P50, device pad group; P51, first device sub-pad; P52, second device sub-pad; HV1, first power via; HV2, second power via; HV3, third power via; HV4, fourth power via; HV5, fifth power via; HV6, sixth power via; HV7, seventh Power via; HV8, eighth power via; HV9, ninth power via; HV10, tenth power via; HI1, first input via; HI2, second input via; HI3, third input via; HI4, fourth input via; HI5, fifth input via; HI6, sixth input via; HI7, seventh input via; HI8, eighth input via; HI9, ninth input via; HI10, tenth input via; HR1, first reference via; HR2, second reference via; HR3, third reference via; HR4, fourth reference via; HR5, fifth reference via; HR6, sixth reference via; HR7, seventh reference via; HR8, eighth reference via; HR9, ninth reference via; HR10, tenth reference via; HD1, first address via; HD2, second address via; HD3, third address via; A, device area; B, binding area; C, first direction; D, second direction. ; DETAILED DESCRIPTION

[0139] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0140] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0141] In the related art, an array substrate used as an actively driven Mini LED substrate may include a base substrate, a first metal wiring layer, an insulating material layer, a second metal wiring layer, an insulating protective layer, and a microchip and a light-emitting element bound to the second metal wiring layer, which are stacked in sequence. Among them, the first metal wiring layer may be provided with a driving lead; the second metal wiring layer is provided with a device pad group for binding the light-emitting element and a chip pad group for binding the microchip, and is also provided with a connecting lead for connecting the device pad group, the chip pad group and the driving lead. Under the control of the microchip, the light-emitting element can emit light in a controlled manner. In the related art, there are many different microchips that can be used for array substrates.

[0142] For example, see Figure 1 As a microchip, the first chip 010 has four different pins, namely, a first input pin 013, a second input pin 014, a reference voltage pin 011, and an output pin 012. The four pins are distributed in a rectangular area and are respectively located at the four vertices of the rectangular area. The reference voltage pin 011 is used to load the reference voltage GND to the first chip 010, the first input pin 013 is used to load the first input signal Pwr to the first chip 010, and the second input pin 014 is used to load the second input signal Di to the first chip 010.

[0143] The first chip 010 can be configured to output a relay signal through the output pin 012 in a first time period according to the first input signal Pwr loaded on the first input pin 013 and the second input signal Di loaded on the second input pin 014, and provide a light-emitting path for the light-emitting element through the output pin 012 in a second time period. Among them, the relay signal is an address signal or a selection signal. When the second input pin 014 of a first chip 010 is loaded with the relay signal, the first chip 010 can receive the first input signal Pwr loaded on the first input pin 013. The first input signal Pwr is a power line carrier communication signal, which can provide the chip operating voltage VCC to the first chip 010 while providing driving data. When the first chip 010 is applied to an array substrate, one or more interconnected light-emitting elements can form a light-emitting area, and a light-emitting area can be connected to the output pin 012 of a first chip 010. In this way, a first chip 010 can drive a light-emitting area, and multiple first chips 010 can be cascaded in sequence to form a signal channel. In a signal channel, the nth-stage first chip 010 responds to the relay signal of the (n-1)th-stage first chip 010 and sends the relay signal to the (n+1)th-stage first chip 010 , thereby realizing the control of the first chips 010 at each stage.

[0144] See also Figure 2 In order to connect with the first chip 010, a first pad group P10 as a chip pad group needs to be provided on the array substrate, and the first pad group P10 has a plurality of sub-pads corresponding to the respective pins of the first chip 010. The first pad group P10 may include a reference voltage sub-pad P11 for binding and connecting with the reference voltage pin 011 of the first chip 010, an output sub-pad P12 for binding and connecting with the output pin 012 of the first chip 010, a first input sub-pad P13 for binding and connecting with the first input pin 013 of the first chip 010, and a second input sub-pad P14 for binding and connecting with the second input pin 014 of the first chip 010.

[0145] For example, see Figure 3As a microchip, the second chip 020 has eight different pins, namely, a chip power pin 023, a drive data pin 024, an address pin 025, a reference voltage pin 011, and four output pins (including a first output pin 0221, a second output pin 0222, a third output pin 0223, and a fourth output pin 0224). The eight pins are distributed in a rectangular area, four output pins are respectively arranged at the four vertices of the rectangular area, and the chip power pin 023, the drive data pin 024, the address pin 025, and the reference voltage pin 021 are respectively arranged in the middle of the four edges of the rectangular area. The chip power pin 023 and the drive data pin 024 are respectively located on two edges arranged opposite to each other. Among them, the chip power pin 023 is used to load the chip operating voltage VCC to the second chip 020, the drive data pin 024 is used to load the drive data Data to the second chip 020, the reference voltage pin 021 is used to load the reference voltage GND to the second chip 020, the address pin 025 is used to load the selection signal to the second chip 020, and the four output pins are respectively used to load the drive signals output by the second chip 020.

[0146] The second chip 020 is configured to receive the driving data Data loaded on the driving data pin 024 under the control of the selection signal loaded on the address pin 025; then, according to the received driving data Data, the chip working voltage VCC loaded on the chip power pin 023, and the reference voltage GND loaded on the reference voltage pin 021, the four output pins are used to provide light-emitting paths for the light-emitting elements. When the second chip 020 is applied to the array substrate, one or more interconnected light-emitting elements can form a light-emitting area, and a light-emitting area can be connected to an output pin of a second chip 020. In this way, any output pin of the second chip 020 can be used to control a light-emitting area; that is, a second chip 020 can control four light-emitting areas to emit light independently. Multiple second chips 020 can be arranged in multiple rows, and the array substrate controls each second chip 020 by scanning each second chip row row by row.

[0147] See also Figure 4In order to complete the connection with the second chip 020, a second pad group P20 as a chip pad group needs to be set on the array substrate. The second pad group P20 includes eight sub-pads, namely, a chip power sub-pad P23 for binding and connecting with the chip power pin 023, a drive data sub-pad P24 for binding and connecting with the drive data pin 024, an address sub-pad P25 for binding and connecting with the address pin 025, a reference voltage sub-pad P11 for binding and connecting with the reference voltage pin 011, and four output sub-pads for binding and connecting with four output pins in a one-to-one correspondence. Among them, the four output sub-pads include a first output sub-pad P221 for binding and connecting with the first output pin 0221, a second output sub-pad P222 for binding and connecting with the second output pin 0222, a third output sub-pad P223 for binding and connecting with the third output pin 0223, and a fourth output sub-pad P224 for binding and connecting with the fourth output pin 0224. See Figure 4 , eight sub-pads are distributed in a rectangular area, four output sub-pads are respectively arranged at the four vertices of the rectangular area, and chip power sub-pad P23, drive data sub-pad P24, address sub-pad P5, and reference voltage sub-pad P21 are respectively arranged in the middle of the four edges of the rectangular area. The chip power sub-pad P23 and the drive data sub-pad P24 are respectively located on two edges that are arranged oppositely, and the reference voltage sub-pad P11 and the address sub-pad P25 are respectively located on two edges that are arranged oppositely; the reference voltage sub-pad P11 can also extend to the center of the rectangular area.

[0148] For example, see Figure 5The third chip 030 is a microchip, comprising nine pins, namely, a chip power pin 033, a driving data pin 034, a strobe signal pin 035, a relay signal pin 036, a reference voltage pin 031 and four output pins, wherein the four output pins respectively comprise a first output pin 0321, a second output pin 0322, a third output pin 0323 and a fourth output pin 0324. The nine pins are arranged in a three-row and three-column array in a rectangular area, wherein four output pins are respectively arranged at the four vertices of the rectangular area, a strobe signal pin 035 is arranged at the center of the rectangular area, and a relay signal pin 036, a chip power pin 033, a reference voltage pin 031 and a driving data pin 034 are respectively arranged at the four edges of the rectangular area. Among them, the chip power pin 033 and the driving data pin 034 are respectively located on two opposite edges, and the relay signal pin 036 and the reference voltage pin 031 are respectively located on two opposite edges. The chip power pin 033 is used to load the chip working voltage VCC to the third chip 030, the driving data pin 034 is used to load the driving data Data to the third chip 030, the reference voltage pin 031 is used to load the reference voltage GND to the third chip 030, the selection signal pin 035 is used to load the selection signal to the third chip 030, the relay signal pin 036 is used to load the relay signal output by the third chip 030, and the four output pins are respectively used to load the driving signal output by the third chip 030. The relay signal is a selection signal, and when the selection signal pin 035 of a third chip 030 is loaded with the relay signal, the third chip 030 can receive the driving data Data loaded on the driving data pin 034.

[0149] The third chip 030 is configured to output a relay signal through the relay signal pin 036 according to the strobe signal or relay signal loaded on the strobe signal pin 035 and the drive data Data loaded on the drive data pin 034, and to provide a light-emitting path for the light-emitting element through four output pins. When the third chip 030 is applied to the array substrate, one or more interconnected light-emitting elements can form a light-emitting area, and a light-emitting area can be connected to an output pin of a third chip 030. The four output pins of a third chip 030 can drive a light-emitting area respectively, that is, a third chip 030 can drive four light-emitting areas. Multiple third chips 030 can be cascaded in sequence to form a signal channel; in a signal channel, the first-level third chip 030 responds to the strobe signal and sends a relay signal to the second-level third chip 030, and the n-th-level third chip 030 responds to the relay signal of the (n-1)-th-level third chip 030 and sends a relay signal to the (n+1)-th-level third chip 030, thereby realizing the control of the third chips 030 at each level.

[0150] See also Figure 6 In order to achieve connection with the third chip 030, a third pad group P30 as a chip pad group needs to be set on the array substrate. The third pad group P30 includes nine sub-pads corresponding to the nine pins of the third chip 030, namely, a chip power sub-pad P33 for binding and connecting with the chip power pin 033, a drive data sub-pad P34 for binding and connecting with the drive data pin 034, a strobe signal sub-pad P35 for binding and connecting with the strobe signal pin 035, a relay signal sub-pad P36 for binding and connecting with the relay signal pin 036, a reference voltage sub-pad P31 for binding and connecting with the reference voltage pin 031, and four output sub-pads for binding and connecting with the four output pins in a one-to-one correspondence. The four output sub-pads include a first output sub-pad P321, a second output sub-pad P322, a third output sub-pad P323, and a fourth output sub-pad P324. Nine sub-pads are arranged in a three-row and three-column array in a rectangular area, four output sub-pads are respectively arranged at the four vertices of the rectangular area, a strobe signal sub-pad P35 is arranged at the center of the rectangular area, and a relay signal sub-pad P36, a chip power sub-pad P33, a reference voltage sub-pad P31 and a drive data sub-pad P34 are respectively arranged at the four edges of the rectangular area. Among them, the chip power sub-pad P33 and the drive data sub-pad P34 are respectively located on two opposite edges, and the relay signal sub-pad P36 and the reference voltage sub-pad P31 are respectively located on two opposite edges.

[0151] For example, see Figure 7As a microchip, the fourth chip 040 includes ten pins, namely, a chip power pin 043, a drive data pin 044, a strobe signal pin 045, a relay signal pin 046, two reference voltage pins 041 and four output pins. The four output pins include a first output pin 0421, a second output pin 0422, a third output pin 0423 and a fourth output pin 0424. The ten pins are arranged in two columns and five rows in a rectangular area, wherein the first column is provided with the first output pin 0421, the relay signal pin 046, the chip power pin 043, the strobe signal pin 045 and the third output pin 0423 in sequence; the second column is provided with the second output pin 0422, the reference voltage pin 041, the drive data pin 044, the reference voltage pin 041 and the fourth output pin 0424 in sequence. Among them, the chip power pin 043 is used to load the chip working voltage VCC to the fourth chip 040, the driving data pin 044 is used to load the driving data Data to the fourth chip 040, the reference voltage pin 041 is used to load the reference voltage GND to the fourth chip 040, the selection signal pin 045 is used to load the selection signal to the fourth chip 040, the relay signal pin 046 is used to load the relay signal output by the fourth chip 040, and the four output pins are used to load the driving signal output by the fourth chip 040. Among them, the relay signal is a selection signal, and when the selection signal pin 045 of a fourth chip 040 is loaded with the relay signal, the fourth chip 040 can receive the driving data Data loaded on the driving data pin 044.

[0152] The fourth chip 040 is configured to output a relay signal through the relay signal pin 046 according to the strobe signal or relay signal loaded on the strobe signal pin 045 and the drive data loaded on the drive data pin 044, and to provide a light-emitting path for the light-emitting element through four output pins. When the fourth chip 040 is applied to the array substrate, one or more interconnected light-emitting elements can form a light-emitting area, and a light-emitting area can be connected to an output pin of a fourth chip 030. In this way, the four output pins of the fourth chip 040 can drive a light-emitting area respectively, that is, a fourth chip 040 can drive four light-emitting areas. Multiple fourth chips 040 can be cascaded in sequence to form a signal channel; in a signal channel, the nth-level fourth chip 040 responds to the relay signal of the (n-1)th-level fourth chip 040 and sends the relay signal to the (n+1)th-level fourth chip 040, thereby realizing the control of each fourth chip 040.

[0153] See also Figure 8In order to complete the electrical connection with the fourth chip 040, a fourth pad group P40 as a chip pad group needs to be set on the array substrate. The fourth pad group P40 includes ten sub-pads corresponding one-to-one to the ten pins of the fourth chip 040, namely, a chip power sub-pad P43 for binding and connecting to the chip power pin 043, a driving data sub-pad P44 for binding and connecting to the driving data pin 044, a selection signal sub-pad P45 for binding and connecting to the selection signal pin 045, a relay signal sub-pad P46 for binding and connecting to the relay signal pin 046, two reference voltage sub-pads P41 for binding and connecting one-to-one with the two reference voltage pins 041, and four output sub-pads for binding and connecting one-to-one with the four output pins. The four output sub-pads include a first output sub-pad P421 for binding and connecting with the first output pin 0421, a second output sub-pad P422 for binding and connecting with the second output pin 0422, a third output sub-pad P423 for binding and connecting with the third output pin 0423, and a fourth output sub-pad P424 for binding and connecting with the fourth output pin 0424. The ten sub-pads are distributed in a rectangular area in two columns and five rows, wherein the first column sequentially arranges the first output sub-pad P421, the relay signal sub-pad P46, the chip power sub-pad P43, the strobe signal sub-pad P45 and the third output sub-pad P423; the second column sequentially arranges the second output sub-pad P422, the reference voltage sub-pad P41, the drive data sub-pad P44, the reference voltage sub-pad P41 and the fourth output sub-pad P424.

[0154] As can be seen from the above, there are differences in the number of pins of different microchips, the signals loaded by each pin, the position distribution of the pins that load the same signal, etc., and the number of light-emitting areas that can be driven by different microchips may also be different. This leads to different requirements for the arrangement of the driving leads located in the first metal wiring layer, the arrangement of the connecting leads and the device pad group located in the second metal wiring layer when forming the array substrate, resulting in great differences in the structure of different array substrates.

[0155] Moreover, in the related art, when preparing the array substrate, uncontrolled short circuits are likely to occur between the driving leads of the first metal wiring layer and the connecting leads of the second metal wiring layer. If the connecting leads are adjusted at will, the probability of short circuits between the connecting leads and the driving leads of different signals may increase, which will reduce the yield of the array substrate.

[0156] In order to simplify the preparation process of different array substrates, reduce the preparation cost of different array substrates without reducing the yield of the array substrates, the present disclosure provides a wiring substrate. Fig.48The wiring substrate of the present disclosure includes a base substrate 101, a first metal wiring layer 102 and an insulating material layer 103 which are stacked in sequence, and can be used to further prepare at least two different types of array substrates, and the types of microchips used on each type of array substrate can be different. In other words, based on the wiring substrate provided by the present disclosure, see Fig.49 , the required second metal wiring layer 104 and insulating protection layer 105 can be further prepared, and functional devices ( Fig.49 Not shown) and the required microchip ( Fig.49 In this way, the wiring substrate of the present disclosure can be used as an intermediate substrate and is applicable to different types of array substrates, so that different types of array substrates can use the same process, materials and equipment in the preparation stage of the wiring substrate, such as sharing the same mask plate, thereby reducing the cost of different types of array substrates and facilitating the improvement of the production capacity and yield of different types of array substrates.

[0157] In the wiring substrate provided in the present disclosure, see Fig.48 The insulating material layer 103 may be provided with a plurality of vias exposing the first metal wiring layer 102. When preparing an array substrate based on the wiring substrate disclosed in the present invention, refer to Fig.49 , the second metal wiring layer 104 can be connected to the first metal wiring layer 102 through at least some of the vias, and the rest of the vias can be filled with the insulating protective layer 105. When different array substrates are prepared based on the wiring substrate of the present disclosure, the vias used to connect the second metal wiring layer 104 to the first metal wiring layer 102 in one array substrate can still be used to connect the second metal wiring layer 104 to the first metal wiring layer 102 in another array substrate, or can be filled with the insulating protective layer 105 without overlapping with the second metal wiring layer 104. Of course, when different array substrates are prepared based on the wiring substrate of the present disclosure, the vias filled with the insulating protective layer 105 and not overlapping with the second metal wiring layer 104 in one array substrate can be used to connect the second metal wiring layer 104 to the first metal wiring layer 102 in another array substrate, or can still be filled with the insulating protective layer 105 without overlapping with the second metal wiring layer 104. In this way, the insulating material layer 103 of the wiring substrate of the present disclosure can be adapted to different types of array substrates by providing redundant vias.

[0158] In the present disclosure, when describing that two structures overlap, it means that the orthographic projection of one structure on the substrate substrate overlaps with the orthographic projection of another structure on the substrate substrate. When describing that two structures completely overlap, it means that the orthographic projection of one structure on the substrate substrate is completely within the orthographic projection of the other structure on the substrate substrate.

[0159] In the wiring substrate and array substrate of the present disclosure, the substrate substrate 101 can be a substrate substrate of an inorganic material, or a substrate substrate of an organic material. For example, in one embodiment of the present disclosure, the material of the substrate substrate can be a glass material such as soda-lime glass, quartz glass, sapphire glass, or can be a metal material such as stainless steel, aluminum, nickel, etc. In another embodiment of the present disclosure, the material of the substrate substrate can be polymethyl methacrylate (PMMA), polyvinyl alcohol (PVA), polyvinyl phenol (PVP), polyether sulfone (PES), polyimide, polyamide, polyacetal, polycarbonate (PC), polyethylene terephthalate (PET), polyethylene naphthalate (PEN) or a combination thereof.

[0160] Optionally, in one embodiment of the present disclosure, the base substrate 101 may be a glass substrate.

[0161] Optionally, in terms of pattern and function, the first metal wiring layer 102 may include a driving lead and a fan-out lead connected to the driving lead. In one embodiment of the present disclosure, the first metal wiring layer 102 may also include a binding pad connected to the fan-out lead. It is understood that the area of ​​the first metal wiring layer that serves as the binding pad has no surface covered by any other insulating film layer to ensure electrical connection with an external signal source circuit such as a printed circuit board.

[0162] From the perspective of hierarchical structure, the first metal wiring layer 102 may include a single metal layer or multiple metal layers. Fig.48 , the first metal wiring layer 102 may include a copper seed layer 1021 and a copper growth layer 1022 sequentially stacked on one side of the base substrate 101. In some embodiments, the copper growth layer 1022 may be disposed on a surface of the copper seed layer 1021 away from the base substrate 101, and at least part of the side surface of the copper seed layer 1021 may be exposed, for example, the orthographic projections of the copper seed layer 1021 and the copper growth layer 1022 on the base substrate 101 may substantially overlap. In other embodiments, the copper growth layer 1022 may completely cover the side surface of the copper seed layer 1021 and its surface away from the base substrate 101.

[0163] In some embodiments, the copper seed layer 1021 may be formed by a magnetron sputtering method, and the copper growth layer 1022 may be formed by an electroplating or chemical plating method. Optionally, the copper seed layer 1021 may include a first metal adhesion layer and a first copper metal layer sequentially stacked on one side of the base substrate 101, and the first metal adhesion layer may enhance the bonding force between the first copper metal layer and the base substrate 101; the material of the first metal adhesion layer may be an alloy material containing molybdenum, for example, a molybdenum-niobium alloy, a molybdenum-niobium-copper alloy, etc. Optionally, the first metal wiring layer 102 may also include a first metal protective layer located on a side of the copper growth layer 1022 away from the base substrate 101, and the first metal protective layer may prevent the surface of the copper growth layer 1022 from being oxidized; the material of the first metal protective layer may be an alloy containing nickel or molybdenum, for example, a copper-nickel alloy, a molybdenum-niobium alloy, a molybdenum-titanium-nickel (MTD) alloy, etc. In some embodiments, the first metal wiring layer 102 may further include an etch stop layer located on a surface of the first metal wiring layer 102 away from the base substrate 101, so as to reduce or avoid etching of the first metal wiring layer 102 when preparing the second metal wiring layer 104 of the array substrate. The material of the etch stop layer may be a conductive metal oxide, such as indium zinc oxide.

[0164] The first metal wiring layer 102 may be prepared by a variety of different methods. By way of example, in one embodiment of the present disclosure, an unpatterned copper seed layer 1021 covering the base substrate 101 may be formed first, and then copper may be deposited by electroplating copper to form an unpatterned copper growth layer 1022, and finally the patterned copper seed layer 1021 and the unpatterned copper growth layer 1022 may be patterned to obtain the first metal wiring layer 102. By way of example again, in another embodiment of the present disclosure, a patterned copper seed layer 1021 may be formed first, and then a pattern defining layer covering the base substrate 101 and exposing the copper seed layer 1021 may be formed, and then a patterned copper growth layer 1022 may be formed on the patterned copper seed layer 1021 by electroplating copper to obtain the first metal wiring layer 102; and the pattern defining layer may be removed. As another example, in another embodiment of the present disclosure, an unpatterned copper seed layer 1021 covering the base substrate 101 may be first formed, and then a pattern defining layer may be formed on a side of the copper seed layer 1021 away from the base substrate 101, wherein the pattern defining layer only exposes a position where a copper growth layer 1022 needs to be formed; then, a patterned copper growth layer 1022 may be formed on the unpatterned copper seed layer 1021 by copper electroplating, and after removing the pattern defining layer, the unpatterned copper seed layer 1021 may be patterned to obtain a first metal wiring layer 102.

[0165] It is understandable that the first metal wiring layer can also be formed by multiple magnetron sputtering methods. Exemplarily, the first metal wiring material layer can be formed by multiple magnetron sputtering, and the thickness of the metal layer formed by each magnetron sputtering is not more than 1 micron; then the first metal wiring material layer is patterned to form the first metal wiring layer. Another exemplary embodiment, a plurality of metal wiring sublayers with the same pattern can be formed in sequence, and each metal wiring sublayer is stacked in sequence to form the first metal wiring layer. When forming any metal wiring sublayer, a metal wiring material sublayer can be first formed by magnetron sputtering, and the thickness of the metal wiring material sublayer is not more than 1 micron; then the metal wiring material sublayer is patterned to form a metal wiring sublayer.

[0166] It can be understood that the above introduction to the structure, materials and preparation method of the first metal wiring layer is only an exemplary introduction to the first metal wiring layer; in other embodiments of the present disclosure, the first metal wiring layer may present other film layer structures, or be made of other materials, or be prepared by other methods.

[0167] Alternatively, see Fig.48 , the insulating material layer 103 may include a planarized organic material layer 1032. The material of the planarized organic material layer 1032 may be an organic material, such as polyimide, epoxy resin, phenolic resin or other organic materials. In one embodiment of the present disclosure, the planarized organic material layer 1032 may be an organic material containing a photosensitizer. The planarized organic material layer 1032 may provide a planarized surface for the second metal wiring layer of the array substrate, and adjust the capacitance value between the first metal wiring layer and the second metal wiring layer.

[0168] Alternatively, see Fig.48 The insulating material layer 103 may further include a first passivation layer 1031, which is located between the planarization organic material layer 1032 and the first metal wiring layer 102 to protect the first metal wiring layer 102. The material of the first passivation layer 1031 may be an inorganic dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment of the present disclosure, the material of the first passivation layer 1031 may be silicon nitride.

[0169] Optionally, the wiring substrate and array substrate of the present disclosure may further include a buffer layer 108, which is located between the base substrate 101 and the first metal wiring layer 102, and is used to eliminate the stress of the first metal wiring layer 102 and the insulating material layer 103 on the base substrate 101. The material of the buffer layer 108 may be an inorganic dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment of the present disclosure, the material of the buffer layer 108 may be silicon nitride.

[0170] See also Fig.49 In the array substrate provided in the present disclosure, the wiring substrate provided in the present disclosure may include a second metal wiring layer 104 and an insulating protection layer 105 sequentially stacked on the surface of the wiring substrate, and a functional device ( Fig.49 Not shown) and microchip ( Fig.49 104). The second metal wiring layer 104 is located on the side of the insulating material layer 103 away from the base substrate 101, and is connected to the first metal wiring layer 102 through the vias located on the insulating material layer 103. It can be understood that, in some embodiments, some of the vias on the insulating material layer 103 are not used to connect the first metal wiring layer 102 and the second metal wiring layer 104, and are filled with the insulating protection layer 105. In other words, in an array substrate, at least some of the vias on the insulating material layer 103 can be filled with the insulating protection layer 105.

[0171] The second metal wiring layer 104 may include a second metal adhesion layer and a second copper metal layer stacked in sequence, and the second metal adhesion layer is used to enhance the bonding force between the second copper metal layer and the planarized organic material layer 1032; the material of the second metal adhesion layer may be an alloy material containing molybdenum, such as a molybdenum-niobium alloy, a molybdenum-niobium-copper alloy, etc. Further, the second metal wiring layer 104 may also include a second metal protective layer located on the side of the second copper metal layer away from the base substrate 101 to prevent the surface of the second copper metal layer from being oxidized, and to improve the bonding force between the functional device and the microchip and the second metal wiring layer 104. The material of the second metal protective layer may be an alloy containing nickel, such as a copper-nickel alloy or a copper-titanium alloy. In terms of pattern and function, the second metal wiring layer 104 may include a plurality of device pad groups for binding functional devices, a plurality of chip pad groups for binding microchips, and a plurality of connecting leads 500. In the array substrate, the functional device is bound and connected to the device pad group, the microchip is bound and connected to the chip pad group, and the device pad group and the chip pad group are connected to the connecting leads 500. At least part of the connecting leads 500 are connected to the first metal wiring layer 102 through at least part of the via holes provided on the insulating material layer 103 .

[0172] Optionally, at least part of these connecting leads 500 may extend along the second direction D, or at least part of them may extend along the second direction D, so as to reduce the overlapping length between part of the connecting leads 500 and part of the driving leads, and reduce the risk of short circuit failure caused by local failure of the insulating material layer 103. Further, for some connecting leads 500, especially for connecting leads 500 overlapping with multiple different driving leads, when the connecting leads 500 are bent, at least part of the lead segments of the connecting leads 500 may extend along the second direction D, and the remaining lead segments may extend along the first direction.

[0173] For example, in some embodiments, see Figure 31 to Figure 33 , the connecting leads electrically connected to the first input lead or the second input lead can extend along the second direction without being bent, so that the extending direction of these connecting leads 500 is perpendicular to the extending direction of the driving leads, thereby reducing the overlapping length between these connecting leads and the reference voltage leads, thereby reducing the risk of short circuit failure. For example, in another embodiment of the present disclosure, see Figure 24 to Figure 26 , the connecting leads connected to the first input lead or the second input lead can extend along the second direction to a position overlapping with the input lead, and then bend and continue to extend along the first direction to overlap with the input via. The lead segments extending along the second direction of these connecting leads 500 have a small overlapping length with the reference voltage lead, so that the short circuit defect of the array substrate can be avoided. The lead segments extending along the first direction of these connecting leads can overlap with the first input lead or the second input lead, so even if a short circuit occurs, it will not cause a change in the potential on these connecting leads, that is, no short circuit defect will be shown.

[0174] The insulating protective layer 105 may include an organic protective layer 1052, and the organic protective layer 1052 may include an organic insulating material, such as a resin material. Optionally, the organic protective layer 1052 may also include an inorganic material, such as inorganic particles dispersed in a resin. Exemplarily, the organic protective layer 1052 may be an organic-inorganic composite layer formed by cross-linking and curing an acrylic monomer in which nano titanium oxide particles are dispersed.

[0175] Optionally, the insulating protection layer 105 may further include a second passivation layer 1051 located between the organic protection layer 1052 and the second metal wiring layer 104. The second passivation layer 1051 is used to protect the second metal wiring layer 104, and its material may be an inorganic dielectric material, such as silicon nitride, silicon oxide, or silicon oxynitride. In one embodiment of the present disclosure, the material of the second passivation layer 1051 may be silicon nitride.

[0176] The insulating protection layer 105 may have via holes exposing each sub-pad of the device pad group and each sub-pad of the chip pad group, so as to bind and connect the functional device and the microchip on the array substrate.

[0177] In the present disclosure, the array substrate may be bound with functional devices and microchips, and the microchips are used to control each functional device. Among them, the functional device may be a current-driven element, such as a heating element, a light-emitting element, a sound-emitting element, etc., or an electronic element that realizes a sensing function, such as a photosensitive element, a thermal element, etc. In some embodiments, the functional device may be a light-emitting element, such as a Micro LED or a Mini LED. In other embodiments, some functional devices may be light-emitting elements, and other functional devices may be sensors, such as temperature sensors, pressure sensors, infrared sensors and other electronic elements.

[0178] See also Fig. 9 , Fig.15 , Fig.21 , Fig. 27 and Fig.33 The wiring substrate provided by the present disclosure has a plurality of control regions 201 distributed in an array, and the plurality of control regions 201 are arranged into a plurality of control region rows 210 and a plurality of control region columns 220. Any control region column 220 includes a plurality of control regions 201 arranged along a first direction C, and any control region row 210 includes a plurality of control regions 201 arranged along a second direction D; the second direction D is parallel to the plane where the wiring substrate is located and intersects with the first direction C.

[0179] Optionally, the included angle between the second direction D and the first direction C may be 85° to 90°. In one embodiment of the present disclosure, the second direction D and the first direction C are perpendicular to each other.

[0180] See also Fig. 9 , Fig.15 , Fig.21 , Fig. 27 and Fig.33 , any one control region 201 includes four device regions A distributed in an array, and the device regions A are used to set mutually electrically connected functional devices 107. In the array substrate of the present disclosure, a device control circuit may be set in a device region A, and the device control circuit includes one functional device or multiple electrically connected functional devices. For example, see Fig.11 In one embodiment of the present disclosure, a control circuit may include four light emitting elements connected in series. Fig.47 The device control circuit may include a connection lead 500 located in the second metal wiring layer 104 and a connection lead 501 connected to the functional device ( Fig.47The device pad group P50 is connected to the connecting lead 500 and is bound and connected to the functional device. Exemplarily, in one embodiment of the present disclosure, a device pad group P50 includes a first device sub-pad P51 and a second device sub-pad P52 arranged in pairs, and the first device sub-pad P51 and the second device sub-pad P52 are respectively used for binding and connecting with the positive and negative electrodes of the light-emitting element.

[0181] In some implementations, the device regions A on the wiring substrate may be arranged in an array, wherein four 2*2 adjacent device regions A may constitute a control region 201 disclosed herein.

[0182] See also Fig.10 , Fig.16 , Fig. 22 , Fig.28 and Fig.34 , in a control region 201, four device regions A can be numbered as a first device region A(1,1), a second device region A(1,2), a third device region A(2,1), and a fourth device region A(2,2). The first device region A(1,1) is a device region A located in the first row in the first direction C and in the first column in the second direction D in the control region 201; the second device region A(1,2) is a device region A located in the first row in the first direction C and in the second column in the second direction D in the control region 201; the third device region A(2,1) is a device region A located in the second row in the first direction C and in the first column in the second direction D in the control region 201; and the fourth device region A(2,2) is a device region A located in the second row in the first direction C and in the second column in the second direction D in the control region 201.

[0183] See also Fig. 9 , Fig.15 , Fig.21 , Fig. 27 and Fig.33 In the wiring substrate and array substrate of the present disclosure, the first metal wiring layer 102 is provided with a driving lead 300 extending along the first direction C. In any control region column 220, the driving lead 300 at least includes a first power supply voltage lead 310, a first input lead 320, a reference voltage lead 330, a second input lead 340, and a second power supply voltage lead 350 arranged in sequence along the second direction D. The wiring substrate also has at least one signal channel extending along the first direction C, and any one signal channel includes at least one control region column 220; in any one signal channel, the driving lead 300 also includes at least one address lead 360. In some embodiments, one signal channel includes one control region column 220.

[0184] The first power supply voltage lead 310 and the second power supply voltage lead 350 can be power supply voltage leads of the wiring substrate and the array substrate; the first input lead 320 and the second input lead 340 can be input leads of the wiring substrate and the array substrate. The insulating material layer 103 can be provided with a power via that exposes a partial area of ​​the power supply voltage lead (the first power supply voltage lead 310 or the second power supply voltage lead 350) so that one end of the device control circuit is connected to the power supply voltage lead through the power via. The insulating material layer 103 can be provided with a reference via that exposes a partial area of ​​the reference voltage lead 330, and the reference voltage lead 330 supplies power to the reference voltage pin of the microchip through the reference via. The insulating material layer 103 can be provided with an input via that exposes a partial area of ​​the input lead (the first input lead 320 or the second input lead 340) so that some pins of the microchip are connected to the input lead through the input via.

[0185] See also Fig. 9 , Fig.15 , Fig.21 , Fig. 27 and Fig.33 , the control region 201 may include a first control region 2011. In the first control region 2011, the insulating material layer 103 is provided with first to sixth power vias, first to fourth input vias, a first reference via HR1 and a second reference via HR2.

[0186] See also Fig.10 , Fig.16 , Fig. 22 and Fig.28 The first power via HV1, the second power via HV2 and the third power via HV3 are sequentially arranged along the first direction C and expose a portion of the first power voltage lead 310; the first power via HV1 is located on the side of the first device area A(1,1) away from the third device area A(2,1) or between the first device area A(1,1) and the third device area A(2,1); the second power via HV2 is located between the first device area A(1,1) and the third device area A(2,1); the third power via HV3 is located on the side of the third device area A(2,1) away from the first device area A(1,1). The fourth power via HV4, the fifth power via HV5 and the sixth power via HV6 are sequentially arranged along the first direction C and expose a portion of the second power voltage lead 350. The fourth power via HV4 is located on a side of the second device area A(1,2) away from the fourth device area A(2,2) or between the second device area A(1,2) and the fourth device area A(2,2); the fifth power via HV5 is located between the second device area A(1,2) and the fourth device area A(2,2); the sixth power via HV6 is located on a side of the fourth device area A(2,2) away from the second device area A(1,2).

[0187] In the wiring substrate, the specific positions of the first power via HV1 and the fourth power via HV4 can be determined in advance according to the setting mode of the device control circuit of the device area A. The device control circuit in the device area A can have a first end and a second end, wherein the second end is used to be electrically connected to the microchip, and the first end is used to be connected to the power supply voltage lead through a connecting lead overlapping the power via. Under the design principle of minimizing the length of the connecting lead in the device control circuit, the first end of the device control circuit can be close to a vertex of the device area, and the vertex is located on the side of the device area away from the reference voltage lead in the second direction. In the first device area A (1, 1) and the second device area A (1, 2), when the vertex is located on the first direction side of the device area in the first direction, the first power via HV1 can be located on the side of the first device area A (1, 1) close to the third device area A (2, 1), and the fourth power via HV4 can be located on the side of the second device area A (1, 2) close to the fourth device area A (2, 2). In the first device area A(1,1) and the second device area A(1,2), when the vertex is located on the side of the device area in the first direction opposite to the first direction, the first power via HV1 can be located on the side of the first device area A(1,1) away from the third device area A(2,1), and the fourth power via HV4 can be located on the side of the second device area A(1,2) away from the fourth device area A(2,2).

[0188] In some embodiments, the device area A is provided with N*N array-distributed and serially connected functional devices 107. When N is an even number not less than 2, the first power via HV1 can be located on the side of the first device area A(1,1) close to the third device area A(2,1), and the fourth power via HV4 can be located on the side of the second device area A(1,2) close to the fourth device area A(2,2). When N is an odd number not less than 2, the first power via HV1 can be located on the side of the first device area A(1,1) away from the third device area A(2,1), and the fourth power via HV4 can be located on the side of the second device area A(1,2) away from the fourth device area A(2,2). In this way, the arrangement of the connecting leads 500 in the first device area A(1,1) and the second device area A(1,2) can be simplified as much as possible. It can be understood that, since the second power via HV2 and the third power via HV3 are located on both sides of the third device area A(2,1), the device control circuit in the third device area A(2,1) can be connected to one of the second power via HV2 and the third power via HV3 according to the wiring requirements of the connecting lead 500. Correspondingly, since the fifth power via HV5 and the sixth power via HV6 are located on both sides of the fourth device area A(2,2), the device control circuit in the fourth device area A(2,2) can be connected to one of the fifth power via HV5 and the sixth power via HV6 according to the wiring requirements of the connecting lead 500.

[0189] In some other embodiments, the wiring substrate of the present disclosure is provided with two first power vias HV1 and two fourth power vias HV4 in the first control area 2011. The two first power vias HV1 are respectively located on both sides of the first device area A(1,1), and the two fourth power vias HV4 are respectively located on both sides of the second device area A(1,2). In this way, the array substrate can select one of the first power vias HV1 to realize the electrical connection between the device control circuit in the first device area A(1,1) and the first power supply voltage lead 310, and select one of the fourth power vias HV4 to realize the electrical connection between the device control circuit in the second device area A(1,2) and the fifth power supply voltage lead 350 according to the wiring requirements of the second metal wiring layer.

[0190] The first input via HI1 and the second input via HI2 expose a portion of the first input lead 320; the first input via HI1 is located between the edge of the first device area A(1,1) away from the third device area A(2,1) and the edge of the third device area A(2,1) close to the first device area A(1,1); the second input via HI2 is located on the side of the third device area A(2,1) away from the first device area A(1,1). The third input via HI3 and the fourth input via HI4 expose a portion of the second input lead 340. The third input via HI3 is located between the edge of the second device area A(1,2) away from the fourth device area A(2,2) and the edge of the fourth device area A(2,2) close to the second device area A(1,2); the fourth input via HI4 is located on the side of the fourth device area A(2,2) away from the second device area A(1,2).

[0191] Both the first reference via HR1 and the second reference via HR2 expose a portion of the reference voltage lead 330; along the first direction C, the first reference via HR1 is located between the first device area A(1,1) and the third device area A(2,1), and the second reference via HR2 is located on the side of the third device area A(2,1) away from the first device area A(1,1).

[0192] In any signal channel region, the insulating material layer 103 is further provided with at least one address via hole exposing a portion of the address lead 360 .

[0193] Alternatively, see Fig.50 The wiring substrate may also have a fan-out region and a binding region B, wherein the first metal wiring layer 102 is provided with fan-out leads 400 connected one-to-one with each driving lead 300 in the fan-out region, and the binding region B is provided with binding pads connected one-to-one with each fan-out lead 400. Fig.50In one embodiment of the present disclosure, the fan-out lead 400 and the binding pad are located on one side of the first direction C of the corresponding driving lead 300; that is, along the first direction C, the binding area B is located at the end of the wiring substrate. In another embodiment of the present disclosure, the driving lead is located on one side of the first direction C of the corresponding fan-out lead and the binding pad; that is, along the first direction C, the binding area B is located at the starting end of the wiring substrate.

[0194] In some embodiments, the binding area B may be arranged near an edge of the wiring substrate, for example, an edge of the wiring substrate in the first direction C or an edge in the opposite direction of the first direction C. The wiring substrate and the array substrate of the present disclosure may be provided with at least one row of binding pads in the binding area B. Further, in the same row of binding pads, each binding pad may be arranged along the second direction D. In one embodiment of the present disclosure, each binding pad is arranged in a row along the second direction D, and is arranged one-to-one with each driving lead 300.

[0195] Optionally, the two binding pads corresponding to the two adjacent power supply voltage leads in the two adjacent signal channels are interconnected as a whole. Furthermore, the two fan-out leads 400 connected to the two adjacent power supply voltage leads can also be connected to each other as a whole. In this way, it is equivalent to that the two adjacent power supply voltage leads are connected to the same binding pad through the same fan-out lead 400. Optionally, the binding area is provided with a plurality of binding electrodes arranged at equal intervals along the second direction D, and the width of each binding electrode is the same. One or more adjacent binding electrodes can be connected to the same fan-out lead, and as a whole serve as a binding pad connected to the binding lead. The more binding electrodes a binding pad includes, the larger the width of the binding pad.

[0196] The wiring substrate provided by the present disclosure can be applied to at least two different microchips to prepare different array substrates with different microchips. These array substrates include the wiring substrate provided by the present disclosure, and the second metal wiring layer 104 and the insulating protection layer 105 stacked on the side of the insulating material layer 103 of the wiring substrate away from the base substrate 101, and are also bound with microchips and functional devices.

[0197] Optionally, in the array substrate of the wiring substrate according to the present disclosure, in the first control area 2011, one of the second power via HV2 and the third power via HV3 is used to overlap with the connection lead 500 so that the device control circuit in the third device area A (2, 1) is connected to the first power voltage lead 310; the other may not overlap with any second metal wiring layer 104 and is filled with the insulating protection layer 105. One of the fifth power via HV5 and the sixth power via HV6 is used to overlap with the connection lead 500 so that the device control circuit in the fourth device area A (2, 2) is connected to the second power voltage lead 350; the other may not overlap with any second metal wiring layer 104 and is filled with the insulating protection layer 105.

[0198] The wiring substrate provided by the present disclosure can be used to prepare an array substrate having a first chip, for example, can be used to prepare a first array substrate. The base substrate 101, the first metal wiring layer 102 and the insulating material layer 103 of the first array substrate form the wiring substrate in this embodiment. Fig.11 A schematic diagram of the structure of a first array substrate in a first control area 2011 is shown; wherein, Fig.11 Only the driving leads 300, the positions of at least part of the vias provided in the insulating material layer 103, the connecting leads 500 (indicated by thick lines), the first pad group P10 for binding the first chip, the functional devices 107 in each device area A, etc. are shown.

[0199] See also Fig.11 In a first control area 2011, the first array substrate may be provided with four first pad groups P10 corresponding to four device areas A one by one; any first pad group P10 is located on the first direction C side of the corresponding device area A. The first pad group P10 corresponding to the second device area A(1,2) is located on the second direction D side of the first pad group P10 corresponding to the first device area A(1,1); the first pad group P10 corresponding to the fourth device area A(2,2) is located on the second direction D side of the first pad group P10 corresponding to the third device area A(2,1).

[0200] In the first control area 2011 of the first array substrate, the reference voltage sub-pad P11 of the first pad group P10 corresponding to the first device area A(1,1) and the reference voltage sub-pad P11 of the first pad group P10 corresponding to the second device area A(1,2) are connected to the reference voltage lead 330 through a connecting lead 500 overlapping the first reference via HR1.

[0201] The reference voltage sub-pad P11 of the first pad group P10 corresponding to the third device area A(2,1) and the reference voltage sub-pad P11 of the first pad group P10 corresponding to the fourth device area A(2,2) are connected to the reference voltage lead 330 through the connection lead 500 overlapping the second reference via HR2. This allows the reference voltage sub-pad P11 of each first pad group P10 to be electrically connected to the reference voltage lead 330. Further, in the first control area 2011 of the first array substrate, the connection lead 500 overlapping the first reference via HR1 and the connection lead 500 overlapping the second reference via HR2, their orthographic projections on the first metal wiring layer 102 do not exceed the range of the reference voltage lead 330. In this way, even if the layout failure of the insulating material layer 103 causes a short circuit between these connection leads 500 and the reference voltage lead 330, the voltage on these leads will not be changed to cause defects.

[0202] In a signal channel of the first array substrate, each device area A can be numbered in sequence, wherein the first pad group P10 corresponding to the device area A numbered 1 can be located at one end of the signal channel in its extension direction, for example, it can be located at one end close to the binding area B or at one end away from the binding area B. In the signal channel, the first pad group P10 corresponding to each device area A can be numbered in sequence row by row and column by column in a Z shape, or in sequence row by row and column in an S shape, or in sequence row by row and column in an N shape, or in sequence row by row and column in a U shape or an inverted U shape. In the present disclosure, the row direction is the direction along the second direction D or the opposite direction thereof, and the column direction is the direction along the first direction C or the opposite direction thereof. In a signal channel, the first pad group P10 corresponding to each device area A can be cascaded in sequence in the order of numbering, wherein the second input sub-pad P14 of the first pad group P10 corresponding to the device area A numbered 1 is connected to one of the address leads 360 through a connecting lead 50 overlapping the address via. The output sub-pad P12 of the first pad group P10 corresponding to the device area A numbered (n-1) is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the device area A numbered n through the connecting wire 500. n is an integer greater than 1 and not greater than the number of device areas in a signal channel.

[0203] For example, in one embodiment of the first array substrate, the first pad group P10 corresponding to the first device area A(1,1), the first pad group P10 corresponding to the second device area A(1,2), the first pad group P10 corresponding to the third device area A(2,1) and the first pad group P10 corresponding to the fourth device area A(2,2) are sequentially cascaded. Among them, the output sub-pad P12 of the first pad group P10 corresponding to the first device area A(1,1) is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the second device area A(1,2), the output sub-pad P12 of the first pad group P10 corresponding to the second device area A(1,2) is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the third device area A(2,1), and the output sub-pad P12 of the first pad group P10 corresponding to the third device area A(2,1) is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the fourth device area A(2,2). In two adjacent control areas 201, the output sub-pad P12 of the first pad group P10 corresponding to the fourth device area A(2,2) of the control area 201 located on the opposite side of the first direction C is connected to the second input sub-pad P14 of the first pad group P10 corresponding to the first device area A(1,1) of the control area 201 located on the side of the first direction C.

[0204] See also Fig.11 The first array substrate is provided with a device control circuit in the device area A, wherein the first end of the device control circuit is connected to the power voltage lead through a connection lead 500 overlapping the power via; the second end of the device control circuit is connected to the output sub-pad P12 of the first pad group P10 corresponding to the device area A through a connection lead 500. Fig.47 , the first end of the device control circuit may be a first device sub-pad P51 in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be a second device sub-pad P52 in a device pad group P50 close to the corresponding first chip 010 in the first direction C and close to the axis of the reference voltage lead 330 in the second direction D. In this way, the length of the connecting lead 500 connecting the output pin 012 of the first chip 010 and the second end of the device control circuit can be minimized, and the overlapping length between these connecting leads 500 and the reference voltage lead 330 can be reduced, thereby reducing the risk of short circuit between these connecting leads 500 and the reference voltage lead 330.

[0205] For example, in one embodiment of the present disclosure, four light-emitting elements connected in series and distributed in a 2*2 array are arranged in a device area A; wherein the first light-emitting element is connected to the power supply voltage lead through a connecting lead 500 overlapping the power supply via, and the fourth light-emitting element is connected to the output sub-pad P12 of the first pad group P10 through a connecting lead 500. The three connecting leads 500 of the four light-emitting elements in series are generally arranged in a U-shaped shape with the opening facing the first direction C. In this embodiment, in the first control area 2011, the first power supply via HV1 can be arranged on the first direction C side of the first device area A(1,1), and the fourth power supply via HV4 can be arranged on the first direction C side of the second device area A(1,2). The first end of the device control circuit in the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the first power supply via HV1. The first end of the device control circuit in the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4. The first end of the device control circuit in the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connection lead 500 overlapping the third power via HV3. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the sixth power via HV6.

[0206] In the first control region 2011, the first input sub-pad P13 of the first pad group P10 corresponding to the first device area A(1,1) is connected to the first input lead 320 through a connecting lead 500 overlapping the first input via HI1; the first input sub-pad P13 of the first pad group P10 corresponding to the third device area A(2,1) is connected to the first input lead 320 through a connecting lead 500 overlapping the second input via HI2; the first input sub-pad P13 of the first pad group P10 corresponding to the second device area A(1,2) is connected to the second input lead 340 through a connecting lead 500 overlapping the third input via HI3; the first input sub-pad P13 of the first pad group P10 corresponding to the fourth device area A(2,2) is connected to the second input lead 340 through a connecting lead 500 overlapping the fourth input via HI4.

[0207] In the first array substrate, the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driving device control circuit. The reference voltage lead 330 can be used to load the reference voltage GND. One of the first input lead 320 and the second input lead 340 can be used to load the first input signal Pwr. In a signal channel, at least one address lead 360 can be used to load the second input signal Di. In this way, under the control of each driving lead 300, each first chip 010 and the functional device 107 can work normally.

[0208] In some embodiments of the present disclosure, see Fig.39 , among the adjacent input leads (e.g., the first input lead 320 and the second input lead 340) and the reference voltage lead 330 of the wiring substrate, the input lead is provided with a protrusion 301 protruding toward one side of the reference voltage lead 330, and the reference voltage lead 330 is provided with an accommodating notch 302 corresponding to the protrusion 301 of the reference voltage lead 330 and capable of accommodating the protrusion 301. Correspondingly, in the first array substrate, the first pad group P10 can be arranged close to the protrusion 301, so that the orthographic projection of the first input sub-pad P13 of the first pad group P10 on the first metal wiring layer 102 is located on the protrusion 301 of the input lead, and the orthographic projection of the reference voltage sub-pad P11 of the first pad group P10 on the first metal wiring layer 102 is located on the reference voltage lead 330. In other words, see Fig.39 , at least part of the protrusion 301 of the input lead can be used as the first supporting metal part 303, and the first supporting metal part 303 can completely overlap with the input sub-pad of the first pad group P10; at least part of the reference voltage lead 330 near the accommodating notch 302 can be used as the second supporting metal part 304, and the second supporting metal part 304 can completely overlap with the reference voltage sub-pad P11 of the first pad group P10. The connecting lead 500 connected to the reference voltage sub-pad P11 and overlapping with the reference via can completely overlap the reference voltage lead 330. In this way, the risk of short circuit caused by insulation failure of the insulating material layer 103 is further reduced.

[0209] Further, see Fig.39In the wiring substrate, the first metal wiring layer 102 may also be provided with a third supporting metal portion 305 and a fourth supporting metal portion 306, both of which are located between the input lead and the reference voltage lead 330, and are insulated from the input lead and the reference voltage lead 330. The orthographic projection of the third supporting metal portion 305 on the base substrate 101 coincides with the orthographic projection of the output sub-pad P12 on the base substrate 101; the orthographic projection of the second supporting metal portion 304 on the base substrate 101 coincides with the orthographic projection of the second input sub-pad P14 on the base substrate 101. In this way, the distances between each sub-pad of the first pad group P10 and the base substrate 101 can be made substantially the same, which is beneficial to the binding of the first chip 010.

[0210] The wiring substrate provided by the present disclosure can also be used to prepare an array substrate having a second chip 020, for example, can be used to prepare a second array substrate. The base substrate 101, the first metal wiring layer 102 and the insulating material layer 103 of the second array substrate form the wiring substrate in this embodiment. Fig.12 A schematic diagram of the structure of a second array substrate in a first control area 2011 is shown; wherein, Fig.12 Only the driving leads 300, the positions of the various vias provided in the insulating material layer 103, the connecting leads 500 (indicated by thick lines), the second pad group P20 for binding the second chip 020, the functional devices 107 in each device area A, etc. are shown.

[0211] See also Fig.12, the second array substrate may be provided with a second pad group P20 for binding the second chip 020 in a first control area 2011, and the second pad group P20 may be located between the four device areas A in the first control area 2011. In other words, in a first control area 2011, along the first direction C, the second pad group P20 is located between the first device area A(1,1) and the third device area A(2,1); along the second direction D, the second pad group P20 is located between the first device area A(1,1) and the second device area A(1,2). Among them, the reference voltage sub-pad P21 of the second pad group P20 is located on the first direction C side of the address sub-pad P25 of the second pad group P20, so as to ensure that the connection lead 500 connected to the reference voltage sub-pad P21 of the second pad group P20 can extend to overlap with the second reference via HR2, and the connection lead 500 completely overlaps with the reference voltage lead 330. In this way, when the connecting lead 500 is short-circuited with the reference voltage lead 330, the second array substrate can avoid being defective. Among them, one of the chip power sub-pad P23 and the drive data sub-pad P24 is connected to the first input lead 320 through the connecting lead 500 overlapping the first input via HI1; the other is connected to the second input lead 340 through the connecting lead 500 overlapping the third input via HI3. The four input sub-pads are respectively connected to the second ends of the device control circuits in the four device areas through the connecting leads 500.

[0212] Alternatively, see Fig.12 In the second array substrate, the chip power sub-pad P23 of the second pad group P20 is located on the opposite side of the second direction D of the drive data sub-pad P24. In this way, the chip power sub-pad P23 of the second pad group P20 and the first input lead 320 can be connected through the connection lead 500 overlapping the first input via HI1; the drive data sub-pad P24 of the second pad group P20 and the second input lead 340 can be connected through the connection lead 500 overlapping the third input via HI3. The address sub-pad P25 of the second pad group P20 and the address lead 360 can be connected through the connection lead 500 overlapping the address via.

[0213] See also Fig.12In the first control region 2011 of the second array substrate, the first end of the device control circuit in the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connection lead 500 overlapping the first power via HV1; the second end of the device control circuit in the first device area A(1,1) is connected to the first output sub-pad P221 of the second pad group P20 through a connection lead 500. The first end of the device control circuit in the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4; the second end of the device control circuit in the second device area A(1,2) is connected to the second output sub-pad P222 of the second pad group P20 through a connection lead 500. The first end of the device control circuit in the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connection lead 500 overlapping the second power via HV2 or the third power via HV3; the second end of the device control circuit in the third device area A(2,1) is connected to the third output sub-pad P223 of the second pad group P20 through a connection lead 500. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power supply voltage lead 320 through a connection lead 500 overlapping the fifth power via HV5 or the sixth power via HV6; the second end of the device control circuit in the fourth device area A(2,2) is connected to the fourth output sub-pad P224 of the second pad group P20 through a connection lead 500. The first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be a sub-pad in a device pad group P50 close to the second chip 020 in the first direction C and close to the axis of the reference voltage lead 330 in the second direction D. This can minimize the length of the connecting lead 500 between the output pin 012 of the second chip 020 and the second end of the device control circuit, reduce the overlapping length between these connecting leads 500 and the reference voltage lead 330, and further reduce the risk of short circuit between these connecting leads 500 and the reference voltage lead 330.

[0214] Optionally, in at least part of the control area, the device control circuit in the first device area A(1,1) has connecting leads connecting various functional devices, and the device control circuit in the third device area A(2,1) has connecting leads connecting various functional devices, and these connecting leads in the first device area A(1,1) and these connecting leads in the third device area A(2,1) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction. The device control circuit in the second device area A(1,2) has connecting leads connecting various functional devices, and the device control circuit in the fourth device area A(2,2) has connecting leads connecting various functional devices, and these connecting leads in the second device area A(1,2) and these connecting leads in the fourth device area A(2,2) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction.

[0215] For example, in one embodiment of the present disclosure, four light-emitting elements connected in series and distributed in a 2*2 array are arranged in a device area A; wherein the first light-emitting element is connected to the power supply voltage lead through a connecting lead 500 overlapping the power supply via; and the fourth light-emitting element is connected to the output sub-pad P12 of the second pad group P20 through the connecting lead 500. In the first device area A(1,1) and the second device area A(1,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the first direction C. In the third device area A(2,1) and the fourth device area A(2,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the opposite direction of the first direction C. In this embodiment, in the first control region 2011, the first power via HV1 can be arranged on the first direction C side of the first device area A(1,1), and the fourth power via HV4 can be arranged on the first direction C side of the second device area A(1,2). The first end of the device control circuit in the first device area A(1,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the first power via HV1. The first end of the device control circuit in the third device area A(2,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the second power via HV2. The first end of the device control circuit in the second device area A(1,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fifth power via HV5.

[0216] In the second array substrate, the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driving device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driving device control circuit. The reference voltage lead 330 can be used to load the reference voltage GND. The first input lead 320 can be used to load the chip operating voltage VCC, and the second input lead 340 can be used to load the driving data Data. At least part of the address lead 360 can be used to load the selection signal. In this way, under the control of each driving lead 300, each second chip 020 and the functional device 107 can work normally.

[0217] Optionally, in the first control region 2011 of the second array substrate, the first reference via HR1 , the second input via HI2 , and the fourth input via HI4 may not overlap with any second metal wiring layer 104 , and may be filled with the insulating protection layer 105 .

[0218] The wiring substrate provided by the present disclosure can be used to prepare an array substrate having a third chip 030, for example, can be used to prepare a third array substrate. The base substrate 101, the first metal wiring layer 102 and the insulating material layer 103 of the third array substrate form the wiring substrate in this embodiment. Exemplarily, Fig.13 A schematic diagram of the structure of a third array substrate in a first control area 2011 is shown; wherein, Fig.13 Only the driving leads 300, the positions of the various vias provided in the insulating material layer 103, the connecting leads 500 (indicated by thick lines), the third pad group P30 for binding the third chip 030, the functional devices 107 in each device area A, etc. are shown.

[0219] See also Fig.13, the third array substrate may be provided with a third pad group P30 for binding the third chip 030 in a first control area 2011, and the third pad group P30 may be located between the four device areas A in the first control area 2011. In other words, in a first control area 2011, along the first direction C, the third pad group P30 is located between the first device area A(1,1) and the third device area A(2,1); along the second direction D, the third pad group P30 is located between the first device area A(1,1) and the second device area A(1,2). Optionally, the reference voltage sub-pad P31 of the third pad group P30 is located on the first direction C side of the relay signal sub-pad P36 of the third pad group P30, which is more conducive to the connection lead 500 connected to the reference voltage sub-pad P31 of the third pad group P30 extending to overlap with the second reference via HR2, and the connection lead 500 completely overlaps with the reference voltage lead 330. In this way, when the connection lead 500 and the reference voltage lead 330 are short-circuited, the third array substrate can avoid being defective.

[0220] In a first control area 2011 of the third array substrate, the reference voltage sub-pad P31 can be connected to the reference voltage lead 330 through a connecting lead 500 overlapping with the second reference via HR2; one of the chip power sub-pad P33 and the drive data sub-pad P34 is connected to the first input lead 320 through a connecting lead 500 overlapping with the first input via HI1, and the other is connected to the second input lead 340 through a connecting lead 500 overlapping with the third input via HI3.

[0221] For example, see Fig.13 In the third array substrate, the chip power sub-pad P33 of the third pad group P30 is located on the opposite side of the second direction D of the drive data sub-pad P34. In this way, the chip power sub-pad P33 of the third pad group P30 is connected to the first input lead 320 through the connection lead 500 overlapping the first input via HI1. The drive data sub-pad P34 of the third pad group P30 is connected to the second input lead 340 through the connection lead 500 overlapping the third input via HI3.

[0222] See also Fig.13In the first control area 2011 of the third array substrate, the first end of the device control circuit in the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connection lead 500 overlapping the first power via HV1; the second end of the device control circuit in the first device area A(1,1) is connected to the first output sub-pad P321 of the third pad group P30 through a connection lead 500. The first end of the device control circuit in the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4; the second end of the device control circuit in the second device area A(1,2) is connected to the second output sub-pad P322 of the third pad group P30 through a connection lead 500. The first end of the device control circuit in the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connection lead 500 overlapping one of the second power via HV2 and the third power via HV3; the second end of the device control circuit in the third device area A(2,1) is connected to the third output sub-pad P323 of the third pad group P30 through a connection lead 500. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping one of the fifth power via HV5 and the sixth power via HV6; the second end of the device control circuit in the fourth device area A(2,2) is connected to the fourth output sub-pad P324 of the third pad group P30 through a connection lead 500. The first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be a sub-pad in a device pad group P50 close to the third chip 030 in the first direction C and close to the axis of the reference voltage lead 330 in the second direction D. This can minimize the length of the connecting lead 500 between the output pin of the third chip 030 and the second end of the device control circuit, reduce the overlapping length between these connecting leads 500 and the reference voltage lead 330, and further reduce the risk of short circuit between these connecting leads 500 and the reference voltage lead 330.

[0223] Optionally, in at least part of the control area, the device control circuit in the first device area A(1,1) has connecting leads connecting various functional devices, and the device control circuit in the third device area A(2,1) has connecting leads connecting various functional devices, and these connecting leads in the first device area A(1,1) and these connecting leads in the third device area A(2,1) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction. The device control circuit in the second device area A(1,2) has connecting leads connecting various functional devices, and the device control circuit in the fourth device area A(2,2) has connecting leads connecting various functional devices, and these connecting leads in the second device area A(1,2) and these connecting leads in the fourth device area A(2,2) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction.

[0224] For example, see Fig.13 In one embodiment of the present disclosure, four light-emitting elements connected in series and distributed in a 2*2 array are arranged in a device area A; wherein the first light-emitting element is connected to the power supply voltage lead through a connecting lead 500 overlapping the power supply via; and the fourth light-emitting element is connected to the output sub-pad of the third pad group P30 through the connecting lead 500. In the first device area A(1,1) and the second device area A(1,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the first direction C. In the third device area A(2,1) and the fourth device area A(2,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the opposite direction of the first direction C. In this embodiment, in the first control region 2011, the first power via HV1 can be arranged on the first direction C side of the first device area A(1,1), and the fourth power via HV4 can be arranged on the first direction C side of the second device area A(1,2). The first end of the device control circuit in the first device area A(1,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the first power via HV1. The first end of the device control circuit in the third device area A(2,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the first power via HV2. The first end of the device control circuit in the second device area A(1,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fifth power via HV5.

[0225] In a signal channel of the third array substrate, each control region 201 may be numbered in sequence, wherein the control region 201 numbered 1 may be located at one end of the signal channel in its extension direction, for example, at one end close to the binding region B or at one end far from the binding region B. When there is only one control region column 220 in a signal channel, each control region 201 may be numbered in sequence along the first direction C or in the opposite direction of the first direction C. When there are multiple control region columns 220 in a signal channel, in the signal channel, each control region 201 may be numbered in sequence row by row and column by column in a Z-shape, or in sequence row by row and column in an S-shape, or in sequence row by row and column in an N-shape, or in sequence row by row and column in a U-shape or an inverted U-shape. In one signal channel, the third pad groups P30 in each control region 201 can be cascaded in sequence according to the numbering order of the control regions 201, wherein the strobe signal sub-pad P35 of the third pad group P30 in the control region 201 numbered 1 is connected to the address lead 360 through a connecting lead 500 overlapping the address via. The relay signal sub-pad P36 of the third pad group P30 in the control region 201 numbered (n-1) is connected to the strobe signal sub-pad P35 of the third pad group P30 in the control region 201 numbered n through a connecting lead 500. In this way, the third array substrate can realize the mutual cascading of each third chip 030 in one signal channel, thereby realizing the control of each device control circuit in the signal channel. n is a positive integer greater than 1 and not greater than the number of control regions in one signal channel.

[0226] In the third array substrate, the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driver device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driver device control circuit. The reference voltage lead 330 can be used to load the reference voltage GND. The first input lead 320 can be used to load the chip operating voltage VCC, and the second input lead 340 can be used to load the drive data Data. In a signal channel, the address lead 360 connected to the third pad group P30 of the first-level control area 201 can load the selection signal. In this way, under the control of each driving lead 300, each third chip 030 and the functional device 107 can work normally.

[0227] Optionally, in the first control region 2011 of the third array substrate, the first reference via HR1 , the second input via HI2 , and the fourth input via HI4 may not overlap with any second metal wiring layer 104 , and may be filled with the insulating protection layer 105 .

[0228] The wiring substrate provided by the present disclosure can also be used to prepare an array substrate having a fourth chip 040, for example, can be used to prepare a fourth array substrate. The base substrate 101, the first metal wiring layer 102 and the insulating material layer 103 of the fourth array substrate form the wiring substrate in this embodiment. Exemplarily, Fig.14 A schematic diagram of the structure of a fourth array substrate in a first control area 2011 is shown; wherein, Fig.14 Only the driving leads 300, the positions of the vias provided in the insulating material layer 103, the connecting leads 500 (indicated by thick lines), the fourth pad group P40 for binding the fourth chip 040, the functional devices 107 in each device area A, etc. are shown.

[0229] See also Fig.14 , the fourth array substrate may be provided with a fourth pad group P40 for binding the fourth chip 040 in a first control area 2011, and the fourth pad group P40 may be located between the four device areas A in the first control area 2011. In other words, in a first control area 2011, along the first direction C, the fourth pad group P40 is located between the first device area A (1, 1) and the third device area A (2, 1); along the second direction D, the fourth pad group P40 is located between the first device area A (1, 1) and the second device area A (1, 2). Among them, the chip power sub-pad P43 and the drive data sub-pad P44 of the fourth pad group P40 are arranged along the second direction D or the opposite direction thereof, so that the fourth pad group P40 has two columns of sub-pads, and each column of sub-pads has five sub-pads arranged along the first direction C. This can simplify the design of the connecting lead 500 of the fourth array substrate, reduce the length of the connecting lead 500 and thus reduce the probability of a short circuit between the connecting lead 500 and the driving lead 300 of the first metal wiring layer 102. Fig.14 , in the second direction D or the opposite direction thereof, the reference voltage sub-pad P41 of the fourth pad group P40 is located at a side close to the first reference via HR1 compared to the strobe signal sub-pad P45 of the fourth pad group P40. In this way, it can be ensured that the connection lead 500 connected to the reference voltage sub-pad P41 of the fourth pad group P40 can extend to overlap with the first reference via HR1 or the second reference via HR2.

[0230] For example, see Fig.14, compared with the second power supply voltage lead 350, the first reference via HR1 is close to the first power supply voltage lead 310. In this way, the fourth pad group P40 includes two columns of sub-pads, and the five sub-pads close to the first power supply voltage lead 310 are sequentially along the first direction C as the fourth output sub-pad P424, the reference voltage sub-pad P41, the drive data sub-pad P44, the reference voltage sub-pad P41 and the second output sub-pad P422, and the five sub-pads close to the second power supply voltage lead 350 are sequentially along the first direction C as the third output sub-pad P423, the strobe signal sub-pad P45, the chip power sub-pad P43, the relay signal sub-pad P46 and the first output sub-pad P421.

[0231] Alternatively, see Fig.14 In the first control region 2011 of the fourth array substrate, the reference voltage sub-pad P41 of the fourth pad group P40 close to the first reference via HR1 is connected to the reference voltage lead 330 via a connection lead 500 overlapping the first reference via HR1; the connection lead 500 may completely overlap the reference voltage lead 330. In the first control region 2011 of the fourth array substrate, the reference voltage sub-pad P41 of the fourth pad group P40 far from the first reference via HR1 is connected to the reference voltage lead 330 via a connection lead 500 overlapping the second reference via HR2.

[0232] In one embodiment of the present disclosure, of the two reference voltage sub-pads P41, only one reference voltage sub-pad may be electrically connected to the reference voltage lead 330, and the other reference voltage sub-pad P41 may not be electrically connected to the reference voltage lead 330. In this way, the fourth chip 040 can obtain the reference voltage through one reference voltage sub-pad P41, which can meet the working requirements of the fourth chip 040. In this embodiment, of the two reference voltage sub-pads P41, the reference voltage sub-pad P41 close to the first reference via HR1 can be electrically connected to the reference voltage lead 330.

[0233] Alternatively, see Fig.14 In the first control region 2011 of the fourth array substrate, the chip power sub-pad P43 and the drive data sub-pad P44 of the fourth pad group P40 are connected to the first input lead 320 through the connection lead 500 overlapping the first input via HI1; the sub-pad far from the first input lead 320 is connected to the second input lead 340 through the connection lead 500 overlapping the third input via HI3. In this way, the length of these connection leads 500 can be minimized, and the risk of short circuit between these connection leads 500 and the reference voltage lead 330 is reduced.

[0234] For example, in one embodiment of the present disclosure, see Fig.14 In the first control area 2011 of the fourth array substrate, the driving data sub-pad P44 is connected to the first input lead 320 through a connecting lead 500 overlapping the first input via HI1; the chip power sub-pad P43 is connected to the second input lead 340 through a connecting lead 500 overlapping the fourth input via HI4.

[0235] In the first control area 2011 of the fourth array substrate, the first ends of the device control circuits of the four device areas A are connected to the power supply voltage lead through the connection lead 500 overlapping the power supply via. The second ends of the device control circuits of the four device areas A are connected to the four output sub-pads of the fourth pad group P40 through the connection lead 500 in a one-to-one correspondence. Among them, the second end of the device control circuit is connected to the output sub-pad closest to it.

[0236] In one embodiment of the present disclosure, see Fig.14In the first control region 2011 of the fourth array substrate, the first end of the device control circuit in the first device area A(1,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the first power via HV1; the second end of the device control circuit in the first device area A(1,1) is connected to the fourth output sub-pad P424 of the fourth pad group P40 through the connection lead 500. The first end of the device control circuit in the third device area A(2,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping one of the second power via HV2 and the third power via HV3; the second end of the device control circuit in the third device area A(2,1) is connected to the second output sub-pad P422 of the fourth pad group P40 through the connection lead 500. The first end of the device control circuit in the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4; the second end of the device control circuit in the second device area A(1,2) is connected to the third output sub-pad P423 of the fourth pad group P40 through a connection lead 500. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping one of the fifth power via HV5 and the sixth power via HV6; the second end of the device control circuit in the fourth device area A(2,2) is connected to the first output sub-pad P421 of the fourth pad group P40 through a connection lead 500. The first end of the device control circuit may be a sub-pad in a device pad group P50 located on the power supply voltage lead, and the second end of the device control circuit may be a sub-pad in a device pad group P50 close to the fourth pad group P40 in the first direction C and close to the axis of the reference voltage lead 330 in the second direction D. This can minimize the length of the connecting lead 500 connecting the output pin of the fourth chip 040 and the second end of the device control circuit, reduce the overlapping length between these connecting leads 500 and the reference voltage lead 330, and further reduce the risk of short circuit between these connecting leads 500 and the reference voltage lead 330.

[0237] Optionally, in at least part of the control area, the device control circuit in the first device area A(1,1) has connecting leads connecting various functional devices, and the device control circuit in the third device area A(2,1) has connecting leads connecting various functional devices, and these connecting leads in the first device area A(1,1) and these connecting leads in the third device area A(2,1) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction. The device control circuit in the second device area A(1,2) has connecting leads connecting various functional devices, and the device control circuit in the fourth device area A(2,2) has connecting leads connecting various functional devices, and these connecting leads in the second device area A(1,2) and these connecting leads in the fourth device area A(2,2) are symmetrical about a symmetry axis, and the symmetry axis is parallel to the second direction.

[0238] For example, in one embodiment of the present disclosure, four light-emitting elements connected in series and distributed in a 2*2 array are arranged in a device area A; wherein the first light-emitting element is connected to the power supply voltage lead through a connecting lead 500 overlapping the power supply via; and the fourth light-emitting element is connected to the output sub-pad of the fourth pad group P40 through the connecting lead 500. In the first device area A(1,1) and the second device area A(1,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the first direction C. In the third device area A(2,1) and the fourth device area A(2,2), the three connecting leads 500 of the four light-emitting elements connected in series are generally distributed in a U-shaped shape with the opening facing the opposite direction of the first direction C. In this embodiment, in the first control region 2011, the first power via HV1 can be arranged on the first direction C side of the first device area A(1,1), and the fourth power via HV4 can be arranged on the first direction C side of the second device area A(1,2). The first end of the device control circuit in the first device area A(1,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the first power via HV1. The first end of the device control circuit in the third device area A(2,1) is connected to the first power voltage lead 310 through a connection lead 500 overlapping the second power via HV2. The first end of the device control circuit in the second device area A(1,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fourth power via HV4. The first end of the device control circuit in the fourth device area A(2,2) is connected to the second power voltage lead 350 through a connection lead 500 overlapping the fifth power via HV5.

[0239] In a signal channel of the fourth array substrate, each control region 201 may be numbered in sequence, wherein the control region 201 numbered 1 may be located at one end of the signal channel in its extension direction, for example, may be located at one end close to the binding region B or at one end far from the binding region B. When there is only one control region column 220 in a signal channel, each control region 201 may be numbered in sequence along the first direction C or in the opposite direction of the first direction C. When there are multiple control region columns 220 in a signal channel, in the signal channel, each control region 201 may be numbered in sequence row by row and column by column in a Z-shape, or in sequence row by row and column in an S-shape, or in sequence row by row and column in an N-shape, or in sequence row by row and column in a U-shape or an inverted U-shape. In one signal channel, the fourth pad groups P40 in each control region 201 can be cascaded in sequence according to the numbering sequence of the control regions 201, wherein the strobe signal sub-pad P45 of the fourth pad group P40 in the first-level control region 201 is connected to the address lead 360 through a connecting lead 500 overlapping the address via; the relay signal sub-pad P46 of the fourth pad group P40 in the (n-1)-th level control region 201 is connected to the strobe signal sub-pad P45 of the fourth pad group P40 in the n-th level control region 201 through a connecting lead 500. In this way, the fourth array substrate can realize the mutual cascading of each fourth chip 040 in one signal channel, thereby realizing the control of each device control circuit in the signal channel.

[0240] In the fourth array substrate, the first power supply voltage lead 310 and the second power supply voltage lead 350 can be used to load the power supply voltage VLED of the driver device control circuit, for example, to load the power supply voltage VLED of each light-emitting element in the driver device control circuit. The reference voltage lead 330 can be used to load the reference voltage GND. Of the first input lead 320 and the second input lead 340, one connected to the chip power sub-pad P43 can be used to load the chip operating voltage VCC, and the other can be used to load the drive data Data. In a signal channel, the address lead 360 electrically connected to the fourth pad group P40 of the first-level control area 201 can load the selection signal. In this way, under the control of each drive lead 300, each fourth chip 040 and the functional device 107 can work normally.

[0241] Optionally, in the first control region 2011 of the fourth array substrate, the second input via HI2 and the fourth input via HI4 may not overlap with any second metal wiring layer 104 , and may be filled with the insulating protection layer 105 .

[0242] Alternatively, see Fig.10 , Fig.16 , Fig. 22 and Fig.28 In the wiring substrate provided by the present disclosure, in a control area column 220, the first power via HV1 and the fourth power via HV4 are symmetrical about the first symmetry axis, the second power via HV2 and the fifth power via HV5 are symmetrical about the second symmetry axis, and the third power via HV3 and the sixth power via HV6 are symmetrical about the third symmetry axis. The first symmetry axis, the second symmetry axis, and the third symmetry axis extend along the first direction C and overlap with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.

[0243] Alternatively, see Fig.10 , Fig.16 , Fig. 22 and Fig.28 In a control region column 220, the first input via HI1 and the third input via HI3 are symmetrical about the fourth symmetry axis, and the second input via HI2 and the fourth input via HI4 are symmetrical about the fifth symmetry axis. The fourth symmetry axis and the fifth symmetry axis extend along the first direction C and overlap with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.

[0244] Alternatively, see Fig.10 , Fig.16 , Fig. 22 and Fig.28 , in a first control area 2011, along the first direction C, the first power via HV1 and the fourth power via HV4 are located between the first device area A(1,1) and the first reference via HR1, the second power via HV2 and the fifth power via HV5 are located between the third device area A(2,1) and the first reference via HR1; the third power via HV3 and the sixth power via HV6 are located between the third device area A(2,1) and the second reference via HR2. Thus, in a first control area 2011, along the first direction C, there is a wiring space for array substrate wiring between the first power via HV1 and the first reference via HR1, there is a wiring space for array substrate wiring between the second power via HV2 and the first reference via HR1, there is a wiring space for array substrate wiring between the fourth power via HV4 and the first reference via HR1, and there is a wiring space for array substrate wiring between the fifth power via HV5 and the first reference via HR1. The array substrate may arrange connection leads 500 extending along the second direction D in these wiring spaces, so that the connection leads 500 can minimize the overlapping lengths with different driving leads 300 .

[0245] In one embodiment of the present disclosure, see Fig.15 and Fig.16In the wiring substrate of the present disclosure, in a first control area 2011, the insulating material layer 103 may also be provided with a third reference via HR3 and a fourth reference via HR4 that expose a portion of the reference voltage lead 330. The third reference via HR3 and the first reference via HR1 are respectively located on both sides of the axis of the reference voltage lead 330, and the fourth reference via HR4 and the second reference via HR2 are respectively located on both sides of the axis of the reference voltage lead 330. In this embodiment, in the first control area 2011 of the wiring substrate, each device area A may have a corresponding reference via. Among them, the first device area A (1, 1) may be arranged corresponding to the first reference via HR1, the second device area A (1, 2) may be arranged corresponding to the third reference via HR3, the third device area A (2, 1) may be arranged corresponding to the second reference via HR2, and the fourth device area A (2, 2) may be arranged corresponding to the fourth reference via HR4.

[0246] Furthermore, the third reference via HR3 is symmetrical with the first reference via HR1 about the sixth symmetry axis, and the fourth reference via HR4 is symmetrical with the second reference via HR2 about the seventh symmetry axis; the sixth symmetry axis and the seventh symmetry axis extend along the first direction C and overlap with each other. In this way, the design and preparation of the wiring substrate can be facilitated, the cost of the wiring substrate can be reduced, and the cost of each array substrate based on the wiring substrate can be further reduced.

[0247] Based on the wiring substrate of this embodiment, in addition to the first to fourth array substrates described above, other array substrates using any one of the first to fourth chips 010 to 040 can also be prepared.

[0248] Exemplarily, the wiring substrate in this embodiment can be used to prepare a fifth array substrate provided with the first chip 010. The structure of the second metal wiring layer 104 of the fifth array substrate can be substantially the same as that of the first array substrate, or can be partially adjusted on this basis. When the wiring substrate of this embodiment is used, the connection method between the reference voltage sub-pad P11 of the first pad group P10 corresponding to the device area A in the fifth array substrate and the reference voltage lead 330 is more flexible, for example, the reference via corresponding to the device area A can be connected to the reference voltage lead 330.

[0249] For example, see Fig.17In the fifth array substrate, the reference voltage sub-pad P11 of the first pad group P10 corresponding to the first device area A(1,1) is connected to the reference voltage lead 330 via a connection lead 500 overlapping the first reference via HR1. The reference voltage sub-pad P11 of the first pad group P10 corresponding to the second device area A(1,2) is connected to the reference voltage lead 330 via a connection lead 500 overlapping the third reference via HR3. The reference voltage sub-pad P11 of the first pad group P10 corresponding to the third device area A(2,1) is connected to the reference voltage lead 330 via a connection lead 500 overlapping the second reference via HR2. The reference voltage sub-pad P11 of the first pad group P10 corresponding to the fourth device area A(2,2) is connected to the reference voltage lead 330 via a connection lead 500 overlapping the fourth reference via HR4. In this way, the length of the connecting lead 500 between the reference voltage sub-pad P11 of each first pad group P10 and the reference voltage lead 330 is basically the same, which can improve the uniformity of the working environment of each first chip 010, thereby improving the working stability of the fifth array substrate and facilitating the debugging of the fifth array substrate.

[0250] As another example, the wiring substrate in this embodiment can be used to prepare a sixth array substrate provided with the second chip 020. Fig.18 , the structure of the second metal wiring layer 104 of the sixth array substrate can be substantially the same as that of the second array substrate, or can be partially adjusted on this basis. When the wiring substrate of this embodiment is used, the connection method between the reference voltage sub-pad P21 of the second pad group P20 and the reference voltage lead 330 in the first control area 2011 of the fifth array substrate is more flexible. In the sixth array substrate, in the first control area 2011, the connection lead 500 connected to the reference voltage sub-pad P21 of the second pad group P20 and the reference voltage lead 330 can overlap with the second reference via HR2, or can overlap with the fourth reference via HR4, or can overlap with the second reference via HR2 and the fourth reference via HR4 at the same time. In the first control area 2011, the connection lead 500 connecting the reference voltage sub-pad P21 and the reference voltage lead 330 can completely overlap with the reference voltage lead 330.

[0251] Optionally, in the first control region 2011 of the sixth array substrate, the first reference via HR1, the third reference via HR3, the second input via HI2, and the fourth input via HI4 may not overlap with any second metal wiring layer 104, and may be filled with the insulating protection layer 105. One of the second reference via HR2 and the fourth reference via HR4 is used to overlap with the connecting lead 500, so that the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connecting lead 500; the other may not overlap with any second metal wiring layer 104, and may be filled with the insulating protection layer 105.

[0252] As another example, the wiring substrate in this embodiment can be used to prepare a seventh array substrate provided with the third chip 030. Fig.19 , the structure of the second metal wiring layer 104 of the seventh array substrate can be substantially the same as that of the third array substrate, or can be partially adjusted on this basis. When the wiring substrate of this embodiment is used, the connection method between the reference voltage sub-pad P31 of the third pad group P30 and the reference voltage lead 330 of the seventh array substrate in the first control area 2011 is more flexible. In the seventh array substrate, in the first control area 2011, the connection lead 500 connected to the reference voltage sub-pad P31 of the third pad group P30 and the reference voltage lead 330 can overlap with the second reference via HR2, or can overlap with the fourth reference via HR4. In the first control area 2011, the connection lead 500 connecting the reference voltage sub-pad P31 and the reference voltage lead 330 can completely overlap with the reference voltage lead 330.

[0253] Optionally, in the first control region 2011 of the seventh array substrate, the first reference via HR1, the third reference via HR3, the second input via HI2, and the fourth input via HI4 may not overlap with any second metal wiring layer 104, and may be filled with the insulating protection layer 105. One of the second reference via HR2 and the fourth reference via HR4 is used to overlap with the connecting lead 500, so that the reference voltage sub-pad P31 is connected to the reference voltage lead 330 through the connecting lead 500; the other may not overlap with any second metal wiring layer 104, and may be filled with the insulating protection layer 105.

[0254] As another example, the wiring substrate in this embodiment can be used to prepare an eighth array substrate provided with the fourth chip 040. Fig. 20 The structure of the second metal wiring layer 104 of the eighth array substrate can be substantially the same as that of the fourth array substrate, or can be partially adjusted on this basis. When using the wiring substrate of this embodiment, the arrangement of the fourth pad group P40 in the first control area 2011 of the eighth array substrate is more flexible.

[0255] In the eighth array substrate, the fourth pad group P40 still includes two columns of sub-pads and the number of sub-pads in each column is 5. Wherein, no matter the reference voltage sub-pad P41 is located on the side close to the first reference via HR1 or the side close to the third reference via HR3, both reference voltage sub-pads P41 can be connected to the reference via.

[0256] In one embodiment of the present disclosure, of the two reference voltage sub-pads P41, only one of the reference voltage sub-pads P41 may be electrically connected to the reference voltage lead 330 through the connection lead 500, and the other reference voltage sub-pad P41 may not be electrically connected to the reference voltage lead 330. In this way, the fourth chip 040 can obtain the reference voltage GND through one reference voltage sub-pad P41, which can meet the working requirements of the fourth chip 040. In this embodiment, of the two reference voltage sub-pads P41, the reference voltage sub-pad P41 close to the first reference via HR1 or the third reference via HR3 can be electrically connected to the reference voltage lead 330 through the connection lead 500.

[0257] Optionally, in the first control region 2011 of the eighth array substrate, the second input via HI2 and the fourth input via HI4 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105. At least one of the first reference via HR1 to the fourth reference via HR4 is used to overlap with the connection lead 500, and the remaining reference vias may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0258] Optionally, in the wiring substrate provided in the present disclosure, see Fig.16 In a first control region 2011 , the third reference via HR3 and the fourth reference via HR4 are located on a side of the first reference via HR1 and the second reference via HR2 away from the first power supply voltage lead 310 .

[0259] In a first control area 2011, the first power via HV1, the first input via HI1, the first reference via HR1, the fourth power via HV4, the third input via HI3 and the third reference via HR3 form a first via group; the second power via HV2 and one of the third power via HV3, the second input via HI2, the second reference via HR2, the fifth power via HV5 and one of the sixth power via HV6, the fourth input via HI4 and the fourth reference via HR4 form a second via group. The relative positions between the vias in the first via group are the same as the relative positions between the vias in the second via group. This can simplify the design and preparation of the wiring substrate and reduce the cost of various array substrates. Not only that, this can also simplify the design and preparation of the array substrate and facilitate the debugging of the array substrate.

[0260] In one embodiment of the present disclosure, in the wiring substrate provided by the present disclosure, see Fig.21 and Fig. 22 In a first control region 2011, the insulating material layer 103 is further provided with a fifth reference via HR5 exposing a portion of the reference voltage lead 330, and the fifth reference via HR5 is located between the four device regions A. In this way, when the wiring substrate is used to prepare different array substrates, the connection leads 500 of some array substrates can be further simplified.

[0261] Exemplarily, the wiring substrate in this embodiment can be used to prepare a ninth array substrate provided with the first chip 010. Fig.23 The structure of the second metal wiring layer 104 of the ninth array substrate may be the same as that of the first array substrate or the fifth array substrate, or may be partially adjusted on this basis. Optionally, in the first control region 2011 of the ninth array substrate, the fifth reference via HR5 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0262] As another example, the wiring substrate in this embodiment can be used to prepare a tenth array substrate provided with a second chip 020. The structure of the second metal wiring layer 104 of the tenth array substrate can be the same as that of the second array substrate or the sixth array substrate, or can be partially adjusted thereon.

[0263] In one embodiment of the tenth array substrate, see Fig.24 , relative to the second array substrate or the sixth array substrate, the reference voltage sub-pad P21 of the tenth array substrate is connected to the reference voltage lead 330 through a connection lead 500 overlapping the fifth reference via HR5.

[0264] In one embodiment of the tenth array substrate, relative to the second array substrate or the sixth array substrate, the reference voltage sub-pad P21 of the tenth array substrate may also be located on the side opposite to the first direction C of the address sub-pad P25; at this time, the reference voltage sub-pad P21 and the reference voltage lead 330 may be connected through a connecting lead 500 overlapping with the fifth reference via HR5.

[0265] Optionally, in the first control region 2011 of the tenth array substrate, the reference voltage sub-pad P21 of the tenth array substrate is connected to the reference voltage lead 330 via a connection lead 500 overlapping the fifth reference via HR5. The first reference via HR1 to the fourth reference via HR4 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0266] As another example, the wiring substrate in this embodiment can be used to prepare an eleventh array substrate provided with a third chip 030. The structure of the second metal wiring layer 104 of the eleventh array substrate can be the same as that of the third array substrate or the seventh array substrate, or can be partially adjusted on this basis.

[0267] In one embodiment of the eleventh array substrate, see Fig.25 , relative to the seventh array substrate, the reference voltage sub-pad P31 of the eleventh array substrate is connected to the reference voltage lead 330 through a connection lead 500 overlapping the fifth reference via HR5.

[0268] Optionally, in the first control area 2011 of the eleventh array substrate, the reference voltage sub-pad P31 of the eleventh array substrate is connected to the reference voltage lead 330 through a connecting lead 500 overlapping with the fifth reference via HR5; the first reference via HR1 to the fourth reference via HR4 may not overlap with any second metal wiring layer 104 and be filled with the insulating protective layer 105.

[0269] As another example, the wiring substrate in this embodiment can be used to prepare a twelfth array substrate provided with a fourth chip 040. The structure of the second metal wiring layer 104 of the twelfth array substrate can be the same as that of the fourth array substrate or the eighth array substrate, or can be partially adjusted on this basis.

[0270] In one embodiment of the twelfth array substrate, see Fig.26 Relative to the fourth array substrate or the eighth array substrate, the reference voltage sub-pad P41 of the twelfth array substrate away from the first reference via HR1 or away from the third reference via HR3 is connected to the reference voltage lead 330 through a connecting lead 500 overlapping the fifth reference via HR5.

[0271] For example, in the first control region 2011 of the twelfth array substrate, along the second direction D or the opposite direction thereof, of the two sub-pad columns of the fourth pad group P40, the sub-pad column provided with the reference voltage sub-pad P41 is located on the side close to the fifth reference via HR5. In other words, in the second direction D, the reference voltage sub-pad P41 is located between the strobe signal sub-pad P45 and the first reference via HR1; the fourth pad group P40 is located on the second direction D side of the fifth reference via HR5. In this way, the reference voltage sub-pad P41 can be conveniently electrically connected to the reference voltage lead 330 through the fifth reference via HR5.

[0272] Optionally, in the first control region 2011 of the twelfth array substrate, one reference voltage sub-pad P41 of the twelfth array substrate is connected to the reference voltage lead 330 via a connection lead 500 overlapping one of the first reference via HR1 and the third reference via HR3. Another reference voltage sub-pad P41 is connected to the reference voltage lead 330 via a connection lead 500 overlapping the fifth reference via HR5. The remaining reference vias may not be stacked with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0273] Optionally, in some embodiments of the wiring substrate of the present disclosure, see Fig. 27 and Fig.28 In a first control region 2011, the insulating material layer 103 is further provided with a fifth input via HI5 exposing a portion of the first input lead 320; along the first direction C, the fifth input via HI5 is located between the first reference via HR1 and the third device region A(2,1); the insulating material layer 103 may also be provided with a sixth input via HI6 exposing a portion of the second input lead 340; the sixth input via HI6 and the fifth input via HI5 are symmetrical about the axis of the reference voltage lead 330. In this way, the wiring substrate provided by the present disclosure can also be applied to different microchips, thereby preparing different array substrates.

[0274] Exemplarily, the wiring substrate in this embodiment can be used to prepare a thirteenth array substrate provided with the first chip 010. Fig.29 The structure of the thirteenth array substrate in the second metal wiring layer 104 may be substantially the same as that of the first array substrate, the fifth array substrate or the ninth array substrate, or may be partially adjusted on this basis.

[0275] Optionally, in an implementation manner of the thirteenth array substrate, in the first control region 2011 , the fifth input via HI5 and the sixth input via HI6 may not overlap with any second metal wiring layer 104 , and may be filled with the insulating protection layer 105 .

[0276] Optionally, in another embodiment of the thirteenth array substrate, in the first control region 2011, the first input sub-pad P13 of the first pad group P10 corresponding to the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the fifth input via HI5. The first input via HI1 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0277] Optionally, in another embodiment of the thirteenth array substrate, in the first control region 2011, the first input sub-pad P13 of the first pad group P10 corresponding to the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connection lead 500 overlapping the sixth input via HI6. The third input via HI3 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0278] As another example, the wiring substrate in this embodiment can be used to prepare a fourteenth array substrate provided with a second chip 020. The structure of the second metal wiring layer 104 of the fourteenth array substrate can be substantially the same as that of the first array substrate, the fifth array substrate or the tenth array substrate, or can be partially adjusted on this basis.

[0279] In one embodiment of the fourteenth array substrate, in the first control region 2011, the reference voltage sub-pad P21 of the fourteenth array substrate is connected to the reference voltage lead 330 through a connection lead 500 overlapping any one of the first reference via HR1, the second reference via HR2, and the fifth reference via HR5. One of the chip power sub-pad P23 and the drive data sub-pad P24 is connected to the first input lead 320 through a connection lead 500 overlapping the fifth input via HI5; the other is connected to the second input lead 340 through a connection lead 500 overlapping the sixth input via HI6. Optionally, the connection lead 500 overlapping the fifth input via HI5 and the connection lead 500 overlapping the sixth input via HI6 may extend in a straight line along the second direction D to reduce the overlapping length with the reference voltage lead 330.

[0280] In one embodiment of the present disclosure, see Fig.30 , relative to the tenth array substrate, in the first control region 2011, the chip power sub-pad P23 of the fourteenth array substrate is connected to the first input lead 320 through a connection lead 500 overlapping the fifth input via HI5; optionally, the connection lead 500 extends straight along the second direction to reduce the overlapping length with the reference voltage lead 330. The drive data sub-pad P24 is connected to the second input lead 340 through a connection lead 500 overlapping the sixth input via HI6; optionally, the connection lead 500 extends straight along the second direction. The first input via HI1 and the third input via HI3 may not overlap with any second metal wiring layer 104 and are filled with the insulating protection layer 105.

[0281] As another example, the wiring substrate in this embodiment can be used to prepare a fifteenth array substrate provided with a third chip 030. The structure of the fifteenth array substrate in the second metal wiring layer 104 can be the same as that of the third array substrate, the seventh array substrate or the tenth array substrate, or can be partially adjusted on this basis.

[0282] In one embodiment of the fifteenth array substrate, see Fig.31 , relative to the eleventh array substrate, in the first control region 2011, the chip power sub-pad P33 of the fifteenth array substrate is connected to the first input lead 320 through a connection lead 500 overlapping the fifth input via HI5; optionally, the connection lead 500 extends in a straight line along the second direction D. The drive data sub-pad P34 is connected to the second input lead 340 through a connection lead 500 overlapping the sixth input via HI6; optionally, the connection lead 500 extends in a straight line along the second direction D. The first input via HI1 and the third input via HI3 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0283] As another example, the wiring substrate in this embodiment can be used to prepare a sixteenth array substrate provided with a fourth chip 040. The structure of the second metal wiring layer 104 of the sixteenth array substrate can be the same as that of the fourth array substrate, the eighth array substrate or the twelfth array substrate, or can be partially adjusted on this basis.

[0284] In one embodiment of the sixteenth array substrate, see Fig.32 , relative to the twelfth array substrate, in the first control region 2011, the chip power sub-pad P43 of the sixteenth array substrate is connected to the first input lead 320 through a connection lead 500 overlapping the fifth input via HI5; optionally, the connection lead 500 extends linearly along the second direction D. The drive data sub-pad P44 of the sixteenth array substrate is connected to the second input lead 340 through a connection lead 500 overlapping the sixth input via HI6; optionally, the connection lead 500 extends linearly along the second direction D. The first input via HI1 and the third input via HI3 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protection layer 105.

[0285] Alternatively, in some embodiments, see Fig.33In the wiring substrate and each array substrate prepared in the present disclosure, the control area 201 may further include a second control area 2012. In any one of the control area columns 220, the second control area 2012 is located on one side of the first direction C of each of the first control areas 2011. In other words, in one of the control area columns 220, the last control area 201 along the first direction C may be the second control area 2012, and the remaining control areas 201 may be the first control areas 2011. Optionally, in any one of the control area columns 220, the number of the second control area 2012 is one.

[0286] Alternatively, see Fig.34 In this embodiment, the wiring substrate includes a fan-out region, and the first metal wiring layer 102 is provided with fan-out leads 400 connected to each driving lead 300 in the fan-out region; wherein the driving lead 300 is connected to the corresponding fan-out lead 400 in the second control region 2012. In other words, the connection position of the fan-out lead 400 and the driving lead 300 is located within the range of each second control region 2012; the fan-out region and the second control region 2012 at least partially overlap.

[0287] Alternatively, see Fig.34 In the second control region 2012 , the first device region A(1,1) and the second device region A(1,2) both partially overlap with the driving lead 300 and neither overlaps with the fan-out lead 400 ; the third device region A(2,1) and the fourth device region A(2,2) may partially overlap with the fan-out lead 400 .

[0288] See also Fig.34 In the wiring substrate and each array substrate of this embodiment, within a second control region 2012, the insulating material layer 103 is provided with seventh to tenth power vias, seventh to tenth input vias, and sixth to tenth reference vias.

[0289] Among them, the seventh power via HV7 and the eighth power via HV8 both expose at least part of the first power voltage lead 310. The eighth power via HV8 is located on one side of the first direction of the seventh power via HV7, and is located between the first device area A(1,1) and the third device area A(2,1). In other words, the seventh power via HV7 can be located between the first device area A(1,1) and the third device area A(2,1), or can be located on the side of the first device area A(1,1) away from the third device area A(2,1). In one embodiment of the present disclosure, the relative position relationship between the seventh power via HV7 and the first device area A(1,1) in the second control area 2012 is the same as the relative position relationship between the first power via HV1 and the first device area A(1,1) in the first control area 2011.

[0290] Among them, the ninth power via HV9 and the tenth power via HV10 both expose at least part of the second power voltage lead 350. The tenth power via HV10 is located on the first direction side of the ninth power via HV9, and is located between the second device area A(1,2) and the fourth device area A(2,2). In other words, the seventh power via HV7 can be located between the second device area A(1,2) and the fourth device area A(2,2), or can be located on the side of the second device area A(1,2) away from the fourth device area A(2,2). In one embodiment of the present disclosure, the relative position relationship between the ninth power via HV9 and the second device area A(1,2) in the second control area 2012 is the same as the relative position relationship between the fourth power via HV4 and the second device area A(1,2) in the first control area 2011.

[0291] The seventh input via HI7 and the eighth input via HI8 both expose a portion of the first input lead 320; the seventh input via HI7 is located on a side of the first device area A(1,1) away from the third device area A(2,1); the eighth input via HI8 is located between the first device area A(1,1) and the third device area A(2,1).

[0292] The ninth input via HI9 and the tenth input via HI10 both expose a portion of the second input lead 340; the ninth input via HI9 is ​​located on the side of the second device area A(1,2) away from the fourth device area A(2,2); the tenth input via HI10 is located between the second device area A(1,2) and the fourth device area A(2,2).

[0293] The sixth to tenth reference vias all expose a partial area of ​​the reference voltage lead 330; wherein, the sixth reference via HR6 and the seventh reference via HR7 are arranged along the second direction D and are located between the first device area A(1,1) and the third device area A(2,1); the eighth reference via HR8 is located between the first device area A(1,1) and the third device area A(2,1), the ninth reference via HR9 is located between the second device area A(1,2) and the fourth device area A(2,2), and the tenth reference via HR10 is located between the four device areas A of the second control area 2012.

[0294] See also Fig.34In the second control area 2012, a driving lead 300 and the fan-out lead 400 connected thereto can be a bent metal lead as a whole; in the metal lead, the portion located in the extension direction of the driving lead 300 is the driving lead 300. In other words, in the second control area 2012, near the junction of the driving lead 300 and the connecting lead 500, the size of the driving lead 300 in the second direction D may have shown a trend of gradually shrinking. In the wiring substrate of this embodiment, the seventh to tenth power vias, the seventh to tenth input vias, and the sixth to tenth reference vias may all expose part of the driving lead 300, so that the connecting lead 500 of the array substrate can be connected to the driving lead 300 instead of the fan-out lead 400. In this way, although the fan-out leads 400 overlapped by different second control areas 2012 are different, the layout of the driving leads 300 overlapped by different second control areas 2012 is basically the same. In this way, the wiring substrate of the present invention sets various vias above the relatively fixed driving leads 300 in each second control area 2012, which can avoid the differences in fan-out leads 400 and thus simplify the design and preparation of the wiring substrate, and facilitate the design, preparation and debugging of the array substrate.

[0295] The wiring substrate with the second control area 2012 provided in this embodiment can still be applicable to different microchips and used to prepare different array substrates.

[0296] Illustratively, the wiring substrate of this embodiment can be used to prepare a seventeenth array substrate having the first chip 010. The structure of the first control region 2011 of the seventeenth array substrate can be the same as any one of the first array substrate, the fifth array substrate, the ninth array substrate, and the thirteenth array substrate.

[0297] See also Fig.35 In the second control area 2012 , the second metal wiring layer 104 of the seventeenth array substrate may include four first pad groups P10 corresponding one-to-one to the four device areas A; the pattern of each pad group may be the same as the pattern of the first pad group P10 in the first control area 2011 .

[0298] The first pad group P10 corresponding to the first device area A(1,1) and the first pad group P10 corresponding to the second device area A(1,2) are located between the first device area A(1,1) and the second device area A(1,2); and the first pad group P10 corresponding to the first device area A(1,1) is arranged close to the first device area A(1,1), and the first pad group P10 corresponding to the second device area A(1,2) is arranged close to the second device area A(1,2). In the first direction C, the first pad group P10 corresponding to the third device area A(2,1) is between the first device area A(1,1) and the third device area A(2,1), and the first pad group P10 corresponding to the fourth device area A(2,2) is between the second device area A(1,2) and the fourth device area A(2,2). Optionally, the first pad group P10 corresponding to the third device area A(2,1) and the first pad group P10 corresponding to the fourth device area A(2,2) both at least partially overlap with the reference voltage lead 330. Optionally, the first pad group P10 corresponding to the first device area A(1,1) and the first pad group P10 corresponding to the second device area A(1,2) are arranged along the second direction D, and the first pad group P10 corresponding to the third device area A(2,1) and the first pad group P10 corresponding to the fourth device area A(2,2) are arranged along the second direction D.

[0299] See also Fig.35 In the second control area 2012, the connection mode of each first pad group P10 and the device control circuit and the cascade mode between them can be the same as that of the first control area. In other words, the first pad groups P10 corresponding to each device area A in a signal channel can be cascaded in sequence, so that the output sub-pad P12 of the first pad group P10 corresponding to the (n-1)th level device area A is connected to the first input sub-pad P13 of the first pad group P10 corresponding to the nth level device area A through the connecting lead 500. The second end of the device control circuit of the device area A is connected to the output sub-pad P12 of the corresponding second pad group P20 through the connecting lead 500.

[0300] In the first pad group P10 corresponding to the first device area A(1,1) in the second control region 2012, the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connection lead 500 overlapping the sixth reference via HR6; the first input sub-pad P13 is connected to the first input lead 320 through the connection lead 500 overlapping the seventh input via HI7. In the first pad group P10 corresponding to the second device area A(1,2) in the second control region 2012, the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connection lead 500 overlapping the seventh reference via HR7; the first input sub-pad P13 is connected to the second input lead 340 through the connection lead 500 overlapping the ninth input via HI9. In the first pad group P10 corresponding to the third device area A(2,1) in the second control region 2012, the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connection lead 500 overlapping the eighth reference via HR8; the first input sub-pad P13 is connected to the first input lead 320 through the connection lead 500 overlapping the eighth input via HI8. In the first pad group P10 corresponding to the fourth device area A(2,2) in the second control region 2012, the reference voltage sub-pad P11 is connected to the reference voltage lead 330 through the connection lead 500 overlapping the ninth reference via HR9; the first input sub-pad P13 is connected to the second input lead 340 through the connection lead 500 overlapping the tenth input via HI10.

[0301] See also Fig.35 In the second control region 2012, the first end of the device control circuit of the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the seventh power via HV7; the first end of the device control circuit of the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the ninth power via HV9; the first end of the device control circuit of the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the eighth power via HV8; the first end of the device control circuit of the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the tenth power via HV10.

[0302] Optionally, in an implementation of the seventeenth array substrate, the tenth reference via hole HR10 may not overlap with any second metal wiring layer 104 , and may be filled with the insulating protection layer 105 .

[0303] In the seventeenth array substrate, by adjusting the positions of the four first pad groups P10 in the second control area 2012, the four first pad groups P10 can be dispersedly arranged, thereby avoiding the close arrangement of two adjacent first pad groups P10, and further avoiding the close arrangement of two adjacent first chips to cause a large blockage of light, and further avoiding the bad light spot (mura) caused by the shading of the first chip.

[0304] As another example, the wiring substrate of this embodiment can be used to prepare an eighteenth array substrate having a second chip 020. The structure of the first control region 2011 of the eighteenth array substrate can be the same as any one of the second array substrate, the sixth array substrate, the tenth array substrate, and the fourteenth array substrate.

[0305] See also Fig.36 In the second control region 2012, the second metal wiring layer 104 of the eighteenth array substrate may include a second pad group P20. Optionally, the patterns of the second pad group P20 in the first control region 2011 and the second control region 2012 may be the same.

[0306] See also Fig.36 In the second control region 2012 of the eighteenth array substrate, the second pad group P20 may be located between four device regions A. In other words, in one second control region 2012, along the first direction C, the second pad group P20 is located between the first device region A(1,1) and the third device region A(2,1); along the second direction D, the second pad group P20 is located between the first device region A(1,1) and the second device region A(1,2).

[0307] In the eighteenth array substrate, in the second control area 2012, the reference voltage sub-pad P21 of the second pad group P20 is connected to the reference voltage lead 330 through a connection lead 500 overlapping at least one of the sixth reference via HR6, the seventh reference via HR7, and the tenth reference via HR10. One of the drive data sub-pad P24 and the chip power sub-pad P23 is connected to the first input lead 320 through a connection lead 500 overlapping the eighth input via HI8; the other is connected to the second input lead 340 through a connection lead 500 overlapping the tenth input via HI10. The four output sub-pads P12 are respectively connected to the second ends of the device control circuits of the four device areas A.

[0308] For example, in one embodiment of the eighteenth array substrate, in the second control region 2012, the reference voltage sub-pad P21 of the second pad group P20 is located on the first direction C side of the address sub-pad P25 of the second pad group P20, so as to ensure that the connection lead 500 connected to the reference voltage sub-pad P21 of the second pad group P20 can extend to overlap with the tenth reference via HR10, and the connection lead 500 completely overlaps with the reference voltage lead 330. In this way, when the connection lead 500 and the reference voltage lead 330 are short-circuited, the eighteenth array substrate can avoid being defective.

[0309] In the second control area 2012, the chip power sub-pad P23 is connected to the first input lead 320 through a connecting lead 500 overlapping the eighth input via HI8; the driving data sub-pad P24 is connected to the second input lead 340 through a connecting lead 500 overlapping the tenth input via HI10; and the address sub-pad P25 is connected to the address lead 360 through a connecting lead 500 overlapping the address via. The first output sub-pad P221 can be connected to the second end of the device control circuit of the first device area A(1,1) through the connecting lead 500; the second output sub-pad P222 can be connected to the second end of the device control circuit of the second device area A(1,2) through the connecting lead 500; the third output sub-pad P223 can be connected to the second end of the device control circuit of the third device area A(2,1) through the connecting lead 500; and the fourth output sub-pad P224 can be connected to the second end of the device control circuit of the fourth device area A(2,2) through the connecting lead 500. The first end of the device control circuit of the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the seventh power via HV7; the first end of the device control circuit of the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the ninth power via HV9; the first end of the device control circuit of the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the eighth power via HV8; the first end of the device control circuit of the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the tenth power via HV10.

[0310] Optionally, in one embodiment of the eighteenth array substrate, the seventh input via HI7, the ninth input via HI9, the sixth reference via HR6, the seventh reference via HR7, the eighth reference via HR8, and the ninth reference via HR9 in the second control area 2012 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protective layer 105.

[0311] As another example, the wiring substrate of this embodiment can be used to prepare a nineteenth array substrate having a third chip 030. The structure of the first control region 2011 of the nineteenth array substrate can be the same as any one of the third array substrate, the seventh array substrate, the eleventh array substrate, and the fifteenth array substrate.

[0312] See also Fig.37 In the second control region 2012, the second metal wiring layer 104 of the nineteenth array substrate may include a third pad group P30. Optionally, the patterns of the third pad group P30 in the first control region 2011 and the second control region 2012 may be the same.

[0313] See also Fig.37 In the second control region 2012 of the nineteenth array substrate, the third pad group P30 may be located between four device regions A. In other words, in one second control region 2012, along the first direction C, the third pad group P30 is located between the first device region A(1,1) and the third device region A(2,1); along the second direction D, the third pad group P30 is located between the first device region A(1,1) and the second device region A(1,2).

[0314] In the nineteenth array substrate, in the second control area 2012, the reference voltage sub-pad P31 of the third pad group P30 is connected to the reference voltage lead 330 through a connection lead 500 overlapping at least one of the sixth reference via HR6, the seventh reference via HR7, and the tenth reference via HR10. One of the drive data sub-pad P34 and the chip power sub-pad P33 is connected to the first input lead 320 through a connection lead 500 overlapping the eighth input via HI8; the other is connected to the second input lead 340 through a connection lead 500 overlapping the tenth input via HI10. The four output sub-pads are respectively connected to the second ends of the device control circuits of the four device areas A. In a signal channel, each third pad group P30 is cascaded in sequence, wherein the selection signal sub-pad P35 of the third pad group P30 of the first level is connected to the address lead 360 through a connecting lead 500 overlapping the address via; the relay signal sub-pad P36 of the third pad group P30 of the (n-1)th level and the selection signal sub-pad P35 of the third pad group P30 of the nth level are connected through a connecting lead 500.

[0315] For example, in one embodiment of the nineteenth array substrate, see Fig.37In the second control region 2012, the reference voltage sub-pad P31 of the third pad group P30 is located at the first direction C side of the relay signal sub-pad P36 of the third pad group P30. In this way, the connection lead 500 connected to the reference voltage sub-pad P31 of the third pad group P30 can extend to overlap with the tenth reference via HR10, and the connection lead 500 completely overlaps with the reference voltage lead 330. When the connection lead 500 and the reference voltage lead 330 are short-circuited, the nineteenth array substrate can avoid being defective. In the second control area 2012, the chip power sub-pad P33 is connected to the first input lead 320 through the connecting lead 500 overlapping the eighth input via HI8; the driving data sub-pad P34 is connected to the second input lead 340 through the connecting lead 500 overlapping the tenth input via HI10; the first output sub-pad P321 can be connected to the second end of the device control circuit of the first device area A(1,1) through the connecting lead 500; the second output sub-pad P222 can be connected to the second end of the device control circuit of the second device area A(1,2) through the connecting lead 500; the third output sub-pad P223 can be connected to the second end of the device control circuit of the third device area A(2,1) through the connecting lead 500; and the fourth output sub-pad P224 can be connected to the second end of the device control circuit of the fourth device area A(2,2) through the connecting lead 500. In the second control region 2012, the first end of the device control circuit of the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the seventh power via HV7; the first end of the device control circuit of the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the ninth power via HV9; the first end of the device control circuit of the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the eighth power via HV8; the first end of the device control circuit of the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the tenth power via HV10.

[0316] Optionally, in one embodiment of the nineteenth array substrate, the seventh input via HI7, the ninth input via HI9, the sixth reference via HR6, the seventh reference via HR7, the eighth reference via HR8, and the ninth reference via HR9 in the second control area 2012 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protective layer 105.

[0317] As another example, the wiring substrate of this embodiment can be used to prepare a twentieth array substrate having a fourth chip 040. The structure of the first control region 2011 of the twentieth array substrate can be the same as any one of the fourth array substrate, the eighth array substrate, the twelfth array substrate, and the sixteenth array substrate.

[0318] In the second control region 2012, the second metal wiring layer 104 of the twentieth array substrate may include a fourth pad group P40, wherein the patterns of the fourth pad group P40 in the first control region 2011 and the second control region 2012 may be the same.

[0319] See also Fig.38 , in the second control region 2012 of the twentieth array substrate, the fourth pad group P40 may be located between four device regions A. In other words, in one second control region 2012, along the first direction C, the fourth pad group P40 is located between the first device region A(1,1) and the third device region A(2,1); along the second direction D, the fourth pad group P40 is located between the first device region A(1,1) and the second device region A(1,2).

[0320] In the twentieth array substrate, in the second control area 2012, the fourth pad group P40 has two sub-pad columns, each of which includes five sub-pads arranged along the first direction C. Among them, along the second direction D, in the two sub-pad columns, the sub-pad column provided with the reference voltage sub-pad P41 can be located on the side close to the tenth reference via HR10. In this way, the connecting lead 500 connected to one of the reference voltage sub-pads 41 can extend to overlap with the tenth reference via HR10; the connecting lead 500 connected to the other reference voltage sub-pad 41 can extend to overlap with the eighth reference via HR8 or the ninth reference via HR9. In the second control area 2012, one of the driving data sub-pad P44 and the chip power sub-pad P43 of the fourth pad group P40 is connected to the first input lead 320 through a connecting lead 500 overlapping the eighth input via HI8; the other is connected to the second input lead 340 through a connecting lead 500 overlapping the tenth input via HI10; and the four output sub-pads are respectively connected to the second ends of the device control circuits of the four device areas A. In a signal channel, each fourth pad group P40 is cascaded in sequence, wherein the strobe signal sub-pad P45 of the first-stage fourth pad group P40 is connected to the address lead 360 through a connecting lead 500 overlapping the address via; the relay signal sub-pad P46 of the fourth pad group P40 of the (n-1)th stage is connected to the strobe signal sub-pad P45 of the fourth pad group P40 of the nth stage through a connecting lead 500.

[0321] For example, in one embodiment of the twentieth array substrate, see Fig.38 , in the second control area 2012, along the second direction D, the relay signal sub-pad P46 of the fourth pad group P40 is located on the second direction D side of the reference voltage sub-pad P41, and the reference voltage sub-pad P41 is located on the second direction D side of the tenth reference via HR10. The connecting lead 500 connected to one reference voltage sub-pad P41 of the fourth pad group P40 extends to overlap with the tenth reference via HR10, and the connecting lead 500 connected to another reference voltage sub-pad P41 extends to overlap with the eighth reference via HR8. The driving data sub-pad P44 is connected to the first input lead 320 through the connecting lead 500 overlapping with the eighth input via HI8; the chip power sub-pad P43 is connected to the second input lead 340 through the connecting lead 500 overlapping with the tenth input via HI10. The first output sub-pad P421 can be connected to the second end of the device control circuit of the fourth device area A(2,2) through the connecting lead 500; the second output sub-pad P422 can be connected to the second end of the device control circuit of the third device area A(2,1) through the connecting lead 500; the third output sub-pad P423 can be connected to the second end of the device control circuit of the second device area A(1,2) through the connecting lead 500; the fourth output sub-pad P424 can be connected to the second end of the device control circuit of the first device area A(1,1) through the connecting lead 500. The first end of the device control circuit of the first device area A(1,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the seventh power via HV7; the first end of the device control circuit of the third device area A(2,1) is connected to the first power supply voltage lead 310 through a connecting lead 500 overlapping the eighth power via HV8; the first end of the device control circuit of the second device area A(1,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the ninth power via HV9; the first end of the device control circuit of the fourth device area A(2,2) is connected to the second power supply voltage lead 350 through a connecting lead 500 overlapping the tenth power via HV10.

[0322] Optionally, in one embodiment of the twentieth array substrate, the seventh input via HI7, the ninth input via HI9, the sixth reference via HR6, the seventh reference via HR7, and the ninth reference via HR9 in the second control area 2012 may not overlap with any second metal wiring layer 104 and may be filled with the insulating protective layer 105.

[0323] In the wiring substrate provided by the present disclosure, at least one address lead 360 may be provided in a signal channel. The insulating material layer 103 may be provided with an address via that exposes a portion of the address lead 360. Thus, in the array substrate of the present disclosure, the second metal wiring layer 104 may be provided with a connecting lead 500 that overlaps with the address via, and the connecting lead 500 may be connected to a chip pad group corresponding to the microchip, so as to provide the required signal to the microchip.

[0324] Alternatively, see Fig.40 , two address leads 360 may be provided in one control region column 220. For example, see Fig.10 , Fig.16 , Fig. 22 , Fig.28 and Fig.34 In a control area column 220 , the address lead 360 includes a first address lead 361 and a second address lead 362 , wherein the first address lead 361 is arranged between the first power supply voltage lead 310 and the first input lead 320 , and the second address lead 361 is arranged between the second power supply voltage lead 350 and the second input lead 340 .

[0325] Optionally, among the two address leads 360 in a control region column 220, one of the address leads 360 may extend to an end of the control region column 220 away from the binding region B, and the other address lead 360 may be disposed only in the control region 201 closest to the binding region B. For example, see Fig.50 A first address lead 361 and a second address lead 362 are provided in a control area column 220; wherein the first address lead 361 can extend in a direction away from the binding area B and overlap with each control area 201 in the control area column 220, and the second address lead 362 only overlaps with the second control area 2012, that is, it can be located only in the control area 201 close to the binding area B.

[0326] Optionally, the number of address leads 360 provided on the wiring substrate is not less than the number of control region rows 210, and at least one address lead 360 is provided in one signal channel. The address vias include at least a first address via HD1 and a second address via HD2. In one embodiment of the present disclosure, the number of address leads 360 provided on the wiring substrate is equal to the number of control region rows 210.

[0327] See also Fig.40 The first address via HD1 can be disposed near one end of the address lead 360, and at least one first address via HD1 is disposed in any signal channel. Fig.41When the microchip is the first chip 010, the third chip 030 or the fourth chip 040, the microchip and the address lead 360 can be connected through the connection lead 500 overlapping the first address via HD1, and then receive the control of the selection signal loaded on the address lead 360. Further, in a signal channel, the first address via HD1 used to connect the first-level microchip and the address lead 360 can be located in the same control area 201 as the first-level microchip.

[0328] Alternatively, see Fig.40 In one embodiment of the wiring substrate and the array substrate disclosed in the present invention, each first address via hole HD1 may be arranged in a straight line along the second direction D.

[0329] Optionally, in one embodiment of the wiring substrate and the array substrate of the present disclosure, the first address via HD1 may be located at an end of the wiring substrate away from the binding area B. Of course, in another embodiment of the wiring substrate and the array substrate of the present disclosure, the first address via HD1 may be located at an end of the wiring substrate close to the binding area B.

[0330] Optionally, in an embodiment of the wiring substrate and the array substrate of the present disclosure, see Fig.41 , only one first address via HD1 may be provided in one signal channel.

[0331] Optionally, in another embodiment of the wiring substrate and the array substrate of the present disclosure, see Fig.43 The first address vias HD1 are arranged in one-to-one correspondence with each address lead 360, wherein any first address via HD1 can expose a portion of the corresponding address lead 360. Fig.44 , the number of first address vias HD1 may exceed the required number; when setting the second metal wiring layer 104, one of the first address vias HD1 may be selected in any signal channel as the first address via HD1 corresponding to the signal channel, and the corresponding first address via HD1 is used to electrically connect the address lead 360 with the first-stage microchip of the cascade, and the remaining first address vias HD1 may be filled with the insulating protection layer 105. In this way, the array substrate may more flexibly select the first address vias HD1 overlapping with the connecting leads 500 according to the wiring requirements of the second metal wiring layer 104, and make the other first address vias HD1 not overlap with any connecting leads 500 and be filled with the insulating protection layer 105.

[0332] Alternatively, see Fig.40, at least one second address via HD2 is provided in any control region row 210, and a second address via HD2 can be selected from the control region row 210 as the second address via HD2 corresponding to the control region row 210. In the wiring substrate of the present disclosure, the second address vias HD2 corresponding to each control region row 210 respectively expose different address leads 360. In other words, a second address via HD2 corresponding to the control region row 210 is provided in any control region row 210, and the second address vias HD2 corresponding to each control region row 210 respectively expose partial areas of different address leads. It can be understood that, in some embodiments, part of the first address vias HD1 can be reused as the second address vias HD2.

[0333] In the array substrate of the present disclosure, when the microchip is the second chip or other microchips that need to be scanned row by row, refer to Fig.42 , the second metal wiring layer 104 may be provided with a plurality of connection leads 500 corresponding to each control region row 210 and serving as scan leads. The scan leads overlap with each control region 201 of the corresponding control region row 210, and overlap with the second address via HD2 corresponding to the control region row 210. Each address sub-pad P25 in the control region row 210 may be connected to the scan lead through the connection lead 500. In this way, the address lead 360 connected to the scan lead may be used to load a selection signal to the scan lead, thereby enabling each second chip 020 in the control region row 210 to be selected.

[0334] In some embodiments, the scan lead may extend along the second direction D, and its two ends may be respectively located in two control regions 201 at two ends of the control region row 210 , and the scan lead passes through other control regions 201 in the control region row 210 .

[0335] See also Fig.42 In some embodiments, the scan lead may extend in a straight line along the second direction D and overlap one of the second address vias HD2. In another embodiment of the present disclosure, the scan lead may include an extension section and a connection section, wherein the extension section may extend along the second direction D and not overlap any of the second address vias HD2; and the connection section is connected to the extension section and overlaps one of the second address vias HD2.

[0336] In some embodiments, see Fig.40, the number of the second address vias HD2 on the wiring substrate is the same as the number of the control region rows 210, and they expose different address leads 360 respectively; wherein each second address via HD2 is arranged in a one-to-one correspondence with each control region row 210, and any second address via HD2 is located in the corresponding control region row 210. In this way, the number of the second address vias HD2 is small, which can reduce the impact of the second address vias HD2 on the address leads 360.

[0337] In other embodiments, see Fig.43 In the array substrate and wiring substrate of the present disclosure, in any control region row 210, the number of second address vias HD2 is the same as the number of address leads 360 and they are arranged one-to-one, and any second address via HD2 exposes the corresponding address lead 360. In other words, at least one second address via HD2 is arranged in the overlapping range of each address lead 360 and the control region row 210. Fig.45 In the array substrate of the present disclosure, a second address via HD2 can be selected in a control region row 210 as the second address via HD2 corresponding to the control region row 210; the second address via HD2 corresponding to the control region row 210 overlaps with the connecting lead 500 to drive each microchip in the control region row 210. In this way, the flexibility of the array substrate wiring can be increased, and the design, preparation and debugging of the wiring substrate and the array substrate are also facilitated.

[0338] Optionally, the address via hole may further include a third address via hole HD3. Fig.40 and Fig.43, the third address via HD3 can be arranged near one end of the address lead 360; wherein, along the first direction C, the first address via HD1 and the third address via HD3 can be respectively distributed at the two ends of the wiring substrate of the present disclosure. In a signal channel, at least one third address via HD3 can be arranged, and the number of address leads is at least two; at least one first address via HD1 and at least one third address via HD3 respectively expose different address leads. When the microchip of the array substrate is the first chip 010, the output pin 012 of the last-stage first chip 010 can be connected to the address lead 360 through the connection lead 500 stacked with the third address via HD3, thereby forming a loop for the cascaded first chip 010. When the microchip of the array substrate is the third chip 030 or the fourth chip 040, the output pin of the last-stage third chip 030 or the fourth chip 040 can be connected to the address lead 360 through the connection lead 500 stacked with the third address via HD3, thereby forming a loop for the cascaded third chip 030 or the fourth chip 040. It can be understood that the first address via HD1 and the third address via HD3 are two relative concepts defined according to the connection relationship between the microchip and the address lead 360 in the array substrate; an address via can be the first address via HD1 in one array substrate, and can be the third address via HD3 in another array substrate. It can also be understood that in some embodiments, at least part of the third address via HD3 can be reused as the second address via HD2.

[0339] In some embodiments, see Fig.40 In the array substrate and wiring substrate of the present disclosure, the first address via HD1 and the third address via HD3 are not provided on one address lead 360 at the same time. For example, two address leads may be provided in one control area column, and one first address via HD1 and one third address via HD3 may be provided. The first address via HD1 exposes one of the address leads, and the third address via HD3 exposes the other address lead. In another embodiment of the present disclosure, see Fig.43 In the array substrate and wiring substrate of the present disclosure, the first address via HD1 and the third address via HD3 can be simultaneously provided on any address lead 360. In other words, both ends of any address lead 360 are exposed by the first address via HD1 and the third address via HD3, respectively. In any signal channel of the array substrate, for a plurality of microchips cascaded in sequence, the microchips of the first stage and the microchips of the last stage are respectively connected to different address leads 360. In this way, the flexibility of the wiring of the array substrate can be improved.

[0340] Optionally, in the array substrate of the present disclosure, some of the address vias may be stacked with the connection leads 500, so that the address leads 360 can load signals to the microchip through the connection leads 500 stacked with the address vias. The remaining address vias may not be stacked with any second metal wiring layer 104, and may be filled with the insulating protection layer 105.

[0341] Alternatively, see Fig.46 In the wiring substrate disclosed in the present invention, the first metal wiring layer 102 may also have a first voltage distribution line 371 extending along the second direction D, and each driving lead 300 may be located on the first direction C side of the first voltage distribution line 371. Among them, one of the power supply voltage lead and the reference voltage lead 330 may extend in the opposite direction of the first direction C to connect with the first voltage distribution line 371. In other words, the first power supply voltage lead and the second power supply voltage lead may extend in the opposite direction of the first direction to connect with the first voltage distribution line, or the reference voltage lead may extend in the opposite direction of the first direction to connect with the first voltage distribution line. This allows each power supply voltage lead or each reference voltage lead 330 to be electrically connected to each other, thereby improving the signal disturbance resistance and voltage stability of the array substrate used for the wiring substrate.

[0342] Further, in the wiring substrate of the present disclosure, see Fig.46 , the first metal wiring layer 102 may also have a second voltage distribution line 372 extending along the second direction D. Among them, the first voltage distribution line 371 may be located between the second voltage distribution line 372 and each driving lead 300. One of the power supply voltage lead and the reference voltage lead 330 may extend in the opposite direction of the first direction C to connect with the first voltage distribution line 371; another driving lead 300 at least partially extends in the opposite direction of the first direction C to connect with the second voltage distribution line 372, and the driving lead 300 is not connected to the first voltage distribution lead. In an array substrate based on a wiring substrate, the second metal wiring layer 104 may be provided with a jumper lead 373, which crosses the first voltage distribution line 371, and connects the second voltage distribution line 372 to the above-mentioned another driving lead 300 through a via.

[0343] For example, see Fig.46 In one embodiment of the present disclosure, in the first metal wiring layer 102, each reference voltage lead 330 may extend in the opposite direction of the first direction C to connect with the first voltage distribution line 371. In the first metal wiring layer 102, the first voltage distribution line 371 is located between the second voltage distribution line 372 and at least part of the power supply voltage lead, so that at least part of the power supply voltage lead and the second voltage distribution line 372 cannot be electrically connected through the second voltage distribution line 372. In the array substrate based on the array substrate, see Fig.46 , the second metal wiring layer 104 may be provided with a plurality of jumper leads 373, and each power supply voltage lead that is disconnected from the second voltage distribution line 372 on the first metal wiring layer 102 is provided in one-to-one correspondence with each jumper lead 373. Among them, the jumper lead 373 crosses the first voltage distribution line 371, and one end is connected to the second voltage distribution line 372 through a via, and the other end can be connected to the corresponding power supply voltage lead through a via. In this way, in the array substrate, the power supply voltage leads are electrically connected to each other, which can realize mutual shunting between different power supply voltage leads, improve the overload resistance of the power supply voltage leads, and improve the signal disturbance resistance and voltage stabilization performance of the array substrate. The reference voltage leads 330 are electrically connected to each other, which can improve the signal disturbance resistance of the array substrate and improve the stability of the voltage on the reference voltage lead 330.

[0344] Further, see Fig.46 In the wiring substrate, the first voltage distribution line 371 may be located between two power supply voltage leads on the two sides of the wiring substrate in the second direction D. Thus, in the first metal wiring layer 102, the power supply voltage leads on the two sides may extend in the opposite direction of the first direction C to connect with the second voltage distribution line 372.

[0345] As another example, in another embodiment of the present disclosure, in the first metal wiring layer 102, each power supply voltage lead may extend in the opposite direction of the first direction C to connect with the first voltage distribution line 371. In the first metal wiring layer 102, the first voltage distribution line 371 is located between the second voltage distribution line 372 and the reference voltage lead 330, so that the reference voltage lead 330 and the second voltage distribution line 372 cannot be electrically connected through the first metal wiring layer 102. In an array substrate based on this array substrate, the second metal wiring layer 104 may be provided with a jumper lead 373 corresponding to each reference voltage lead 330. The jumper lead 373 crosses the first voltage distribution line 371, and one end is connected to the second voltage distribution line 372 through a via, and the other end can be connected to the corresponding reference voltage lead 330 through a via. Thus, in the array substrate, the power supply voltage leads are electrically connected to each other, which can realize mutual shunting between different power supply voltage leads, improve the overload resistance of the power supply voltage leads, and improve the signal disturbance resistance and voltage stabilization performance of the array substrate. The reference voltage leads 330 are electrically connected to each other, which can improve the signal disturbance resistance of the array substrate and improve the stability of the voltage on the reference voltage lead 330.

[0346] Optionally, in the array substrate of the present disclosure, see Fig.46, the jumper lead 373 can overlap with the device area A; at this time, the direction of the connecting lead 500 in the device control circuit can be adjusted so that the connecting lead 500 avoids the jumper lead 373. In this way, the relative position of the functional device 107 in the device area A is the same in different device areas A, which can ensure that the functional devices 107 are evenly distributed on the array substrate.

[0347] Alternatively, see Fig.47 The array substrate further includes a plurality of conductive connecting portions 374, and the adjacent first power supply voltage leads 310 and the second power supply voltage leads 350 are connected via the plurality of conductive connecting portions 374. Thus, two adjacent power supply voltage leads are connected via the plurality of conductive connecting portions 374 to form a grid shape, which can not only make the signal shunting between the two power supply voltage leads fully and effectively, but also avoid the two adjacent power supply voltage leads being completely merged into one power supply voltage lead, which would cause the metal area of ​​the first metal wiring layer 102 to occupy too large a proportion.

[0348] It is understandable that in some other embodiments, two adjacent power supply voltage leads may be completely merged into one power supply voltage lead to reduce the impedance of the power supply voltage lead and improve its overload resistance. Furthermore, the metal area ratio of the metal wiring layer may be adjusted by adjusting the spacing between different drive leads 300, hollowing out some drive leads 300, etc., to meet the preparation process requirements of the array substrate.

[0349] In one embodiment of the present disclosure, the conductive connection portion 374 may be located in the first metal wiring layer 102, and the conductive connection portion 374 is located between two adjacent power supply voltage leads and connected to the two power supply voltage leads, so that the two adjacent power supply voltage leads and the conductive connection portion 374 therebetween form a grid.

[0350] Of course, in other embodiments of the array substrate of the present disclosure, part or all of the conductive connection portion 374 may also be located in the second metal wiring layer 104. For example, the conductive connection portion 374 is located in the second metal wiring layer 104, and the conductive connection portion 374 is connected to two adjacent power supply voltage leads through a via. For another example, the conductive connection portion 374 may include a first portion and a second portion, wherein the first portion is located in the first metal wiring layer 102 and connected to one of the power supply voltage leads, and the second portion is located in the second metal wiring layer 104 and connected to the first portion and the other power supply voltage lead through a via.

[0351] The embodiment of the present disclosure also provides a light-emitting module, which includes any one of the array substrates described in the above array substrate embodiments. The light-emitting module can be a light-emitting module of a computer monitor, a light-emitting module of a mobile phone screen, a light-emitting module of a television, or a light-emitting module of other liquid crystal displays, and can be a direct-type light-emitting module of a transmissive liquid crystal display or a direct-type light-emitting module of a reflective liquid crystal display. Since the light-emitting module has any one of the array substrates described in the above array substrate embodiments, it has the same beneficial effects, and the present disclosure will not repeat them here.

[0352] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any modification, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A wiring substrate, comprising a plurality of control regions distributed in an array, wherein the plurality of control regions are arranged into a plurality of control region rows and a plurality of control region columns; any one of the control region columns comprises at least two of the control regions arranged along a first direction, and any one of the control region rows comprises at least two of the control regions arranged along a second direction; the second direction is parallel to a plane where the wiring substrate is located and intersects with the first direction; Any one of the control regions includes four device regions distributed in an array, and the device regions are used to set functional devices electrically connected to each other; the four device regions in any one of the control regions are respectively a first device region, a second device region, a third device region and a fourth device region; wherein, The first device region is the device region located in the first row in the first direction and in the first column in the second direction within the control region; the second device region is the device region located in the first row in the first direction and in the second column in the second direction within the control region; the third device region is the device region located in the second row in the first direction and in the first column in the second direction within the control region; the fourth device region is the device region located in the second row in the first direction and in the second column in the second direction within the control region; The wiring substrate comprises a base substrate, a first metal wiring layer and an insulating material layer which are stacked in sequence; the first metal wiring layer is provided with a driving lead extending along the first direction; in any one of the control area columns, the driving lead at least comprises a first power supply voltage lead, a first input lead, a reference voltage lead, a second input lead and a second power supply voltage lead which are arranged in sequence along the second direction; the wiring substrate also has at least one signal channel extending along the first direction, and any one of the signal channels comprises at least one of the control area columns; in any one of the signal channels, the driving lead further comprises at least one address lead; The control region includes a first control region; in one of the first control regions, the insulating material layer is provided with a first power via to a sixth power via, a first input via to a fourth input via, a first reference via and a second reference via; The first power via to the third power via are arranged in sequence along the first direction and expose a portion of the first power voltage lead respectively; the first power via is located on a side of the device area A(1,1) away from the device area A(2,1) or between the device area A(1,1) and the device area A(2,1); the second power via is located between the device area A(1,1) and the device area A(2,1); the third power via is located on a side of the device area A(2,1) away from the device area A(1,1); The fourth power via to the sixth power via are arranged in sequence along the first direction and expose a portion of the second power voltage lead respectively; the fourth power via is located at a side of the second device area away from the fourth device area or between the second device area and the fourth device area; the fifth power via is located between the second device area and the fourth device area; the sixth power via is located at a side of the fourth device area away from the second device area; The first input via and the second input via respectively expose a portion of the first input lead; the first input via is located between an edge of the first device region away from the third device region and an edge of the third device region close to the first device region; the second input via is located on a side of the third device region away from the first device region; The third input via and the fourth input via respectively expose a portion of the second input lead; the third input via is located between an edge of the second device region away from the fourth device region and an edge of the fourth device region close to the second device region; the fourth input via is located on a side of the fourth device region away from the second device region; The first reference via and the second reference via both expose a portion of the reference voltage lead; Along the first direction, the first reference via is located between the first device region and the third device region, and the second reference via is located on a side of the third device region away from the first device region; In any one of the signal channels, the insulating material layer is further provided with at least one address via hole exposing a partial area of ​​the at least one address lead.

2. The wiring substrate according to claim 1, wherein: In one of the control area columns, the first power via and the fourth power via are symmetrical about a first symmetry axis, the second power via and the fifth power via are symmetrical about a second symmetry axis, and the third power via and the sixth power via are symmetrical about a third symmetry axis.

3. The wiring substrate according to claim 1, wherein In one of the control region columns, the first input via and the third input via are symmetrical about a fourth symmetry axis, and the second input via and the fourth input via are symmetrical about a fifth symmetry axis.

4. The wiring substrate according to claim 1, wherein: In one of the first control regions, along the first direction, the first power via and the fourth power via are located between the first device area and the first reference via, the second power via and the fifth power via are located between the third device area and the first reference via; the third power via and the sixth power via are located between the third device area and the second reference via.

5. The wiring substrate according to claim 1, wherein In one of the first control areas, the insulating material layer is also provided with a third reference via and a fourth reference via exposing a partial area of ​​the reference voltage lead; the third reference via is symmetrical with the first reference via about the sixth symmetry axis, and the fourth reference via is symmetrical with the second reference via about the seventh symmetry axis.

6. The wiring substrate according to claim 5, wherein: In one of the first control regions, in the second direction, the third reference via and the fourth reference via are located on a side of the first reference via and the second reference via away from the first power supply voltage lead; In one of the first control regions, the first power via, the first input via, the first reference via, the fourth power via, the third input via and the third reference via form a first via group; One of the second power via and the third power via, the second input via, the second reference via, one of the fifth power via and the sixth power via, the fourth input via and the fourth reference via form a second via group; The relative positions between the via holes in the first via hole group are the same as the relative positions between the via holes in the second via hole group.

7. The wiring substrate according to claim 1, wherein: In one of the first control regions, the insulating material layer is further provided with a fifth reference via hole exposing a portion of the reference voltage lead, and the fifth reference via hole is located between the four device regions.

8. The wiring substrate according to claim 1, wherein In one of the first control regions, the insulating material layer is further provided with a fifth input via exposing a partial area of ​​the first input lead; along the first direction, the fifth input via is located between the first reference via and the third device region; the insulating material layer may also be provided with a sixth input via exposing a partial area of ​​the second input lead; the sixth input via is symmetrical to the fifth input via about an eighth symmetry axis, and the eighth symmetry axis extends along the first direction.

9. The wiring substrate according to claim 1, wherein: The control area further includes a second control area; in any one of the control area columns, the second control area is located on one side of the first direction of each of the first control areas; In one of the second control regions, the insulating material layer is provided with a seventh power via to a tenth power via, a seventh input via to a tenth input via, and a sixth reference via to a tenth reference via; The seventh power via and the eighth power via both expose at least a portion of the first power voltage lead, and the ninth power via and the tenth power via both expose at least a portion of the second power voltage lead; the eighth power via is located on one side of the first direction of the seventh power via and between the first device area and the third device area; the tenth power via is located on one side of the first direction of the ninth power via and between the second device area and the fourth device area; The seventh input via and the eighth input via both expose a portion of the first input lead; the seventh input via is located on a side of the first device region away from the third device region; The eighth input via is located between the first device area and the third device area; the ninth input via and the tenth input via both expose a portion of the second input lead; the ninth input via is located on a side of the second device area away from the fourth device area; the tenth input via is located between the second device area and the fourth device area; The sixth reference via to the tenth reference via all expose a partial area of ​​the reference voltage lead; wherein the sixth reference via and the seventh reference via are arranged along the second direction and are located between the first device area and the third device area; the eighth reference via is located between the first device area and the third device area, the ninth reference via is located between the second device area and the fourth device area, and the tenth reference via is located between the four device areas of the second control area.

10. The wiring substrate according to claim 9, wherein: The wiring substrate includes a fan-out area, and the first metal wiring layer is provided with fan-out leads connected to each of the driving leads in the fan-out area; wherein the driving leads are connected to the corresponding fan-out leads in the second control area.

11. The wiring substrate according to claim 1, wherein The number of the address leads is not less than the number of the control area rows; The address vias include a first address via and a second address via; the first address via is arranged near one end of the address leads, and at least one of the first address vias is arranged in any one of the signal channels; the second address via corresponding to the control area row is arranged in any one of the control area rows, and the second address vias corresponding to each of the control area rows respectively expose partial areas of different address leads.

12. The wiring substrate according to claim 11, wherein The address via also includes a third address via; along the first direction, the first address via and the third address via are respectively distributed at both ends of the wiring substrate; in one of the signal channels, the number of the address leads is at least two, the number of the third address via is at least 1, and at least one of the first address via and at least one of the third address vias respectively expose different address leads.

13. The wiring substrate according to claim 12, wherein: Two address leads are arranged in one control region column, and one first address via and one third address via are arranged; the first address via exposes one of the address leads, and the third address via exposes the other address lead.

14. The wiring substrate according to claim 12, wherein: Two ends of any one of the address leads are exposed by the first address via and the third address via, respectively.

15. The wiring substrate according to claim 11, wherein The number of the second address vias is the same as the number of the control area rows, and each of the second address vias is arranged in a one-to-one correspondence with each of the control area rows; each of the second address vias exposes a different address lead, and any second address via is located in the corresponding control area row.

16. The wiring substrate according to claim 11, wherein In any one of the control region rows, the number of the second address vias is the same as the number of the address leads and are arranged in a one-to-one correspondence, and any one of the second address vias exposes the corresponding address lead.

17. The wiring substrate according to claim 1, wherein: The first metal wiring layer also has a first voltage distribution line extending along the second direction, and each of the driving leads is located on one side of the first direction of the first voltage distribution line; the first power supply voltage lead and the second power supply voltage lead extend in the opposite direction of the first direction to connect to the first voltage distribution line, or the reference voltage lead extends in the opposite direction of the first direction to connect to the first voltage distribution line.

18. The wiring substrate according to claim 17, wherein: The first metal wiring layer further includes a second voltage distribution line extending along the second direction; wherein the first voltage distribution line is located between the second voltage distribution line and each of the driving leads.

19. An array substrate, comprising the wiring substrate according to any one of claims 1 to 18.

20. The array substrate according to claim 19, wherein: The array substrate further comprises a second metal wiring layer and an insulating protection layer sequentially stacked on the insulating material layer of the wiring substrate away from the base substrate, and comprises a plurality of functional devices and a plurality of microchips; Among them, the second metal wiring layer includes multiple connecting leads, multiple device pad groups and multiple chip pad groups, the functional device is bound and connected to the device pad group, and the microchip is bound and connected to the chip pad group; the device pad group and the chip pad group are connected to the connecting leads; at least part of the connecting leads are connected to the first metal wiring layer through at least part of the vias provided on the insulating material layer.

21. The array substrate according to claim 20, wherein: A device control circuit is provided in any one of the device areas, and the device control circuit includes one of the functional devices or a plurality of electrically connected functional devices; In the first control region, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the first power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the second power via or the third power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the fourth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the fifth power via or the sixth power via.

22. The array substrate according to claim 21, wherein: In one of the control regions, the array substrate is provided with four chip pad groups corresponding to the four device regions one by one; any one of the chip pad groups includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad, and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to the output sub-pad of the chip pad group corresponding to the device region through the connecting lead; In one of the signal channels, the device areas are numbered in sequence, and the device area numbered 1 is located at one end of the signal channel in the first direction; the chip pad groups corresponding to the device areas are cascaded in sequence according to the numbering order of the device areas; the second input sub-pad of the chip pad group corresponding to the device area numbered 1 is connected to one of the address leads through the connecting lead overlapping the address via; the output sub-pad of the chip pad group corresponding to the device area numbered (n-1) is connected to the second input sub-pad of the chip pad group corresponding to the device area numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels; In any one of the first control regions, the reference voltage sub-pad of the chip pad group corresponding to the first device area and the reference voltage sub-pad of the chip pad group corresponding to the second device area are connected to the reference voltage lead through the connecting lead overlapping the first reference via hole; the reference voltage sub-pad of the chip pad group corresponding to the third device area and the reference voltage sub-pad of the chip pad group corresponding to the fourth device area are connected to the reference voltage lead through the connecting lead overlapping the second reference via hole; the first input sub-pad of the chip pad group corresponding to the first device area is connected to the reference voltage lead through the connecting lead overlapping the second reference via hole. The pad is connected to the first input lead through the connecting lead overlapping the first input via; the first input sub-pad of the chip pad group corresponding to the third device area and the first input lead are connected through the connecting lead overlapping the second input via; the first input sub-pad of the chip pad group corresponding to the second device area and the second input lead are connected through the connecting lead overlapping the third input via; the first input sub-pad of the chip pad group corresponding to the fourth device area and the second input lead are connected through the connecting lead overlapping the fourth input via.

23. The array substrate according to claim 22, wherein: In one of the control regions, the array substrate is provided with four chip pad groups corresponding to the four device regions one by one; any one of the chip pad groups includes a reference voltage sub-pad, an output sub-pad, a first input sub-pad, and a second input sub-pad; the second end of the device control circuit in any one of the device regions is connected to the output sub-pad of the chip pad group corresponding to the device region through the connecting lead; In one of the signal channels, the device areas are numbered in sequence, and the device area numbered 1 is located at one end of the signal channel in the first direction; the chip pad groups corresponding to the device areas are cascaded in sequence according to the numbering order of the device areas; the second input sub-pad of the chip pad group corresponding to the device area numbered 1 is connected to one of the address leads through the connecting lead overlapping the address via; the output sub-pad of the chip pad group corresponding to the device area numbered (n-1) is connected to the second input sub-pad of the chip pad group corresponding to the device area numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the device areas in one of the signal channels; In any one of the first control regions, the first input sub-pad of the chip pad group corresponding to the first device region is connected to the first input lead via the connecting lead overlapping the first input via; the first input sub-pad of the chip pad group corresponding to the third device region is connected to the first input lead via the connecting lead overlapping the second input via; the first input sub-pad of the chip pad group corresponding to the second device region is connected to the second input lead via the connecting lead overlapping the third input via; the first input sub-pad of the chip pad group corresponding to the fourth device region is connected to the second input lead via the connecting lead overlapping the fourth input via; When the wiring substrate is provided with the third reference via and the fourth reference via, in any one of the first control regions, the reference voltage sub-pad of the chip pad group corresponding to the first device region and the reference voltage lead are connected via the connecting lead overlapping the first reference via; the reference voltage sub-pad of the chip pad group corresponding to the third device region and the reference voltage lead are connected via the connecting lead overlapping the second reference via; the reference voltage sub-pad of the chip pad group corresponding to the second device region and the reference voltage lead are connected via the connecting lead overlapping the third reference via; The reference voltage sub-pad of the chip pad group corresponding to the fourth device region and the reference voltage lead are connected through the connection lead overlapping the fourth reference via.

24. The array substrate according to claim 22 or 23, wherein: When the wiring substrate includes the second control area, in any one of the second control areas, the chip pad group corresponding to the first device area and the chip pad group corresponding to the second device area are located between the first device area and the second device area; and the chip pad group corresponding to the first device area is arranged close to the first device area, and the chip pad group corresponding to the second device area is arranged close to the second device area; in the first direction, the chip pad group corresponding to the third device area is between the first device area and the third device area, and the chip pad group corresponding to the fourth device area is between the second device area and the fourth device area; In any one of the chip pad groups corresponding to the first device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the sixth reference via, and the first input sub-pad is connected to the first input lead through the connection lead overlapping the seventh input via; In the chip pad group corresponding to the second device area in any one of the second control regions, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the seventh reference via, and the first input sub-pad is connected to the second input lead through the connection lead overlapping the ninth input via; In any one of the chip pad groups corresponding to the third device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the eighth reference via, and the first input sub-pad is connected to the first input lead through the connection lead overlapping the eighth input via; In any one of the chip pad groups corresponding to the fourth device region in the second control region, the reference voltage sub-pad is connected to the reference voltage lead through the connection lead overlapping the ninth reference via, and the first input sub-pad is connected to the second input lead through the connection lead overlapping the tenth input via; In any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via.

25. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second end of the device control circuit in the four device areas is electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting lead; the reference voltage sub-pad is located on one side of the first direction of the address sub-pad; In any one of the first control areas, the reference voltage sub-pad is located on one side of the first direction of the address sub-pad; the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the second reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

26. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; When the wiring substrate is provided with the fifth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

27. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, an address sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; When the wiring substrate is provided with the fifth input via and the sixth input via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping with the fifth input via, and the other is connected to the second input lead through the connecting lead overlapping with the sixth input via; the address sub-pad is connected to the address lead through the connecting lead overlapping with the address via.

28. The array substrate according to any one of claims 25 to 27, wherein: When the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence; The reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the eighth input via, and the other is connected to the second input lead through the connecting lead overlapping the tenth input via; the address sub-pad is connected to the address lead through the connecting lead overlapping the address via.

29. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels; In any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the second reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

30. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering sequence of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; When the wiring substrate includes the fifth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

31. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes a reference voltage sub-pad, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels; When the wiring substrate includes the fifth reference via and the sixth reference via, in any one of the first control areas, the reference voltage sub-pad is connected to the reference voltage lead through the connecting lead; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the fifth input via, and the other is connected to the second input lead through the connecting lead overlapping the sixth input via.

32. The array substrate according to any one of claims 29 to 31, wherein: When the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence; The reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the eighth input via, and the other is connected to the second input lead through the connecting lead overlapping the tenth input via.

33. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes two reference voltage sub-pads, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering order of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; n is a positive integer greater than 1 and not greater than the number of the control regions in one of the signal channels; In any one of the first control areas, in the second direction, the reference voltage sub-pad is located between the selection signal sub-pad and the first reference via; one of the reference voltage sub-pads is connected to the reference voltage lead through the connecting lead overlapping the first reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

34. The array substrate according to claim 21, wherein: In any one of the control areas, the array substrate is provided with a chip pad group, and the chip pad group is located between the four device areas of the control area; the chip pad group includes two reference voltage sub-pads, a chip power sub-pad, a drive data sub-pad, a strobe signal sub-pad, a relay signal sub-pad and four output sub-pads; the second ends of the device control circuits in the four device areas are electrically connected to the four output sub-pads in a one-to-one correspondence through the connecting leads; In one of the signal channel regions, each of the control regions is numbered in sequence, wherein the control region numbered 1 is located at one end of the signal channel region in its extension direction; the chip pad groups in each of the control regions are cascaded in sequence according to the numbering sequence of the control regions; the strobe signal sub-pad of the chip pad group in the control region numbered 1 is connected to the address lead through the connecting lead overlapping the address via; the relay signal sub-pad of the chip pad group in the control region numbered (n-1) is connected to the strobe signal sub-pad of the chip pad group in the control region numbered n through the connecting lead; When the wiring substrate includes the fifth reference via, in any one of the first control areas, in the second direction, the reference voltage sub-pad is located between the selection signal sub-pad and the first reference via; the chip pad group is located on the second direction side of the fifth reference via; one of the reference voltage sub-pads is connected to the reference voltage lead through the connecting lead overlapping the first reference via; the other reference voltage sub-pad is connected to the reference voltage lead through the connecting lead overlapping the fifth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead through the connecting lead overlapping the first input via, and the other is connected to the second input lead through the connecting lead overlapping the third input via.

35. The array substrate according to claim 33 or 34, wherein: When the wiring substrate includes the second control area, in any one of the second control areas, the first end of the device control circuit in the first device area is connected to the first power supply voltage lead through the connecting lead overlapping the seventh power via; the first end of the device control circuit in the third device area is connected to the first power supply voltage lead through the connecting lead overlapping the eighth power via; the first end of the device control circuit in the second device area is connected to the second power supply voltage lead through the connecting lead overlapping the ninth power via; the first end of the device control circuit in the fourth device area is connected to the second power supply voltage lead through the connecting lead overlapping the tenth power via; the second ends of the device control circuits in the four device areas are connected to the four output sub-pads through connecting leads in a one-to-one correspondence; One of the reference voltage sub-pads is connected to the reference voltage lead via the connecting lead overlapping the tenth reference via; one of the chip power sub-pad and the drive data sub-pad is connected to the first input lead via the connecting lead overlapping the eighth input via, and the other is connected to the second input lead via the connecting lead overlapping the tenth input via.

36. A light-emitting module, comprising the array substrate according to any one of claims 19 to 35.

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