Method for manufacturing memory and memory
By setting up a barrier layer on the filling hole wall of the memory, the problem of difficult oxide removal on the surface of the wire is solved, more efficient electrical connection is achieved, and the memory storage speed and efficiency are improved.
Patent Information
- Application Number
- CN202110371860.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-04-07
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2041-04-07
Smart Images
Figure CN115172277B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of storage devices, and in particular to a method for manufacturing a memory and a memory. Background Art
[0002] With the gradual development of storage device technology, dynamic random access memory (DRAM) has been gradually applied in various electronic devices with its higher density and faster read and write speed. Dynamic random access memory usually includes a substrate and a dielectric layer arranged on the substrate, the substrate includes a core area and a peripheral area, and a word line is arranged in the core area. The dielectric layer is provided with a first wire electrically connected to the word line located in the core area and a second wire connected to the substrate located in the peripheral area.
[0003] In the related art, when forming the first conductive line and the second conductive line, it is necessary to first expose the core area, the word line and the substrate of the peripheral area. The metal surface of the word line and the surface of the substrate are easily oxidized to produce oxides during the exposure process. If these oxides are not completely cleaned, the resistance of the electrical connection will increase, which will directly affect the storage speed and storage efficiency. Summary of the invention
[0004] In view of the above problems, an embodiment of the present invention provides a method for manufacturing a memory and a memory, so as to improve the storage speed and storage efficiency of the memory.
[0005] In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:
[0006] In a first aspect, an embodiment of the present invention provides a method for manufacturing a memory, comprising: providing a substrate, wherein a word line is arranged in a core area of the substrate; forming a dielectric layer on the substrate, etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on the hole wall of the first filling hole, wherein the barrier layer located in the first filling hole is arranged to form a first middle hole, wherein the first middle hole exposes the word line; etching the word line exposed in the first middle hole to remove a first residue on the word line; forming a first conductive wire in the first middle hole, wherein the first conductive wire is electrically connected to the word line.
[0007] The method for manufacturing a memory provided by the embodiment of the present invention has the following advantages:
[0008] The manufacturing method of the memory provided by the embodiment of the present invention includes: providing a substrate, in which a word line is arranged in the core area of the substrate; forming a dielectric layer on the substrate, etching the dielectric layer, and forming a first filling hole exposing the word line; forming a barrier layer on the wall of the first filling hole, the barrier layer located in the first filling hole is arranged to form a first middle hole, and the first middle hole exposes the word line; etching the word line exposed in the first middle hole to remove the first residue on the word line; forming a first wire in the first middle hole, and the first wire is electrically connected to the word line. By forming a barrier layer on the wall of the first filling hole, when the first residue on the word line is removed later, the barrier layer protects the wall of the first filling hole, so that the first residue can be fully removed, reducing the content of the first residue, thereby reducing the contact resistance between the first wire and the word line, and improving the performance of the memory. In addition, the barrier layer can also reduce or even avoid the bending of the wall of the first filling hole, so that the gap inside the first wire formed later is less or even no, thereby improving the ability of the first wire to transmit charge, and further improving the storage speed and storage efficiency of the memory.
[0009] According to the manufacturing method of the memory as described above, a barrier layer is formed on the wall of the first filling hole, the barrier layer located in the first filling hole is arranged to form a first middle hole, and the step of exposing the word line through the first middle hole includes: forming the barrier layer on the wall and bottom of the first filling hole and the dielectric layer, the barrier layer located in the first filling hole is arranged to form the first middle hole; and removing the barrier layer on the dielectric layer and at the bottom of the first middle hole.
[0010] In the method for manufacturing the memory as described above, the word line exposed in the first middle hole is etched, and the step of removing the first residue on the word line includes: removing the first residue on the word line by plasma etching to generate a first reactant; and removing the first reactant by wet etching.
[0011] In the manufacturing method of the memory as described above, the first etching gas used in plasma etching is a mixture of hydrogen and argon; the material of the word line is tungsten, the first residue is tungsten oxide, and the first reactant is tungsten.
[0012] In the manufacturing method of the memory as described above, in the horizontal direction, the size of the first filling hole is larger than the size of the word line, and the hole wall of the first filling hole and the edge of the word line have a distance difference of 1-3 nm.
[0013] In the manufacturing method of the memory as described above, the substrate further includes a peripheral region, and a second filling hole is formed in the dielectric layer on the peripheral region, and the second filling hole exposes the substrate.
[0014] According to the method for manufacturing the memory as described above, after the steps of forming a dielectric layer on the substrate, etching the dielectric layer, and forming a first filling hole exposing the word line, the method for manufacturing the memory further includes: forming a barrier layer on the wall of the second filling hole, the barrier layer located in the second filling hole enclosing a second middle hole, and the second middle hole exposing the substrate.
[0015] In the manufacturing method of the memory as described above, the barrier layer is formed on the first filling hole wall and the second filling hole wall at the same time.
[0016] In the method for manufacturing the memory as described above, the step of simultaneously forming the barrier layer on the first filling hole wall and the second filling hole wall includes: forming the barrier layer on the first filling hole wall and hole bottom, the second filling hole wall and hole bottom, and the dielectric layer; removing the barrier layer located on the dielectric layer, at the bottom of the first middle hole, and at the bottom of the second middle hole.
[0017] According to the method for manufacturing the memory as described above, a barrier layer is formed on the wall of the second filling hole, the barrier layer in the second filling hole is arranged to form a second middle hole, and after the step of exposing the substrate through the second middle hole, the method for manufacturing the memory further includes: etching the substrate exposed in the second middle hole to remove the second residue on the substrate; and forming a second wire in the second middle hole, the second wire being electrically connected to the substrate.
[0018] The manufacturing method of the memory as described above etches the substrate exposed in the second middle hole, and the step of removing the second residue on the substrate includes: removing the second residue on the substrate by plasma etching to generate a second reactant; and removing the second reactant by wet etching.
[0019] In the manufacturing method of the memory as described above, the second etching gas used in plasma etching is a mixture of ozone and dilute hydrofluoric acid; the material of the substrate is silicon, and the second residue is silicon oxide.
[0020] According to the manufacturing method of the memory as described above, while forming the first conductive line in the first middle hole, the second conductive line is formed in the second middle hole.
[0021] In the method for manufacturing a memory as described above, before the step of forming a second conductive line in the second middle hole and electrically connecting the second conductive line to the substrate, the method for manufacturing a memory further includes: forming a metal composite in the second middle hole.
[0022] In a second aspect, an embodiment of the present invention further provides a memory, comprising: a substrate, the substrate comprising a core area and a peripheral area, a word line being arranged in the core area; a dielectric layer, the dielectric layer being arranged on the substrate, the dielectric layer being provided with a first filling hole and a second filling hole penetrating the dielectric layer, the first filling hole being located on the core area and extending to the word line, the second filling hole being located on the peripheral area and extending to the substrate; a blocking layer, the blocking layer being arranged on the hole wall of the first filling hole and the hole wall of the second filling hole, the blocking layer located in the first filling hole being arranged to form a first middle hole, the first middle hole exposing the word line, the blocking layer located in the second filling hole being arranged to form a second middle hole, the second middle hole exposing the substrate; a first conductive wire, the first conductive wire being filled in the first middle hole and being electrically connected to the word line; a second conductive wire, the second conductive wire being filled in the second middle hole and being electrically connected to the substrate.
[0023] The memory provided by the embodiment of the present invention has the following advantages:
[0024] The memory provided by the embodiment of the present invention comprises: a substrate, a dielectric layer arranged on the substrate, the substrate comprising a core region and a peripheral region, and a word line is arranged in the core region. The dielectric layer is provided with a first filling hole and a second filling hole penetrating the layer, the first filling hole is located on the core region and extends to the word line, so that the word line is exposed in the first filling hole, and the second filling hole is located on the peripheral region and extends to the substrate, so that the substrate is exposed in the second filling hole. The hole wall of the first filling hole and the hole wall of the second filling hole are provided with a barrier layer, the barrier layer located in the first filling hole is arranged to form a first middle hole, the first middle hole is filled with a first wire, and the first wire is electrically connected to the word line; the barrier layer located in the second filling hole is arranged to form a second middle hole, the second middle hole is filled with a second wire, and the second wire is electrically connected to the substrate. By setting a barrier layer on the hole wall of the first filling hole and the hole wall of the second filling hole, the barrier layer protects the hole wall of the first filling hole and the hole wall of the second filling hole, and when cleaning the word line in the first middle hole and the substrate in the second middle hole, it can be fully carried out to make the surface of the word line in the first middle hole and the substrate in the second middle hole smooth and free of foreign matter, thereby reducing the contact resistance between the first wire and the word line, and between the second wire and the substrate, and improving the storage speed and storage efficiency of the memory. In addition, the barrier layer can also reduce or even avoid the bending of the hole wall of the first filling hole and the hole wall of the second filling hole, and the internal gaps of the first wire and the second wire formed subsequently are less, thereby improving the ability of the first wire and the second wire to transmit charge, and further improving the storage speed and storage efficiency of the memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 is a schematic diagram of a first residue and a second residue in the related art;
[0027] Figure 2 It is a schematic diagram after forming a first filling hole and a second filling hole in the related art;
[0028] Figure 3 It is a schematic diagram after forming a first conductive line and a second conductive line in the related art;
[0029] Figure 4 for Figure 3 A partial enlarged view of point C in the middle;
[0030] Figure 5 is a flow chart of a method for manufacturing a memory in an embodiment of the present invention;
[0031] Figure 6 is a schematic diagram of the structure after the first filling hole is formed in an embodiment of the present invention;
[0032] Figure 7 is a schematic diagram of the structure after forming a barrier layer in an embodiment of the present invention;
[0033] Figure 8 It is a schematic diagram of the structure after a portion of the barrier layer is removed in an embodiment of the present invention;
[0034] Fig. 9 is a schematic diagram of the structure after the first residue is removed in an embodiment of the present invention;
[0035] Fig.10 is a schematic diagram of a structure after forming a first conductive line in an embodiment of the present invention;
[0036] Fig.11 for Fig.10 The enlarged view of point D in the middle;
[0037] Fig.12 is a schematic diagram of the structure after removing the second residue in an embodiment of the present invention;
[0038] Fig.13 It is a schematic diagram of the structure after the second conductive line is formed in an embodiment of the present invention.
[0039] Description of reference numerals:
[0040] 100-substrate; 110-word line;
[0041] 120-first residue; 130-second residue;
[0042] 140-isolation structure; 200-dielectric layer;
[0043] 210-first protective layer; 220-intermediate layer;
[0044] 230 - second protective layer; 240 - first filling hole;
[0045] 250 - a second filling hole; 260 - a transistor;
[0046] 300-barrier layer; 310-first intermediate hole;
[0047] 320-second middle hole; 400-first wire;
[0048] 500-second conductor; 600-gap;
[0049] 700 - second conductive layer; 800 - metal composite. DETAILED DESCRIPTION
[0050] Reference Figures 1 to 4 In the related art, when manufacturing a memory, a dielectric layer 200 is usually formed on a substrate 100, and then a first filling hole 240 and a second filling hole 250 are formed in the dielectric layer 200. The first filling hole 240 extends to the word line 110 located in the core area of the substrate 100, and the second filling hole 250 extends to the substrate 100 located in the peripheral area. Figure 1 As shown, the first filling hole 240 exposes the word line 110, and the second filling hole 250 exposes the substrate 100. The first residue 120 is easily formed on the surface of the exposed word line 110, and the second residue 130 is easily formed on the surface of the exposed substrate 100. Before forming the first conductive line 400 in the first filling hole 240 and forming the second conductive line 500 in the second filling hole 250, it is usually necessary to remove the first residue 120 and the second residue 130 to reduce the resistance between the first conductive line 400 and the word line 110, and between the second conductive line 500 and the substrate 100, so as to improve the storage efficiency and storage speed.
[0051] However, in the process of removing the first residue 120 and the second residue 130, the first residue 120 and the second residue 130 are not easy to remove, which affects the performance of the memory. In addition, the hole wall of the first filling hole 240 and the hole wall of the second filling hole 250 are prone to Figure 2 The bending shown in the figure makes the first conductive line 400 and the second conductive line 500 formed later form Figure 3 and Figure 4The gap 600 shown reduces the ability of the first conductive line 400 and the second conductive line 500 to transfer charges, resulting in lower storage efficiency and storage speed.
[0052] In order to improve the storage efficiency and storage speed of the memory, an embodiment of the present invention provides a method for manufacturing the memory, wherein a barrier layer is formed on the hole wall of the first filling hole, and during the process of removing the first residue, the barrier layer protects the hole wall of the first filling hole, so that the first residue can be removed more fully, thereby improving the performance of the memory. In addition, the barrier layer can also reduce or even avoid the bending of the hole wall of the first filling hole, so that there are fewer or even no gaps inside the first wire formed subsequently, thereby improving the ability of the first wire to transmit charges, and further improving the storage speed and storage efficiency of the memory.
[0053] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.
[0054] Embodiment 1
[0055] Reference Figure 5 The present invention provides a method for manufacturing a memory, the method comprising the following steps:
[0056] Step S101, providing a substrate, wherein a buried word line is disposed in a core region of the substrate.
[0057] The substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. Of course, the present invention is not limited thereto, and illustratively, the substrate may also be a germanium (Ge) substrate, a silicon on insulator (SOI), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate, etc.
[0058] The substrate 100 includes a core region located at Figure 6 At A shown, a word line 110 is disposed in the core region, for example, the word line 110 is a buried word line. The word line 110 may include a first conductive layer and an anti-diffusion layer disposed on the sidewall and bottom wall of the first conductive layer. Exemplarily, the material of the first conductive layer is tungsten, and the material of the anti-diffusion layer is titanium nitride.
[0059] There may be a plurality of word lines 110 , and the plurality of word lines 110 are spaced apart from each other. For example, an isolation structure 140 is disposed between the word lines 110 to electrically isolate each word line 110 , and the isolation structure 140 may be filled with insulating materials such as silicon oxide (SiO 2 ).
[0060] In one possible example, Figure 6 As shown, the substrate 100 includes a core region and a peripheral region, and the core region and the peripheral region are adjacent to each other. Figure 6 At A shown, the peripheral area is located Figure 6 B is shown. A capacitor is subsequently formed on the core region of the substrate 100 , and a peripheral circuit, such as a transistor 260 , is subsequently formed on the peripheral region of the substrate 100 .
[0061] Step S102: forming a dielectric layer on the substrate, and etching the dielectric layer to form an exposed first filling hole.
[0062] Continue to refer to Figure 6 , a dielectric layer 200 is formed on the substrate 100 , and the dielectric layer 200 is etched to form a first filling hole 240 penetrating the dielectric layer 200 , wherein the first filling hole 240 extends to the word line 110 to expose the word line 110 .
[0063] like Figure 6 As shown, the bottom of the first filling hole 240 is located in the substrate 100, that is, the upper hole wall of the first filling hole 240 is the dielectric layer 200, the lower hole wall of the first filling hole 240 is the substrate 100, and the word line 110 is exposed in the first filling hole 240 to facilitate the subsequent formation of the first conductive wire 400 electrically connected to the word line 110.
[0064] The dielectric layer 200 may be a laminated structure, such as Figure 6 As shown, the dielectric layer 200 includes a first protective layer 210, an intermediate layer 220 and a second protective layer 230. The first protective layer 210 is arranged on the substrate 100. The material of the first protective layer 210 and the second protective layer 230 includes silicon nitride (Si3N4), and the material of the intermediate layer 220 includes silicon oxide.
[0065] In a possible example, a first protective layer 210, an intermediate layer 220, and a second protective layer 230 are sequentially deposited on a substrate 100; a portion of the first protective layer 210, a portion of the intermediate layer 220, and a portion of the second protective layer 230 are removed by etching to form an etched hole, wherein the etched hole exposes the substrate 100; the substrate 100 is etched along the etched hole to form an etched groove in the substrate 100, wherein the etched groove exposes the word line 110, and the etched hole and the etched groove form a first filling hole 240.
[0066] In the horizontal direction, the size of the first filling hole 240 is larger than the size of the word line 110, so as to form the barrier layer 300 and the first conductive line 400. That is, the plane perpendicular to the word line 110 is taken as the cross section. Figure 6 In the horizontal direction (X direction) shown in FIG. 1 , the cross-sectional width of the first filling hole 240 is greater than the cross-sectional width of the word line 110. Figure 6 In the horizontal direction shown, the hole wall of the first filling hole 240 and the edge of the word line 110 have a distance difference of 1-3 nm.
[0067] It is understandable that after forming the first filling hole 240, an oxide will be formed on the surface of the exposed word line 110, and the oxide is the first residue 120 on the word line 110. The first residue 120 is exposed in the first filling hole 240 and needs to be removed later to reduce the influence of the first residue 120 on the contact resistance between the word line 110 and the first conductive line 400.
[0068] Step S103, forming a barrier layer on the wall of the first filling hole, the barrier layer in the first filling hole surrounds a first middle hole, and the first middle hole exposes the word line.
[0069] Reference Figure 7 and Figure 8 The barrier layer 300 is formed on the wall of the first filling hole 240 to protect the wall of the first filling hole 240 and prevent the wall of the first filling hole 240 from being damaged during subsequent etching. The barrier layer 300 located in the first filling hole 240 surrounds the first middle hole 310, and the barrier layer 300 can be a titanium nitride (TiN) layer.
[0070] In a possible example, forming a barrier layer on the wall of the first filling hole, the barrier layer in the first filling hole is surrounded by a first middle hole, and the first middle hole exposes the word line, which may include the following steps:
[0071] A barrier layer is formed on the hole wall and the hole bottom of the first filling hole and the dielectric layer, and the barrier layer in the first filling hole surrounds the first middle hole.
[0072] like Figure 7 As shown, a barrier layer 300 is deposited on the hole wall and the bottom of the first filling hole 240 and the dielectric layer 200. Exemplarily, the barrier layer 300 is formed by an atomic layer deposition (ALD) process to obtain a barrier layer 300 with good density. Of course, the barrier layer 300 can also be formed by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.
[0073] After forming a barrier layer on the hole wall and the hole bottom of the first filling hole and on the dielectric layer, the barrier layer on the dielectric layer and at the hole bottom of the first middle hole is removed.
[0074] Reference Figure 8 , the barrier layer 300 on the dielectric layer 200 and at the bottom of the first middle hole 310 is removed by directional etching to expose the dielectric layer 200 and the word line 110. It can be understood that along Figure 8 The vertical direction (Y direction) shown in the figure is used to etch away part of the barrier layer 300 to reduce Figure 8 The etching in the horizontal direction (X direction) shown, that is, the lateral etching is reduced, and less etching is done on the barrier layer 300 on the hole wall of the first filling hole 240. Exemplarily, by controlling the plasma directionality, the barrier layer 300 is etched in a desired direction.
[0075] like Figure 8 As shown, after removing the barrier layer 300 on the dielectric layer 200 and at the bottom of the first middle hole 310, the word line 110 is exposed in the first middle hole 310, and the surface of the exposed word line 110 has the first residue 120, that is, the first residue 120 on the word line 110 is also exposed in the first middle hole 310. The first residue 120 may be an oxide formed after the word line 110 is oxidized.
[0076] Step S104 , etching the word line exposed in the first middle hole to remove the first residue on the word line.
[0077] Reference Fig. 9 The word line 110 and the first residue 120 on the word line 110 are exposed in the first middle hole 310, and the exposed word line 110 is etched to remove the first residue 120 on the word line 110. Fig. 9 As shown, at least a portion of the first residue 120 on the surface of the word line 110 is removed, that is, less or even no first residue 120 remains.
[0078] In an embodiment of the present invention, the word line exposed in the first middle hole is etched to remove the first residue on the word line, which may include: removing the first residue on the word line by plasma etching to generate a first reactant; and then removing the first reactant by wet etching.
[0079] Exemplarily, the material of the word line 110 is tungsten (W), the first residue 120 is tungsten oxide (WO3), the first reactant is tungsten, and the first etching gas used in plasma etching is a mixture of hydrogen (H2) and argon (Ar). The reaction formula for plasma etching the first residue 120 is:
[0080] WO3+3H2→W+3H2O↑;
[0081] When the first residue 120 is etched by the first etching gas, the first residue 120 undergoes a reduction reaction to generate tungsten, which is then removed by wet etching, thereby removing the first residue 120 on the word line 110 to form a smoother word line 110 surface.
[0082] It is understood that, in the process of removing the first residue 120 on the word line 110, the barrier layer 300 is less removed, and the hole wall of the first filling hole 240 can be protected, so that the first residue 120 can fully react, improve the removal effect of the first residue 120, and the first residue 120 is less or no residue. For example, the first residue 120 and the barrier layer 300 can have a large etching rate selection ratio, so that in the process of etching the first residue 120, the barrier layer 300 is less etched.
[0083] Step S105 , forming a first conductive line in the first middle hole, wherein the first conductive line is electrically connected to the word line.
[0084] Reference Fig.10 and Fig.11 , the first wire 400 is filled in the first middle hole 310, and the first wire 400 is located above the word line 110 and contacts the word line 110, so that the first wire 400 is electrically connected to the word line 110. Exemplarily, a conductive material is deposited in the first middle hole 310 to form the first wire 400, and the material of the first wire 400 includes tungsten.
[0085] like Fig.10 and Fig.11 As shown, there is less or even no first residue 120 between the first conductive wire 400 and the word line 110, the contact resistance between the first conductive wire 400 and the word line 110 is small, the charge transfer between the first conductive wire 400 and the word line 110 is good, and the storage speed and storage efficiency of the memory are high. In addition, the barrier layer 300 is etched less, on the one hand, it protects the hole wall of the first filling hole 240 from being etched, and the hole wall of the first filling hole 240 is straighter; on the other hand, it also reduces the bowing degree of the first filling hole 240 and the first middle hole 310. When the first conductive wire 400 is filled in the first middle hole 310, it is not easy to have a gap inside the first conductive wire 400, which reduces the resistance value of the first conductive wire 400, improves the ability of the first conductive wire 400 to transfer charge, and further improves the performance of the memory.
[0086] The manufacturing method of the memory provided by the embodiment of the present invention includes: providing a substrate 100, wherein a word line 110 is arranged in a core area of the substrate 100; forming a dielectric layer 200 on the substrate 100, etching the dielectric layer 200, and forming a first filling hole 240 exposing the word line 110; forming a barrier layer 300 on the hole wall of the first filling hole 240, wherein the barrier layer 300 located in the first filling hole 240 is arranged to form a first middle hole 310, and the first middle hole 310 exposes the word line 110; etching the word line 110 exposed in the first middle hole 310 to remove the first residue 120 on the word line 110; forming a first conductive wire 400 in the first middle hole 310, and the first conductive wire 400 is electrically connected to the word line 110. By forming the barrier layer 300 on the hole wall of the first filling hole 240, when the first residue 120 on the word line 110 is subsequently removed, the barrier layer 300 protects the hole wall of the first filling hole 240, so that the first residue 120 can be fully removed, the content of the first residue 120 is reduced, and the resistance between the first conductive line 400 and the word line 110 is reduced, thereby improving the performance of the memory. In addition, the barrier layer 300 can also reduce or even avoid the bending of the hole wall of the first filling hole 240, so that the internal gap 600 of the first conductive line 400 formed subsequently is less, thereby improving the ability of the first conductive line 400 to transmit charges, and further improving the storage speed and storage efficiency of the memory.
[0087] Refer to Figures 6 to 11 The substrate 100 in the embodiment of the present invention further includes a peripheral region, and a second filling hole 250 is formed in the dielectric layer 200 located in the peripheral region. The second filling hole 250 extends to the substrate 100 to expose a portion of the substrate 100 .
[0088] like Figure 6 As shown, the dielectric layer 200 located above the core area is provided with a first filling hole 240, which penetrates the dielectric layer 200 and extends to the word line 110; the dielectric layer 200 located above the peripheral area is provided with a second filling hole 250, which penetrates the dielectric layer 200, and the substrate 100 is exposed in the second filling hole 250.
[0089] The first filling hole 240 and the second filling hole 250 can be formed in the same etching process. Exemplarily, a dielectric layer 200 is deposited on the substrate 100; a portion of the dielectric layer 200 is etched and removed to form an etched hole located above the core region and a second filling hole 250 located above the peripheral region, wherein the substrate 100 is exposed in the etched hole and the second filling hole 250; the substrate 100 is etched along the etched hole to form an etched groove, wherein the word line 110 is exposed in the etched groove, and the etched hole and the etched groove form the first filling hole 240.
[0090] It is understandable that after forming the second filling hole 250, an oxide will be formed on the exposed surface of the substrate 100, and the oxide is the second residue 130 on the substrate 100. The second residue 130 is exposed in the second filling hole 250 and needs to be removed later to reduce the influence of the second residue 130 on the resistance between the substrate 100 and the second conductive line 500.
[0091] It is understood that the size of the first filling hole 240 may be the same as or different from the size of the second filling hole 250. The size of the first filling hole 240 refers to the aperture of the first filling hole 240, and the size of the second filling hole 250 refers to the aperture of the second filling hole 250. Figure 6 Dimensions along the X direction are shown.
[0092] It should be noted that after the steps of forming a dielectric layer on the substrate, etching the dielectric layer, and forming a first filling hole exposing the word line, the memory manufacturing method also includes: forming a blocking layer on the wall of the second filling hole, the blocking layer located in the second filling hole is arranged to form a second middle hole, and the second middle hole exposes the substrate.
[0093] Reference Figure 7 and Figure 8 The barrier layer 300 is formed on the wall of the second filling hole 250 to protect the wall of the second filling hole 250 and prevent the wall of the second filling hole 250 from being damaged during subsequent etching. The barrier layer 300 located in the second filling hole 250 is set as a second middle hole 320, and the barrier layer 300 can be a titanium nitride layer. The step of forming the barrier layer 300 on the wall of the second filling hole 250 can refer to the step of forming the barrier layer 300 on the wall of the first filling hole 240, and will not be repeated here.
[0094] In one possible example, a barrier layer 300 is formed on the wall of the first filling hole 240 and the wall of the second filling hole 250 at the same time, specifically including the following processes: forming a barrier layer on the wall and bottom of the first filling hole, the wall and bottom of the second filling hole, and the dielectric layer; removing the barrier layer located on the dielectric layer, at the bottom of the first middle hole, and at the bottom of the second middle hole.
[0095] like Figure 7 As shown, a barrier layer 300 is deposited on the wall and bottom of the first filling hole 240, the wall and bottom of the second filling hole 250, and the dielectric layer 200. The barrier layer 300 located in the first filling hole 240 forms a first middle hole 310, and the barrier layer 300 located in the second filling hole 250 forms a second middle hole 320.
[0096] like Figure 8As shown, the barrier layer 300 located on the dielectric layer 200, at the bottom of the first middle hole 310 and at the bottom of the second middle hole 320 is etched, and after removing part of the barrier layer 300, the surface of the dielectric layer 200 away from the substrate 100, the word line 110, the first residue 120 on the word line 110, part of the substrate 100 and the second residue 130 on the substrate 100 are exposed. Exemplarily, the barrier layer 300 is etched along a desired direction by controlling the plasma directionality.
[0097] It should be noted that, after the step of forming a barrier layer on the wall of the second filling hole, the barrier layer in the second filling hole is arranged to form a second middle hole, and the second middle hole exposes the substrate, the method for manufacturing the memory in the embodiment of the present invention also includes: etching the substrate exposed in the second middle hole to remove the second residue on the substrate; forming a second wire in the second middle hole, and the second wire is electrically connected to the substrate.
[0098] The step of etching the substrate exposed in the second middle hole to remove the second residue on the substrate includes: removing the second residue on the substrate by plasma etching to generate a second reactant; and removing the second reactant by wet etching.
[0099] Exemplarily, the material of the substrate 100 is silicon, the second residue 130 is silicon oxide, the second etching gas used in the plasma etching is a mixture of ozone (O3) and dilute hydrofluoric acid (DHF), and the reaction formula for plasma etching the second residue 130 is:
[0100] SiO2+xHF+O3→SiF x +5H2O↑;
[0101] After the second residue 130 is etched by the second etching gas, the first residue 120 generates a second reactant, which is then removed by wet etching, thereby removing the second residue 130 on the substrate 100 to form a smoother surface of the substrate 100 .
[0102] It can be understood that during the process of removing the second residue 130 on the substrate 100, the barrier layer 300 is less removed, and the hole wall of the second filling hole 250 can be protected to allow the second residue 130 to fully react, thereby improving the removal effect of the second residue 130, and less or no second residue 130 remains.
[0103] It should be noted that the first reactant and the second reactant can be removed in the same wet etching process, that is, the first reactant is removed by wet etching while the second reactant is removed by wet etching. For example, the etching solution during wet etching can be a solution prepared by mixing water and hydrofluoric acid in a ratio of 200:1.
[0104] In one possible example, refer to Fig. 9 and Fig.12 The substrate 100 exposed in the second middle hole 320 may be etched to remove the second residue 130 on the substrate 100. Fig.12 Then the word line 110 exposed in the first middle hole 310 is etched to remove the first residue 120 on the word line 110, such as Fig. 9 shown.
[0105] In this configuration, during the process of removing the first residue 120 using a mixture of hydrogen and argon, the semiconductor structure is located in the hydrogen and argon, that is, the hydrogen and argon fill the second middle hole 320 to protect the substrate 100 and prevent the substrate 100 from being oxidized again.
[0106] While the second wire 500 is formed in the second middle hole 320, the first wire 400 is formed in the first middle hole 310, that is, the first wire 400 and the second wire 500 are formed simultaneously. Exemplarily, conductive materials are deposited in the first middle hole 310 and the second middle hole 320 to form the first wire 400 in the first middle hole 310 and the second wire 500 in the second middle hole 320.
[0107] Reference Fig.10 and Fig.11 , the first wire 400 is electrically connected to the word line 110, and the second wire 500 is electrically connected to the substrate 100. The first wire 400 and the second wire 500 may also be electrically connected. Fig.10 As shown, a conductive material is deposited in the first middle hole 310 , in the second middle hole 320 and on the dielectric layer 200 to form a second conductive layer 700 .
[0108] It can be understood that the second conductive layer 700 covers the upper surface of the dielectric layer 200, the second conductive layer 700 located in the first middle hole 310 is the first conductive wire 400, and the second conductive layer 700 located in the second middle hole 320 is the second conductive wire 500, and the first conductive wire 400 and the second conductive wire 500 are electrically connected by the second conductive layer 700 located on the dielectric layer 200.
[0109] In one possible example, refer to Fig.13 Before the step of forming a second conductive line in the second middle hole and electrically connecting the second conductive line to the substrate, the memory manufacturing method further includes: forming a metal composite in the second middle hole. Fig.13 As shown, a metal composite 800 is formed at the bottom of the second intermediate hole 320 . Exemplarily, a silicon-cobalt composite (CoSix) is formed at the bottom of the second intermediate hole 320 by high-temperature compounding.
[0110] Embodiment 2
[0111] Reference Fig.10 and Fig.11 The embodiment of the present invention further provides a memory, which includes: a substrate 100, a dielectric layer 200 disposed on the substrate 100, and a first conductive line 400 and a second conductive line 500 disposed in the dielectric layer 200.
[0112] The substrate 100 includes a core region and a peripheral region, and the core region and the peripheral region are adjacent to each other. Fig.10 At A shown, the peripheral area is located Fig.10 B is shown. A capacitor is subsequently formed on the core area of the substrate 100 , and a peripheral circuit is subsequently formed on the peripheral area of the substrate 100 .
[0113] The word line 110 is disposed in the core region of the substrate 100, that is, the word line 110 may be a buried word line. Fig.10 The word line 110 includes a first conductive layer and an anti-diffusion layer disposed on the sidewall and bottom wall of the first conductive layer. Exemplarily, the material of the first conductive layer is tungsten, and the material of the anti-diffusion layer is titanium nitride. A plurality of word lines 110 may be provided, and the plurality of word lines 110 are spaced apart. For example, an isolation structure 140 is disposed between the word lines 110 to electrically isolate each word line 110.
[0114] The dielectric layer 200 is disposed on the substrate 100. A first filling hole 240 and a second filling hole 250 penetrating the dielectric layer 200 are disposed in the dielectric layer 200. The first filling hole 240 is located on the core region and extends to the word line 110, and the second filling hole 250 is located on the peripheral region and extends to the substrate 100. It can be understood that the first filling hole 240 exposes the word line 110, and the second filling hole 250 exposes the substrate 100.
[0115] The size of the first filling hole 240 may be the same as or different from the size of the second filling hole 250 , wherein the size of the first filling hole 240 refers to the aperture of the first filling hole 240 , and the size of the second filling hole 250 refers to the aperture of the second filling hole 250 .
[0116] The first filling hole 240 and the second filling hole 250 are provided with a barrier layer 300, and the barrier layer 300 may be made of silicon nitride. The barrier layer 300 in the first filling hole 240 is arranged to form a first middle hole 310, and the first middle hole 310 exposes the word line 110; the barrier layer 300 in the second filling hole 250 is arranged to form a second middle hole 320, and the second middle hole 320 exposes the substrate 100.
[0117] The first conductive wire 400 is filled in the first middle hole 310 and electrically connected to the word line 110, and the second conductive wire 500 is filled in the second middle hole 320 and electrically connected to the substrate 100. The first conductive wire 400 and the second conductive wire 500 may be made of tungsten, cobalt, or the like.
[0118] In a possible example, a second conductive layer 700 is disposed in the first middle hole 310, in the second middle hole 320, and on the dielectric layer 200. Fig.10 As shown, the second conductive layer 700 covers the dielectric layer 200, and the second conductive layer 700 is flush with the surface facing away from the substrate 100. The second conductive layer 700 located in the first middle hole 310 is the first conductive wire 400, and the second conductive layer 700 located in the second middle hole 320 is the second conductive wire 500. The first conductive wire 400 and the second conductive wire 500 are electrically connected by the second conductive layer 700 located on the dielectric layer 200.
[0119] The memory provided by the embodiment of the present invention includes: a substrate 100, and a dielectric layer 200 disposed on the substrate 100, wherein the substrate 100 includes a core region and a peripheral region, and a word line 110 is disposed in the core region. The dielectric layer 200 is provided with a first filling hole 240 and a second filling hole 250 penetrating the dielectric layer 200, wherein the first filling hole 240 is located on the core region and extends to the word line 110, so that the word line 110 is exposed in the first filling hole 240, and the second filling hole 250 is located on the peripheral region and extends to the substrate 100, so that the substrate 100 is exposed in the second filling hole 250. The hole wall of the first filling hole 240 and the hole wall of the second filling hole 250 are provided with a barrier layer 300. The barrier layer 300 located in the first filling hole 240 is arranged to form a first middle hole 310. The first middle hole 310 is filled with a first conductive wire 400. The first conductive wire 400 is electrically connected to the word line 110. The barrier layer 300 located in the second filling hole 250 is arranged to form a second middle hole 320. The second middle hole 320 is filled with a second conductive wire 500. The second conductive wire 500 is electrically connected to the substrate 100. By setting the barrier layer 300 on the hole wall of the first filling hole 240 and the hole wall of the second filling hole 250, the barrier layer 300 protects the hole wall of the first filling hole 240 and the hole wall of the second filling hole 250, and when cleaning the word line 110 in the first middle hole 310 and the substrate 100 in the second middle hole 320, the reaction can be fully carried out to make the surface of the word line 110 in the first middle hole 310 and the substrate 100 in the second middle hole 320 smooth and free of foreign matter, thereby reducing the resistance between the first wire 400 and the word line 110, and between the second wire 500 and the substrate 100, and improving the storage speed and storage efficiency of the memory. In addition, the barrier layer 300 can also reduce or even avoid the bending of the hole wall of the first filling hole 240 and the hole wall of the second filling hole 250, and the internal gap 600 of the first wire 400 and the second wire 500 formed subsequently is small, thereby improving the ability of the first wire 400 and the second wire 500 to transmit charge, and further improving the storage speed and storage efficiency of the memory.
[0120] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.
[0121] In the description of this specification, the description of reference terms such as "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0122] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a memory, characterized in that: include: Providing a substrate, wherein a word line is arranged in a core region of the substrate; forming a dielectric layer on the substrate, and etching the dielectric layer to form a first filling hole exposing the word line; forming a barrier layer on the wall of the first filling hole, wherein the barrier layer in the first filling hole is arranged to form a first middle hole, and the first middle hole exposes the word line; Performing an etching process on the word line exposed in the first middle hole to remove a first residue on the word line; A first conductive line is formed in the first middle hole, and the first conductive line is electrically connected to the word line.
2. The method for manufacturing a memory according to claim 1, characterized in that: The step of forming a barrier layer on the wall of the first filling hole, the barrier layer in the first filling hole is arranged to form a first middle hole, and exposing the word line through the first middle hole comprises: The barrier layer is formed on the hole wall and the hole bottom of the first filling hole and the dielectric layer, and the barrier layer located in the first filling hole surrounds the first middle hole; The barrier layer on the dielectric layer and at the bottom of the first intermediate hole is removed.
3. The method for manufacturing a memory according to claim 1, characterized in that: The step of etching the word line exposed in the first middle hole to remove the first residue on the word line comprises: Plasma etching removes the first residue on the word line to generate a first reactant; The first reactant is removed by wet etching.
4. The method for manufacturing a memory according to claim 3, characterized in that: The first etching gas used in plasma etching is a mixture of hydrogen and argon; The word line is made of tungsten, the first residue is tungsten oxide, and the first reactant is tungsten.
5. The method for manufacturing a memory according to claim 1, characterized in that: In the horizontal direction, a size of the first filling hole is larger than a size of the word line, and a hole wall of the first filling hole and an edge of the word line have a distance difference of 1-3 nm.
6. The method for manufacturing a memory according to any one of claims 1 to 5, characterized in that: The substrate also includes a peripheral region, and a second filling hole is formed in the dielectric layer on the peripheral region, wherein the second filling hole exposes the substrate.
7. The method for manufacturing a memory according to claim 6, characterized in that: After forming a dielectric layer on the substrate, etching the dielectric layer, and forming a first filling hole exposing the word line, the method for manufacturing the memory further includes: A barrier layer is formed on the wall of the second filling hole, and the barrier layer in the second filling hole is arranged to form a second middle hole, and the second middle hole exposes the substrate.
8. The method for manufacturing a memory according to claim 7, characterized in that: At the same time, the barrier layer is formed on the first filling hole wall and the second filling hole wall.
9. The method for manufacturing a memory according to claim 8, characterized in that: The step of simultaneously forming the barrier layer on the first filling hole wall and the second filling hole wall comprises: forming the barrier layer on the hole wall and hole bottom of the first filling hole, the hole wall and hole bottom of the second filling hole, and the dielectric layer; The blocking layer located on the dielectric layer, at the bottom of the first middle hole, and at the bottom of the second middle hole is removed.
10. The method for manufacturing a memory according to claim 7, characterized in that: After the step of forming a barrier layer on the wall of the second filling hole, the barrier layer in the second filling hole enclosing a second middle hole, and the second middle hole exposing the substrate, the method for manufacturing the memory further includes: performing an etching process on the substrate exposed in the second middle hole to remove second residues on the substrate; A second conductive line is formed in the second middle hole, and the second conductive line is electrically connected to the substrate.
11. The method for manufacturing a memory according to claim 10, characterized in that: The step of etching the substrate exposed in the second middle hole to remove the second residue on the substrate comprises: Plasma etching removes the second residue on the substrate to generate a second reactant; The second reactant is removed by wet etching.
12. The method for manufacturing a memory according to claim 11, characterized in that: The second etching gas used in plasma etching is a mixture of ozone and dilute hydrofluoric acid; The substrate is made of silicon, and the second residue is silicon oxide.
13. The method for manufacturing a memory according to claim 10, characterized in that: A first conductive line is formed in the first middle hole while a second conductive line is formed in the second middle hole.
14. The method for manufacturing a memory according to claim 10, characterized in that: Before the step of forming a second conductive line in the second middle hole and electrically connecting the second conductive line to the substrate, the method for manufacturing the memory further includes: A metal composite is formed in the second intermediate pore.
15. A memory, characterized in that: include: A substrate, the substrate comprising a core region and a peripheral region, wherein a word line is arranged in the core region; a dielectric layer, the dielectric layer being disposed on the substrate, the dielectric layer being provided with a first filling hole and a second filling hole penetrating the dielectric layer, the first filling hole being located on the core region and extending to the word line, the second filling hole being located on the peripheral region and extending to the substrate; a barrier layer, the barrier layer being arranged on the first filling hole wall and the second filling hole wall, the barrier layer in the first filling hole being arranged to form a first middle hole, the first middle hole exposing the word line, the barrier layer in the second filling hole being arranged to form a second middle hole, the second middle hole exposing the substrate; a first conductive line filled in the first middle hole and electrically connected to the word line; A second conductive wire is filled in the second middle hole and is electrically connected to the substrate.
Citation Information
Patent Citations
Semiconductor memory device
US20220122984A1