A control circuit for SNSPD with wide dynamic response range

Abstract

The present invention provides a control circuit for a wide dynamic response range of an SNSPD, and belongs to the field of signal acquisition technology. The control circuit includes a Bias-Tee module, a signal preprocessing circuit, and a main control module. The input end of the Bias-Tee module is used to connect to the output end of the SNSPD, the power end of the Bias-Tee module is connected to the main control module, the output end of the Bias-Tee module is connected to the input end of the signal preprocessing circuit, the output end of the signal preprocessing circuit is connected to the input end of the main control module, and the Bias-Tee module realizes the adjustment of the dynamic response of the SNSPD under the control of the main control module. The control circuit has a fast response and can effectively enhance the dynamic response range of the SNSPD.

Description

Technical Field

[0001] The invention belongs to the technical field of signal acquisition, and in particular relates to a control circuit of a SNSPD with a wide dynamic response range. Background Art

[0002] Superconducting nanowire single photon detector (SNSPD) is a new type of single photon detector that can achieve a system detection efficiency of more than 90%. The SNSPD needs to set an operating current Ib. Under high bias current, the device has high detection efficiency but a small dynamic range. Reducing the operating current of the SNSPD can increase its light response dynamic range, but reduce the detection efficiency.

[0003] In some application scenarios, the incident light will suddenly increase and exceed the dynamic response range of the SNSPD, after which the SNSPD will enter a long-term latched state (latch) and will no longer be able to respond to light. The manual restart time is long, and in the latched state, the optical signal is completely lost and cannot be detected. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a control circuit with a wide dynamic response range of an SNSPD, so as to enhance the dynamic response range of the SNSPD.

[0005] The objective of the present invention can be achieved through the following technical scheme: a control circuit for a wide dynamic response range of an SNSPD, comprising a Bias-Tee module, a signal preprocessing circuit and a main control module, wherein the input end of the Bias-Tee module is used to be connected to the output end of the SNSPD, the power end of the Bias-Tee module is connected to the main control module, the output end of the Bias-Tee module is connected to the input end of the signal preprocessing circuit, the output end of the signal preprocessing circuit is connected to the input end of the main control module, and the Bias-Tee module realizes the regulation of the dynamic response of the SNSPD under the control of the main control module.

[0006] The main control module of the present invention collects the signal output by the SNSPD, counts the number of signals through its internal timing counter, and presets a threshold value in the main control module. When the counter count value exceeds the threshold value per unit time, the main control module controls the DAC to reduce the set bias voltage to a certain value, thereby realizing a large dynamic range SNSPD.

[0007] Preferably, the main control module includes a trigger, a buffer, a follower and a main control chip, the trigger input is connected to the output of the signal preprocessing circuit, the buffer input is connected to the trigger output, the buffer output is connected to the main control chip signal input, and the follower is connected between the main control chip and the Bias-Tee module. The trigger is used to correct the TTL high-level pulse width to ensure that the main control chip can recognize the count; the buffer is used to divide the input TTL waveform into two paths, which are respectively connected to the main control chip and an external counter or oscilloscope; the follower is used to ensure the stability of the bias voltage.

[0008] Preferably, the main control chip includes a counter and at least one DAC, the counter is connected to the signal preprocessing circuit module, and the DAC is connected to the power supply end of the Bias-Tee module.

[0009] Preferably, the main control chip is FPGA or CPU.

[0010] Preferably, the follower includes a first operational amplifier and a second operational amplifier, the input end of the first operational amplifier is connected to the DAC of the main control chip, and the output end of the first operational amplifier is connected to the ADC1 pin of the main control chip; the input end of the second operational amplifier is connected to the bias voltage of the Bias-Tee module, and the second operational amplifier is connected to the ADC2 pin of the main control chip. The follower ensures the stability of the bias voltage, and the main control chip monitors ADC1 and ADC2 in real time to ensure the accuracy of the bias voltage.

[0011] Preferably, the signal preprocessing circuit comprises an amplifier module and a comparator module connected in series, the input end of the amplifier module is connected to the output end of the Bias-Tee module, and the output end of the comparator module is connected to the input end of the main control module.

[0012] Preferably, the amplifier module comprises a first-stage amplifier and a second-stage amplifier connected in series, the first-stage amplifier input is connected to the Bias-Tee module output, and the second-stage amplifier output is connected to the comparator input.

[0013] Preferably, the parameters of the first-stage amplifier and the second-stage amplifier are: NF<1.5dB; Gain>50dB; bandwidth 1kHz-1GHz.

[0014] Preferably, a π-type attenuator is connected in series between the first-stage amplifier and the second-stage amplifier.

[0015] Compared with the prior art, the SNSPD wide dynamic response range control circuit has the following advantages: 1. It can greatly enhance the dynamic response range of the SNSPD, making its detection range wider; 2. The response time is short, reaching the ms level, and the detection efficiency is high; 3. It can prevent the SNSPD from entering a long-term latched state. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 4 is a circuit schematic diagram of a control circuit for a SNSPD with a wide dynamic response range according to an embodiment.

[0017] Figure 2 It is a circuit diagram of a regulation circuit for a SNSPD with a wide dynamic response range according to the second embodiment.

[0018] In the figure, 1, SNSPD; 2, Bias-Tee module; 3, amplifier module; 301, first-stage amplifier; 302, π-type attenuator; 303, second-stage amplifier; 4, comparator module; 5, main control module; 501, trigger; 502, buffer; 503, follower; 504, main control chip. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, but are not to be construed as limiting the present invention.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0021] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0022] like Figure 1As shown, the present invention provides a control circuit for a wide dynamic response range of SNSPD, including a Bias-Tee module 2, an amplifier module 3, a comparator module 4 and a main control module 5, wherein the amplifier module 3 and the comparator module 4 are connected in series to form a signal preprocessing circuit. The input end of the Bias-Tee module 2 is used to connect to the output end of the SNSPD1, the power end of the Bias-Tee module 2 is connected to the main control module 5, the output end of the Bias-Tee module 2 is connected to the input end of the amplifier module 3, and the output end of the comparator module 4 is connected to the input end of the main control module 5. The Bias-Tee module 2 gives a bias current to the detector in the SNSPD1 system. When a photon hits the detector, a resistor is formed, thereby generating a pulse signal of a certain voltage. The pulse signal sent by the Bias-Tee module 2 is amplified by the amplifier module 3, and the comparator outputs a signal lower than the set trigger level VDAC_REF as 0V, and an output higher than the trigger level VDAC_REF as 5V. The main control module 5 counts according to the received level signal. When the count value exceeds the preset threshold per unit time, the set bias voltage is reduced by controlling the DAC therein and provided to the Bias-Tee module 2, thereby quickly adjusting the dynamic response range of SNSPD1 and realizing a large dynamic range SNSPD1.

[0023] Combination Figure 2Specifically, in this embodiment, the main control module 5 includes a trigger 501, a buffer 502, a follower 503 and a main control chip 504. The main control chip 504 adopts a CPU chip of model STM32F307VET6, whose frequency is >100MHz, and has at least one 12-bit DAC, a multiplexed timing counter, etc. The trigger 501 is composed of a SN74LVC1G74 chip and its peripheral circuits. The input end of the trigger 501 is connected to the output end of the comparator module 4. Its function is to correct the TTL high-level pulse width output by the comparator module 4 to be consistent, ensuring that the main control chip 504 can recognize the count. The pulse width is determined by the resistor R13 and the capacitor C15, and the calculation formula is: T=RC. Buffer 502 is composed of CDCLV1102PW chip and its peripheral circuit. The input end of buffer 502 is connected to the output end of trigger 501105. The function of buffer 502106 is to divide one 5V TTL waveform into two 2.5V TTL waveforms. After the TTL multiplexing, one is connected to SMA for access to an external counter or oscilloscope, and the other is connected to the main control chip 504. Follower 503 uses LMV358DR2G chip, which includes two operational amplifiers, operational amplifier A and operational amplifier B. The input end of operational amplifier A is connected to the DAC of the main control chip 504, and the output end of operational amplifier A is connected to the ADC1 pin of the main control chip 504; the input end of operational amplifier B is connected to the bias voltage of Bias-Tee module 2, and operational amplifier B is connected to the ADC2 pin of the main control chip 504. The function of follower 503 is to ensure the stability of the bias voltage. At the same time, the main control chip 504 monitors the ADC1 pin and the ADC2 pin in real time to ensure the accuracy of the bias voltage. It should be noted that, in other embodiments of the present invention, the main control chip 504 may also be implemented by using FPGA instead.

[0024] The amplifier module 3 includes a first-stage amplifier 301, a π-type attenuator 302, and a second-stage amplifier 303 connected in series. The input end of the first-stage amplifier 301 is connected to the output end of the Bias-Tee module 2, and the output end of the second-stage amplifier 303 is connected to the input end of the comparator. The parameters of the first-stage amplifier 301 and the second-stage amplifier 303 are: NF<1.5dB; Gain>50dB; bandwidth 1kHz-1GHz, and the pulse amplitude of the pulse signal after amplification by the amplifier is about 100mV. The signal output by the first-stage amplifier 301 is attenuated by the π-type attenuator 302, and impedance matching is performed at the same time to achieve load power regulation and signal reflection suppression, thereby improving signal quality.

[0025] The principle of the present invention is as follows: the main control module 5 presets the counting threshold, and when in use, the main control chip 504 recognizes the TTL signal at the output end of the comparator, and counts the number of signals through its internal timing counter. When the counter count value exceeds the threshold within a unit time, the DAC part inside the control chip outputs the voltage. The control of the main control chip is implemented using the following algorithm:

[0026] Ib(i+1)=Ib(i){1-Kp[logCR(i+1)-logCR(i)]}(i≥1)

[0027] Among them, Ib(i) is the Ib value of the i-th second, CR(i) is the count value of the i-th second, and Kp is the adjustment factor, which can be obtained through the relationship diagram between the count rate CR and Ib of different types of devices.

[0028] By giving an initial count CR(i) and Ib(i), when the received count rate fluctuates, the main control module 5 performs operational feedback control according to the above algorithm, so that Ib(i+1) changes accordingly, thereby controlling CR(i+1) to reach a steady state. In this way, the dynamic response range of SNSPD1 can be greatly enhanced while responding quickly.

[0029] The specific embodiments described herein are merely examples of the spirit of the present invention. Those skilled in the art may make various modifications or additions to the specific embodiments described or replace them in similar ways, but they will not deviate from the spirit of the present invention or exceed the scope defined by the appended claims.

Claims

1. A control circuit for a SNSPD with a wide dynamic response range, comprising a Bias-Tee module (2), a signal preprocessing circuit and a main control module (5), wherein the input end of the Bias-Tee module (2) is used to be connected to the output end of the SNSPD (1), the power end of the Bias-Tee module (2) is connected to the main control module (5), the output end of the Bias-Tee module (2) is connected to the input end of the signal preprocessing circuit, the output end of the signal preprocessing circuit is connected to the input end of the main control module (5), and the Bias-Tee module (2) realizes the regulation of the dynamic response of the SNSPD (1) under the control of the main control module (5); The main control module (5) comprises a trigger (501), a buffer (502), a follower (503) and a main control chip (504); the input end of the trigger (501) is connected to the output end of the signal preprocessing circuit, the input end of the buffer (502) is connected to the output end of the trigger (501), the output end of the buffer (502) is connected to the signal input end of the main control chip (504), and the follower (503) is connected between the main control chip (504) and the Bias-Tee module (2); The follower (503) comprises a first operational amplifier and a second operational amplifier, wherein the input end of the first operational amplifier is connected to the DAC of the main control chip (504), and the output end of the first operational amplifier is connected to the ADC1 pin of the main control chip (504); the input end of the second operational amplifier is connected to the bias voltage of the Bias-Tee module (2), and the second operational amplifier is connected to the ADC2 pin of the main control chip (504); The signal preprocessing circuit comprises an amplifier module (3) and a comparator module (4) connected in series, the input end of the amplifier module (3) is connected to the output end of the Bias-Tee module (2), and the output end of the comparator module (4) is connected to the input end of the main control module (5); The amplifier module (3) comprises a first-stage amplifier (301) and a second-stage amplifier (303) connected in series, the input end of the first-stage amplifier (301) is connected to the output end of the Bias-Tee module (2), and the output end of the second-stage amplifier (303) is connected to the input end of the comparator module (4).

2. The SNSPD wide dynamic response range control circuit according to claim 1, characterized in that: The main control chip (504) comprises a counter and at least one DAC, the counter is connected to the signal preprocessing circuit module, and the DAC is connected to the power supply end of the Bias-Tee module (2).

3. The SNSPD wide dynamic response range control circuit according to claim 2, characterized in that: The main control chip (504) is an FPGA or a CPU.

4. The SNSPD wide dynamic response range control circuit according to claim 1, characterized in that: The parameters of the first-stage amplifier (301) and the second-stage amplifier (303) are: NF<1.5dB; Gain>50dB; bandwidth 1kHz-1GHz.

5. The SNSPD wide dynamic response range control circuit according to claim 1, characterized in that: A π-type attenuator (302) is also connected in series between the first-stage amplifier (301) and the second-stage amplifier (303).

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