Switch clock circuit
By using high-precision programmable clock chip U1 and peripheral clock X1 in the switch clock circuit, multiple LVDS differential clocks are output and clock deviation are adjusted, which solves the problems of low accuracy and poor signal stability in traditional switch clock circuits in high-end switches, and high-precision and stable clock signals and high-speed transmission capabilities are achieved.
Patent Information
- Application Number
- CN202210654323.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-06-10
- Publication Date
- 2025-04-22
- Estimated Expiration
- 2042-06-10
AI Technical Summary
In high-end switch clock circuits in traditional switches have many reference clocks and low accuracy, resulting in poor signal stability and poor connection of each group.
A switch clock circuit including a high-precision programmable clock chip U1 and a peripheral clock vibration X1 is adopted. A clock source is provided to the clock chip U1 through a single and accurate peripheral clock vibration X1, multiple LVDS differential clocks are output, and the clock deviation is adjusted through a synchronous clock input unit.
It realizes a switch clock circuit with high clock accuracy and stable signal, reducing each clock error, saving circuit space, and ensuring the high-speed transmission capability of the backend, reaching a rate of nearly 25Gbps.
Smart Images
Figure CN115189794B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of clocks, and in particular to a switch clock circuit. Background Art
[0002] The digital system of the switch processes signals step by step according to the beat, and each part of the system also operates according to the beat. To make the various parts of the circuit operate in a unified beat, a "clock signal" is required. The circuit that generates this clock signal is the clock circuit.
[0003] Traditional switches originally use a separate clock source for each group of clocks. When applied to high-end switch product lines, because high-end switches have more network ports, more reference clocks will be used, resulting in low accuracy and poor connectivity between each group.
[0004] Therefore, it is necessary to provide a switch clock circuit to solve the above problems. Summary of the invention
[0005] The object of the present invention is to provide a switch clock circuit with high clock accuracy and stable signal to solve the above technical problems.
[0006] To achieve the above object, the present invention adopts the following technical solution:
[0007] A switch clock circuit comprises an integrated circuit chip unit, a clock input circuit unit connected to the integrated circuit chip unit, and a filtering and voltage-stabilizing circuit unit, wherein the integrated circuit chip unit comprises a chip, the clock input circuit unit is provided with a clock oscillator X1, and the clock oscillator X1 provides an active clock oscillator with a predetermined fluctuation frequency for the chip, the filtering and voltage-stabilizing circuit unit comprises an isolation element and a filtering component both connected to the chip, the chip U1 is connected to a coupling and direct-isolation circuit unit, and the coupling and direct-isolation circuit unit outputs a multi-channel LVDS differential clock circuit, and further comprises a synchronous clock input unit for adjusting the output clock deviation.
[0008] As a further improved technical solution of the present invention, pin 8 of the chip U1 is connected to pin 3 of the clock oscillator X1, and the clock input circuit unit also includes a resistor R13 and a resistor R14, and the resistor R13 and the resistor R14 are connected in series between pin 3 of the clock oscillator X1 and pin 8 of the chip U1.
[0009] As a further improved technical solution of the present invention, the clock input circuit unit also includes a magnetic bead L1, a capacitor C12, and a capacitor C13. The magnetic bead L1 is connected to pin 4 of the clock oscillator X1. One end of the capacitor C12 and the capacitor C13 after being connected in parallel is connected between the magnetic bead L1 and pin 4 of the clock oscillator X1, and the other end is grounded.
[0010] As a further improved technical solution of the present invention, the clock input circuit unit 20 also includes capacitor C10 and capacitor C14, one end of each capacitor C10 and capacitor C14 is connected between the resistor R14 and pin 8 of the chip U1, and the other end of the capacitor C14 is grounded.
[0011] As a further improved technical solution of the present invention, the isolation element includes magnetic beads L2, magnetic beads L9, and magnetic beads L11, and the magnetic beads L2, L9, and L11 are 95ohm-145ohm magnetic beads.
[0012] As a further improved technical solution of the present invention, the magnetic bead L2 is connected to pin 13 of the chip U1, and the magnetic bead L9 and the magnetic bead L11 are connected in parallel to pins 46 and 60 of the chip U1.
[0013] As a further improved technical solution of the present invention, the filtering component selects inductor filtering LC, including magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14, and the magnetic beads are high-impedance magnetic beads of 480ohm-720ohm.
[0014] As a further improved technical solution of the present invention, the chip U1 is a programmable clock chip of model Au5315.
[0015] As a further improved technical solution of the present invention, the switch clock circuit also includes a control unit connected to the integrated circuit chip unit, the control unit is a communication interface, the chip U1 is programmed through an internal peripheral I2C or SPI bus interface, and the control unit is configured or outputs different clocks through the I2C or SPI bus interface.
[0016] As a further improved technical solution of the present invention, the switch clock circuit further includes a peripheral configuration circuit unit connected to the integrated circuit chip unit.
[0017] Compared with the prior art, the beneficial effects of the present invention are:
[0018] 1. A high-precision and programmable clock chip U1 is used to drive the circuit of the back-end load. A single accurate peripheral clock X1 provides the clock source to the clock chip U1, which can output 8 different forms of differential clocks to the load end. The internal frequency multiplication is accurate. The clock wiring is not long, the generated signal is not easy to oscillate, and the product is stable.
[0019] 2. Share a peripheral clock oscillator X1 to multiply the frequency, without adding a clock oscillator to each channel. The error of each clock channel is small, saving circuit space;
[0020] 3. The differential clock circuit can be provided to the back-end CPU load for operation. The circuit signal has the characteristics of low voltage value, strong anti-interference, high precision, etc., which can ensure that the back-end has a transmission capacity of nearly 25Gbps. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a block diagram of a switch clock circuit of the present invention;
[0022] Figure 2 yes Figure 1 Circuit diagram of
[0023] Figure 3 yes Figure 2 The circuit diagram of the clock input circuit unit;
[0024] Figure 4 yes Figure 2 Circuit diagram of the filter and voltage stabilization circuit unit;
[0025] Figure 5 yes Figure 2 A circuit diagram of a peripheral configuration circuit unit;
[0026] Figure 6 yes Figure 2 A circuit diagram of a coupling isolation circuit unit;
[0027] Figure 7 yes Figure 2 Circuit diagram of the synchronous clock input unit. DETAILED DESCRIPTION
[0028] The exemplary embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. If there are several embodiments, the features of these embodiments can be combined with each other without conflict. When the description refers to the drawings, unless otherwise specified, the same numbers in different drawings represent the same or similar elements. The contents described in the following exemplary embodiments do not represent all embodiments consistent with the present invention; on the contrary, they are only examples of devices, products and / or methods consistent with some aspects of the present invention as recorded in the claims of the present invention.
[0029] The terms used in the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the scope of protection of the present invention. The singular forms "a", "said" or "the" used in the specification and claims of the present invention are also intended to include plural forms, unless the context clearly indicates other meanings.
[0030] It should be understood that the words used in the specification and claims of the present invention, such as "first", "second" and similar words, do not indicate any order, quantity or importance, but are only used to distinguish the names of features. Similarly, words such as "one" or "an" do not indicate a quantitative limitation, but indicate the existence of at least one. Unless otherwise specified, words such as "front", "rear", "upper", "lower" and similar words appearing in the present invention are only for the convenience of explanation and are not limited to a specific position or a spatial orientation. Words such as "include" or "comprise" are an open-ended expression, meaning that the elements appearing before "include" or "comprise" include the elements appearing after "include" or "comprise" and their equivalents, which does not exclude that the elements appearing before "include" or "comprise" may also include other elements. If "several" appears in the present invention, it means two or more.
[0031] See also Figures 1 to 7 The present invention discloses a switch clock circuit, including an integrated circuit chip unit 10, a clock input circuit unit 20 connected to the integrated circuit chip unit 10, and a control unit 50.
[0032] The integrated circuit chip unit 10 includes a chip U1 of model Au5315, which is a programmable clock chip that needs to be connected to a power supply before working. Specifically, pins 13, 46, and 60 of the chip U1 are control power input pins. When the input is 3.3V, the product can work simply and the external bus interface can work.
[0033] See also Figure 2 and Figure 4 , the 13th, 46th and 60th pins of the chip U1 are connected to the filter and voltage stabilizing circuit unit 30. The filter and voltage stabilizing circuit unit 30 is a power filter circuit, the power supply voltage is 3.3V, and an isolation component is used for isolation. Preferably, the isolation component includes magnetic beads L2, magnetic beads L9, and magnetic beads L11, and the magnetic beads L2, L9, and L11 are magnetic beads between 95ohm and 145ohm (about 20% tolerance). As a preferred method, the magnetic beads L2, L9, and L11 use magnetic beads with an impedance of 120ohm at a frequency of 100MHz to avoid noise introduction and effectively prevent high-frequency noise from crosstalking to the power supply end. The output clock circuit has high stability and will not cause packet loss or even disconnection problems when working at high speed.
[0034] The filter and voltage stabilization circuit unit 30 uses a filter component for filtering, such as Figure 4As shown, the filter component uses an inductor filter LC to improve the cleanliness of the power supply. This part of the inductor filter LC includes magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14. Specifically, magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14 are selected from high-resistance magnetic beads between 480ohm and 720ohm (about 20% tolerance). As a preferred embodiment, magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14 use magnetic beads with an impedance of 600ohm at a frequency of 100MHz to effectively prevent high-frequency noise from crosstalking to the power supply end.
[0035] Pins 7, 8, 9 and 10 of the chip U1 are external clock input pins, and pins 8 and 9 of the chip U1 are connected to the clock input circuit unit 20 .
[0036] See also Figure 2 and Figure 3 The clock input circuit unit 20 is provided with a clock oscillator X1, which provides a 48.0012MHz active clock oscillator for the chip U1 to ensure the accuracy of the clock. The chip U1 is programmed through the internal peripheral I2C (Inter-Integrated Circuit) or full-duplex synchronous serial SPI bus interface.
[0037] Specifically, Figure 3 As shown, pin 3 of the clock X1 is connected to pin 8 of the chip U1, and the clock input circuit unit 20 includes a resistor R13 and a resistor R14. The resistor R13 and the resistor R14 are connected in series between pin 3 of the clock X1 and pin 8 of the chip U1. The resistor R13 is connected to pin 3 of the clock X1, and the resistor R14 is connected to pin 8 of the chip U1.
[0038] Continue to see Figure 3 , the clock input circuit unit 20 also includes a magnetic bead L1, a capacitor C12, a capacitor C13, a capacitor C10, and a capacitor C14. Specifically, one end of the magnetic bead L1 is connected to the power supply, and the other end is connected to the 4th pin of the clock X1. After the capacitors C12 and C13 are connected in parallel, one end is connected between the magnetic bead L1 and the 4th pin of the clock X1, and the other end is grounded. Pin 1 of the clock X1 is connected to the resistor R16 included in the clock input circuit unit 20, and the other end of the resistor R16 is connected to the power supply. Pin 2 of the clock X1 is grounded. Preferably, the magnetic bead L1 is selected to be 120 ohms for isolation, and is given to the chip U1 as a reference clock after back-end filtering and capacitor coupling.
[0039] The clock oscillator X1 uses an active clock oscillator to ensure a frequency deviation of at least 20ppm, which can meet the requirements of a good frequency deviation response and provide an external reference clock for the chip U1 to meet the internal frequency division.
[0040] The capacitors C10 and C14 are connected between the resistor R14 and the 8th pin of the chip U1, and the other end of the capacitor C14 is grounded. The resistor R15 and the capacitor C17 included in the clock input circuit unit 20 are connected in series, one end of which is connected between the resistor R14 and the capacitor C10, and the other end is grounded.
[0041] The clock input circuit unit 20 is used to input a pure clock source to the chip U1 integrated circuit for operation. After inputting a stable and pure clock, the internal frequency division circuit is performed to achieve the output that meets the demand.
[0042] Pin 13 of chip U1 is connected to magnetic bead L2 of filter voltage stabilizing circuit unit 30, and the other end of magnetic bead L2 is connected to the power supply. Magnetic beads L9 and L11 of filter voltage stabilizing circuit unit 30 are connected in parallel to pins 46 and 60 of chip U1.
[0043] Pins 22, 57, 52, 49, 43, 40, 36, 33, 29, and 26 of chip U1 are the power pins for the internal clock circuit. Figure 4As shown, the filter voltage stabilizing circuit unit 30 includes a magnetic bead L3 and a capacitor C23 connected to the 26th pin of the chip U1, the other end of the capacitor C23 is grounded, and the other end of the magnetic bead L3 is connected to the power supply; the magnetic bead L4 and the capacitor C26 are connected to the 29th pin of the chip U1, the other end of the capacitor C26 is grounded, and the other end of the magnetic bead L4 is connected to the power supply; the magnetic bead L5 and the capacitor C27 are connected to the 33rd pin of the chip U1, the other end of the capacitor C27 is grounded, and the other end of the magnetic bead L5 is connected to the power supply; the magnetic bead L6 and the capacitor C28 are connected to the 36th pin of the chip U1, the other end of the capacitor C28 is grounded, and the other end of the magnetic bead L6 is connected to the power supply; the magnetic bead L7 and the capacitor C29 are connected to the 40th pin of the chip U1, the other end of the capacitor C29 is grounded, and the other end of the magnetic bead L7 is connected to the power supply The included magnetic beads L8 and capacitor C30 are connected to the 43rd pin of the chip U1, the other end of the capacitor C30 is grounded, and the other end of the magnetic beads L8 is connected to the power supply; the included magnetic beads L10 and capacitor C31 are connected to the 49th pin of the chip U1, the other end of the capacitor C31 is grounded, and the other end of the magnetic beads L10 is connected to the power supply; the included magnetic beads L12 and capacitor C32 are connected to the 52nd pin of the chip U1, the other end of the capacitor C32 is grounded, and the other end of the magnetic beads L12 is connected to the power supply; the included magnetic beads L13 and capacitor C33 are connected to the 57th pin of the chip U1, the other end of the capacitor C33 is grounded, and the other end of the magnetic beads L13 is connected to the power supply; the included magnetic beads L14 and capacitor C37 are connected to the 22nd pin of the chip U1, the other end of the capacitor C37 is grounded, and the other end of the magnetic beads L14 is connected to the power supply. Among them, the 65th pin of the chip U1 is grounded.
[0044] Continue to see Figure 4 The capacitors C24 and C25 included in the filter and voltage stabilization circuit unit 30 are connected in parallel, one end of which is connected between the magnetic bead L2 and the 13th pin of the chip U1, and the other end is grounded. The capacitors C34, C35, and C36 included in the filter and voltage stabilization circuit unit 30 are connected to the 46th and 60th pins of the chip U1 at one end, and the other end is grounded.
[0045] Pins 16, 17, 18, 19, and 39 of chip U1 are interface circuit pins. The interface circuits are SPI or I2C bus, which are used to connect to the front-end MCU. Specifically, the MCU is connected to the SPI or I2C bus and is given to chip U1 for burning. The main purpose of burning is to allow this editable clock circuit to output different frequency requirements to meet different product applications, including 156.25Mhz, 125Mhz, and 50MHz LVDS clock signals.
[0046] Pins 17, 19, and 39 of chip U1 are connected to peripheral configuration circuit unit 40. For details, see Figure 2 and Figure 5, the peripheral configuration circuit unit 40 is a configuration circuit, and the periphery can flexibly configure high and low levels. It includes four configuration circuits. The first configuration circuit is a peripheral circuit connected to the DPLL_IN_SEL0 pin and the DPLL_IN_SEL1 pin, which is set to 00, 01, 10, and 11 in binary, and the high and low levels are set by pull-up and pull-down to select the input clock synchronization channel. Among them, pull-up is to clamp the uncertain signal at a high level through a resistor, and the resistor also plays a current limiting role; pull-down is also to clamp the uncertain signal at a low level through a resistor. The second configuration circuit is the peripheral circuit connected to the DPLL_OEB pin, and the configuration instructions require whether the output is allowed or closed. The third configuration circuit is a peripheral circuit connected to the DPLL_LOLB pin, which is used to set whether to latch. The default is to latch, that is, it is a high level, and there is a pull-up inside the chip U1. The fourth configuration circuit is a peripheral circuit connected to the two pins DPLL_I2CADDR_A0 and DPLL_I2CADDR_A1, which are set to 00, 01, 10, and 11 according to binary. Usually, the front-end master communicates with the chip U1 of the integrated circuit through I2C. As a slave device, a corresponding address is required to contact. The two configuration pins DPLL_I2CADDR_A0 and DPLL_I2CADDR_A1 are used to configure the address of the integrated circuit.
[0047] Pins 3 and 4 of chip U1 are mainly configuration pins, which can be configured with different clock comparisons. Figure 5 As shown, the peripheral configuration circuit unit 40 includes a resistor R20, a resistor R21, a resistor R26, a resistor R27 and a resistor R28. Among them, one end of the resistor R20 is connected to the power supply, and the other end is connected to the 4th pin of the chip U1; one end of the resistor R21 is connected to the power supply, and the other end is connected to the 3rd pin of the chip U1; one end of the resistor R26 is connected to the 17th pin of the chip U1, and the other end is grounded; one end of the resistor R27 is connected to the 19th pin of the chip U1, and the other end is grounded; one end of the resistor R28 included in the peripheral configuration circuit unit 40 is connected to the power supply, and the other end is connected to the 39th pin of the chip U1.
[0048] Pin 6 of chip U1 is the reset pin of the programmable logic chip, which can be pulled down and held for 10ms to reset, so as to perform a simple reset when the output is incorrect under some special circumstances.
[0049] Continue to see Figure 5 The peripheral configuration circuit unit 40 also includes a resistor R22, a resistor R24, a resistor R25 and a capacitor C22. One end of the resistor R22 is connected to the power supply, and the other end is connected to the 6th pin of the chip U1. The capacitor C22 is arranged in series between the resistor R22 and the 6th pin of the chip U1. One end of the resistor R24 is connected to the 11th pin of the chip U1, and the other end is grounded. One end of the resistor R25 is connected to the power supply, and the other end is connected to the 12th pin of the chip U1.
[0050] See also Figure 2 The control unit 50 is a communication interface, which is used for communication between the CPU and the chip U1. It controls the output of different clocks through the I2C or SPI interface, and can be configured as well as output.
[0051] The control unit 50 includes a DPLL_I2C_SCL interface corresponding to pin 16 of the chip U1, a DPLL_I2C_ADDR_A1 interface corresponding to pin 17 of the chip U1, a DPLL_I2C_SDA interface corresponding to pin 18 of the chip U1, a DPLL_I2C_ADDR_A0 interface corresponding to pin 19 of the chip U1, and a DPLL_I2C_SEL interface corresponding to pin 39 of the chip U1.
[0052] The integrated circuit chip unit 10 is connected to a coupling isolation circuit unit, and outputs 10 LVDS differential clock circuits through the coupling isolation circuit unit. For details, see Figure 2 and Figure 6 The coupling blocking circuit unit includes a first coupling blocking circuit unit 60 and a second coupling blocking circuit unit 70. The first coupling blocking circuit unit 60 is connected to the first load end, and the second coupling blocking circuit unit 70 is connected to the second load end.
[0053] Continue to see Figure 6 , chip U1 outputs 10 LVDS differential clock circuits. The application circuit of this embodiment shares 6 156.25MHZ LVDS outputs, 1 125MHZ LVDS output, and 1 50MHZ LVDS output, outputting a total of 8 groups of clocks, which are given to the back-end switching chip. The switching chip needs to have high-speed transmission, which requires a stable clock as a reference, and the switching chip has more optical module ports, such as 1Gbps, 10Gbps, 25Gbps, 100Gbps, etc., which require a relatively stable clock as a reference to have a high transmission rate. By using capacitive coupling, the center voltage of the front and back ends will not be affected. It is simply used as an LVDS AC signal to meet the LVDS protocol oscillation amplitude requirements. If the back end needs to change the center voltage, pull-up and pull-down resistors can be used.
[0054] Chip U1 outputs 10 LVDS differential clock circuits, with a maximum output of 350MHz, which can meet the minimum LVDS swing and has a good effect on EMI. The differential clock circuit can be given to the back-end CPU load for work, and the circuit signal has the characteristics of low volt value, strong anti-interference, and high precision, which can ensure that the back-end can have a transmission rate of nearly 25Gbps.
[0055] Chip U1 provides 8 groups of clocks to the back-end load, each of which is related to each other, so as to achieve higher accuracy and form a closed-loop regulation.
[0056] like Figure 6 As shown, the first coupling isolation circuit unit 60 outputs a 156.25MHz LVDS differential clock to the CPU internal PHY operation. The first coupling isolation circuit unit 60 includes a capacitor C1 and a resistor R1 connected in parallel to the 59th pin of the chip U1; a capacitor C2 and a resistor R3 connected in parallel to the 58th pin of the chip U1; a capacitor C3 and a capacitor C4 connected to the 54th and 53th pins of the chip U1; a capacitor C5 and a capacitor C6 connected to the 51st and 50th pins of the chip U1; a capacitor C7 and a capacitor C8 connected to the 45th and 44th pins of the chip U1; a capacitor C9 and a capacitor C11 connected to the 42nd and 41st pins of the chip U1; a capacitor C15 and a capacitor C16 connected to the 38th and 37th pins of the chip U1; and a resistor R17 connected to the 35th pin of the chip U1.
[0057] Continue to see Figure 6 The second coupling isolation circuit unit 70 outputs 125M and 50M LVDS differential clocks for the PHY chip to work. The capacitors C18 and C19 included in the second coupling isolation circuit unit 70 are connected to the 28th and 27th pins of the chip U1; the capacitors C20 and C21 included in the second coupling isolation circuit unit 70 are connected to the 24th and 23rd pins of the chip U1.
[0058] See also Figure 2 and Figure 7 Pins 1, 2, 14, 15, 61, 62, 63 and 64 of chip U1 are connected to the synchronous clock input unit 80.
[0059] The synchronous clock input unit 80 synchronizes the closed loop of the integrated circuit output and is used to adjust the output clock deviation.
[0060] Specifically, the input of the synchronous clock input unit 80 is fed back to the chip U1 through the first load end and the second load end. The chip U1 receives the feedback signals from the first load end and the second load end, and adjusts the output clock based on this signal. The chip U1 can compare the signals output by the first load end and the second load end to make adjustments, so that the entire output can ensure good accuracy, meet many us-level application scenarios, and complete the closed loop.
[0061] See also Figure 7The synchronous clock input unit 80 includes a resistor R4, one end of which is connected to the 63rd pin of U1, and the other end is grounded; a resistor R7, one end of which is connected to the 64th pin of U1, and the other end is grounded; a resistor R8, one end of which is connected to the 1st pin of U1, and the other end is grounded; a resistor R9, one end of which is connected to the 2nd pin of U1, and the other end is grounded; a resistor R6, one end of which is connected to the 14th pin of U1, and the other end is grounded; a resistor R10, one end of which is connected to the 15th pin of U1, and the other end is grounded; a resistor R11, one end of which is connected to the 61st pin of U1, and the other end is grounded; a resistor R12, one end of which is connected to the 62nd pin of U1, and the other end is grounded; a resistor R2, one end of which is connected between the resistor R4 and the 63rd pin of the chip U1, and the other end is grounded; a resistor R5, one end of which is connected between the resistor R8 and the 1st pin of the chip U1, and the other end is grounded.
[0062] In summary, the circuit structure of the present invention mainly adopts a high-precision and programmable clock chip chip U1 to drive the circuit of the back-end load. The clock oscillator X1 of the clock input circuit unit 20 can provide a 48.0012MHz active clock oscillator to ensure the accuracy of the clock; the chip U1 is programmed through the internal peripheral I2C or SPI bus interface, and can output 10 LVDS differential circuits. The differential clock circuit can be given to the back-end CPU load for work. The circuit signal has the characteristics of low volt value, strong anti-interference, high precision, etc., which can ensure that the back-end has a transmission rate of nearly 25Gbps; in addition, the clock line is not long, the generated signal is not easy to oscillate, and the product is stable; through a single accurate peripheral clock oscillator X1 to provide a clock source to this clock chip U1, 8 different forms of differential clocks can be output to the load end, the internal precise frequency multiplication, sharing a peripheral clock oscillator to multiply the frequency, there is no need to add a clock oscillator to each channel, the error of each clock is small, and the circuit space is saved.
[0063] The above embodiments are only used to illustrate the present invention but not to limit the technical solutions described in the present invention. The understanding of this specification should be based on the technicians in the relevant technical field. For example, the directional descriptions such as "front", "back", "left", "right", "up", and "down" are described in detail in this specification with reference to the above embodiments. However, ordinary technicians in this field should understand that technicians in the relevant technical field can still modify or replace the present invention with equivalents, and all technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.
Claims
1. A switch clock circuit, characterized in that: The invention comprises an integrated circuit chip unit (10), a clock input circuit unit (20) and a filtering and voltage stabilizing circuit unit (30) connected to the integrated circuit chip unit (10), wherein the integrated circuit chip unit (10) comprises a chip (U1), the clock input circuit unit (20) is provided with a clock oscillator (X1), and the clock oscillator (X1) provides an active clock oscillator with a predetermined fluctuation frequency for the chip (U1), and the filtering and voltage stabilizing circuit unit (30) comprises an isolation element and a filtering component both connected to the chip (U1), and the chip (U1) is connected with a coupling isolation circuit. A circuit unit, wherein the coupling and direct-line blocking circuit unit outputs a multi-channel LVDS differential clock circuit, and further comprises a synchronous clock input unit (80) for adjusting the output clock deviation, wherein the chip (U1) is a programmable clock chip; the chip (U1) model is Au5315, and the coupling and direct-line blocking circuit unit comprises a first coupling and direct-line blocking circuit unit (60) and a second coupling and direct-line blocking circuit unit (70), wherein the first coupling and direct-line blocking circuit unit (60) is connected to a first load end, and the second coupling and direct-line blocking circuit unit (70) is connected to a second load end; The first coupling and direct-current isolation circuit unit (60) outputs 6 LVDS differential clocks for PHY operation inside the CPU; The second coupling isolation circuit unit (70) outputs two LVDS differential clocks for the PHY chip to operate.
2. The switch clock circuit according to claim 1, characterized in that: Pin 8 of the chip (U1) is connected to pin 3 of the clock oscillator (X1), and the clock input circuit unit (20) further comprises a resistor R13 and a resistor R14, wherein the resistor R13 and the resistor R14 are sequentially connected in series between pin 3 of the clock oscillator (X1) and pin 8 of the chip (U1).
3. The switch clock circuit according to claim 2, characterized in that: The clock input circuit unit (20) further comprises a magnetic bead L1, a capacitor C12 and a capacitor C13, wherein the magnetic bead L1 is connected to the 4th pin of the clock oscillator (X1), and one end of the capacitor C12 and the capacitor C13 connected in parallel is connected between the magnetic bead L1 and the 4th pin of the clock oscillator (X1), and the other end is grounded.
4. The switch clock circuit according to claim 3, characterized in that: The clock input circuit unit (20) further comprises a capacitor C10 and a capacitor C14, one end of each of the capacitors C10 and C14 is connected between the resistor R14 and pin 8 of the chip (U1), and the other end of the capacitor C14 is grounded.
5. The switch clock circuit according to claim 1, characterized in that: The isolation element includes magnetic beads L2, magnetic beads L9, and magnetic beads L11, and the magnetic beads L2, L9, and L11 are 95ohm-145ohm magnetic beads.
6. The switch clock circuit according to claim 5, characterized in that: The magnetic bead L2 is connected to pin 13 of the chip (U1), and the magnetic bead L9 and the magnetic bead L11 are connected in parallel to pins 46 and 60 of the chip (U1).
7. The switch clock circuit according to claim 1 or 6, characterized in that: The filtering component selects inductor filtering LC, including magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14. The magnetic beads L3, L4, L5, L6, L7, L8, L10, L12, L13, and L14 are high-impedance magnetic beads of 480ohm-720ohm.
8. The switch clock circuit according to claim 1, characterized in that: It also includes a control unit (50) connected to the integrated circuit chip unit (10), the control unit (50) being a communication interface, the chip (U1) being programmed via an internal peripheral I2C (Inter-Integrated Circuit) or a full-duplex synchronous serial bus (SPI) interface, and the control unit (50) being configured or outputting different clocks via the I2C or (SPI) bus interface.
9. The switch clock circuit according to claim 1, characterized in that: It also includes a peripheral configuration circuit unit (40) connected to the integrated circuit chip unit (10).