A chip for online monitoring of the operating status of Superbuck converters

Abstract

The present invention discloses a chip for online monitoring of the operating state of a Superbuck converter, which belongs to the field of power electronics technology and integrated circuit design. The chip is arranged at the output end of the Superbuck converter, and includes: a disturbance coupling circuit and an oscillation capture circuit connected in series. The disturbance coupling circuit analyzes the output voltage of the Superbuck converter under disturbance, eliminates the DC component and reduces the ripple component, thereby obtaining the disturbance component. The oscillation capture circuit outputs pulses representing different oscillation events by calculating the number of zero crossings of the disturbance component in the sampled voltage, thereby capturing the oscillation events in the output voltage. The disturbance coupling circuit in the chip provided by the present invention obtains the disturbance component of the output voltage of the Superbuck converter under disturbance, so that the oscillation capture circuit obtains the oscillation event in the output voltage according to the disturbance component, thereby realizing the stability evaluation and adaptive control of the operating state of the Superbuck converter.

Description

Technical Field

[0001] The invention belongs to the field of power electronic technology and integrated circuit design, and more specifically, relates to a chip for online monitoring of the operating state of a Superbuck converter. Background Art

[0002] Superbuck converters are widely used in photovoltaic power generation and other fields because of their continuous input and output currents. Their steady-state performance is similar to that of traditional Buck converters, but their dynamic performance is very different. The transfer function of the Superbuck converter has four poles and two right-half-plane zeros, which not only reduces the dynamic performance, but also makes the design of the feedback controller more complicated, especially the right-half-plane zeros, which greatly reduces the stability of the closed-loop system because it increases the amplitude-frequency response and reduces the phase-frequency response. At present, a practical strategy to eliminate the right-half-plane zeros is to add a damping network to the main converter. With an appropriate damping network, the right-half-plane zero can be adjusted to the left-half-plane zero, which is beneficial to the stability of the closed loop. However, due to the strong nonlinearity of the Superbuck converter, the optimal damping network is difficult to calculate, and the required damping always changes with the change of the operating point.

[0003] In order to solve the nonlinear problem of the Superbuck converter, an adaptive control strategy has been proposed to optimize the dynamic performance. There are many adaptive control strategies. One method is to inject a square wave into the feedback loop, obtain the crossover frequency and phase margin online, and adjust them automatically. Another method is adaptive phase margin adjustment, which can dynamically expand the bandwidth under different load conditions while maintaining a certain phase margin. Other adaptive controls are mainly based on parameter identification and estimation. The online estimation strategy can well evaluate transient stability and uncertainty. At present, the perturbation observation method is a more commonly used online estimation strategy, which can obtain the stability information of the circuit and thus adjust the performance of the closed-loop system.

[0004] Although there are many control strategies based on disturbance observation for different power systems, the existing control strategies are relatively complex and require expensive digital hardware. In addition, the existing methods are not optimized for specific applications, such as some applications that need to consider the impact of ripples and potential dynamics during the observation process. Summary of the invention

[0005] In view of the above defects or improvement needs of the prior art, the present invention provides a chip for online monitoring of the operating status of a Superbuck converter, the purpose of which is to obtain the oscillation data of the converter output in real time by connecting a chip to the output end of the Superbuck converter, so as to realize stability evaluation and adaptive adjustment of the operating status of the Superbuck converter; thereby solving the technical problems of the existing disturbance observation control strategy being complex and having high implementation cost.

[0006] To achieve the above object, according to one aspect of the present invention, there is provided a chip for online monitoring of the operating status of a Superbuck converter, which is arranged at the output end of the Superbuck converter and includes:

[0007] The disturbance coupling circuit is used to analyze the output voltage of the Superbuck converter under disturbance, eliminate the DC component and reduce the ripple component, thereby obtaining the disturbance component; the disturbance coupling circuit includes an impedance Z1 and an impedance Z2 connected in series, and the transfer function H sense (s) = Z2 / (Z1+Z2);

[0008] The oscillation capture circuit is used to output pulses representing different oscillation events by counting the number of zero crossings of the disturbance component in the sampled voltage, thereby capturing the oscillation events in the output voltage.

[0009] In one embodiment, in the first case, the impedance Z1 in the disturbance coupling circuit is connected to the output end of the Superbuck converter and is provided with a series inductor L s and capacitor C s The impedance Z2 includes two branches connected in parallel, one of which is provided with an impedance R s , the other branch is equipped with a series inductor L f and capacitor C f ;

[0010] Among them, the lower edge ω of the amplitude-frequency characteristic curve corresponding to the disturbance coupling circuit L =1 / R s C s , upper edgeω H =R s / L s ; 1 / R s C s =(1 / 3~1 / 2)ω min ,ω min is the minimum oscillation frequency, R s / L s =ω sw / K1,ω sw is the switching frequency, K1 is the coefficient, which is set within 1 to 5; Lf and C f The resonant frequency is set to ω sw ;

[0011] In one of the embodiments, the harmonic gain damping HGD of the disturbance coupling circuit in the first case is a gain ratio of the kth harmonic of the switching frequency to the signal in the passband;

[0012]

[0013] Among them, ω passband is the passband frequency.

[0014] In one embodiment, in the second case, the impedance Z1 in the disturbance coupling circuit is connected to the output end of the Superbuck converter and is provided with a series impedance R r and capacitor C s The impedance Z2 includes three branches connected in parallel, and the first branch is provided with an impedance R s , the second branch is equipped with a series inductor L f and capacitor C f , the third branch is equipped with a capacitor C h ;

[0015] The lower edge of the amplitude-frequency characteristic curve corresponding to the disturbance coupling circuit Upper edge Impedance R r and impedance R s The resistance value is equal to that of the load and is more than 100 times greater than the load resistance, thereby reducing the current flowing into the disturbance coupling circuit.

[0016] In one embodiment, the design principle of the disturbance coupling circuit in the second case is:

[0017]

[0018] In one of the embodiments, the harmonic gain damping HGD of the disturbance coupling circuit in the second case is expressed as:

[0019]

[0020] Among them, ω passband is the passband frequency.

[0021] In one embodiment, the oscillation capture circuit includes two parallel branches, respectively used to detect the output voltage V of the disturbance coupling circuit. sense Each parallel branch includes a hysteresis comparator, a monostable trigger, an RC timing circuit and a counter. The hysteresis comparator captures Vsense The single pulse trigger converts it into a pulse signal, and the counter counts the narrow pulses to obtain V sense The number of up-crossings and down-crossings is measured, and the RC timing circuit is used to reset the counter, indicating that the oscillation signal has been captured. The counters at the back end of the two parallel branches are connected to the logic processing unit, which processes the output signal of the counter and finally outputs the corresponding signal of the captured oscillation event.

[0022] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0023] (1) The online stability monitoring strategy for the Superbuck converter proposed in this invention can determine the current working state of the circuit by collecting the oscillation signal in the output voltage, thereby adjusting the damping of the converter accordingly and improving the dynamic performance of the circuit at different working points. Compared with the existing adaptive control strategy based on disturbance observation, the control system is simple to implement, does not require expensive digital hardware, and takes into account the influence of ripples and potential dynamics.

[0024] (2) In order to implement the above-mentioned online stability monitoring strategy, the online monitoring chip designed by the present invention is mainly composed of a disturbance coupling circuit and an oscillation capture circuit. The two disturbance coupling circuits designed therein can not only effectively eliminate the DC and ripple components in the output voltage of the main circuit, but also retain the disturbance signal without distortion. The two coupling circuits only require a few passive components, and the volume and cost are small. The oscillation capture circuit can capture the oscillation signal in the output of the coupling circuit, and output the corresponding oscillation event signal through processing. The signal contains rich time-varying oscillation event information and can be used for stability evaluation and protection. The output of the 2-bit oscillation capture circuit is buffered and sampled at a rate of once every 0.1 seconds, and only 3.3Mb of memory is required to record for 24 hours.

[0025] (3) The internal circuit structure of the online monitoring chip is relatively simple and does not interfere with the original system. It can be expanded and used in other switching DC-DC converters to achieve adaptive control or stability monitoring. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a basic topological structure diagram of the Superbuck converter provided in the prior art;

[0027] Figure 2 This is an application scenario diagram of a chip for online monitoring of the operating status of a Superbuck converter provided in one embodiment of the present invention;

[0028] Figure 3is i provided in one embodiment of the present invention when D≈0 or D≈1 out and v out Spectrum analysis diagram of

[0029] Figure 4 is i provided in one embodiment of the present invention when D≈0.5 out and v out Spectrum analysis diagram of

[0030] Figure 5 is provided in one embodiment of the present invention. out The spectrum and frequency response diagram of the ideal disturbance coupling circuit;

[0031] Figure 6 is a first disturbance coupling circuit and its amplitude-frequency characteristic curve diagram provided in one embodiment of the present invention;

[0032] Figure 7 is a second disturbance coupling circuit and its amplitude-frequency characteristic curve diagram provided in one embodiment of the present invention;

[0033] Figure 8 is a circuit structure diagram of an oscillation capture circuit provided in one embodiment of the present invention;

[0034] Fig. 9 is a schematic diagram of a capture process of an oscillation capture circuit provided in one embodiment of the present invention;

[0035] Fig.10 It is a schematic diagram of an oscillation event that can be captured by a 2-bit capture circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0037] like Figure 1 As shown in the figure, the basic topology of the Superbuck converter has the same transformation ratio as the traditional Buck circuit, but with an additional inductor and a capacitor. The addition of these two components enables the converter to have continuous input and output currents, making it suitable for photovoltaic power generation. The basic working principle of the Superbuck converter is as follows:

[0038] First, based on the volt-second balance of inductors L1 and L2, it can be obtained that the voltage of capacitor C1 in steady state is approximately equal to the input voltage. Therefore, when the switch is turned on, the diode is turned off, and the voltage of L1 is equal to vin -v out , L2 voltage is equal to v C1 -v out ≈v in -v out At the same time, since capacitor C1 is close to a short circuit at the switching frequency, the inductor current i L1 and i L2 All flow to the load through the switch tube S1. When the switch is turned off, the inductor current i L1 and i L2 All of them are freewheeling through the diode, and the voltage of L1 is equal to v in -v C1 -v out ≈-v out , L2 voltage is equal to -v out Through the volt-second balance of inductors L1 and L2, the relationship between the input voltage and the output voltage in steady state can be obtained: v out =Dv in , where D is the duty cycle. That is, the output voltage of the Superbuck converter in steady state is equal to that of the traditional Buck converter. However, through the small signal model analysis, it can be seen that the transfer function of the Superbuck converter is fourth-order, which makes the design of its feedback compensator more difficult, and G vd There are right half plane zeros in (s), which reduces the stability of the system.

[0039] In order to eliminate G vd (s) is the right half plane zero point, adding a d and C d The damping circuit composed of series is connected in parallel at both ends of C1 (such as Figure 2 As shown). By reasonably designing the parameters of the components, the right half plane zero point can be converted into the left half plane zero point, which can improve the stability of the closed-loop system. However, the parameters of the optimal damping circuit will change with the change of the circuit operating point. Therefore, the present invention proposes an online monitoring chip, which mainly consists of a disturbance coupling circuit and an oscillation capture circuit. Adding it to the original system can realize adaptive damping adjustment.

[0040] like Figure 2 As shown, the present invention provides a chip for online monitoring of the operation status of the Superbuck converter, which is arranged at the output end of the Superbuck converter and includes: a disturbance coupling circuit and an oscillation capture circuit connected in series. The disturbance coupling circuit is used to analyze the output voltage of the Superbuck converter under disturbance, eliminate the DC component and reduce the ripple component, thereby obtaining the disturbance component; the disturbance coupling circuit includes impedance Z1 and impedance Z2 connected in series, and the transfer function H sense(s) = Z2 / (Z1+Z2); an oscillation capture circuit, used to output pulses representing different oscillation events by counting the number of zero crossings of the disturbance component in the sampled voltage, thereby capturing oscillation events in the output voltage.

[0041] In order to illustrate the design principle of the disturbance coupling circuit, it is first necessary to analyze the potential frequency components in the output voltage of the Superbuck converter. The converter output voltage contains DC and AC components, and the AC component contains disturbance and ripple components. In order to ensure the stability of monitoring, the disturbance coupling circuit should only pass the disturbance component of the output voltage. Therefore, the DC part of the output voltage collected in the disturbance coupling circuit should be eliminated, and the ripple component should be attenuated, thereby improving the accuracy of system monitoring.

[0042] First, the disturbance component of the output voltage is analyzed. The frequency range of the disturbance component mainly depends on the real-time operating state of the Superbuck converter, feedback compensator and circuit. Since the feedback compensation and operating state are uncertain in general design, the following will focus on analyzing the potential oscillation frequency under typical working conditions (i.e., resistive load, voltage source, moderate compensation).

[0043] Generally, the feedback loop uses PI compensation, in which the zero point can compensate G vd (s), and the pole located at the origin can provide infinite DC gain, thereby eliminating steady-state errors. In order to provide sufficient phase margin, the crossover frequency of the system must be much lower than the first non-dominant pole, but too low a crossover frequency will reduce the dynamic performance of the circuit. The appropriate design is to place it in the frequency range of 1 / 3 to 1 / 2 of the non-dominant pole so that the phase margin is between 63 and 72°. However, the dominant poles of the Superbuck converter are usually conjugate, that is, both conjugate poles are dominant poles. When compensating for the conjugate poles, a moderate design is to place the zero near the conjugate pole and limit the crossover frequency to be lower than the conjugate pole. But even so, oscillation may be induced, and its frequency is determined by the conjugate pole (depending on the crossover frequency and damping coefficient of the conjugate pole). In addition, the right half plane zero of the Superbuck converter will also destroy the stability of the system and cause oscillation at the corresponding frequency, and its position is usually higher than the dominant pole.

[0044] In summary, by PI compensation control of the Superbuck converter, the frequency range of the output oscillation component is generally distributed near the dominant pole (conjugate pole) and the right half plane zero.

[0045] Next, we analyze the ripple component of the output voltage. The output of a switching power supply will have ripples, which are mainly caused by the changing output current flowing to the load. Since for a resistive load, the output is equivalent to an RC network with a low-pass characteristic, the output current spectrum is first obtained through Fourier analysis, and then the output voltage spectrum can be calculated based on the relationship between the output current and the output voltage. Since the output current is related to the duty cycle, it is necessary to perform spectrum analysis based on different duty cycles. In order to simplify the analysis, the output ripple spectrum when D≈0, D≈1 and D≈0.5 is given here, as shown in the attached figure. Figure 3 and attached Figure 4 shown.

[0046] Through the above analysis, it is obtained that the output ripple components mainly include fundamental wave, second harmonic and third harmonic, where the frequency of the fundamental wave is equal to the switching frequency of the main circuit.

[0047] The design principle of the disturbance coupling circuit is to eliminate the DC and ripple components of the output analyzed above while retaining the disturbance component. Therefore, the designed disturbance coupling circuit should have a bandpass characteristic, as shown in the attached figure. Figure 5 As shown. The lower edge of the passband is ω L , its position cannot be too low or too high. If it is too low, the speed of attenuating the DC component will be reduced, and if it is too high, the disturbance signal will be distorted. From the above analysis, it can be seen that the output voltage will oscillate at a frequency close to or higher than the dominant pole. Assuming the minimum oscillation frequency is ω min , in order to allow the oscillation (disturbance) signal to pass through the disturbance coupling circuit without distortion, ω L Should be placed at (1 / 3~1 / 2)ω min The upper edge of the passband is ω H , its position cannot be too low or too high. If it is too low, it will limit the bandwidth of the disturbance coupling circuit. If it is too high, it will not provide sufficient attenuation for the ripple component. Assume ω H =ω sw / K1, generally K1 should be set within 1 to 5, which will be discussed later when designing the disturbance coupling circuit.

[0048] In the first embodiment of the disturbance coupling circuit, the impedance Z1 of the upper half of the circuit is composed of a series inductor Ls and a capacitor Cs; the impedance Z2 of the lower half includes two parallel branches, one of which is provided with an impedance Rs, and the other is provided with a series inductor Lf and a capacitor Cf. Figure 6 As shown. According to the amplitude-frequency characteristic curve, its lower edge ω L ≈1 / R s C s , upper edgeω H ≈R s / L sAccording to the above analysis, the passband requirement of the disturbance coupling circuit is obtained (i.e. ω L =(1 / 3~1 / 2)ω min ,ω H =ω sw / K1), we can get 1 / R s C s =(1 / 3~1 / 2)ω min , R s / L s =ω sw / K1.

[0049] In order to make the output of the disturbance coupling circuit form zero impedance to the ground at the switching frequency, thereby eliminating the ripple component, L f and C f The resonant frequency is set to ω sw At the same time, in order not to affect the impedance of Z2 at other frequencies, the curve |1 / sC f | and |sL f |With R s The frequency of the crossover point should be as close to ω as possible. sw Considering the error of the actual value of the components, it is recommended to set:

[0050]

[0051] The harmonic gain damping HGD of the disturbance coupling circuit embodiment is the gain ratio of the kth harmonic of the switching frequency to the signal in the passband;

[0052]

[0053] Among them, ω passband is the passband frequency, and k represents the kth harmonic.

[0054] It can be seen that the disturbance coupling circuit can make the fundamental component in the ripple infinitely attenuated, and the harmonic component can be further reduced by increasing K1. When K1 = 2, the second harmonic in the ripple can be attenuated by 12dB, and the third harmonic can be attenuated by 15.6dB.

[0055] In the second embodiment of the disturbance coupling circuit, the impedance Z1 is composed of a series impedance Rr and a capacitor Cs; the impedance Z2 includes three parallel branches, the first branch is provided with an impedance Rs, the second branch is provided with a series inductor Lf and a capacitor Cf, and the third branch is provided with a capacitor Ch. Figure 7 shown.

[0056] Specifically, compared with the first disturbance coupling circuit, this circuit uses R r Replaced L s , because R r and Ch The size will be relatively smaller than L s In order to keep the gain constant within the bandwidth, R r and R s The resistance value should be equal to and much larger than the load resistance value, thereby reducing the current flowing into the disturbance coupling circuit. From the amplitude-frequency characteristic curve, it can be seen that the gain in the passband is R s / (R s +R r ), the lower and upper edges are:

[0057]

[0058] At the same time, there is a double pole in the transfer function at and a double zero at

[0059] In order to eliminate the fundamental component in the ripple, the double zero should be placed at the switching frequency, and the frequency of the double pole should be higher than the double zero, and it should not be placed at the harmonic component of the ripple to prevent the increase of the harmonic component. Assuming that the frequency of the double pole is 1.2 times that of the double zero, the design principle of the disturbance coupling circuit is:

[0060]

[0061] The harmonic gain damping HGD of the disturbance coupling circuit embodiment is expressed as:

[0062]

[0063] Among them, ω passband is the passband frequency. It can be seen that it is very close to the HGD of the first disturbance coupling circuit, but the second disturbance coupling circuit removes L s , only an inductor needs to be connected to the chip, which can effectively reduce the size and weight of the circuit.

[0064] In an embodiment of the oscillation coupling circuit, the oscillation capture circuit is connected after the disturbance coupling circuit to capture the oscillation event in the output voltage. The oscillation capture circuit includes two parallel branches, which are respectively used to detect the output voltage V sense Each parallel branch includes a hysteresis comparator, a monostable trigger, an RC timing circuit and a counter in sequence; the counters at the back end of the two parallel branches are connected to the logic processing unit, and finally output the corresponding signal of the captured oscillation event. Figure 8 shown.

[0065] The specific oscillation capture process of the oscillation capture circuit embodiment is shown in the attached Fig. 9 As shown. When V senseWhen the value exceeds the threshold voltage of the hysteresis comparator of any branch, the branch will detect and generate a narrow pulse, namely, p up or p down The counter then counts these narrow pulses to record the number of times the oscillation signal crosses upward and downward. At the same time, when a narrow pulse arrives, the switch of the RC timing circuit is closed and the capacitor is charged; when there is no narrow pulse, the switch of the RC timing circuit is opened, and the capacitor is discharged through the resistor. If the voltage across the capacitor is lower than V th , the counter will be reset, indicating that the current oscillation signal has been captured and the next oscillation signal will be captured. The capture time of each oscillation signal is determined by the time constant of the RC timing circuit. Finally, the logic unit processes the counter output and outputs the corresponding oscillation event signal.

[0066] The bit width of the counter determines the maximum number of different oscillation events that the circuit can capture. It needs to be adjusted in terms of power consumption, circuit size, memory size, etc. according to specific application requirements. The oscillation events that can be captured by the 2-bit capture circuit are shown in the attached figure. Fig.10 shown.

[0067] When the output of the counter is cut up =1, cut down =1, the logic unit will output the signal of event 1, indicating that oscillation event 1 is captured. This event indicates that any frequency signal within the bandwidth of the disturbance coupling circuit oscillates for one cycle. up =2, cut down =2, the logic unit will output the signal of event 2, indicating that oscillation event 2 is captured. This event indicates that any frequency signal within the bandwidth of the disturbance coupling circuit oscillates for two cycles. up =3, cut down =3, the logic unit will output the signal of event 3, indicating that oscillation event 3 is captured. This event indicates that any frequency signal within the bandwidth of the perturbation coupling circuit oscillates for three cycles. Signals with more oscillation cycles can be captured by increasing the number of bits.

[0068] In order to determine the logical unit, cut up 、cut down The logic of the 2-bit capture circuit required is shown in Table 1. The relevant event signal is only available at a specific cut up and cut down In addition, an error signal can be added to diagnose the capture circuit. up and cut down It is only effective when the difference is greater than or equal to 2, which is impossible during normal oscillation.

[0069] <![CDATA[cnt up ]]> <![CDATA[cnt down ]]> Event 1 Event 2 Event 3 mistake 00 00 0 0 0 0 00 01 0 0 0 0 00 10 x x x 1 00 11 x x x 1 01 00 0 0 0 0 01 01 1 0 0 0 01 10 0 0 0 0 01 11 x x x 1 10 00 x x x 1 10 01 0 0 0 0 10 10 0 1 0 0 10 11 0 0 0 0 11 00 x x x 1 11 01 x x x 1 11 10 0 0 0 0 11 11 0 0 1 0

[0070] Table 1

[0071] Based on the above logic table, the logic function expression of the logic unit can be obtained:

[0072]

[0073] From this we can see that this logic is very easy to implement.

[0074] Assuming that the output of a 2-bit capture circuit is buffered and sampled at a rate of once every 0.1 seconds, the memory required for recording for 24 hours is (86400s)*(10Hz)*4bits=3.3Mb, which is very small. Therefore, with 3.3Mb of memory, all oscillation events in the output voltage can be captured with a time resolution of 0.1s. The specific memory requirement depends on the time resolution and number of bits of the capture circuit.

[0075] Based on the above chip consisting of the disturbance coupling circuit and the oscillation capture circuit, the oscillation event in the output voltage of the Superbuck circuit can be captured, and the circuit is simple and easy to implement. At the same time, the output is very simple and can be used for stability monitoring, power management or adaptive control.

[0076] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip for online monitoring of the operating status of a Superbuck converter, characterized in that: The output end of the Superbuck converter is provided, including: The disturbance coupling circuit is used to analyze the output voltage of the Superbuck converter under disturbance, eliminate the DC component and reduce the ripple component, thereby obtaining the disturbance component; the disturbance coupling circuit includes an impedance Z1 and an impedance Z2 connected in series, and the transfer function H sense (s) = Z2 / (Z1+Z2); An oscillation capture circuit is used to output pulses representing different oscillation events by counting the number of zero crossings of the disturbance component in the sampled voltage, thereby capturing oscillation events in the output voltage; In the first case, the impedance Z1 in the disturbance coupling circuit is connected to the output end of the Superbuck converter and is provided with a series inductor L s and capacitor C s The impedance Z2 includes two branches connected in parallel, one of which is provided with an impedance R s , the other branch is equipped with a series inductor L f and capacitor C f ; In the second case, the impedance Z1 in the disturbance coupling circuit is connected to the output end of the Superbuck converter, and a series impedance R is provided. r and capacitor C s The impedance Z2 includes three branches connected in parallel, and the first branch is provided with an impedance R s , the second branch is equipped with a series inductor L f and capacitor C f , the third branch is equipped with a capacitor C h ; The oscillation capture circuit includes two parallel branches, which are respectively used to detect the output voltage V of the disturbance coupling circuit. sense The up-crossing and down-crossing of each parallel branch include a hysteresis comparator, a monostable trigger, an RC timing circuit and a counter connected in sequence.

2. The chip for online monitoring of the operation status of the Superbuck converter according to claim 1, characterized in that: In the first case, the lower edge ω of the amplitude-frequency characteristic curve corresponding to the disturbance coupling circuit L =1 / R s C s , upper edgeω H =R s / L s ; 1 / R s C s =(1 / 3~1 / 2)ω min ,ω min is the minimum oscillation frequency, R s / L s =ω sw / K1,ω sw is the switching frequency, K1 is the coefficient, which is set within 1 to 5; L f and C f The resonant frequency is set to ω sw ; 3. The chip for online monitoring of the operation status of the Superbuck converter according to claim 2, characterized in that: The harmonic gain damping HGD of the disturbance coupling circuit is the gain ratio of the kth harmonic of the switching frequency to the signal in the passband; Among them, ω passband is the passband frequency.

4. The chip for online monitoring of the operation status of a Superbuck converter according to claim 1, characterized in that: In the second case, the lower edge of the amplitude-frequency characteristic curve corresponding to the disturbance coupling circuit Upper edge Impedance R r and impedance R s The resistance value is equal to that of the load and is more than 100 times greater than the load resistance, thereby reducing the current flowing into the disturbance coupling circuit.

5. The chip for online monitoring of the operation status of the Superbuck converter according to claim 4, characterized in that: The design principle of the disturbance coupling circuit is:

6. The chip for online monitoring of the operation status of a Superbuck converter according to claim 4, characterized in that: The harmonic gain damping HGD of the disturbance coupling circuit is expressed as: Among them, ω passband is the passband frequency.

7. The chip for online monitoring of the operation status of a Superbuck converter according to any one of claims 1 to 6, characterized in that: The hysteresis comparator captures V sense The single pulse trigger converts it into a pulse signal, and the counter counts the narrow pulses to obtain V sense The number of up-crossings and down-crossings is measured, and the RC timing circuit is used to reset the counter, indicating that the oscillation signal has been captured. The counters at the back end of the two parallel branches are connected to the logic processing unit, which processes the output signal of the counter and finally outputs the corresponding signal of the captured oscillation event.

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